1 /* $OpenBSD: athn.c,v 1.72 2012/06/10 21:23:36 kettenis Exp $ */ 2 3 /*- 4 * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2008-2010 Atheros Communications Inc. 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Driver for Atheros 802.11a/g/n chipsets. 22 */ 23 24 #include "athn_usb.h" 25 #include "bpfilter.h" 26 27 #include <sys/param.h> 28 #include <sys/sockio.h> 29 #include <sys/mbuf.h> 30 #include <sys/kernel.h> 31 #include <sys/socket.h> 32 #include <sys/systm.h> 33 #include <sys/malloc.h> 34 #include <sys/queue.h> 35 #include <sys/timeout.h> 36 #include <sys/conf.h> 37 #include <sys/device.h> 38 #include <sys/stdint.h> /* uintptr_t */ 39 40 #include <machine/bus.h> 41 #include <machine/endian.h> 42 #include <machine/intr.h> 43 44 #if NBPFILTER > 0 45 #include <net/bpf.h> 46 #endif 47 #include <net/if.h> 48 #include <net/if_arp.h> 49 #include <net/if_dl.h> 50 #include <net/if_media.h> 51 #include <net/if_types.h> 52 53 #include <netinet/in.h> 54 #include <netinet/in_systm.h> 55 #include <netinet/in_var.h> 56 #include <netinet/if_ether.h> 57 #include <netinet/ip.h> 58 59 #include <net80211/ieee80211_var.h> 60 #include <net80211/ieee80211_amrr.h> 61 #include <net80211/ieee80211_radiotap.h> 62 63 #include <dev/ic/athnreg.h> 64 #include <dev/ic/athnvar.h> 65 66 #ifdef ATHN_DEBUG 67 int athn_debug = 0; 68 #endif 69 70 void athn_radiotap_attach(struct athn_softc *); 71 void athn_get_chanlist(struct athn_softc *); 72 const char * athn_get_mac_name(struct athn_softc *); 73 const char * athn_get_rf_name(struct athn_softc *); 74 void athn_led_init(struct athn_softc *); 75 void athn_set_led(struct athn_softc *, int); 76 void athn_btcoex_init(struct athn_softc *); 77 void athn_btcoex_enable(struct athn_softc *); 78 void athn_btcoex_disable(struct athn_softc *); 79 void athn_set_rxfilter(struct athn_softc *, uint32_t); 80 void athn_get_chipid(struct athn_softc *); 81 int athn_reset_power_on(struct athn_softc *); 82 int athn_reset(struct athn_softc *, int); 83 void athn_init_pll(struct athn_softc *, 84 const struct ieee80211_channel *); 85 int athn_set_power_awake(struct athn_softc *); 86 void athn_set_power_sleep(struct athn_softc *); 87 void athn_write_serdes(struct athn_softc *, 88 const struct athn_serdes *); 89 void athn_config_pcie(struct athn_softc *); 90 void athn_config_nonpcie(struct athn_softc *); 91 int athn_set_chan(struct athn_softc *, struct ieee80211_channel *, 92 struct ieee80211_channel *); 93 int athn_switch_chan(struct athn_softc *, 94 struct ieee80211_channel *, struct ieee80211_channel *); 95 void athn_get_delta_slope(uint32_t, uint32_t *, uint32_t *); 96 void athn_reset_key(struct athn_softc *, int); 97 int athn_set_key(struct ieee80211com *, struct ieee80211_node *, 98 struct ieee80211_key *); 99 void athn_delete_key(struct ieee80211com *, struct ieee80211_node *, 100 struct ieee80211_key *); 101 void athn_iter_func(void *, struct ieee80211_node *); 102 void athn_calib_to(void *); 103 int athn_init_calib(struct athn_softc *, 104 struct ieee80211_channel *, struct ieee80211_channel *); 105 uint8_t athn_chan2fbin(struct ieee80211_channel *); 106 int athn_interpolate(int, int, int, int, int); 107 void athn_get_pier_ival(uint8_t, const uint8_t *, int, int *, 108 int *); 109 void athn_init_dma(struct athn_softc *); 110 void athn_rx_start(struct athn_softc *); 111 void athn_inc_tx_trigger_level(struct athn_softc *); 112 int athn_stop_rx_dma(struct athn_softc *); 113 int athn_rx_abort(struct athn_softc *); 114 void athn_tx_reclaim(struct athn_softc *, int); 115 int athn_tx_pending(struct athn_softc *, int); 116 void athn_stop_tx_dma(struct athn_softc *, int); 117 int athn_txtime(struct athn_softc *, int, int, u_int); 118 void athn_set_sta_timers(struct athn_softc *); 119 void athn_set_hostap_timers(struct athn_softc *); 120 void athn_set_opmode(struct athn_softc *); 121 void athn_set_bss(struct athn_softc *, struct ieee80211_node *); 122 void athn_enable_interrupts(struct athn_softc *); 123 void athn_disable_interrupts(struct athn_softc *); 124 void athn_init_qos(struct athn_softc *); 125 int athn_hw_reset(struct athn_softc *, struct ieee80211_channel *, 126 struct ieee80211_channel *, int); 127 struct ieee80211_node *athn_node_alloc(struct ieee80211com *); 128 void athn_newassoc(struct ieee80211com *, struct ieee80211_node *, 129 int); 130 int athn_media_change(struct ifnet *); 131 void athn_next_scan(void *); 132 int athn_newstate(struct ieee80211com *, enum ieee80211_state, 133 int); 134 void athn_updateedca(struct ieee80211com *); 135 int athn_clock_rate(struct athn_softc *); 136 void athn_updateslot(struct ieee80211com *); 137 void athn_start(struct ifnet *); 138 void athn_watchdog(struct ifnet *); 139 void athn_set_multi(struct athn_softc *); 140 int athn_ioctl(struct ifnet *, u_long, caddr_t); 141 int athn_init(struct ifnet *); 142 void athn_stop(struct ifnet *, int); 143 void athn_init_tx_queues(struct athn_softc *); 144 int32_t athn_ani_get_rssi(struct athn_softc *); 145 void athn_ani_ofdm_err_trigger(struct athn_softc *); 146 void athn_ani_cck_err_trigger(struct athn_softc *); 147 void athn_ani_lower_immunity(struct athn_softc *); 148 void athn_ani_restart(struct athn_softc *); 149 void athn_ani_monitor(struct athn_softc *); 150 151 /* Extern functions. */ 152 int ar5416_attach(struct athn_softc *); 153 int ar9280_attach(struct athn_softc *); 154 int ar9285_attach(struct athn_softc *); 155 int ar9287_attach(struct athn_softc *); 156 int ar9380_attach(struct athn_softc *); 157 int ar5416_init_calib(struct athn_softc *, 158 struct ieee80211_channel *, struct ieee80211_channel *); 159 int ar9285_init_calib(struct athn_softc *, 160 struct ieee80211_channel *, struct ieee80211_channel *); 161 int ar9003_init_calib(struct athn_softc *); 162 void ar9285_pa_calib(struct athn_softc *); 163 void ar9271_pa_calib(struct athn_softc *); 164 void ar9287_1_3_enable_async_fifo(struct athn_softc *); 165 void ar9287_1_3_setup_async_fifo(struct athn_softc *); 166 void ar9003_reset_txsring(struct athn_softc *); 167 168 struct cfdriver athn_cd = { 169 NULL, "athn", DV_IFNET 170 }; 171 172 int 173 athn_attach(struct athn_softc *sc) 174 { 175 struct ieee80211com *ic = &sc->sc_ic; 176 struct ifnet *ifp = &ic->ic_if; 177 int error; 178 179 /* Read hardware revision. */ 180 athn_get_chipid(sc); 181 182 if ((error = athn_reset_power_on(sc)) != 0) { 183 printf("%s: could not reset chip\n", sc->sc_dev.dv_xname); 184 return (error); 185 } 186 187 if ((error = athn_set_power_awake(sc)) != 0) { 188 printf("%s: could not wakeup chip\n", sc->sc_dev.dv_xname); 189 return (error); 190 } 191 192 if (AR_SREV_5416(sc) || AR_SREV_9160(sc)) 193 error = ar5416_attach(sc); 194 else if (AR_SREV_9280(sc)) 195 error = ar9280_attach(sc); 196 else if (AR_SREV_9285(sc)) 197 error = ar9285_attach(sc); 198 #if NATHN_USB > 0 199 else if (AR_SREV_9271(sc)) 200 error = ar9285_attach(sc); 201 #endif 202 else if (AR_SREV_9287(sc)) 203 error = ar9287_attach(sc); 204 else if (AR_SREV_9380(sc) || AR_SREV_9485(sc)) 205 error = ar9380_attach(sc); 206 else 207 error = ENOTSUP; 208 if (error != 0) { 209 printf("%s: could not attach chip\n", sc->sc_dev.dv_xname); 210 return (error); 211 } 212 213 /* We can put the chip in sleep state now. */ 214 athn_set_power_sleep(sc); 215 216 if (!(sc->flags & ATHN_FLAG_USB)) { 217 error = sc->ops.dma_alloc(sc); 218 if (error != 0) { 219 printf("%s: could not allocate DMA resources\n", 220 sc->sc_dev.dv_xname); 221 return (error); 222 } 223 /* Steal one Tx buffer for beacons. */ 224 sc->bcnbuf = SIMPLEQ_FIRST(&sc->txbufs); 225 SIMPLEQ_REMOVE_HEAD(&sc->txbufs, bf_list); 226 } 227 228 if (sc->flags & ATHN_FLAG_RFSILENT) { 229 DPRINTF(("found RF switch connected to GPIO pin %d\n", 230 sc->rfsilent_pin)); 231 } 232 DPRINTF(("%d key cache entries\n", sc->kc_entries)); 233 /* 234 * In HostAP mode, the number of STAs that we can handle is 235 * limited by the number of entries in the HW key cache. 236 * TKIP keys consume 2 entries in the cache. 237 */ 238 ic->ic_max_nnodes = (sc->kc_entries / 2) - IEEE80211_WEP_NKID; 239 if (ic->ic_max_nnodes > IEEE80211_CACHE_SIZE) 240 ic->ic_max_nnodes = IEEE80211_CACHE_SIZE; 241 242 DPRINTF(("using %s loop power control\n", 243 (sc->flags & ATHN_FLAG_OLPC) ? "open" : "closed")); 244 245 DPRINTF(("txchainmask=0x%x rxchainmask=0x%x\n", 246 sc->txchainmask, sc->rxchainmask)); 247 /* Count the number of bits set (in lowest 3 bits). */ 248 sc->ntxchains = 249 ((sc->txchainmask >> 2) & 1) + 250 ((sc->txchainmask >> 1) & 1) + 251 ((sc->txchainmask >> 0) & 1); 252 sc->nrxchains = 253 ((sc->rxchainmask >> 2) & 1) + 254 ((sc->rxchainmask >> 1) & 1) + 255 ((sc->rxchainmask >> 0) & 1); 256 257 if (AR_SINGLE_CHIP(sc)) { 258 printf("%s: %s rev %d (%dT%dR), ROM rev %d, address %s\n", 259 sc->sc_dev.dv_xname, athn_get_mac_name(sc), sc->mac_rev, 260 sc->ntxchains, sc->nrxchains, sc->eep_rev, 261 ether_sprintf(ic->ic_myaddr)); 262 } else { 263 printf("%s: MAC %s rev %d, RF %s (%dT%dR), ROM rev %d, " 264 "address %s\n", 265 sc->sc_dev.dv_xname, athn_get_mac_name(sc), sc->mac_rev, 266 athn_get_rf_name(sc), sc->ntxchains, sc->nrxchains, 267 sc->eep_rev, ether_sprintf(ic->ic_myaddr)); 268 } 269 270 timeout_set(&sc->scan_to, athn_next_scan, sc); 271 timeout_set(&sc->calib_to, athn_calib_to, sc); 272 273 sc->amrr.amrr_min_success_threshold = 1; 274 sc->amrr.amrr_max_success_threshold = 15; 275 276 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 277 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 278 ic->ic_state = IEEE80211_S_INIT; 279 280 /* Set device capabilities. */ 281 ic->ic_caps = 282 IEEE80211_C_WEP | /* WEP. */ 283 IEEE80211_C_RSN | /* WPA/RSN. */ 284 #ifndef IEEE80211_STA_ONLY 285 IEEE80211_C_HOSTAP | /* Host Ap mode supported. */ 286 #endif 287 IEEE80211_C_MONITOR | /* Monitor mode supported. */ 288 IEEE80211_C_SHSLOT | /* Short slot time supported. */ 289 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 290 IEEE80211_C_PMGT; /* Power saving supported. */ 291 292 #ifndef IEEE80211_NO_HT 293 if (sc->flags & ATHN_FLAG_11N) { 294 int i, ntxstreams, nrxstreams; 295 296 /* Set HT capabilities. */ 297 ic->ic_htcaps = 298 IEEE80211_HTCAP_SMPS_DIS | 299 IEEE80211_HTCAP_CBW20_40 | 300 IEEE80211_HTCAP_SGI40 | 301 IEEE80211_HTCAP_DSSSCCK40; 302 if (AR_SREV_9271(sc) || AR_SREV_9287_10_OR_LATER(sc)) 303 ic->ic_htcaps |= IEEE80211_HTCAP_SGI20; 304 if (AR_SREV_9380_10_OR_LATER(sc)) 305 ic->ic_htcaps |= IEEE80211_HTCAP_LDPC; 306 if (AR_SREV_9280_10_OR_LATER(sc)) { 307 ic->ic_htcaps |= IEEE80211_HTCAP_TXSTBC; 308 ic->ic_htcaps |= 1 << IEEE80211_HTCAP_RXSTBC_SHIFT; 309 } 310 ntxstreams = sc->ntxchains; 311 nrxstreams = sc->nrxchains; 312 if (!AR_SREV_9380_10_OR_LATER(sc)) { 313 ntxstreams = MIN(ntxstreams, 2); 314 nrxstreams = MIN(nrxstreams, 2); 315 } 316 /* Set supported HT rates. */ 317 for (i = 0; i < nrxstreams; i++) 318 ic->ic_sup_mcs[i] = 0xff; 319 /* Set the "Tx MCS Set Defined" bit. */ 320 ic->ic_sup_mcs[12] |= 0x01; 321 if (ntxstreams != nrxstreams) { 322 /* Set "Tx Rx MCS Set Not Equal" bit. */ 323 ic->ic_sup_mcs[12] |= 0x02; 324 ic->ic_sup_mcs[12] |= (ntxstreams - 1) << 2; 325 } 326 } 327 #endif 328 329 /* Set supported rates. */ 330 if (sc->flags & ATHN_FLAG_11G) { 331 ic->ic_sup_rates[IEEE80211_MODE_11B] = 332 ieee80211_std_rateset_11b; 333 ic->ic_sup_rates[IEEE80211_MODE_11G] = 334 ieee80211_std_rateset_11g; 335 } 336 if (sc->flags & ATHN_FLAG_11A) { 337 ic->ic_sup_rates[IEEE80211_MODE_11A] = 338 ieee80211_std_rateset_11a; 339 } 340 341 /* Get the list of authorized/supported channels. */ 342 athn_get_chanlist(sc); 343 344 /* IBSS channel undefined for now. */ 345 ic->ic_ibss_chan = &ic->ic_channels[0]; 346 347 ifp->if_softc = sc; 348 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 349 ifp->if_ioctl = athn_ioctl; 350 ifp->if_start = athn_start; 351 ifp->if_watchdog = athn_watchdog; 352 IFQ_SET_READY(&ifp->if_snd); 353 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 354 355 if_attach(ifp); 356 ieee80211_ifattach(ifp); 357 ic->ic_node_alloc = athn_node_alloc; 358 ic->ic_newassoc = athn_newassoc; 359 ic->ic_updateslot = athn_updateslot; 360 ic->ic_updateedca = athn_updateedca; 361 #ifdef notyet 362 ic->ic_set_key = athn_set_key; 363 ic->ic_delete_key = athn_delete_key; 364 #endif 365 366 /* Override 802.11 state transition machine. */ 367 sc->sc_newstate = ic->ic_newstate; 368 ic->ic_newstate = athn_newstate; 369 ieee80211_media_init(ifp, athn_media_change, ieee80211_media_status); 370 371 #if NBPFILTER > 0 372 athn_radiotap_attach(sc); 373 #endif 374 375 return (0); 376 } 377 378 void 379 athn_detach(struct athn_softc *sc) 380 { 381 struct ifnet *ifp = &sc->sc_ic.ic_if; 382 int qid; 383 384 timeout_del(&sc->scan_to); 385 timeout_del(&sc->calib_to); 386 387 if (!(sc->flags & ATHN_FLAG_USB)) { 388 for (qid = 0; qid < ATHN_QID_COUNT; qid++) 389 athn_tx_reclaim(sc, qid); 390 391 /* Free Tx/Rx DMA resources. */ 392 sc->ops.dma_free(sc); 393 } 394 /* Free ROM copy. */ 395 if (sc->eep != NULL) 396 free(sc->eep, M_DEVBUF); 397 398 ieee80211_ifdetach(ifp); 399 if_detach(ifp); 400 } 401 402 #if NBPFILTER > 0 403 /* 404 * Attach the interface to 802.11 radiotap. 405 */ 406 void 407 athn_radiotap_attach(struct athn_softc *sc) 408 { 409 bpfattach(&sc->sc_drvbpf, &sc->sc_ic.ic_if, DLT_IEEE802_11_RADIO, 410 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN); 411 412 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 413 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 414 sc->sc_rxtap.wr_ihdr.it_present = htole32(ATHN_RX_RADIOTAP_PRESENT); 415 416 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 417 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 418 sc->sc_txtap.wt_ihdr.it_present = htole32(ATHN_TX_RADIOTAP_PRESENT); 419 } 420 #endif 421 422 void 423 athn_get_chanlist(struct athn_softc *sc) 424 { 425 struct ieee80211com *ic = &sc->sc_ic; 426 uint8_t chan; 427 int i; 428 429 if (sc->flags & ATHN_FLAG_11G) { 430 for (i = 1; i <= 14; i++) { 431 chan = i; 432 ic->ic_channels[chan].ic_freq = 433 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_2GHZ); 434 ic->ic_channels[chan].ic_flags = 435 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 436 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 437 } 438 } 439 if (sc->flags & ATHN_FLAG_11A) { 440 for (i = 0; i < nitems(athn_5ghz_chans); i++) { 441 chan = athn_5ghz_chans[i]; 442 ic->ic_channels[chan].ic_freq = 443 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ); 444 ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A; 445 } 446 } 447 } 448 449 void 450 athn_rx_start(struct athn_softc *sc) 451 { 452 struct ieee80211com *ic = &sc->sc_ic; 453 uint32_t rfilt; 454 455 /* Setup Rx DMA descriptors. */ 456 sc->ops.rx_enable(sc); 457 458 /* Set Rx filter. */ 459 rfilt = AR_RX_FILTER_UCAST | AR_RX_FILTER_BCAST | AR_RX_FILTER_MCAST; 460 #ifndef IEEE80211_NO_HT 461 /* Want Compressed Block Ack Requests. */ 462 rfilt |= AR_RX_FILTER_COMPR_BAR; 463 #endif 464 rfilt |= AR_RX_FILTER_BEACON; 465 if (ic->ic_opmode != IEEE80211_M_STA) { 466 rfilt |= AR_RX_FILTER_PROBEREQ; 467 if (ic->ic_opmode == IEEE80211_M_MONITOR) 468 rfilt |= AR_RX_FILTER_PROM; 469 #ifndef IEEE80211_STA_ONLY 470 if (AR_SREV_9280_10_OR_LATER(sc) && 471 ic->ic_opmode == IEEE80211_M_HOSTAP) 472 rfilt |= AR_RX_FILTER_PSPOLL; 473 #endif 474 } 475 athn_set_rxfilter(sc, rfilt); 476 477 /* Set BSSID mask. */ 478 AR_WRITE(sc, AR_BSSMSKL, 0xffffffff); 479 AR_WRITE(sc, AR_BSSMSKU, 0xffff); 480 481 athn_set_opmode(sc); 482 483 /* Set multicast filter. */ 484 AR_WRITE(sc, AR_MCAST_FIL0, 0xffffffff); 485 AR_WRITE(sc, AR_MCAST_FIL1, 0xffffffff); 486 487 AR_WRITE(sc, AR_FILT_OFDM, 0); 488 AR_WRITE(sc, AR_FILT_CCK, 0); 489 AR_WRITE(sc, AR_MIBC, 0); 490 AR_WRITE(sc, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); 491 AR_WRITE(sc, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); 492 493 /* XXX ANI. */ 494 AR_WRITE(sc, AR_PHY_ERR_1, 0); 495 AR_WRITE(sc, AR_PHY_ERR_2, 0); 496 497 /* Disable HW crypto for now. */ 498 AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_ENCRYPT_DIS | AR_DIAG_DECRYPT_DIS); 499 500 /* Start PCU Rx. */ 501 AR_CLRBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 502 AR_WRITE_BARRIER(sc); 503 } 504 505 void 506 athn_set_rxfilter(struct athn_softc *sc, uint32_t rfilt) 507 { 508 AR_WRITE(sc, AR_RX_FILTER, rfilt); 509 510 #ifdef notyet 511 reg = AR_READ(sc, AR_PHY_ERR); 512 reg &= (AR_PHY_ERR_RADAR | AR_PHY_ERR_OFDM_TIMING | 513 AR_PHY_ERR_CCK_TIMING); 514 AR_WRITE(sc, AR_PHY_ERR, reg); 515 if (reg != 0) 516 AR_SETBITS(sc, AR_RXCFG, AR_RXCFG_ZLFDMA); 517 else 518 AR_CLRBITS(sc, AR_RXCFG, AR_RXCFG_ZLFDMA); 519 #else 520 AR_WRITE(sc, AR_PHY_ERR, 0); 521 AR_CLRBITS(sc, AR_RXCFG, AR_RXCFG_ZLFDMA); 522 #endif 523 AR_WRITE_BARRIER(sc); 524 } 525 526 int 527 athn_intr(void *xsc) 528 { 529 struct athn_softc *sc = xsc; 530 struct ifnet *ifp = &sc->sc_ic.ic_if; 531 532 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) != 533 (IFF_UP | IFF_RUNNING)) 534 return (0); 535 536 return (sc->ops.intr(sc)); 537 } 538 539 void 540 athn_get_chipid(struct athn_softc *sc) 541 { 542 uint32_t reg; 543 544 reg = AR_READ(sc, AR_SREV); 545 if (MS(reg, AR_SREV_ID) == 0xff) { 546 sc->mac_ver = MS(reg, AR_SREV_VERSION2); 547 sc->mac_rev = MS(reg, AR_SREV_REVISION2); 548 if (!(reg & AR_SREV_TYPE2_HOST_MODE)) 549 sc->flags |= ATHN_FLAG_PCIE; 550 } else { 551 sc->mac_ver = MS(reg, AR_SREV_VERSION); 552 sc->mac_rev = MS(reg, AR_SREV_REVISION); 553 if (sc->mac_ver == AR_SREV_VERSION_5416_PCIE) 554 sc->flags |= ATHN_FLAG_PCIE; 555 } 556 } 557 558 const char * 559 athn_get_mac_name(struct athn_softc *sc) 560 { 561 switch (sc->mac_ver) { 562 case AR_SREV_VERSION_5416_PCI: 563 return ("AR5416"); 564 case AR_SREV_VERSION_5416_PCIE: 565 return ("AR5418"); 566 case AR_SREV_VERSION_9160: 567 return ("AR9160"); 568 case AR_SREV_VERSION_9280: 569 return ("AR9280"); 570 case AR_SREV_VERSION_9285: 571 return ("AR9285"); 572 case AR_SREV_VERSION_9271: 573 return ("AR9271"); 574 case AR_SREV_VERSION_9287: 575 return ("AR9287"); 576 case AR_SREV_VERSION_9380: 577 return ("AR9380"); 578 case AR_SREV_VERSION_9485: 579 return ("AR9485"); 580 } 581 return ("unknown"); 582 } 583 584 /* 585 * Return RF chip name (not for single-chip solutions). 586 */ 587 const char * 588 athn_get_rf_name(struct athn_softc *sc) 589 { 590 KASSERT(!AR_SINGLE_CHIP(sc)); 591 592 switch (sc->rf_rev) { 593 case AR_RAD5133_SREV_MAJOR: /* Dual-band 3T3R. */ 594 return ("AR5133"); 595 case AR_RAD2133_SREV_MAJOR: /* Single-band 3T3R. */ 596 return ("AR2133"); 597 case AR_RAD5122_SREV_MAJOR: /* Dual-band 2T2R. */ 598 return ("AR5122"); 599 case AR_RAD2122_SREV_MAJOR: /* Single-band 2T2R. */ 600 return ("AR2122"); 601 } 602 return ("unknown"); 603 } 604 605 int 606 athn_reset_power_on(struct athn_softc *sc) 607 { 608 int ntries; 609 610 /* Set force wake. */ 611 AR_WRITE(sc, AR_RTC_FORCE_WAKE, 612 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 613 614 if (!AR_SREV_9380_10_OR_LATER(sc)) { 615 /* Make sure no DMA is active by doing an AHB reset. */ 616 AR_WRITE(sc, AR_RC, AR_RC_AHB); 617 } 618 /* RTC reset and clear. */ 619 AR_WRITE(sc, AR_RTC_RESET, 0); 620 AR_WRITE_BARRIER(sc); 621 DELAY(2); 622 if (!AR_SREV_9380_10_OR_LATER(sc)) 623 AR_WRITE(sc, AR_RC, 0); 624 AR_WRITE(sc, AR_RTC_RESET, 1); 625 626 /* Poll until RTC is ON. */ 627 for (ntries = 0; ntries < 1000; ntries++) { 628 if ((AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) == 629 AR_RTC_STATUS_ON) 630 break; 631 DELAY(10); 632 } 633 if (ntries == 1000) { 634 DPRINTF(("RTC not waking up\n")); 635 return (ETIMEDOUT); 636 } 637 return (athn_reset(sc, 0)); 638 } 639 640 int 641 athn_reset(struct athn_softc *sc, int cold) 642 { 643 int ntries; 644 645 /* Set force wake. */ 646 AR_WRITE(sc, AR_RTC_FORCE_WAKE, 647 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 648 649 if (AR_READ(sc, AR_INTR_SYNC_CAUSE) & 650 (AR_INTR_SYNC_LOCAL_TIMEOUT | AR_INTR_SYNC_RADM_CPL_TIMEOUT)) { 651 AR_WRITE(sc, AR_INTR_SYNC_ENABLE, 0); 652 AR_WRITE(sc, AR_RC, AR_RC_HOSTIF | 653 (!AR_SREV_9380_10_OR_LATER(sc) ? AR_RC_AHB : 0)); 654 } else if (!AR_SREV_9380_10_OR_LATER(sc)) 655 AR_WRITE(sc, AR_RC, AR_RC_AHB); 656 657 AR_WRITE(sc, AR_RTC_RC, AR_RTC_RC_MAC_WARM | 658 (cold ? AR_RTC_RC_MAC_COLD : 0)); 659 AR_WRITE_BARRIER(sc); 660 DELAY(50); 661 AR_WRITE(sc, AR_RTC_RC, 0); 662 for (ntries = 0; ntries < 1000; ntries++) { 663 if (!(AR_READ(sc, AR_RTC_RC) & 664 (AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD))) 665 break; 666 DELAY(10); 667 } 668 if (ntries == 1000) { 669 DPRINTF(("RTC stuck in MAC reset\n")); 670 return (ETIMEDOUT); 671 } 672 AR_WRITE(sc, AR_RC, 0); 673 AR_WRITE_BARRIER(sc); 674 return (0); 675 } 676 677 int 678 athn_set_power_awake(struct athn_softc *sc) 679 { 680 int ntries, error; 681 682 /* Do a Power-On-Reset if shutdown. */ 683 if ((AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) == 684 AR_RTC_STATUS_SHUTDOWN) { 685 if ((error = athn_reset_power_on(sc)) != 0) 686 return (error); 687 if (!AR_SREV_9380_10_OR_LATER(sc)) 688 athn_init_pll(sc, NULL); 689 } 690 AR_SETBITS(sc, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 691 AR_WRITE_BARRIER(sc); 692 DELAY(50); /* Give chip the chance to awake. */ 693 694 /* Poll until RTC is ON. */ 695 for (ntries = 0; ntries < 4000; ntries++) { 696 if ((AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) == 697 AR_RTC_STATUS_ON) 698 break; 699 DELAY(50); 700 AR_SETBITS(sc, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 701 } 702 if (ntries == 4000) { 703 DPRINTF(("RTC not waking up\n")); 704 return (ETIMEDOUT); 705 } 706 707 AR_CLRBITS(sc, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 708 AR_WRITE_BARRIER(sc); 709 return (0); 710 } 711 712 void 713 athn_set_power_sleep(struct athn_softc *sc) 714 { 715 AR_SETBITS(sc, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 716 /* Allow the MAC to go to sleep. */ 717 AR_CLRBITS(sc, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 718 if (!AR_SREV_9380_10_OR_LATER(sc)) 719 AR_WRITE(sc, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); 720 /* 721 * NB: Clearing RTC_RESET_EN when setting the chip to sleep mode 722 * results in high power consumption on AR5416 chipsets. 723 */ 724 if (!AR_SREV_5416(sc) && !AR_SREV_9271(sc)) 725 AR_CLRBITS(sc, AR_RTC_RESET, AR_RTC_RESET_EN); 726 AR_WRITE_BARRIER(sc); 727 } 728 729 void 730 athn_init_pll(struct athn_softc *sc, const struct ieee80211_channel *c) 731 { 732 uint32_t pll; 733 734 if (AR_SREV_9380_10_OR_LATER(sc)) { 735 if (AR_SREV_9485(sc)) 736 AR_WRITE(sc, AR_RTC_PLL_CONTROL2, 0x886666); 737 pll = SM(AR_RTC_9160_PLL_REFDIV, 0x5); 738 pll |= SM(AR_RTC_9160_PLL_DIV, 0x2c); 739 } else if (AR_SREV_9280_10_OR_LATER(sc)) { 740 pll = SM(AR_RTC_9160_PLL_REFDIV, 0x05); 741 if (c != NULL && IEEE80211_IS_CHAN_5GHZ(c)) { 742 if (sc->flags & ATHN_FLAG_FAST_PLL_CLOCK) 743 pll = 0x142c; 744 else if (AR_SREV_9280_20(sc)) 745 pll = 0x2850; 746 else 747 pll |= SM(AR_RTC_9160_PLL_DIV, 0x28); 748 } else 749 pll |= SM(AR_RTC_9160_PLL_DIV, 0x2c); 750 } else if (AR_SREV_9160_10_OR_LATER(sc)) { 751 pll = SM(AR_RTC_9160_PLL_REFDIV, 0x05); 752 if (c != NULL && IEEE80211_IS_CHAN_5GHZ(c)) 753 pll |= SM(AR_RTC_9160_PLL_DIV, 0x50); 754 else 755 pll |= SM(AR_RTC_9160_PLL_DIV, 0x58); 756 } else { 757 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2; 758 if (c != NULL && IEEE80211_IS_CHAN_5GHZ(c)) 759 pll |= SM(AR_RTC_PLL_DIV, 0x0a); 760 else 761 pll |= SM(AR_RTC_PLL_DIV, 0x0b); 762 } 763 DPRINTFN(5, ("AR_RTC_PLL_CONTROL=0x%08x\n", pll)); 764 AR_WRITE(sc, AR_RTC_PLL_CONTROL, pll); 765 if (AR_SREV_9271(sc)) { 766 /* Switch core clock to 117MHz. */ 767 AR_WRITE_BARRIER(sc); 768 DELAY(500); 769 AR_WRITE(sc, 0x50050, 0x304); 770 } 771 AR_WRITE_BARRIER(sc); 772 DELAY(100); 773 AR_WRITE(sc, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); 774 AR_WRITE_BARRIER(sc); 775 } 776 777 void 778 athn_write_serdes(struct athn_softc *sc, const struct athn_serdes *serdes) 779 { 780 int i; 781 782 /* Write sequence to Serializer/Deserializer. */ 783 for (i = 0; i < serdes->nvals; i++) 784 AR_WRITE(sc, AR_PCIE_SERDES, serdes->vals[i]); 785 AR_WRITE(sc, AR_PCIE_SERDES2, 0); 786 AR_WRITE_BARRIER(sc); 787 } 788 789 void 790 athn_config_pcie(struct athn_softc *sc) 791 { 792 /* Disable PLL when in L0s as well as receiver clock when in L1. */ 793 athn_write_serdes(sc, sc->serdes); 794 795 DELAY(1000); 796 /* Allow forcing of PCIe core into L1 state. */ 797 AR_SETBITS(sc, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 798 799 #ifndef ATHN_PCIE_WAEN 800 AR_WRITE(sc, AR_WA, sc->workaround); 801 #else 802 AR_WRITE(sc, AR_WA, ATHN_PCIE_WAEN); 803 #endif 804 AR_WRITE_BARRIER(sc); 805 } 806 807 /* 808 * Serializer/Deserializer programming for non-PCIe devices. 809 */ 810 static const uint32_t ar_nonpcie_serdes_vals[] = { 811 0x9248fc00, 812 0x24924924, 813 0x28000029, 814 0x57160824, 815 0x25980579, 816 0x00000000, 817 0x1aaabe40, 818 0xbe105554, 819 0x000e1007 820 }; 821 822 static const struct athn_serdes ar_nonpcie_serdes = { 823 nitems(ar_nonpcie_serdes_vals), 824 ar_nonpcie_serdes_vals 825 }; 826 827 void 828 athn_config_nonpcie(struct athn_softc *sc) 829 { 830 athn_write_serdes(sc, &ar_nonpcie_serdes); 831 } 832 833 int 834 athn_set_chan(struct athn_softc *sc, struct ieee80211_channel *c, 835 struct ieee80211_channel *extc) 836 { 837 struct athn_ops *ops = &sc->ops; 838 int error, qid; 839 840 /* Check that Tx is stopped, otherwise RF Bus grant will not work. */ 841 for (qid = 0; qid < ATHN_QID_COUNT; qid++) 842 if (athn_tx_pending(sc, qid)) 843 return (EBUSY); 844 845 /* Request RF Bus grant. */ 846 if ((error = ops->rf_bus_request(sc)) != 0) 847 return (error); 848 849 ops->set_phy(sc, c, extc); 850 851 /* Change the synthesizer. */ 852 if ((error = ops->set_synth(sc, c, extc)) != 0) 853 return (error); 854 855 sc->curchan = c; 856 sc->curchanext = extc; 857 858 /* Set transmit power values for new channel. */ 859 ops->set_txpower(sc, c, extc); 860 861 /* Release the RF Bus grant. */ 862 ops->rf_bus_release(sc); 863 864 /* Write delta slope coeffs for modes where OFDM may be used. */ 865 if (sc->sc_ic.ic_curmode != IEEE80211_MODE_11B) 866 ops->set_delta_slope(sc, c, extc); 867 868 ops->spur_mitigate(sc, c, extc); 869 /* XXX Load noisefloor values and start calibration. */ 870 871 return (0); 872 } 873 874 int 875 athn_switch_chan(struct athn_softc *sc, struct ieee80211_channel *c, 876 struct ieee80211_channel *extc) 877 { 878 int error, qid; 879 880 /* Disable interrupts. */ 881 athn_disable_interrupts(sc); 882 883 /* Stop all Tx queues. */ 884 for (qid = 0; qid < ATHN_QID_COUNT; qid++) 885 athn_stop_tx_dma(sc, qid); 886 for (qid = 0; qid < ATHN_QID_COUNT; qid++) 887 athn_tx_reclaim(sc, qid); 888 889 /* Stop Rx. */ 890 AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 891 AR_WRITE(sc, AR_MIBC, AR_MIBC_FMC); 892 AR_WRITE(sc, AR_MIBC, AR_MIBC_CMC); 893 AR_WRITE(sc, AR_FILT_OFDM, 0); 894 AR_WRITE(sc, AR_FILT_CCK, 0); 895 athn_set_rxfilter(sc, 0); 896 error = athn_stop_rx_dma(sc); 897 if (error != 0) 898 goto reset; 899 900 #ifdef notyet 901 /* AR9280 needs a full reset. */ 902 if (AR_SREV_9280(sc)) 903 #endif 904 goto reset; 905 906 /* If band or bandwidth changes, we need to do a full reset. */ 907 if (c->ic_flags != sc->curchan->ic_flags || 908 ((extc != NULL) ^ (sc->curchanext != NULL))) { 909 DPRINTFN(2, ("channel band switch\n")); 910 goto reset; 911 } 912 error = athn_set_power_awake(sc); 913 if (error != 0) 914 goto reset; 915 916 error = athn_set_chan(sc, c, extc); 917 if (error != 0) { 918 reset: /* Error found, try a full reset. */ 919 DPRINTFN(3, ("needs a full reset\n")); 920 error = athn_hw_reset(sc, c, extc, 0); 921 if (error != 0) /* Hopeless case. */ 922 return (error); 923 } 924 athn_rx_start(sc); 925 926 /* Re-enable interrupts. */ 927 athn_enable_interrupts(sc); 928 return (0); 929 } 930 931 void 932 athn_get_delta_slope(uint32_t coeff, uint32_t *exponent, uint32_t *mantissa) 933 { 934 #define COEFF_SCALE_SHIFT 24 935 uint32_t exp, man; 936 937 /* exponent = 14 - floor(log2(coeff)) */ 938 for (exp = 31; exp > 0; exp--) 939 if (coeff & (1 << exp)) 940 break; 941 exp = 14 - (exp - COEFF_SCALE_SHIFT); 942 943 /* mantissa = floor(coeff * 2^exponent + 0.5) */ 944 man = coeff + (1 << (COEFF_SCALE_SHIFT - exp - 1)); 945 946 *mantissa = man >> (COEFF_SCALE_SHIFT - exp); 947 *exponent = exp - 16; 948 #undef COEFF_SCALE_SHIFT 949 } 950 951 void 952 athn_reset_key(struct athn_softc *sc, int entry) 953 { 954 /* 955 * NB: Key cache registers access special memory area that requires 956 * two 32-bit writes to actually update the values in the internal 957 * memory. Consequently, writes must be grouped by pair. 958 */ 959 AR_WRITE(sc, AR_KEYTABLE_KEY0(entry), 0); 960 AR_WRITE(sc, AR_KEYTABLE_KEY1(entry), 0); 961 962 AR_WRITE(sc, AR_KEYTABLE_KEY2(entry), 0); 963 AR_WRITE(sc, AR_KEYTABLE_KEY3(entry), 0); 964 965 AR_WRITE(sc, AR_KEYTABLE_KEY4(entry), 0); 966 AR_WRITE(sc, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR); 967 968 AR_WRITE(sc, AR_KEYTABLE_MAC0(entry), 0); 969 AR_WRITE(sc, AR_KEYTABLE_MAC1(entry), 0); 970 971 AR_WRITE_BARRIER(sc); 972 } 973 974 int 975 athn_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 976 struct ieee80211_key *k) 977 { 978 struct athn_softc *sc = ic->ic_softc; 979 const uint8_t *txmic, *rxmic, *key, *addr; 980 uintptr_t entry, micentry; 981 uint32_t type, lo, hi; 982 983 switch (k->k_cipher) { 984 case IEEE80211_CIPHER_WEP40: 985 type = AR_KEYTABLE_TYPE_40; 986 break; 987 case IEEE80211_CIPHER_WEP104: 988 type = AR_KEYTABLE_TYPE_104; 989 break; 990 case IEEE80211_CIPHER_TKIP: 991 type = AR_KEYTABLE_TYPE_TKIP; 992 break; 993 case IEEE80211_CIPHER_CCMP: 994 type = AR_KEYTABLE_TYPE_CCM; 995 break; 996 default: 997 /* Fallback to software crypto for other ciphers. */ 998 return (ieee80211_set_key(ic, ni, k)); 999 } 1000 1001 if (!(k->k_flags & IEEE80211_KEY_GROUP)) 1002 entry = IEEE80211_WEP_NKID + IEEE80211_AID(ni->ni_associd); 1003 else 1004 entry = k->k_id; 1005 k->k_priv = (void *)entry; 1006 1007 /* NB: See note about key cache registers access above. */ 1008 key = k->k_key; 1009 if (type == AR_KEYTABLE_TYPE_TKIP) { 1010 #ifndef IEEE80211_STA_ONLY 1011 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 1012 txmic = &key[16]; 1013 rxmic = &key[24]; 1014 } else 1015 #endif 1016 { 1017 rxmic = &key[16]; 1018 txmic = &key[24]; 1019 } 1020 /* Tx+Rx MIC key is at entry + 64. */ 1021 micentry = entry + 64; 1022 AR_WRITE(sc, AR_KEYTABLE_KEY0(micentry), LE_READ_4(&rxmic[0])); 1023 AR_WRITE(sc, AR_KEYTABLE_KEY1(micentry), LE_READ_2(&txmic[2])); 1024 1025 AR_WRITE(sc, AR_KEYTABLE_KEY2(micentry), LE_READ_4(&rxmic[4])); 1026 AR_WRITE(sc, AR_KEYTABLE_KEY3(micentry), LE_READ_2(&txmic[0])); 1027 1028 AR_WRITE(sc, AR_KEYTABLE_KEY4(micentry), LE_READ_4(&txmic[4])); 1029 AR_WRITE(sc, AR_KEYTABLE_TYPE(micentry), AR_KEYTABLE_TYPE_CLR); 1030 } 1031 AR_WRITE(sc, AR_KEYTABLE_KEY0(entry), LE_READ_4(&key[ 0])); 1032 AR_WRITE(sc, AR_KEYTABLE_KEY1(entry), LE_READ_2(&key[ 4])); 1033 1034 AR_WRITE(sc, AR_KEYTABLE_KEY2(entry), LE_READ_4(&key[ 6])); 1035 AR_WRITE(sc, AR_KEYTABLE_KEY3(entry), LE_READ_2(&key[10])); 1036 1037 AR_WRITE(sc, AR_KEYTABLE_KEY4(entry), LE_READ_4(&key[12])); 1038 AR_WRITE(sc, AR_KEYTABLE_TYPE(entry), type); 1039 1040 if (!(k->k_flags & IEEE80211_KEY_GROUP)) { 1041 addr = ni->ni_macaddr; 1042 lo = LE_READ_4(&addr[0]); 1043 hi = LE_READ_2(&addr[4]); 1044 lo = lo >> 1 | hi << 31; 1045 hi = hi >> 1; 1046 } else 1047 lo = hi = 0; 1048 AR_WRITE(sc, AR_KEYTABLE_MAC0(entry), lo); 1049 AR_WRITE(sc, AR_KEYTABLE_MAC1(entry), hi | AR_KEYTABLE_VALID); 1050 AR_WRITE_BARRIER(sc); 1051 return (0); 1052 } 1053 1054 void 1055 athn_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 1056 struct ieee80211_key *k) 1057 { 1058 struct athn_softc *sc = ic->ic_softc; 1059 uintptr_t entry; 1060 1061 switch (k->k_cipher) { 1062 case IEEE80211_CIPHER_WEP40: 1063 case IEEE80211_CIPHER_WEP104: 1064 case IEEE80211_CIPHER_CCMP: 1065 entry = (uintptr_t)k->k_priv; 1066 athn_reset_key(sc, entry); 1067 break; 1068 case IEEE80211_CIPHER_TKIP: 1069 entry = (uintptr_t)k->k_priv; 1070 athn_reset_key(sc, entry); 1071 athn_reset_key(sc, entry + 64); 1072 break; 1073 default: 1074 /* Fallback to software crypto for other ciphers. */ 1075 ieee80211_delete_key(ic, ni, k); 1076 } 1077 } 1078 1079 void 1080 athn_led_init(struct athn_softc *sc) 1081 { 1082 struct athn_ops *ops = &sc->ops; 1083 1084 ops->gpio_config_output(sc, sc->led_pin, AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 1085 /* LED off, active low. */ 1086 athn_set_led(sc, 0); 1087 } 1088 1089 void 1090 athn_set_led(struct athn_softc *sc, int on) 1091 { 1092 struct athn_ops *ops = &sc->ops; 1093 1094 sc->led_state = on; 1095 ops->gpio_write(sc, sc->led_pin, !sc->led_state); 1096 } 1097 1098 #ifdef ATHN_BT_COEXISTENCE 1099 void 1100 athn_btcoex_init(struct athn_softc *sc) 1101 { 1102 struct athn_ops *ops = &sc->ops; 1103 uint32_t reg; 1104 1105 if (sc->flags & ATHN_FLAG_BTCOEX2WIRE) { 1106 /* Connect bt_active to baseband. */ 1107 AR_CLRBITS(sc, sc->gpio_input_en_off, 1108 AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF | 1109 AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF); 1110 AR_SETBITS(sc, sc->gpio_input_en_off, 1111 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB); 1112 1113 reg = AR_READ(sc, AR_GPIO_INPUT_MUX1); 1114 reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_ACTIVE, 1115 AR_GPIO_BTACTIVE_PIN); 1116 AR_WRITE(sc, AR_GPIO_INPUT_MUX1, reg); 1117 AR_WRITE_BARRIER(sc); 1118 1119 ops->gpio_config_input(sc, AR_GPIO_BTACTIVE_PIN); 1120 } else { /* 3-wire. */ 1121 AR_SETBITS(sc, sc->gpio_input_en_off, 1122 AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB | 1123 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB); 1124 1125 reg = AR_READ(sc, AR_GPIO_INPUT_MUX1); 1126 reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_ACTIVE, 1127 AR_GPIO_BTACTIVE_PIN); 1128 reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_PRIORITY, 1129 AR_GPIO_BTPRIORITY_PIN); 1130 AR_WRITE(sc, AR_GPIO_INPUT_MUX1, reg); 1131 AR_WRITE_BARRIER(sc); 1132 1133 ops->gpio_config_input(sc, AR_GPIO_BTACTIVE_PIN); 1134 ops->gpio_config_input(sc, AR_GPIO_BTPRIORITY_PIN); 1135 } 1136 } 1137 1138 void 1139 athn_btcoex_enable(struct athn_softc *sc) 1140 { 1141 struct athn_ops *ops = &sc->ops; 1142 uint32_t reg; 1143 1144 if (sc->flags & ATHN_FLAG_BTCOEX3WIRE) { 1145 AR_WRITE(sc, AR_BT_COEX_MODE, 1146 SM(AR_BT_MODE, AR_BT_MODE_SLOTTED) | 1147 SM(AR_BT_PRIORITY_TIME, 2) | 1148 SM(AR_BT_FIRST_SLOT_TIME, 5) | 1149 SM(AR_BT_QCU_THRESH, ATHN_QID_AC_BE) | 1150 AR_BT_TXSTATE_EXTEND | AR_BT_TX_FRAME_EXTEND | 1151 AR_BT_QUIET | AR_BT_RX_CLEAR_POLARITY); 1152 AR_WRITE(sc, AR_BT_COEX_WEIGHT, 1153 SM(AR_BTCOEX_BT_WGHT, AR_STOMP_LOW_BT_WGHT) | 1154 SM(AR_BTCOEX_WL_WGHT, AR_STOMP_LOW_WL_WGHT)); 1155 AR_WRITE(sc, AR_BT_COEX_MODE2, 1156 SM(AR_BT_BCN_MISS_THRESH, 50) | 1157 AR_BT_HOLD_RX_CLEAR | AR_BT_DISABLE_BT_ANT); 1158 1159 AR_SETBITS(sc, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE); 1160 AR_CLRBITS(sc, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX); 1161 AR_WRITE_BARRIER(sc); 1162 1163 ops->gpio_config_output(sc, AR_GPIO_WLANACTIVE_PIN, 1164 AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL); 1165 1166 } else { /* 2-wire. */ 1167 ops->gpio_config_output(sc, AR_GPIO_WLANACTIVE_PIN, 1168 AR_GPIO_OUTPUT_MUX_AS_TX_FRAME); 1169 } 1170 reg = AR_READ(sc, AR_GPIO_PDPU); 1171 reg &= ~(0x3 << (AR_GPIO_WLANACTIVE_PIN * 2)); 1172 reg |= 0x2 << (AR_GPIO_WLANACTIVE_PIN * 2); 1173 AR_WRITE(sc, AR_GPIO_PDPU, reg); 1174 AR_WRITE_BARRIER(sc); 1175 1176 /* Disable PCIe Active State Power Management (ASPM). */ 1177 if (sc->sc_disable_aspm != NULL) 1178 sc->sc_disable_aspm(sc); 1179 1180 /* XXX Start periodic timer. */ 1181 } 1182 1183 void 1184 athn_btcoex_disable(struct athn_softc *sc) 1185 { 1186 struct athn_ops *ops = &sc->ops; 1187 1188 ops->gpio_write(sc, AR_GPIO_WLANACTIVE_PIN, 0); 1189 1190 ops->gpio_config_output(sc, AR_GPIO_WLANACTIVE_PIN, 1191 AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 1192 1193 if (sc->flags & ATHN_FLAG_BTCOEX3WIRE) { 1194 AR_WRITE(sc, AR_BT_COEX_MODE, 1195 SM(AR_BT_MODE, AR_BT_MODE_DISABLED) | AR_BT_QUIET); 1196 AR_WRITE(sc, AR_BT_COEX_WEIGHT, 0); 1197 AR_WRITE(sc, AR_BT_COEX_MODE2, 0); 1198 /* XXX Stop periodic timer. */ 1199 } 1200 AR_WRITE_BARRIER(sc); 1201 /* XXX Restore ASPM setting? */ 1202 } 1203 #endif 1204 1205 void 1206 athn_iter_func(void *arg, struct ieee80211_node *ni) 1207 { 1208 struct athn_softc *sc = arg; 1209 struct athn_node *an = (struct athn_node *)ni; 1210 1211 ieee80211_amrr_choose(&sc->amrr, ni, &an->amn); 1212 } 1213 1214 void 1215 athn_calib_to(void *arg) 1216 { 1217 extern int ticks; 1218 struct athn_softc *sc = arg; 1219 struct athn_ops *ops = &sc->ops; 1220 struct ieee80211com *ic = &sc->sc_ic; 1221 int s; 1222 1223 s = splnet(); 1224 1225 /* Do periodic (every 4 minutes) PA calibration. */ 1226 if (AR_SREV_9285_11_OR_LATER(sc) && 1227 !AR_SREV_9380_10_OR_LATER(sc) && 1228 ticks >= sc->pa_calib_ticks + 240 * hz) { 1229 sc->pa_calib_ticks = ticks; 1230 if (AR_SREV_9271(sc)) 1231 ar9271_pa_calib(sc); 1232 else 1233 ar9285_pa_calib(sc); 1234 } 1235 1236 /* Do periodic (every 30 seconds) temperature compensation. */ 1237 if ((sc->flags & ATHN_FLAG_OLPC) && 1238 ticks >= sc->olpc_ticks + 30 * hz) { 1239 sc->olpc_ticks = ticks; 1240 ops->olpc_temp_compensation(sc); 1241 } 1242 1243 #ifdef notyet 1244 /* XXX ANI. */ 1245 athn_ani_monitor(sc); 1246 1247 ops->next_calib(sc); 1248 #endif 1249 if (ic->ic_fixed_rate == -1) { 1250 if (ic->ic_opmode == IEEE80211_M_STA) 1251 athn_iter_func(sc, ic->ic_bss); 1252 else 1253 ieee80211_iterate_nodes(ic, athn_iter_func, sc); 1254 } 1255 timeout_add_msec(&sc->calib_to, 500); 1256 splx(s); 1257 } 1258 1259 int 1260 athn_init_calib(struct athn_softc *sc, struct ieee80211_channel *c, 1261 struct ieee80211_channel *extc) 1262 { 1263 struct athn_ops *ops = &sc->ops; 1264 int error; 1265 1266 if (AR_SREV_9380_10_OR_LATER(sc)) 1267 error = ar9003_init_calib(sc); 1268 else if (AR_SREV_9285_10_OR_LATER(sc)) 1269 error = ar9285_init_calib(sc, c, extc); 1270 else 1271 error = ar5416_init_calib(sc, c, extc); 1272 if (error != 0) 1273 return (error); 1274 1275 if (!AR_SREV_9380_10_OR_LATER(sc)) { 1276 /* Do PA calibration. */ 1277 if (AR_SREV_9285_11_OR_LATER(sc)) { 1278 extern int ticks; 1279 sc->pa_calib_ticks = ticks; 1280 if (AR_SREV_9271(sc)) 1281 ar9271_pa_calib(sc); 1282 else 1283 ar9285_pa_calib(sc); 1284 } 1285 /* Do noisefloor calibration. */ 1286 ops->noisefloor_calib(sc); 1287 } 1288 if (AR_SREV_9160_10_OR_LATER(sc)) { 1289 /* Support IQ calibration. */ 1290 sc->sup_calib_mask = ATHN_CAL_IQ; 1291 if (AR_SREV_9380_10_OR_LATER(sc)) { 1292 /* Support temperature compensation calibration. */ 1293 sc->sup_calib_mask |= ATHN_CAL_TEMP; 1294 } else if (IEEE80211_IS_CHAN_5GHZ(c) || extc != NULL) { 1295 /* 1296 * ADC gain calibration causes uplink throughput 1297 * drops in HT40 mode on AR9287. 1298 */ 1299 if (!AR_SREV_9287(sc)) { 1300 /* Support ADC gain calibration. */ 1301 sc->sup_calib_mask |= ATHN_CAL_ADC_GAIN; 1302 } 1303 /* Support ADC DC offset calibration. */ 1304 sc->sup_calib_mask |= ATHN_CAL_ADC_DC; 1305 } 1306 } 1307 return (0); 1308 } 1309 1310 /* 1311 * Adaptive noise immunity. 1312 */ 1313 int32_t 1314 athn_ani_get_rssi(struct athn_softc *sc) 1315 { 1316 return (0); /* XXX */ 1317 } 1318 1319 void 1320 athn_ani_ofdm_err_trigger(struct athn_softc *sc) 1321 { 1322 struct athn_ani *ani = &sc->ani; 1323 struct athn_ops *ops = &sc->ops; 1324 int32_t rssi; 1325 1326 /* First, raise noise immunity level, up to max. */ 1327 if (ani->noise_immunity_level < 4) { 1328 ani->noise_immunity_level++; 1329 ops->set_noise_immunity_level(sc, ani->noise_immunity_level); 1330 return; 1331 } 1332 1333 /* Then, raise our spur immunity level, up to max. */ 1334 if (ani->spur_immunity_level < 7) { 1335 ani->spur_immunity_level++; 1336 ops->set_spur_immunity_level(sc, ani->spur_immunity_level); 1337 return; 1338 } 1339 1340 #ifndef IEEE80211_STA_ONLY 1341 if (sc->sc_ic.ic_opmode == IEEE80211_M_HOSTAP) { 1342 if (ani->firstep_level < 2) { 1343 ani->firstep_level++; 1344 ops->set_firstep_level(sc, ani->firstep_level); 1345 } 1346 return; 1347 } 1348 #endif 1349 rssi = athn_ani_get_rssi(sc); 1350 if (rssi > ATHN_ANI_RSSI_THR_HIGH) { 1351 /* 1352 * Beacon RSSI is high, turn off OFDM weak signal detection 1353 * or raise first step level as last resort. 1354 */ 1355 if (ani->ofdm_weak_signal) { 1356 ani->ofdm_weak_signal = 0; 1357 ops->disable_ofdm_weak_signal(sc); 1358 ani->spur_immunity_level = 0; 1359 ops->set_spur_immunity_level(sc, 0); 1360 } else if (ani->firstep_level < 2) { 1361 ani->firstep_level++; 1362 ops->set_firstep_level(sc, ani->firstep_level); 1363 } 1364 } else if (rssi > ATHN_ANI_RSSI_THR_LOW) { 1365 /* 1366 * Beacon RSSI is in mid range, we need OFDM weak signal 1367 * detection but we can raise first step level. 1368 */ 1369 if (!ani->ofdm_weak_signal) { 1370 ani->ofdm_weak_signal = 1; 1371 ops->enable_ofdm_weak_signal(sc); 1372 } 1373 if (ani->firstep_level < 2) { 1374 ani->firstep_level++; 1375 ops->set_firstep_level(sc, ani->firstep_level); 1376 } 1377 } else if (sc->sc_ic.ic_curmode != IEEE80211_MODE_11A) { 1378 /* 1379 * Beacon RSSI is low, if in b/g mode, turn off OFDM weak 1380 * signal detection and zero first step level to maximize 1381 * CCK sensitivity. 1382 */ 1383 if (ani->ofdm_weak_signal) { 1384 ani->ofdm_weak_signal = 0; 1385 ops->disable_ofdm_weak_signal(sc); 1386 } 1387 if (ani->firstep_level > 0) { 1388 ani->firstep_level = 0; 1389 ops->set_firstep_level(sc, 0); 1390 } 1391 } 1392 } 1393 1394 void 1395 athn_ani_cck_err_trigger(struct athn_softc *sc) 1396 { 1397 struct athn_ani *ani = &sc->ani; 1398 struct athn_ops *ops = &sc->ops; 1399 int32_t rssi; 1400 1401 /* Raise noise immunity level, up to max. */ 1402 if (ani->noise_immunity_level < 4) { 1403 ani->noise_immunity_level++; 1404 ops->set_noise_immunity_level(sc, ani->noise_immunity_level); 1405 return; 1406 } 1407 1408 #ifndef IEEE80211_STA_ONLY 1409 if (sc->sc_ic.ic_opmode == IEEE80211_M_HOSTAP) { 1410 if (ani->firstep_level < 2) { 1411 ani->firstep_level++; 1412 ops->set_firstep_level(sc, ani->firstep_level); 1413 } 1414 return; 1415 } 1416 #endif 1417 rssi = athn_ani_get_rssi(sc); 1418 if (rssi > ATHN_ANI_RSSI_THR_LOW) { 1419 /* 1420 * Beacon RSSI is in mid or high range, raise first step 1421 * level. 1422 */ 1423 if (ani->firstep_level < 2) { 1424 ani->firstep_level++; 1425 ops->set_firstep_level(sc, ani->firstep_level); 1426 } 1427 } else if (sc->sc_ic.ic_curmode != IEEE80211_MODE_11A) { 1428 /* 1429 * Beacon RSSI is low, zero first step level to maximize 1430 * CCK sensitivity. 1431 */ 1432 if (ani->firstep_level > 0) { 1433 ani->firstep_level = 0; 1434 ops->set_firstep_level(sc, 0); 1435 } 1436 } 1437 } 1438 1439 void 1440 athn_ani_lower_immunity(struct athn_softc *sc) 1441 { 1442 struct athn_ani *ani = &sc->ani; 1443 struct athn_ops *ops = &sc->ops; 1444 int32_t rssi; 1445 1446 #ifndef IEEE80211_STA_ONLY 1447 if (sc->sc_ic.ic_opmode == IEEE80211_M_HOSTAP) { 1448 if (ani->firstep_level > 0) { 1449 ani->firstep_level--; 1450 ops->set_firstep_level(sc, ani->firstep_level); 1451 } 1452 return; 1453 } 1454 #endif 1455 rssi = athn_ani_get_rssi(sc); 1456 if (rssi > ATHN_ANI_RSSI_THR_HIGH) { 1457 /* 1458 * Beacon RSSI is high, leave OFDM weak signal detection 1459 * off or it may oscillate. 1460 */ 1461 } else if (rssi > ATHN_ANI_RSSI_THR_LOW) { 1462 /* 1463 * Beacon RSSI is in mid range, turn on OFDM weak signal 1464 * detection or lower first step level. 1465 */ 1466 if (!ani->ofdm_weak_signal) { 1467 ani->ofdm_weak_signal = 1; 1468 ops->enable_ofdm_weak_signal(sc); 1469 return; 1470 } 1471 if (ani->firstep_level > 0) { 1472 ani->firstep_level--; 1473 ops->set_firstep_level(sc, ani->firstep_level); 1474 return; 1475 } 1476 } else { 1477 /* Beacon RSSI is low, lower first step level. */ 1478 if (ani->firstep_level > 0) { 1479 ani->firstep_level--; 1480 ops->set_firstep_level(sc, ani->firstep_level); 1481 return; 1482 } 1483 } 1484 /* 1485 * Lower spur immunity level down to zero, or if all else fails, 1486 * lower noise immunity level down to zero. 1487 */ 1488 if (ani->spur_immunity_level > 0) { 1489 ani->spur_immunity_level--; 1490 ops->set_spur_immunity_level(sc, ani->spur_immunity_level); 1491 } else if (ani->noise_immunity_level > 0) { 1492 ani->noise_immunity_level--; 1493 ops->set_noise_immunity_level(sc, ani->noise_immunity_level); 1494 } 1495 } 1496 1497 void 1498 athn_ani_restart(struct athn_softc *sc) 1499 { 1500 struct athn_ani *ani = &sc->ani; 1501 1502 AR_WRITE(sc, AR_PHY_ERR_1, 0); 1503 AR_WRITE(sc, AR_PHY_ERR_2, 0); 1504 AR_WRITE(sc, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); 1505 AR_WRITE(sc, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); 1506 AR_WRITE_BARRIER(sc); 1507 1508 ani->listen_time = 0; 1509 ani->ofdm_phy_err_count = 0; 1510 ani->cck_phy_err_count = 0; 1511 } 1512 1513 void 1514 athn_ani_monitor(struct athn_softc *sc) 1515 { 1516 struct athn_ani *ani = &sc->ani; 1517 uint32_t cyccnt, txfcnt, rxfcnt, phy1, phy2; 1518 int32_t cycdelta, txfdelta, rxfdelta; 1519 int32_t listen_time; 1520 1521 txfcnt = AR_READ(sc, AR_TFCNT); /* Tx frame count. */ 1522 rxfcnt = AR_READ(sc, AR_RFCNT); /* Rx frame count. */ 1523 cyccnt = AR_READ(sc, AR_CCCNT); /* Cycle count. */ 1524 1525 if (ani->cyccnt != 0 && ani->cyccnt <= cyccnt) { 1526 cycdelta = cyccnt - ani->cyccnt; 1527 txfdelta = txfcnt - ani->txfcnt; 1528 rxfdelta = rxfcnt - ani->rxfcnt; 1529 1530 listen_time = (cycdelta - txfdelta - rxfdelta) / 1531 (athn_clock_rate(sc) * 1000); 1532 } else 1533 listen_time = 0; 1534 1535 ani->cyccnt = cyccnt; 1536 ani->txfcnt = txfcnt; 1537 ani->rxfcnt = rxfcnt; 1538 1539 if (listen_time < 0) { 1540 athn_ani_restart(sc); 1541 return; 1542 } 1543 ani->listen_time += listen_time; 1544 1545 phy1 = AR_READ(sc, AR_PHY_ERR_1); 1546 phy2 = AR_READ(sc, AR_PHY_ERR_2); 1547 1548 if (phy1 < ani->ofdm_phy_err_base) { 1549 AR_WRITE(sc, AR_PHY_ERR_1, ani->ofdm_phy_err_base); 1550 AR_WRITE(sc, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); 1551 } 1552 if (phy2 < ani->cck_phy_err_base) { 1553 AR_WRITE(sc, AR_PHY_ERR_2, ani->cck_phy_err_base); 1554 AR_WRITE(sc, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); 1555 } 1556 if (phy1 < ani->ofdm_phy_err_base || phy2 < ani->cck_phy_err_base) { 1557 AR_WRITE_BARRIER(sc); 1558 return; 1559 } 1560 ani->ofdm_phy_err_count = phy1 - ani->ofdm_phy_err_base; 1561 ani->cck_phy_err_count = phy2 - ani->cck_phy_err_base; 1562 1563 if (ani->listen_time > 5 * ATHN_ANI_PERIOD) { 1564 /* Check to see if we need to lower immunity. */ 1565 if (ani->ofdm_phy_err_count <= 1566 ani->listen_time * ani->ofdm_trig_low / 1000 && 1567 ani->cck_phy_err_count <= 1568 ani->listen_time * ani->cck_trig_low / 1000) 1569 athn_ani_lower_immunity(sc); 1570 athn_ani_restart(sc); 1571 1572 } else if (ani->listen_time > ATHN_ANI_PERIOD) { 1573 /* Check to see if we need to raise immunity. */ 1574 if (ani->ofdm_phy_err_count > 1575 ani->listen_time * ani->ofdm_trig_high / 1000) { 1576 athn_ani_ofdm_err_trigger(sc); 1577 athn_ani_restart(sc); 1578 } else if (ani->cck_phy_err_count > 1579 ani->listen_time * ani->cck_trig_high / 1000) { 1580 athn_ani_cck_err_trigger(sc); 1581 athn_ani_restart(sc); 1582 } 1583 } 1584 } 1585 1586 uint8_t 1587 athn_chan2fbin(struct ieee80211_channel *c) 1588 { 1589 if (IEEE80211_IS_CHAN_2GHZ(c)) 1590 return (c->ic_freq - 2300); 1591 else 1592 return ((c->ic_freq - 4800) / 5); 1593 } 1594 1595 int 1596 athn_interpolate(int x, int x1, int y1, int x2, int y2) 1597 { 1598 if (x1 == x2) /* Prevents division by zero. */ 1599 return (y1); 1600 /* Linear interpolation. */ 1601 return (y1 + ((x - x1) * (y2 - y1)) / (x2 - x1)); 1602 } 1603 1604 void 1605 athn_get_pier_ival(uint8_t fbin, const uint8_t *pierfreq, int npiers, 1606 int *lo, int *hi) 1607 { 1608 int i; 1609 1610 for (i = 0; i < npiers; i++) 1611 if (pierfreq[i] == AR_BCHAN_UNUSED || 1612 pierfreq[i] > fbin) 1613 break; 1614 *hi = i; 1615 *lo = *hi - 1; 1616 if (*lo == -1) 1617 *lo = *hi; 1618 else if (*hi == npiers || pierfreq[*hi] == AR_BCHAN_UNUSED) 1619 *hi = *lo; 1620 } 1621 1622 void 1623 athn_init_dma(struct athn_softc *sc) 1624 { 1625 uint32_t reg; 1626 1627 if (!AR_SREV_9380_10_OR_LATER(sc)) { 1628 /* Set AHB not to do cacheline prefetches. */ 1629 AR_SETBITS(sc, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN); 1630 } 1631 reg = AR_READ(sc, AR_TXCFG); 1632 /* Let MAC DMA reads be in 128-byte chunks. */ 1633 reg = RW(reg, AR_TXCFG_DMASZ, AR_DMASZ_128B); 1634 1635 /* Set initial Tx trigger level. */ 1636 if (AR_SREV_9285(sc) || AR_SREV_9271(sc)) 1637 reg = RW(reg, AR_TXCFG_FTRIG, AR_TXCFG_FTRIG_256B); 1638 else if (!AR_SREV_9380_10_OR_LATER(sc)) 1639 reg = RW(reg, AR_TXCFG_FTRIG, AR_TXCFG_FTRIG_512B); 1640 AR_WRITE(sc, AR_TXCFG, reg); 1641 1642 /* Let MAC DMA writes be in 128-byte chunks. */ 1643 reg = AR_READ(sc, AR_RXCFG); 1644 reg = RW(reg, AR_RXCFG_DMASZ, AR_DMASZ_128B); 1645 AR_WRITE(sc, AR_RXCFG, reg); 1646 1647 /* Setup Rx FIFO threshold to hold off Tx activities. */ 1648 AR_WRITE(sc, AR_RXFIFO_CFG, 512); 1649 1650 /* Reduce the number of entries in PCU TXBUF to avoid wrap around. */ 1651 if (AR_SREV_9285(sc)) { 1652 AR_WRITE(sc, AR_PCU_TXBUF_CTRL, 1653 AR9285_PCU_TXBUF_CTRL_USABLE_SIZE); 1654 } else if (!AR_SREV_9271(sc)) { 1655 AR_WRITE(sc, AR_PCU_TXBUF_CTRL, 1656 AR_PCU_TXBUF_CTRL_USABLE_SIZE); 1657 } 1658 AR_WRITE_BARRIER(sc); 1659 1660 /* Reset Tx status ring. */ 1661 if (AR_SREV_9380_10_OR_LATER(sc)) 1662 ar9003_reset_txsring(sc); 1663 } 1664 1665 void 1666 athn_inc_tx_trigger_level(struct athn_softc *sc) 1667 { 1668 uint32_t reg, ftrig; 1669 1670 reg = AR_READ(sc, AR_TXCFG); 1671 ftrig = MS(reg, AR_TXCFG_FTRIG); 1672 /* 1673 * NB: The AR9285 and all single-stream parts have an issue that 1674 * limits the size of the PCU Tx FIFO to 2KB instead of 4KB. 1675 */ 1676 if (ftrig == ((AR_SREV_9285(sc) || AR_SREV_9271(sc)) ? 0x1f : 0x3f)) 1677 return; /* Already at max. */ 1678 reg = RW(reg, AR_TXCFG_FTRIG, ftrig + 1); 1679 AR_WRITE(sc, AR_TXCFG, reg); 1680 AR_WRITE_BARRIER(sc); 1681 } 1682 1683 int 1684 athn_stop_rx_dma(struct athn_softc *sc) 1685 { 1686 int ntries; 1687 1688 AR_WRITE(sc, AR_CR, AR_CR_RXD); 1689 /* Wait for Rx enable bit to go low. */ 1690 for (ntries = 0; ntries < 100; ntries++) { 1691 if (!(AR_READ(sc, AR_CR) & AR_CR_RXE)) 1692 return (0); 1693 DELAY(100); 1694 } 1695 DPRINTF(("Rx DMA failed to stop\n")); 1696 return (ETIMEDOUT); 1697 } 1698 1699 int 1700 athn_rx_abort(struct athn_softc *sc) 1701 { 1702 int ntries; 1703 1704 AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 1705 for (ntries = 0; ntries < 1000; ntries++) { 1706 if (MS(AR_READ(sc, AR_OBS_BUS_1), AR_OBS_BUS_1_RX_STATE) == 0) 1707 return (0); 1708 DELAY(10); 1709 } 1710 DPRINTF(("Rx failed to go idle in 10ms\n")); 1711 AR_CLRBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 1712 AR_WRITE_BARRIER(sc); 1713 return (ETIMEDOUT); 1714 } 1715 1716 void 1717 athn_tx_reclaim(struct athn_softc *sc, int qid) 1718 { 1719 struct athn_txq *txq = &sc->txq[qid]; 1720 struct athn_tx_buf *bf; 1721 1722 /* Reclaim all buffers queued in the specified Tx queue. */ 1723 /* NB: Tx DMA must be stopped. */ 1724 while ((bf = SIMPLEQ_FIRST(&txq->head)) != NULL) { 1725 SIMPLEQ_REMOVE_HEAD(&txq->head, bf_list); 1726 1727 bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, 1728 bf->bf_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1729 bus_dmamap_unload(sc->sc_dmat, bf->bf_map); 1730 m_freem(bf->bf_m); 1731 bf->bf_m = NULL; 1732 bf->bf_ni = NULL; /* Nodes already freed! */ 1733 1734 /* Link Tx buffer back to global free list. */ 1735 SIMPLEQ_INSERT_TAIL(&sc->txbufs, bf, bf_list); 1736 } 1737 } 1738 1739 int 1740 athn_tx_pending(struct athn_softc *sc, int qid) 1741 { 1742 return (MS(AR_READ(sc, AR_QSTS(qid)), AR_Q_STS_PEND_FR_CNT) != 0 || 1743 (AR_READ(sc, AR_Q_TXE) & (1 << qid)) != 0); 1744 } 1745 1746 void 1747 athn_stop_tx_dma(struct athn_softc *sc, int qid) 1748 { 1749 uint32_t tsflo; 1750 int ntries, i; 1751 1752 AR_WRITE(sc, AR_Q_TXD, 1 << qid); 1753 for (ntries = 0; ntries < 40; ntries++) { 1754 if (!athn_tx_pending(sc, qid)) 1755 break; 1756 DELAY(100); 1757 } 1758 if (ntries == 40) { 1759 for (i = 0; i < 2; i++) { 1760 tsflo = AR_READ(sc, AR_TSF_L32) / 1024; 1761 AR_WRITE(sc, AR_QUIET2, 1762 SM(AR_QUIET2_QUIET_DUR, 10)); 1763 AR_WRITE(sc, AR_QUIET_PERIOD, 100); 1764 AR_WRITE(sc, AR_NEXT_QUIET_TIMER, tsflo); 1765 AR_SETBITS(sc, AR_TIMER_MODE, AR_QUIET_TIMER_EN); 1766 if (AR_READ(sc, AR_TSF_L32) / 1024 == tsflo) 1767 break; 1768 } 1769 AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); 1770 AR_WRITE_BARRIER(sc); 1771 DELAY(200); 1772 AR_CLRBITS(sc, AR_TIMER_MODE, AR_QUIET_TIMER_EN); 1773 AR_WRITE_BARRIER(sc); 1774 1775 for (ntries = 0; ntries < 40; ntries++) { 1776 if (!athn_tx_pending(sc, qid)) 1777 break; 1778 DELAY(100); 1779 } 1780 1781 AR_CLRBITS(sc, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); 1782 } 1783 AR_WRITE(sc, AR_Q_TXD, 0); 1784 AR_WRITE_BARRIER(sc); 1785 } 1786 1787 int 1788 athn_txtime(struct athn_softc *sc, int len, int ridx, u_int flags) 1789 { 1790 #define divround(a, b) (((a) + (b) - 1) / (b)) 1791 int txtime; 1792 1793 /* XXX HT. */ 1794 if (athn_rates[ridx].phy == IEEE80211_T_OFDM) { 1795 txtime = divround(8 + 4 * len + 3, athn_rates[ridx].rate); 1796 /* SIFS is 10us for 11g but Signal Extension adds 6us. */ 1797 txtime = 16 + 4 + 4 * txtime + 16; 1798 } else { 1799 txtime = divround(16 * len, athn_rates[ridx].rate); 1800 if (ridx != ATHN_RIDX_CCK1 && (flags & IEEE80211_F_SHPREAMBLE)) 1801 txtime += 72 + 24; 1802 else 1803 txtime += 144 + 48; 1804 txtime += 10; /* 10us SIFS. */ 1805 } 1806 return (txtime); 1807 #undef divround 1808 } 1809 1810 void 1811 athn_init_tx_queues(struct athn_softc *sc) 1812 { 1813 int qid; 1814 1815 for (qid = 0; qid < ATHN_QID_COUNT; qid++) { 1816 SIMPLEQ_INIT(&sc->txq[qid].head); 1817 sc->txq[qid].lastds = NULL; 1818 sc->txq[qid].wait = NULL; 1819 sc->txq[qid].queued = 0; 1820 1821 AR_WRITE(sc, AR_DRETRY_LIMIT(qid), 1822 SM(AR_D_RETRY_LIMIT_STA_SH, 32) | 1823 SM(AR_D_RETRY_LIMIT_STA_LG, 32) | 1824 SM(AR_D_RETRY_LIMIT_FR_SH, 10)); 1825 AR_WRITE(sc, AR_QMISC(qid), 1826 AR_Q_MISC_DCU_EARLY_TERM_REQ); 1827 AR_WRITE(sc, AR_DMISC(qid), 1828 SM(AR_D_MISC_BKOFF_THRESH, 2) | 1829 AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN); 1830 } 1831 1832 /* Init beacon queue. */ 1833 AR_SETBITS(sc, AR_QMISC(ATHN_QID_BEACON), 1834 AR_Q_MISC_FSP_DBA_GATED | AR_Q_MISC_BEACON_USE | 1835 AR_Q_MISC_CBR_INCR_DIS1); 1836 AR_SETBITS(sc, AR_DMISC(ATHN_QID_BEACON), 1837 SM(AR_D_MISC_ARB_LOCKOUT_CNTRL, 1838 AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL) | 1839 AR_D_MISC_BEACON_USE | 1840 AR_D_MISC_POST_FR_BKOFF_DIS); 1841 AR_WRITE(sc, AR_DLCL_IFS(ATHN_QID_BEACON), 1842 SM(AR_D_LCL_IFS_CWMIN, 0) | 1843 SM(AR_D_LCL_IFS_CWMAX, 0) | 1844 SM(AR_D_LCL_IFS_AIFS, 1)); 1845 1846 /* Init CAB (Content After Beacon) queue. */ 1847 AR_SETBITS(sc, AR_QMISC(ATHN_QID_CAB), 1848 AR_Q_MISC_FSP_DBA_GATED | AR_Q_MISC_CBR_INCR_DIS1 | 1849 AR_Q_MISC_CBR_INCR_DIS0); 1850 AR_SETBITS(sc, AR_DMISC(ATHN_QID_CAB), 1851 SM(AR_D_MISC_ARB_LOCKOUT_CNTRL, 1852 AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL)); 1853 1854 /* Init PS-Poll queue. */ 1855 AR_SETBITS(sc, AR_QMISC(ATHN_QID_PSPOLL), 1856 AR_Q_MISC_CBR_INCR_DIS1); 1857 1858 /* Init UAPSD queue. */ 1859 AR_SETBITS(sc, AR_DMISC(ATHN_QID_UAPSD), 1860 AR_D_MISC_POST_FR_BKOFF_DIS); 1861 1862 if (AR_SREV_9380_10_OR_LATER(sc)) { 1863 /* Enable MAC descriptor CRC check. */ 1864 AR_WRITE(sc, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN); 1865 } 1866 /* Enable DESC interrupts for all Tx queues. */ 1867 AR_WRITE(sc, AR_IMR_S0, 0x00ff0000); 1868 /* Enable EOL interrupts for all Tx queues except UAPSD. */ 1869 AR_WRITE(sc, AR_IMR_S1, 0x00df0000); 1870 AR_WRITE_BARRIER(sc); 1871 } 1872 1873 void 1874 athn_set_sta_timers(struct athn_softc *sc) 1875 { 1876 struct ieee80211com *ic = &sc->sc_ic; 1877 uint32_t tsfhi, tsflo, tsftu, reg; 1878 uint32_t intval, next_tbtt, next_dtim; 1879 int dtim_period, dtim_count, rem_dtim_count; 1880 1881 tsfhi = AR_READ(sc, AR_TSF_U32); 1882 tsflo = AR_READ(sc, AR_TSF_L32); 1883 tsftu = AR_TSF_TO_TU(tsfhi, tsflo) + AR_FUDGE; 1884 1885 /* Beacon interval in TU. */ 1886 intval = ic->ic_bss->ni_intval; 1887 1888 next_tbtt = roundup(tsftu, intval); 1889 #ifdef notyet 1890 dtim_period = ic->ic_dtim_period; 1891 if (dtim_period <= 0) 1892 #endif 1893 dtim_period = 1; /* Assume all TIMs are DTIMs. */ 1894 1895 #ifdef notyet 1896 dtim_count = ic->ic_dtim_count; 1897 if (dtim_count >= dtim_period) /* Should not happen. */ 1898 #endif 1899 dtim_count = 0; /* Assume last TIM was a DTIM. */ 1900 1901 /* Compute number of remaining TIMs until next DTIM. */ 1902 rem_dtim_count = 0; /* XXX */ 1903 next_dtim = next_tbtt + rem_dtim_count * intval; 1904 1905 AR_WRITE(sc, AR_NEXT_TBTT_TIMER, next_tbtt * IEEE80211_DUR_TU); 1906 AR_WRITE(sc, AR_BEACON_PERIOD, intval * IEEE80211_DUR_TU); 1907 AR_WRITE(sc, AR_DMA_BEACON_PERIOD, intval * IEEE80211_DUR_TU); 1908 1909 /* 1910 * Set the number of consecutive beacons to miss before raising 1911 * a BMISS interrupt to 10. 1912 */ 1913 reg = AR_READ(sc, AR_RSSI_THR); 1914 reg = RW(reg, AR_RSSI_THR_BM_THR, 10); 1915 AR_WRITE(sc, AR_RSSI_THR, reg); 1916 1917 AR_WRITE(sc, AR_NEXT_DTIM, 1918 (next_dtim - AR_SLEEP_SLOP) * IEEE80211_DUR_TU); 1919 AR_WRITE(sc, AR_NEXT_TIM, 1920 (next_tbtt - AR_SLEEP_SLOP) * IEEE80211_DUR_TU); 1921 1922 /* CAB timeout is in 1/8 TU. */ 1923 AR_WRITE(sc, AR_SLEEP1, 1924 SM(AR_SLEEP1_CAB_TIMEOUT, AR_CAB_TIMEOUT_VAL * 8) | 1925 AR_SLEEP1_ASSUME_DTIM); 1926 AR_WRITE(sc, AR_SLEEP2, 1927 SM(AR_SLEEP2_BEACON_TIMEOUT, AR_MIN_BEACON_TIMEOUT_VAL)); 1928 1929 AR_WRITE(sc, AR_TIM_PERIOD, intval * IEEE80211_DUR_TU); 1930 AR_WRITE(sc, AR_DTIM_PERIOD, dtim_period * intval * IEEE80211_DUR_TU); 1931 1932 AR_SETBITS(sc, AR_TIMER_MODE, 1933 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | AR_DTIM_TIMER_EN); 1934 1935 /* Set TSF out-of-range threshold (fixed at 16k us). */ 1936 AR_WRITE(sc, AR_TSFOOR_THRESHOLD, 0x4240); 1937 1938 AR_WRITE_BARRIER(sc); 1939 } 1940 1941 #ifndef IEEE80211_STA_ONLY 1942 void 1943 athn_set_hostap_timers(struct athn_softc *sc) 1944 { 1945 struct ieee80211com *ic = &sc->sc_ic; 1946 uint32_t intval, next_tbtt; 1947 1948 /* Beacon interval in TU. */ 1949 intval = ic->ic_bss->ni_intval; 1950 next_tbtt = intval; 1951 1952 AR_WRITE(sc, AR_NEXT_TBTT_TIMER, next_tbtt * IEEE80211_DUR_TU); 1953 AR_WRITE(sc, AR_NEXT_DMA_BEACON_ALERT, 1954 (next_tbtt - AR_BEACON_DMA_DELAY) * IEEE80211_DUR_TU); 1955 AR_WRITE(sc, AR_NEXT_CFP, 1956 (next_tbtt - AR_SWBA_DELAY) * IEEE80211_DUR_TU); 1957 1958 AR_WRITE(sc, AR_BEACON_PERIOD, intval * IEEE80211_DUR_TU); 1959 AR_WRITE(sc, AR_DMA_BEACON_PERIOD, intval * IEEE80211_DUR_TU); 1960 AR_WRITE(sc, AR_SWBA_PERIOD, intval * IEEE80211_DUR_TU); 1961 AR_WRITE(sc, AR_NDP_PERIOD, intval * IEEE80211_DUR_TU); 1962 1963 AR_WRITE(sc, AR_TIMER_MODE, 1964 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN); 1965 1966 AR_WRITE_BARRIER(sc); 1967 } 1968 #endif 1969 1970 void 1971 athn_set_opmode(struct athn_softc *sc) 1972 { 1973 uint32_t reg; 1974 1975 switch (sc->sc_ic.ic_opmode) { 1976 #ifndef IEEE80211_STA_ONLY 1977 case IEEE80211_M_HOSTAP: 1978 reg = AR_READ(sc, AR_STA_ID1); 1979 reg &= ~AR_STA_ID1_ADHOC; 1980 reg |= AR_STA_ID1_STA_AP | AR_STA_ID1_KSRCH_MODE; 1981 AR_WRITE(sc, AR_STA_ID1, reg); 1982 1983 AR_CLRBITS(sc, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 1984 break; 1985 case IEEE80211_M_IBSS: 1986 case IEEE80211_M_AHDEMO: 1987 reg = AR_READ(sc, AR_STA_ID1); 1988 reg &= ~AR_STA_ID1_STA_AP; 1989 reg |= AR_STA_ID1_ADHOC | AR_STA_ID1_KSRCH_MODE; 1990 AR_WRITE(sc, AR_STA_ID1, reg); 1991 1992 AR_SETBITS(sc, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 1993 break; 1994 #endif 1995 default: 1996 reg = AR_READ(sc, AR_STA_ID1); 1997 reg &= ~(AR_STA_ID1_ADHOC | AR_STA_ID1_STA_AP); 1998 reg |= AR_STA_ID1_KSRCH_MODE; 1999 AR_WRITE(sc, AR_STA_ID1, reg); 2000 break; 2001 } 2002 AR_WRITE_BARRIER(sc); 2003 } 2004 2005 void 2006 athn_set_bss(struct athn_softc *sc, struct ieee80211_node *ni) 2007 { 2008 const uint8_t *bssid = ni->ni_bssid; 2009 2010 AR_WRITE(sc, AR_BSS_ID0, LE_READ_4(&bssid[0])); 2011 AR_WRITE(sc, AR_BSS_ID1, LE_READ_2(&bssid[4]) | 2012 SM(AR_BSS_ID1_AID, IEEE80211_AID(ni->ni_associd))); 2013 AR_WRITE_BARRIER(sc); 2014 } 2015 2016 void 2017 athn_enable_interrupts(struct athn_softc *sc) 2018 { 2019 uint32_t mask2; 2020 2021 athn_disable_interrupts(sc); /* XXX */ 2022 2023 AR_WRITE(sc, AR_IMR, sc->imask); 2024 2025 mask2 = AR_READ(sc, AR_IMR_S2); 2026 mask2 &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC | 2027 AR_IMR_S2_CABEND | AR_IMR_S2_CABTO | AR_IMR_S2_TSFOOR); 2028 mask2 |= AR_IMR_S2_GTT | AR_IMR_S2_CST; 2029 AR_WRITE(sc, AR_IMR_S2, mask2); 2030 2031 AR_CLRBITS(sc, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); 2032 2033 AR_WRITE(sc, AR_IER, AR_IER_ENABLE); 2034 2035 AR_WRITE(sc, AR_INTR_ASYNC_ENABLE, AR_INTR_MAC_IRQ); 2036 AR_WRITE(sc, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ); 2037 2038 AR_WRITE(sc, AR_INTR_SYNC_ENABLE, sc->isync); 2039 AR_WRITE(sc, AR_INTR_SYNC_MASK, sc->isync); 2040 AR_WRITE_BARRIER(sc); 2041 } 2042 2043 void 2044 athn_disable_interrupts(struct athn_softc *sc) 2045 { 2046 AR_WRITE(sc, AR_IER, 0); 2047 (void)AR_READ(sc, AR_IER); 2048 2049 AR_WRITE(sc, AR_INTR_ASYNC_ENABLE, 0); 2050 (void)AR_READ(sc, AR_INTR_ASYNC_ENABLE); 2051 2052 AR_WRITE(sc, AR_INTR_SYNC_ENABLE, 0); 2053 (void)AR_READ(sc, AR_INTR_SYNC_ENABLE); 2054 2055 AR_WRITE(sc, AR_IMR, 0); 2056 2057 AR_CLRBITS(sc, AR_IMR_S2, AR_IMR_S2_TIM | AR_IMR_S2_DTIM | 2058 AR_IMR_S2_DTIMSYNC | AR_IMR_S2_CABEND | AR_IMR_S2_CABTO | 2059 AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST); 2060 2061 AR_CLRBITS(sc, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); 2062 AR_WRITE_BARRIER(sc); 2063 } 2064 2065 void 2066 athn_init_qos(struct athn_softc *sc) 2067 { 2068 /* Initialize QoS settings. */ 2069 AR_WRITE(sc, AR_MIC_QOS_CONTROL, 0x100aa); 2070 AR_WRITE(sc, AR_MIC_QOS_SELECT, 0x3210); 2071 AR_WRITE(sc, AR_QOS_NO_ACK, 2072 SM(AR_QOS_NO_ACK_TWO_BIT, 2) | 2073 SM(AR_QOS_NO_ACK_BIT_OFF, 5) | 2074 SM(AR_QOS_NO_ACK_BYTE_OFF, 0)); 2075 AR_WRITE(sc, AR_TXOP_X, AR_TXOP_X_VAL); 2076 /* Initialize TXOP for all TIDs. */ 2077 AR_WRITE(sc, AR_TXOP_0_3, 0xffffffff); 2078 AR_WRITE(sc, AR_TXOP_4_7, 0xffffffff); 2079 AR_WRITE(sc, AR_TXOP_8_11, 0xffffffff); 2080 AR_WRITE(sc, AR_TXOP_12_15, 0xffffffff); 2081 AR_WRITE_BARRIER(sc); 2082 } 2083 2084 int 2085 athn_hw_reset(struct athn_softc *sc, struct ieee80211_channel *c, 2086 struct ieee80211_channel *extc, int init) 2087 { 2088 struct ieee80211com *ic = &sc->sc_ic; 2089 struct athn_ops *ops = &sc->ops; 2090 uint32_t reg, def_ant, sta_id1, cfg_led, tsflo, tsfhi; 2091 int i, error; 2092 2093 /* XXX not if already awake */ 2094 if ((error = athn_set_power_awake(sc)) != 0) { 2095 printf("%s: could not wakeup chip\n", sc->sc_dev.dv_xname); 2096 return (error); 2097 } 2098 2099 /* Preserve the antenna on a channel switch. */ 2100 if ((def_ant = AR_READ(sc, AR_DEF_ANTENNA)) == 0) 2101 def_ant = 1; 2102 /* Preserve other registers. */ 2103 sta_id1 = AR_READ(sc, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; 2104 cfg_led = AR_READ(sc, AR_CFG_LED) & (AR_CFG_LED_ASSOC_CTL_M | 2105 AR_CFG_LED_MODE_SEL_M | AR_CFG_LED_BLINK_THRESH_SEL_M | 2106 AR_CFG_LED_BLINK_SLOW); 2107 2108 /* Mark PHY as inactive. */ 2109 ops->disable_phy(sc); 2110 2111 if (init && AR_SREV_9271(sc)) { 2112 AR_WRITE(sc, AR9271_RESET_POWER_DOWN_CONTROL, 2113 AR9271_RADIO_RF_RST); 2114 DELAY(50); 2115 } 2116 if (AR_SREV_9280(sc) && (sc->flags & ATHN_FLAG_OLPC)) { 2117 /* Save TSF before it gets cleared. */ 2118 tsfhi = AR_READ(sc, AR_TSF_U32); 2119 tsflo = AR_READ(sc, AR_TSF_L32); 2120 2121 /* NB: RTC reset clears TSF. */ 2122 error = athn_reset_power_on(sc); 2123 } else 2124 error = athn_reset(sc, 0); 2125 if (error != 0) { 2126 printf("%s: could not reset chip (error=%d)\n", 2127 sc->sc_dev.dv_xname, error); 2128 return (error); 2129 } 2130 2131 /* XXX not if already awake */ 2132 if ((error = athn_set_power_awake(sc)) != 0) { 2133 printf("%s: could not wakeup chip\n", sc->sc_dev.dv_xname); 2134 return (error); 2135 } 2136 2137 athn_init_pll(sc, c); 2138 ops->set_rf_mode(sc, c); 2139 2140 if (sc->flags & ATHN_FLAG_RFSILENT) { 2141 /* Check that the radio is not disabled by hardware switch. */ 2142 reg = ops->gpio_read(sc, sc->rfsilent_pin); 2143 if (sc->flags & ATHN_FLAG_RFSILENT_REVERSED) 2144 reg = !reg; 2145 if (!reg) { 2146 printf("%s: radio is disabled by hardware switch\n", 2147 sc->sc_dev.dv_xname); 2148 return (EPERM); 2149 } 2150 } 2151 if (init && AR_SREV_9271(sc)) { 2152 AR_WRITE(sc, AR9271_RESET_POWER_DOWN_CONTROL, 2153 AR9271_GATE_MAC_CTL); 2154 DELAY(50); 2155 } 2156 if (AR_SREV_9280(sc) && (sc->flags & ATHN_FLAG_OLPC)) { 2157 /* Restore TSF if it got cleared. */ 2158 AR_WRITE(sc, AR_TSF_L32, tsflo); 2159 AR_WRITE(sc, AR_TSF_U32, tsfhi); 2160 } 2161 2162 if (AR_SREV_9280_10_OR_LATER(sc)) 2163 AR_SETBITS(sc, sc->gpio_input_en_off, AR_GPIO_JTAG_DISABLE); 2164 2165 if (AR_SREV_9287_13_OR_LATER(sc) && !AR_SREV_9380_10_OR_LATER(sc)) 2166 ar9287_1_3_enable_async_fifo(sc); 2167 2168 /* Write init values to hardware. */ 2169 ops->hw_init(sc, c, extc); 2170 2171 /* 2172 * Only >=AR9280 2.0 parts are capable of encrypting unicast 2173 * management frames using CCMP. 2174 */ 2175 if (AR_SREV_9280_20_OR_LATER(sc)) { 2176 reg = AR_READ(sc, AR_AES_MUTE_MASK1); 2177 /* Do not mask the subtype field in management frames. */ 2178 reg = RW(reg, AR_AES_MUTE_MASK1_FC0_MGMT, 0xff); 2179 reg = RW(reg, AR_AES_MUTE_MASK1_FC1_MGMT, 2180 ~(IEEE80211_FC1_RETRY | IEEE80211_FC1_PWR_MGT | 2181 IEEE80211_FC1_MORE_DATA)); 2182 AR_WRITE(sc, AR_AES_MUTE_MASK1, reg); 2183 } else if (AR_SREV_9160_10_OR_LATER(sc)) { 2184 /* Disable hardware crypto for management frames. */ 2185 AR_CLRBITS(sc, AR_PCU_MISC_MODE2, 2186 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE); 2187 AR_SETBITS(sc, AR_PCU_MISC_MODE2, 2188 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT); 2189 } 2190 2191 if (ic->ic_curmode != IEEE80211_MODE_11B) 2192 ops->set_delta_slope(sc, c, extc); 2193 2194 ops->spur_mitigate(sc, c, extc); 2195 ops->init_from_rom(sc, c, extc); 2196 2197 /* XXX */ 2198 AR_WRITE(sc, AR_STA_ID0, LE_READ_4(&ic->ic_myaddr[0])); 2199 AR_WRITE(sc, AR_STA_ID1, LE_READ_2(&ic->ic_myaddr[4]) | 2200 sta_id1 | AR_STA_ID1_RTS_USE_DEF | AR_STA_ID1_CRPT_MIC_ENABLE); 2201 2202 athn_set_opmode(sc); 2203 2204 AR_WRITE(sc, AR_BSSMSKL, 0xffffffff); 2205 AR_WRITE(sc, AR_BSSMSKU, 0xffff); 2206 2207 /* Restore previous antenna. */ 2208 AR_WRITE(sc, AR_DEF_ANTENNA, def_ant); 2209 2210 AR_WRITE(sc, AR_BSS_ID0, 0); 2211 AR_WRITE(sc, AR_BSS_ID1, 0); 2212 2213 AR_WRITE(sc, AR_ISR, 0xffffffff); 2214 2215 AR_WRITE(sc, AR_RSSI_THR, SM(AR_RSSI_THR_BM_THR, 7)); 2216 2217 if ((error = ops->set_synth(sc, c, extc)) != 0) { 2218 printf("%s: could not set channel\n", sc->sc_dev.dv_xname); 2219 return (error); 2220 } 2221 sc->curchan = c; 2222 sc->curchanext = extc; 2223 2224 for (i = 0; i < AR_NUM_DCU; i++) 2225 AR_WRITE(sc, AR_DQCUMASK(i), 1 << i); 2226 2227 athn_init_tx_queues(sc); 2228 2229 /* Initialize interrupt mask. */ 2230 sc->imask = 2231 AR_IMR_TXDESC | AR_IMR_TXEOL | 2232 AR_IMR_RXERR | AR_IMR_RXEOL | AR_IMR_RXORN | 2233 AR_IMR_RXMINTR | AR_IMR_RXINTM | 2234 AR_IMR_GENTMR | AR_IMR_BCNMISC; 2235 if (AR_SREV_9380_10_OR_LATER(sc)) 2236 sc->imask |= AR_IMR_RXERR | AR_IMR_HP_RXOK; 2237 #ifndef IEEE80211_STA_ONLY 2238 if (0 && ic->ic_opmode == IEEE80211_M_HOSTAP) 2239 sc->imask |= AR_IMR_MIB; 2240 #endif 2241 AR_WRITE(sc, AR_IMR, sc->imask); 2242 AR_SETBITS(sc, AR_IMR_S2, AR_IMR_S2_GTT); 2243 AR_WRITE(sc, AR_INTR_SYNC_CAUSE, 0xffffffff); 2244 sc->isync = AR_INTR_SYNC_DEFAULT; 2245 if (sc->flags & ATHN_FLAG_RFSILENT) 2246 sc->isync |= AR_INTR_SYNC_GPIO_PIN(sc->rfsilent_pin); 2247 AR_WRITE(sc, AR_INTR_SYNC_ENABLE, sc->isync); 2248 AR_WRITE(sc, AR_INTR_SYNC_MASK, 0); 2249 if (AR_SREV_9380_10_OR_LATER(sc)) { 2250 AR_WRITE(sc, AR_INTR_PRIO_ASYNC_ENABLE, 0); 2251 AR_WRITE(sc, AR_INTR_PRIO_ASYNC_MASK, 0); 2252 AR_WRITE(sc, AR_INTR_PRIO_SYNC_ENABLE, 0); 2253 AR_WRITE(sc, AR_INTR_PRIO_SYNC_MASK, 0); 2254 } 2255 2256 athn_init_qos(sc); 2257 2258 AR_SETBITS(sc, AR_PCU_MISC, AR_PCU_MIC_NEW_LOC_ENA); 2259 2260 if (AR_SREV_9287_13_OR_LATER(sc) && !AR_SREV_9380_10_OR_LATER(sc)) 2261 ar9287_1_3_setup_async_fifo(sc); 2262 2263 /* Disable sequence number generation in hardware. */ 2264 AR_SETBITS(sc, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM); 2265 2266 athn_init_dma(sc); 2267 2268 /* Program observation bus to see MAC interrupts. */ 2269 AR_WRITE(sc, sc->obs_off, 8); 2270 2271 /* Setup Rx interrupt mitigation. */ 2272 AR_WRITE(sc, AR_RIMT, SM(AR_RIMT_FIRST, 2000) | SM(AR_RIMT_LAST, 500)); 2273 2274 ops->init_baseband(sc); 2275 2276 if ((error = athn_init_calib(sc, c, extc)) != 0) { 2277 printf("%s: could not initialize calibration\n", 2278 sc->sc_dev.dv_xname); 2279 return (error); 2280 } 2281 2282 ops->set_rxchains(sc); 2283 2284 AR_WRITE(sc, AR_CFG_LED, cfg_led | AR_CFG_SCLK_32KHZ); 2285 2286 if (sc->flags & ATHN_FLAG_USB) { 2287 if (AR_SREV_9271(sc)) 2288 AR_WRITE(sc, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); 2289 else 2290 AR_WRITE(sc, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 2291 } 2292 #if BYTE_ORDER == BIG_ENDIAN 2293 else { 2294 /* Default is LE, turn on swapping for BE. */ 2295 AR_WRITE(sc, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 2296 } 2297 #endif 2298 AR_WRITE_BARRIER(sc); 2299 2300 return (0); 2301 } 2302 2303 struct ieee80211_node * 2304 athn_node_alloc(struct ieee80211com *ic) 2305 { 2306 return (malloc(sizeof(struct athn_node), M_DEVBUF, M_NOWAIT | M_ZERO)); 2307 } 2308 2309 void 2310 athn_newassoc(struct ieee80211com *ic, struct ieee80211_node *ni, int isnew) 2311 { 2312 struct athn_softc *sc = ic->ic_softc; 2313 struct athn_node *an = (void *)ni; 2314 struct ieee80211_rateset *rs = &ni->ni_rates; 2315 uint8_t rate; 2316 int ridx, i, j; 2317 2318 ieee80211_amrr_node_init(&sc->amrr, &an->amn); 2319 /* Start at lowest available bit-rate, AMRR will raise. */ 2320 ni->ni_txrate = 0; 2321 2322 for (i = 0; i < rs->rs_nrates; i++) { 2323 rate = rs->rs_rates[i] & IEEE80211_RATE_VAL; 2324 2325 /* Map 802.11 rate to HW rate index. */ 2326 for (ridx = 0; ridx <= ATHN_RIDX_MAX; ridx++) 2327 if (athn_rates[ridx].rate == rate) 2328 break; 2329 an->ridx[i] = ridx; 2330 DPRINTFN(2, ("rate %d index %d\n", rate, ridx)); 2331 2332 /* Compute fallback rate for retries. */ 2333 an->fallback[i] = i; 2334 for (j = i - 1; j >= 0; j--) { 2335 if (athn_rates[an->ridx[j]].phy == 2336 athn_rates[an->ridx[i]].phy) { 2337 an->fallback[i] = j; 2338 break; 2339 } 2340 } 2341 DPRINTFN(2, ("%d fallbacks to %d\n", i, an->fallback[i])); 2342 } 2343 } 2344 2345 int 2346 athn_media_change(struct ifnet *ifp) 2347 { 2348 struct athn_softc *sc = ifp->if_softc; 2349 struct ieee80211com *ic = &sc->sc_ic; 2350 uint8_t rate, ridx; 2351 int error; 2352 2353 error = ieee80211_media_change(ifp); 2354 if (error != ENETRESET) 2355 return (error); 2356 2357 if (ic->ic_fixed_rate != -1) { 2358 rate = ic->ic_sup_rates[ic->ic_curmode]. 2359 rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL; 2360 /* Map 802.11 rate to HW rate index. */ 2361 for (ridx = 0; ridx <= ATHN_RIDX_MAX; ridx++) 2362 if (athn_rates[ridx].rate == rate) 2363 break; 2364 sc->fixed_ridx = ridx; 2365 } 2366 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2367 (IFF_UP | IFF_RUNNING)) { 2368 athn_stop(ifp, 0); 2369 error = athn_init(ifp); 2370 } 2371 return (error); 2372 } 2373 2374 void 2375 athn_next_scan(void *arg) 2376 { 2377 struct athn_softc *sc = arg; 2378 struct ieee80211com *ic = &sc->sc_ic; 2379 int s; 2380 2381 s = splnet(); 2382 if (ic->ic_state == IEEE80211_S_SCAN) 2383 ieee80211_next_scan(&ic->ic_if); 2384 splx(s); 2385 } 2386 2387 int 2388 athn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 2389 { 2390 struct ifnet *ifp = &ic->ic_if; 2391 struct athn_softc *sc = ifp->if_softc; 2392 uint32_t reg; 2393 int error; 2394 2395 timeout_del(&sc->calib_to); 2396 2397 switch (nstate) { 2398 case IEEE80211_S_INIT: 2399 athn_set_led(sc, 0); 2400 break; 2401 case IEEE80211_S_SCAN: 2402 /* Make the LED blink while scanning. */ 2403 athn_set_led(sc, !sc->led_state); 2404 error = athn_switch_chan(sc, ic->ic_bss->ni_chan, NULL); 2405 if (error != 0) 2406 return (error); 2407 timeout_add_msec(&sc->scan_to, 200); 2408 break; 2409 case IEEE80211_S_AUTH: 2410 athn_set_led(sc, 0); 2411 error = athn_switch_chan(sc, ic->ic_bss->ni_chan, NULL); 2412 if (error != 0) 2413 return (error); 2414 break; 2415 case IEEE80211_S_ASSOC: 2416 break; 2417 case IEEE80211_S_RUN: 2418 athn_set_led(sc, 1); 2419 2420 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2421 break; 2422 2423 /* Fake a join to initialize the Tx rate. */ 2424 athn_newassoc(ic, ic->ic_bss, 1); 2425 2426 athn_set_bss(sc, ic->ic_bss); 2427 athn_disable_interrupts(sc); 2428 #ifndef IEEE80211_STA_ONLY 2429 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 2430 athn_set_hostap_timers(sc); 2431 /* Enable sotfware beacon alert interrupts. */ 2432 sc->imask |= AR_IMR_SWBA; 2433 } else 2434 #endif 2435 { 2436 athn_set_sta_timers(sc); 2437 /* Enable beacon miss interrupts. */ 2438 sc->imask |= AR_IMR_BMISS; 2439 2440 /* Stop receiving beacons from other BSS. */ 2441 reg = AR_READ(sc, AR_RX_FILTER); 2442 reg = (reg & ~AR_RX_FILTER_BEACON) | 2443 AR_RX_FILTER_MYBEACON; 2444 AR_WRITE(sc, AR_RX_FILTER, reg); 2445 AR_WRITE_BARRIER(sc); 2446 } 2447 athn_enable_interrupts(sc); 2448 2449 if (sc->sup_calib_mask != 0) { 2450 memset(&sc->calib, 0, sizeof(sc->calib)); 2451 sc->cur_calib_mask = sc->sup_calib_mask; 2452 /* ops->do_calib(sc); */ 2453 } 2454 /* XXX Start ANI. */ 2455 2456 timeout_add_msec(&sc->calib_to, 500); 2457 break; 2458 } 2459 2460 return (sc->sc_newstate(ic, nstate, arg)); 2461 } 2462 2463 void 2464 athn_updateedca(struct ieee80211com *ic) 2465 { 2466 #define ATHN_EXP2(x) ((1 << (x)) - 1) /* CWmin = 2^ECWmin - 1 */ 2467 struct athn_softc *sc = ic->ic_softc; 2468 const struct ieee80211_edca_ac_params *ac; 2469 int aci, qid; 2470 2471 for (aci = 0; aci < EDCA_NUM_AC; aci++) { 2472 ac = &ic->ic_edca_ac[aci]; 2473 qid = athn_ac2qid[aci]; 2474 2475 AR_WRITE(sc, AR_DLCL_IFS(qid), 2476 SM(AR_D_LCL_IFS_CWMIN, ATHN_EXP2(ac->ac_ecwmin)) | 2477 SM(AR_D_LCL_IFS_CWMAX, ATHN_EXP2(ac->ac_ecwmax)) | 2478 SM(AR_D_LCL_IFS_AIFS, ac->ac_aifsn)); 2479 if (ac->ac_txoplimit != 0) { 2480 AR_WRITE(sc, AR_DCHNTIME(qid), 2481 SM(AR_D_CHNTIME_DUR, 2482 IEEE80211_TXOP_TO_US(ac->ac_txoplimit)) | 2483 AR_D_CHNTIME_EN); 2484 } else 2485 AR_WRITE(sc, AR_DCHNTIME(qid), 0); 2486 } 2487 AR_WRITE_BARRIER(sc); 2488 #undef ATHN_EXP2 2489 } 2490 2491 int 2492 athn_clock_rate(struct athn_softc *sc) 2493 { 2494 struct ieee80211com *ic = &sc->sc_ic; 2495 int clockrate; /* MHz. */ 2496 2497 if (ic->ic_curmode == IEEE80211_MODE_11A) { 2498 if (sc->flags & ATHN_FLAG_FAST_PLL_CLOCK) 2499 clockrate = AR_CLOCK_RATE_FAST_5GHZ_OFDM; 2500 else 2501 clockrate = AR_CLOCK_RATE_5GHZ_OFDM; 2502 } else if (ic->ic_curmode == IEEE80211_MODE_11B) { 2503 clockrate = AR_CLOCK_RATE_CCK; 2504 } else 2505 clockrate = AR_CLOCK_RATE_2GHZ_OFDM; 2506 #ifndef IEEE80211_NO_HT 2507 if (sc->curchanext != NULL) 2508 clockrate *= 2; 2509 #endif 2510 return (clockrate); 2511 } 2512 2513 void 2514 athn_updateslot(struct ieee80211com *ic) 2515 { 2516 struct athn_softc *sc = ic->ic_softc; 2517 int slot; 2518 2519 slot = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2520 AR_WRITE(sc, AR_D_GBL_IFS_SLOT, slot * athn_clock_rate(sc)); 2521 AR_WRITE_BARRIER(sc); 2522 } 2523 2524 void 2525 athn_start(struct ifnet *ifp) 2526 { 2527 struct athn_softc *sc = ifp->if_softc; 2528 struct ieee80211com *ic = &sc->sc_ic; 2529 struct ieee80211_node *ni; 2530 struct mbuf *m; 2531 2532 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2533 return; 2534 2535 for (;;) { 2536 if (SIMPLEQ_EMPTY(&sc->txbufs)) { 2537 ifp->if_flags |= IFF_OACTIVE; 2538 break; 2539 } 2540 /* Send pending management frames first. */ 2541 IF_DEQUEUE(&ic->ic_mgtq, m); 2542 if (m != NULL) { 2543 ni = (void *)m->m_pkthdr.rcvif; 2544 goto sendit; 2545 } 2546 if (ic->ic_state != IEEE80211_S_RUN) 2547 break; 2548 2549 /* Encapsulate and send data frames. */ 2550 IFQ_DEQUEUE(&ifp->if_snd, m); 2551 if (m == NULL) 2552 break; 2553 #if NBPFILTER > 0 2554 if (ifp->if_bpf != NULL) 2555 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); 2556 #endif 2557 if ((m = ieee80211_encap(ifp, m, &ni)) == NULL) 2558 continue; 2559 sendit: 2560 #if NBPFILTER > 0 2561 if (ic->ic_rawbpf != NULL) 2562 bpf_mtap(ic->ic_rawbpf, m, BPF_DIRECTION_OUT); 2563 #endif 2564 if (sc->ops.tx(sc, m, ni, 0) != 0) { 2565 ieee80211_release_node(ic, ni); 2566 ifp->if_oerrors++; 2567 continue; 2568 } 2569 2570 sc->sc_tx_timer = 5; 2571 ifp->if_timer = 1; 2572 } 2573 } 2574 2575 void 2576 athn_watchdog(struct ifnet *ifp) 2577 { 2578 struct athn_softc *sc = ifp->if_softc; 2579 2580 ifp->if_timer = 0; 2581 2582 if (sc->sc_tx_timer > 0) { 2583 if (--sc->sc_tx_timer == 0) { 2584 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 2585 athn_stop(ifp, 1); 2586 (void)athn_init(ifp); 2587 ifp->if_oerrors++; 2588 return; 2589 } 2590 ifp->if_timer = 1; 2591 } 2592 2593 ieee80211_watchdog(ifp); 2594 } 2595 2596 void 2597 athn_set_multi(struct athn_softc *sc) 2598 { 2599 struct arpcom *ac = &sc->sc_ic.ic_ac; 2600 struct ifnet *ifp = &ac->ac_if; 2601 struct ether_multi *enm; 2602 struct ether_multistep step; 2603 const uint8_t *addr; 2604 uint32_t val, lo, hi; 2605 uint8_t bit; 2606 2607 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 2608 lo = hi = 0xffffffff; 2609 goto done; 2610 } 2611 lo = hi = 0; 2612 ETHER_FIRST_MULTI(step, ac, enm); 2613 while (enm != NULL) { 2614 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) != 0) { 2615 ifp->if_flags |= IFF_ALLMULTI; 2616 lo = hi = 0xffffffff; 2617 goto done; 2618 } 2619 addr = enm->enm_addrlo; 2620 /* Calculate the XOR value of all eight 6-bit words. */ 2621 val = addr[0] | addr[1] << 8 | addr[2] << 16; 2622 bit = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 2623 val = addr[3] | addr[4] << 8 | addr[5] << 16; 2624 bit ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 2625 bit &= 0x3f; 2626 if (bit < 32) 2627 lo |= 1 << bit; 2628 else 2629 hi |= 1 << (bit - 32); 2630 ETHER_NEXT_MULTI(step, enm); 2631 } 2632 done: 2633 AR_WRITE(sc, AR_MCAST_FIL0, lo); 2634 AR_WRITE(sc, AR_MCAST_FIL1, hi); 2635 AR_WRITE_BARRIER(sc); 2636 } 2637 2638 int 2639 athn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2640 { 2641 struct athn_softc *sc = ifp->if_softc; 2642 struct ieee80211com *ic = &sc->sc_ic; 2643 struct ifaddr *ifa; 2644 struct ifreq *ifr; 2645 int s, error = 0; 2646 2647 s = splnet(); 2648 2649 switch (cmd) { 2650 case SIOCSIFADDR: 2651 ifa = (struct ifaddr *)data; 2652 ifp->if_flags |= IFF_UP; 2653 #ifdef INET 2654 if (ifa->ifa_addr->sa_family == AF_INET) 2655 arp_ifinit(&ic->ic_ac, ifa); 2656 #endif 2657 /* FALLTHROUGH */ 2658 case SIOCSIFFLAGS: 2659 if (ifp->if_flags & IFF_UP) { 2660 if ((ifp->if_flags & IFF_RUNNING) && 2661 ((ifp->if_flags ^ sc->sc_if_flags) & 2662 (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 2663 athn_set_multi(sc); 2664 } else if (!(ifp->if_flags & IFF_RUNNING)) 2665 error = athn_init(ifp); 2666 } else { 2667 if (ifp->if_flags & IFF_RUNNING) 2668 athn_stop(ifp, 1); 2669 } 2670 sc->sc_if_flags = ifp->if_flags; 2671 break; 2672 2673 case SIOCADDMULTI: 2674 case SIOCDELMULTI: 2675 ifr = (struct ifreq *)data; 2676 error = (cmd == SIOCADDMULTI) ? 2677 ether_addmulti(ifr, &ic->ic_ac) : 2678 ether_delmulti(ifr, &ic->ic_ac); 2679 if (error == ENETRESET) { 2680 athn_set_multi(sc); 2681 error = 0; 2682 } 2683 break; 2684 2685 case SIOCS80211CHANNEL: 2686 error = ieee80211_ioctl(ifp, cmd, data); 2687 if (error == ENETRESET && 2688 ic->ic_opmode == IEEE80211_M_MONITOR) { 2689 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2690 (IFF_UP | IFF_RUNNING)) 2691 athn_switch_chan(sc, ic->ic_ibss_chan, NULL); 2692 error = 0; 2693 } 2694 break; 2695 2696 default: 2697 error = ieee80211_ioctl(ifp, cmd, data); 2698 } 2699 2700 if (error == ENETRESET) { 2701 error = 0; 2702 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2703 (IFF_UP | IFF_RUNNING)) { 2704 athn_stop(ifp, 0); 2705 error = athn_init(ifp); 2706 } 2707 } 2708 2709 splx(s); 2710 return (error); 2711 } 2712 2713 int 2714 athn_init(struct ifnet *ifp) 2715 { 2716 struct athn_softc *sc = ifp->if_softc; 2717 struct athn_ops *ops = &sc->ops; 2718 struct ieee80211com *ic = &sc->sc_ic; 2719 struct ieee80211_channel *c, *extc; 2720 int i, error; 2721 2722 c = ic->ic_bss->ni_chan = ic->ic_ibss_chan; 2723 extc = NULL; 2724 2725 /* In case a new MAC address has been configured. */ 2726 IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(ifp->if_sadl)); 2727 2728 /* For CardBus, power on the socket. */ 2729 if (sc->sc_enable != NULL) { 2730 if ((error = sc->sc_enable(sc)) != 0) { 2731 printf("%s: could not enable device\n", 2732 sc->sc_dev.dv_xname); 2733 goto fail; 2734 } 2735 if ((error = athn_reset_power_on(sc)) != 0) { 2736 printf("%s: could not power on device\n", 2737 sc->sc_dev.dv_xname); 2738 goto fail; 2739 } 2740 } 2741 if (!(sc->flags & ATHN_FLAG_PCIE)) 2742 athn_config_nonpcie(sc); 2743 else 2744 athn_config_pcie(sc); 2745 2746 /* Reset HW key cache entries. */ 2747 for (i = 0; i < sc->kc_entries; i++) 2748 athn_reset_key(sc, i); 2749 2750 ops->enable_antenna_diversity(sc); 2751 2752 #ifdef ATHN_BT_COEXISTENCE 2753 /* Configure bluetooth coexistence for combo chips. */ 2754 if (sc->flags & ATHN_FLAG_BTCOEX) 2755 athn_btcoex_init(sc); 2756 #endif 2757 2758 /* Configure LED. */ 2759 athn_led_init(sc); 2760 2761 /* Configure hardware radio switch. */ 2762 if (sc->flags & ATHN_FLAG_RFSILENT) 2763 ops->rfsilent_init(sc); 2764 2765 if ((error = athn_hw_reset(sc, c, extc, 1)) != 0) { 2766 printf("%s: unable to reset hardware; reset status %d\n", 2767 sc->sc_dev.dv_xname, error); 2768 goto fail; 2769 } 2770 2771 /* Enable Rx. */ 2772 athn_rx_start(sc); 2773 2774 /* Enable interrupts. */ 2775 athn_enable_interrupts(sc); 2776 2777 #ifdef ATHN_BT_COEXISTENCE 2778 /* Enable bluetooth coexistence for combo chips. */ 2779 if (sc->flags & ATHN_FLAG_BTCOEX) 2780 athn_btcoex_enable(sc); 2781 #endif 2782 2783 ifp->if_flags &= ~IFF_OACTIVE; 2784 ifp->if_flags |= IFF_RUNNING; 2785 2786 #ifdef notyet 2787 if (ic->ic_flags & IEEE80211_F_WEPON) { 2788 /* Configure WEP keys. */ 2789 for (i = 0; i < IEEE80211_WEP_NKID; i++) 2790 athn_set_key(ic, NULL, &ic->ic_nw_keys[i]); 2791 } 2792 #endif 2793 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2794 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2795 else 2796 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2797 2798 return (0); 2799 fail: 2800 athn_stop(ifp, 1); 2801 return (error); 2802 } 2803 2804 void 2805 athn_stop(struct ifnet *ifp, int disable) 2806 { 2807 struct athn_softc *sc = ifp->if_softc; 2808 struct ieee80211com *ic = &sc->sc_ic; 2809 int qid; 2810 2811 ifp->if_timer = sc->sc_tx_timer = 0; 2812 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2813 2814 timeout_del(&sc->scan_to); 2815 /* In case we were scanning, release the scan "lock". */ 2816 ic->ic_scan_lock = IEEE80211_SCAN_UNLOCKED; 2817 2818 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2819 2820 #ifdef ATHN_BT_COEXISTENCE 2821 /* Disable bluetooth coexistence for combo chips. */ 2822 if (sc->flags & ATHN_FLAG_BTCOEX) 2823 athn_btcoex_disable(sc); 2824 #endif 2825 2826 /* Disable interrupts. */ 2827 athn_disable_interrupts(sc); 2828 /* Acknowledge interrupts (avoids interrupt storms). */ 2829 AR_WRITE(sc, AR_INTR_SYNC_CAUSE, 0xffffffff); 2830 AR_WRITE(sc, AR_INTR_SYNC_MASK, 0); 2831 2832 for (qid = 0; qid < ATHN_QID_COUNT; qid++) 2833 athn_stop_tx_dma(sc, qid); 2834 /* XXX call athn_hw_reset if Tx still pending? */ 2835 for (qid = 0; qid < ATHN_QID_COUNT; qid++) 2836 athn_tx_reclaim(sc, qid); 2837 2838 /* Stop Rx. */ 2839 AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 2840 AR_WRITE(sc, AR_MIBC, AR_MIBC_FMC); 2841 AR_WRITE(sc, AR_MIBC, AR_MIBC_CMC); 2842 AR_WRITE(sc, AR_FILT_OFDM, 0); 2843 AR_WRITE(sc, AR_FILT_CCK, 0); 2844 AR_WRITE_BARRIER(sc); 2845 athn_set_rxfilter(sc, 0); 2846 athn_stop_rx_dma(sc); 2847 2848 athn_reset(sc, 0); 2849 athn_init_pll(sc, NULL); 2850 athn_set_power_awake(sc); 2851 athn_reset(sc, 1); 2852 athn_init_pll(sc, NULL); 2853 2854 athn_set_power_sleep(sc); 2855 2856 /* For CardBus, power down the socket. */ 2857 if (disable && sc->sc_disable != NULL) 2858 sc->sc_disable(sc); 2859 } 2860 2861 void 2862 athn_suspend(struct athn_softc *sc) 2863 { 2864 struct ifnet *ifp = &sc->sc_ic.ic_if; 2865 2866 if (ifp->if_flags & IFF_RUNNING) 2867 athn_stop(ifp, 1); 2868 } 2869 2870 void 2871 athn_resume(struct athn_softc *sc) 2872 { 2873 struct ifnet *ifp = &sc->sc_ic.ic_if; 2874 2875 if (ifp->if_flags & IFF_UP) 2876 athn_init(ifp); 2877 } 2878