1 /* $OpenBSD: ar9380.c,v 1.24 2016/01/05 18:41:15 stsp Exp $ */ 2 3 /*- 4 * Copyright (c) 2011 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2010 Atheros Communications Inc. 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Driver for Atheros 802.11a/g/n chipsets. 22 * Routines for AR9380 and AR9485 chipsets. 23 */ 24 25 #include "bpfilter.h" 26 27 #include <sys/param.h> 28 #include <sys/sockio.h> 29 #include <sys/mbuf.h> 30 #include <sys/kernel.h> 31 #include <sys/socket.h> 32 #include <sys/systm.h> 33 #include <sys/malloc.h> 34 #include <sys/queue.h> 35 #include <sys/conf.h> 36 #include <sys/device.h> 37 #include <sys/endian.h> 38 39 #include <machine/bus.h> 40 41 #if NBPFILTER > 0 42 #include <net/bpf.h> 43 #endif 44 #include <net/if.h> 45 #include <net/if_media.h> 46 47 #include <netinet/in.h> 48 #include <netinet/if_ether.h> 49 50 #include <net80211/ieee80211_var.h> 51 #include <net80211/ieee80211_amrr.h> 52 #include <net80211/ieee80211_radiotap.h> 53 54 #include <dev/ic/athnreg.h> 55 #include <dev/ic/athnvar.h> 56 57 #include <dev/ic/ar9003reg.h> 58 #include <dev/ic/ar9380reg.h> 59 60 int ar9380_attach(struct athn_softc *); 61 void ar9380_setup(struct athn_softc *); 62 const uint8_t *ar9380_get_rom_template(struct athn_softc *, uint8_t); 63 void ar9380_swap_rom(struct athn_softc *); 64 int ar9380_set_synth(struct athn_softc *, struct ieee80211_channel *, 65 struct ieee80211_channel *); 66 void ar9380_get_paprd_masks(struct athn_softc *, struct ieee80211_channel *, 67 uint32_t *, uint32_t *); 68 void ar9380_init_from_rom(struct athn_softc *, struct ieee80211_channel *, 69 struct ieee80211_channel *); 70 void ar9380_init_swreg(struct athn_softc *); 71 int ar9485_pmu_write(struct athn_softc *, uint32_t, uint32_t); 72 void ar9485_init_swreg(struct athn_softc *); 73 void ar9380_spur_mitigate_cck(struct athn_softc *, 74 struct ieee80211_channel *, struct ieee80211_channel *); 75 void ar9380_spur_mitigate_ofdm(struct athn_softc *, 76 struct ieee80211_channel *, struct ieee80211_channel *); 77 void ar9380_spur_mitigate(struct athn_softc *, struct ieee80211_channel *, 78 struct ieee80211_channel *); 79 void ar9380_set_txpower(struct athn_softc *, struct ieee80211_channel *, 80 struct ieee80211_channel *); 81 void ar9380_get_correction(struct athn_softc *, struct ieee80211_channel *, 82 int, int *, int *); 83 void ar9380_set_correction(struct athn_softc *, struct ieee80211_channel *); 84 85 /* Extern functions. */ 86 int athn_interpolate(int, int, int, int, int); 87 uint8_t athn_chan2fbin(struct ieee80211_channel *); 88 void athn_get_pier_ival(uint8_t, const uint8_t *, int, int *, int *); 89 int ar9003_attach(struct athn_softc *); 90 void ar9003_write_txpower(struct athn_softc *, int16_t power[]); 91 void ar9003_get_lg_tpow(struct athn_softc *, struct ieee80211_channel *, 92 uint8_t, const uint8_t *, const struct ar_cal_target_power_leg *, 93 int, uint8_t[]); 94 void ar9003_get_ht_tpow(struct athn_softc *, struct ieee80211_channel *, 95 uint8_t, const uint8_t *, const struct ar_cal_target_power_ht *, 96 int, uint8_t[]); 97 98 99 int 100 ar9380_attach(struct athn_softc *sc) 101 { 102 sc->ngpiopins = 17; 103 sc->ops.setup = ar9380_setup; 104 sc->ops.get_rom_template = ar9380_get_rom_template; 105 sc->ops.swap_rom = ar9380_swap_rom; 106 sc->ops.init_from_rom = ar9380_init_from_rom; 107 sc->ops.set_txpower = ar9380_set_txpower; 108 sc->ops.set_synth = ar9380_set_synth; 109 sc->ops.spur_mitigate = ar9380_spur_mitigate; 110 sc->ops.get_paprd_masks = ar9380_get_paprd_masks; 111 sc->cca_min_2g = AR9380_PHY_CCA_MIN_GOOD_VAL_2GHZ; 112 sc->cca_max_2g = AR9380_PHY_CCA_MAX_GOOD_VAL_2GHZ; 113 sc->cca_min_5g = AR9380_PHY_CCA_MIN_GOOD_VAL_5GHZ; 114 sc->cca_max_5g = AR9380_PHY_CCA_MAX_GOOD_VAL_5GHZ; 115 if (AR_SREV_9485(sc)) { 116 sc->ini = &ar9485_1_1_ini; 117 sc->serdes = &ar9485_1_1_serdes; 118 } else { 119 sc->ini = &ar9380_2_2_ini; 120 sc->serdes = &ar9380_2_2_serdes; 121 } 122 123 return (ar9003_attach(sc)); 124 } 125 126 void 127 ar9380_setup(struct athn_softc *sc) 128 { 129 struct ieee80211com *ic = &sc->sc_ic; 130 struct ar9380_eeprom *eep = sc->eep; 131 struct ar9380_base_eep_hdr *base = &eep->baseEepHeader; 132 uint8_t type; 133 134 if (base->opFlags & AR_OPFLAGS_11A) 135 sc->flags |= ATHN_FLAG_11A; 136 if (base->opFlags & AR_OPFLAGS_11G) 137 sc->flags |= ATHN_FLAG_11G; 138 if (base->opFlags & AR_OPFLAGS_11N) 139 sc->flags |= ATHN_FLAG_11N; 140 141 IEEE80211_ADDR_COPY(ic->ic_myaddr, eep->macAddr); 142 sc->led_pin = base->wlanLedGpio; 143 144 /* Check if we have a hardware radio switch. */ 145 if (base->rfSilent & AR_EEP_RFSILENT_ENABLED) { 146 sc->flags |= ATHN_FLAG_RFSILENT; 147 /* Get GPIO pin used by hardware radio switch. */ 148 sc->rfsilent_pin = MS(base->rfSilent, 149 AR_EEP_RFSILENT_GPIO_SEL); 150 /* Get polarity of hardware radio switch. */ 151 if (base->rfSilent & AR_EEP_RFSILENT_POLARITY) 152 sc->flags |= ATHN_FLAG_RFSILENT_REVERSED; 153 } 154 155 /* Set the number of HW key cache entries. */ 156 sc->kc_entries = AR_KEYTABLE_SIZE; 157 158 sc->txchainmask = MS(base->txrxMask, AR_EEP_TX_MASK); 159 sc->rxchainmask = MS(base->txrxMask, AR_EEP_RX_MASK); 160 161 /* Fast PLL clock is always supported. */ 162 sc->flags |= ATHN_FLAG_FAST_PLL_CLOCK; 163 164 /* Enable PA predistortion if supported. */ 165 if (base->featureEnable & AR_EEP_PAPRD) 166 sc->flags |= ATHN_FLAG_PAPRD; 167 /* 168 * Some 3-stream chips may exceed the PCIe power requirements, 169 * requiring to reduce the number of Tx chains in some cases. 170 */ 171 if ((base->miscConfiguration & AR_EEP_CHAIN_MASK_REDUCE) && 172 sc->txchainmask == 0x7) 173 sc->flags |= ATHN_FLAG_3TREDUCE_CHAIN; 174 175 /* Select initialization values based on ROM. */ 176 type = MS(eep->baseEepHeader.txrxgain, AR_EEP_RX_GAIN); 177 if (!AR_SREV_9485(sc)) { 178 if (type == AR_EEP_RX_GAIN_WO_XLNA) 179 sc->rx_gain = &ar9380_2_2_rx_gain_wo_xlna; 180 else 181 sc->rx_gain = &ar9380_2_2_rx_gain; 182 } else 183 sc->rx_gain = &ar9485_1_1_rx_gain; 184 185 /* Select initialization values based on ROM. */ 186 type = MS(eep->baseEepHeader.txrxgain, AR_EEP_TX_GAIN); 187 if (!AR_SREV_9485(sc)) { 188 if (type == AR_EEP_TX_GAIN_HIGH_OB_DB) 189 sc->tx_gain = &ar9380_2_2_tx_gain_high_ob_db; 190 else if (type == AR_EEP_TX_GAIN_LOW_OB_DB) 191 sc->tx_gain = &ar9380_2_2_tx_gain_low_ob_db; 192 else if (type == AR_EEP_TX_GAIN_HIGH_POWER) 193 sc->tx_gain = &ar9380_2_2_tx_gain_high_power; 194 else 195 sc->tx_gain = &ar9380_2_2_tx_gain; 196 } else 197 sc->tx_gain = &ar9485_1_1_tx_gain; 198 } 199 200 const uint8_t * 201 ar9380_get_rom_template(struct athn_softc *sc, uint8_t ref) 202 { 203 int i; 204 205 /* Retrieve template ROM image for given reference. */ 206 for (i = 0; i < nitems(ar9380_rom_templates); i++) 207 if (ar9380_rom_templates[i][1] == ref) 208 return (ar9380_rom_templates[i]); 209 return (NULL); 210 } 211 212 void 213 ar9380_swap_rom(struct athn_softc *sc) 214 { 215 #if BYTE_ORDER == BIG_ENDIAN 216 struct ar9380_eeprom *eep = sc->eep; 217 struct ar9380_base_eep_hdr *base = &eep->baseEepHeader; 218 struct ar9380_modal_eep_header *modal; 219 int i; 220 221 base->regDmn[0] = swap16(base->regDmn[0]); 222 base->regDmn[1] = swap16(base->regDmn[1]); 223 base->swreg = swap32(base->swreg); 224 225 modal = &eep->modalHeader2G; 226 modal->antCtrlCommon = swap32(modal->antCtrlCommon); 227 modal->antCtrlCommon2 = swap32(modal->antCtrlCommon2); 228 modal->papdRateMaskHt20 = swap32(modal->papdRateMaskHt20); 229 modal->papdRateMaskHt40 = swap32(modal->papdRateMaskHt40); 230 for (i = 0; i < AR9380_MAX_CHAINS; i++) 231 modal->antCtrlChain[i] = swap16(modal->antCtrlChain[i]); 232 233 modal = &eep->modalHeader5G; 234 modal->antCtrlCommon = swap32(modal->antCtrlCommon); 235 modal->antCtrlCommon2 = swap32(modal->antCtrlCommon2); 236 modal->papdRateMaskHt20 = swap32(modal->papdRateMaskHt20); 237 modal->papdRateMaskHt40 = swap32(modal->papdRateMaskHt40); 238 for (i = 0; i < AR9380_MAX_CHAINS; i++) 239 modal->antCtrlChain[i] = swap16(modal->antCtrlChain[i]); 240 #endif 241 } 242 243 void 244 ar9380_get_paprd_masks(struct athn_softc *sc, struct ieee80211_channel *c, 245 uint32_t *ht20mask, uint32_t *ht40mask) 246 { 247 const struct ar9380_eeprom *eep = sc->eep; 248 const struct ar9380_modal_eep_header *modal; 249 250 if (IEEE80211_IS_CHAN_2GHZ(c)) 251 modal = &eep->modalHeader2G; 252 else 253 modal = &eep->modalHeader5G; 254 *ht20mask = modal->papdRateMaskHt20; 255 *ht40mask = modal->papdRateMaskHt40; 256 } 257 258 int 259 ar9380_set_synth(struct athn_softc *sc, struct ieee80211_channel *c, 260 struct ieee80211_channel *extc) 261 { 262 uint32_t freq = c->ic_freq; 263 uint32_t chansel, phy; 264 265 if (IEEE80211_IS_CHAN_2GHZ(c)) { 266 if (AR_SREV_9485(sc)) 267 chansel = ((freq << 16) - 215) / 15; 268 else 269 chansel = (freq << 16) / 15; 270 AR_WRITE(sc, AR_PHY_SYNTH_CONTROL, AR9380_BMODE); 271 } else { 272 chansel = (freq << 15) / 15; 273 chansel >>= 1; 274 AR_WRITE(sc, AR_PHY_SYNTH_CONTROL, 0); 275 } 276 277 /* Enable Long Shift Select for synthesizer. */ 278 AR_SETBITS(sc, AR_PHY_65NM_CH0_SYNTH4, 279 AR_PHY_SYNTH4_LONG_SHIFT_SELECT); 280 AR_WRITE_BARRIER(sc); 281 282 /* Program synthesizer. */ 283 phy = (chansel << 2) | AR9380_FRACMODE; 284 DPRINTFN(4, ("AR_PHY_65NM_CH0_SYNTH7=0x%08x\n", phy)); 285 AR_WRITE(sc, AR_PHY_65NM_CH0_SYNTH7, phy); 286 AR_WRITE_BARRIER(sc); 287 /* Toggle Load Synth Channel bit. */ 288 AR_WRITE(sc, AR_PHY_65NM_CH0_SYNTH7, phy | AR9380_LOAD_SYNTH); 289 AR_WRITE_BARRIER(sc); 290 return (0); 291 } 292 293 void 294 ar9380_init_from_rom(struct athn_softc *sc, struct ieee80211_channel *c, 295 struct ieee80211_channel *extc) 296 { 297 const struct ar9380_eeprom *eep = sc->eep; 298 const struct ar9380_modal_eep_header *modal; 299 uint8_t db, margin, ant_div_ctrl; 300 uint32_t reg; 301 int i, maxchains; 302 303 if (IEEE80211_IS_CHAN_2GHZ(c)) 304 modal = &eep->modalHeader2G; 305 else 306 modal = &eep->modalHeader5G; 307 308 /* Apply XPA bias level. */ 309 if (AR_SREV_9485(sc)) { 310 reg = AR_READ(sc, AR9485_PHY_65NM_CH0_TOP2); 311 reg = RW(reg, AR9485_PHY_65NM_CH0_TOP2_XPABIASLVL, 312 modal->xpaBiasLvl); 313 AR_WRITE(sc, AR9485_PHY_65NM_CH0_TOP2, reg); 314 } else { 315 reg = AR_READ(sc, AR_PHY_65NM_CH0_TOP); 316 reg = RW(reg, AR_PHY_65NM_CH0_TOP_XPABIASLVL, 317 modal->xpaBiasLvl & 0x3); 318 AR_WRITE(sc, AR_PHY_65NM_CH0_TOP, reg); 319 reg = AR_READ(sc, AR_PHY_65NM_CH0_THERM); 320 reg = RW(reg, AR_PHY_65NM_CH0_THERM_XPABIASLVL_MSB, 321 modal->xpaBiasLvl >> 2); 322 reg |= AR_PHY_65NM_CH0_THERM_XPASHORT2GND; 323 AR_WRITE(sc, AR_PHY_65NM_CH0_THERM, reg); 324 } 325 326 /* Apply antenna control. */ 327 reg = AR_READ(sc, AR_PHY_SWITCH_COM); 328 reg = RW(reg, AR_SWITCH_TABLE_COM_ALL, modal->antCtrlCommon); 329 AR_WRITE(sc, AR_PHY_SWITCH_COM, reg); 330 reg = AR_READ(sc, AR_PHY_SWITCH_COM_2); 331 reg = RW(reg, AR_SWITCH_TABLE_COM_2_ALL, modal->antCtrlCommon2); 332 AR_WRITE(sc, AR_PHY_SWITCH_COM_2, reg); 333 334 maxchains = AR_SREV_9485(sc) ? 1 : AR9380_MAX_CHAINS; 335 for (i = 0; i < maxchains; i++) { 336 reg = AR_READ(sc, AR_PHY_SWITCH_CHAIN(i)); 337 reg = RW(reg, AR_SWITCH_TABLE_ALL, modal->antCtrlChain[i]); 338 AR_WRITE(sc, AR_PHY_SWITCH_CHAIN(i), reg); 339 } 340 341 if (AR_SREV_9485(sc)) { 342 ant_div_ctrl = eep->base_ext1.ant_div_control; 343 reg = AR_READ(sc, AR_PHY_MC_GAIN_CTRL); 344 reg = RW(reg, AR_PHY_MC_GAIN_CTRL_ANT_DIV_CTRL_ALL, 345 MS(ant_div_ctrl, AR_EEP_ANT_DIV_CTRL_ALL)); 346 if (ant_div_ctrl & AR_EEP_ANT_DIV_CTRL_ANT_DIV) 347 reg |= AR_PHY_MC_GAIN_CTRL_ENABLE_ANT_DIV; 348 else 349 reg &= ~AR_PHY_MC_GAIN_CTRL_ENABLE_ANT_DIV; 350 AR_WRITE(sc, AR_PHY_MC_GAIN_CTRL, reg); 351 reg = AR_READ(sc, AR_PHY_CCK_DETECT); 352 if (ant_div_ctrl & AR_EEP_ANT_DIV_CTRL_FAST_DIV) 353 reg |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV; 354 else 355 reg &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV; 356 AR_WRITE(sc, AR_PHY_CCK_DETECT, reg); 357 } 358 359 if (eep->baseEepHeader.miscConfiguration & AR_EEP_DRIVE_STRENGTH) { 360 /* Apply drive strength. */ 361 reg = AR_READ(sc, AR_PHY_65NM_CH0_BIAS1); 362 reg = RW(reg, AR_PHY_65NM_CH0_BIAS1_0, 5); 363 reg = RW(reg, AR_PHY_65NM_CH0_BIAS1_1, 5); 364 reg = RW(reg, AR_PHY_65NM_CH0_BIAS1_2, 5); 365 reg = RW(reg, AR_PHY_65NM_CH0_BIAS1_3, 5); 366 reg = RW(reg, AR_PHY_65NM_CH0_BIAS1_4, 5); 367 reg = RW(reg, AR_PHY_65NM_CH0_BIAS1_5, 5); 368 AR_WRITE(sc, AR_PHY_65NM_CH0_BIAS1, reg); 369 370 reg = AR_READ(sc, AR_PHY_65NM_CH0_BIAS2); 371 reg = RW(reg, AR_PHY_65NM_CH0_BIAS2_0, 5); 372 reg = RW(reg, AR_PHY_65NM_CH0_BIAS2_1, 5); 373 reg = RW(reg, AR_PHY_65NM_CH0_BIAS2_2, 5); 374 reg = RW(reg, AR_PHY_65NM_CH0_BIAS2_3, 5); 375 reg = RW(reg, AR_PHY_65NM_CH0_BIAS2_4, 5); 376 reg = RW(reg, AR_PHY_65NM_CH0_BIAS2_5, 5); 377 reg = RW(reg, AR_PHY_65NM_CH0_BIAS2_6, 5); 378 reg = RW(reg, AR_PHY_65NM_CH0_BIAS2_7, 5); 379 reg = RW(reg, AR_PHY_65NM_CH0_BIAS2_8, 5); 380 AR_WRITE(sc, AR_PHY_65NM_CH0_BIAS2, reg); 381 382 reg = AR_READ(sc, AR_PHY_65NM_CH0_BIAS4); 383 reg = RW(reg, AR_PHY_65NM_CH0_BIAS4_0, 5); 384 reg = RW(reg, AR_PHY_65NM_CH0_BIAS4_1, 5); 385 reg = RW(reg, AR_PHY_65NM_CH0_BIAS4_2, 5); 386 AR_WRITE(sc, AR_PHY_65NM_CH0_BIAS4, reg); 387 } 388 389 /* Apply attenuation settings. */ 390 maxchains = AR_SREV_9485(sc) ? 1 : AR9380_MAX_CHAINS; 391 for (i = 0; i < maxchains; i++) { 392 if (IEEE80211_IS_CHAN_5GHZ(c) && 393 eep->base_ext2.xatten1DBLow[i] != 0) { 394 if (c->ic_freq <= 5500) { 395 db = athn_interpolate(c->ic_freq, 396 5180, eep->base_ext2.xatten1DBLow[i], 397 5500, modal->xatten1DB[i]); 398 } else { 399 db = athn_interpolate(c->ic_freq, 400 5500, modal->xatten1DB[i], 401 5785, eep->base_ext2.xatten1DBHigh[i]); 402 } 403 } else 404 db = modal->xatten1DB[i]; 405 if (IEEE80211_IS_CHAN_5GHZ(c) && 406 eep->base_ext2.xatten1MarginLow[i] != 0) { 407 if (c->ic_freq <= 5500) { 408 margin = athn_interpolate(c->ic_freq, 409 5180, eep->base_ext2.xatten1MarginLow[i], 410 5500, modal->xatten1Margin[i]); 411 } else { 412 margin = athn_interpolate(c->ic_freq, 413 5500, modal->xatten1Margin[i], 414 5785, eep->base_ext2.xatten1MarginHigh[i]); 415 } 416 } else 417 margin = modal->xatten1Margin[i]; 418 reg = AR_READ(sc, AR_PHY_EXT_ATTEN_CTL(i)); 419 reg = RW(reg, AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB, db); 420 reg = RW(reg, AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN, margin); 421 AR_WRITE(sc, AR_PHY_EXT_ATTEN_CTL(i), reg); 422 } 423 424 /* Initialize switching regulator. */ 425 if (AR_SREV_9485(sc)) 426 ar9485_init_swreg(sc); 427 else 428 ar9485_init_swreg(sc); 429 430 /* Apply tuning capabilities. */ 431 if (AR_SREV_9485(sc) && 432 (eep->baseEepHeader.featureEnable & AR_EEP_TUNING_CAPS)) { 433 reg = AR_READ(sc, AR9485_PHY_CH0_XTAL); 434 reg = RW(reg, AR9485_PHY_CH0_XTAL_CAPINDAC, 435 eep->baseEepHeader.params_for_tuning_caps[0]); 436 reg = RW(reg, AR9485_PHY_CH0_XTAL_CAPOUTDAC, 437 eep->baseEepHeader.params_for_tuning_caps[0]); 438 AR_WRITE(sc, AR9485_PHY_CH0_XTAL, reg); 439 } 440 AR_WRITE_BARRIER(sc); 441 } 442 443 void 444 ar9380_init_swreg(struct athn_softc *sc) 445 { 446 const struct ar9380_eeprom *eep = sc->eep; 447 448 if (eep->baseEepHeader.featureEnable & AR_EEP_INTERNAL_REGULATOR) { 449 /* Internal regulator is ON. */ 450 AR_CLRBITS(sc, AR_RTC_REG_CONTROL1, 451 AR_RTC_REG_CONTROL1_SWREG_PROGRAM); 452 AR_WRITE(sc, AR_RTC_REG_CONTROL0, eep->baseEepHeader.swreg); 453 AR_SETBITS(sc, AR_RTC_REG_CONTROL1, 454 AR_RTC_REG_CONTROL1_SWREG_PROGRAM); 455 } else 456 AR_SETBITS(sc, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_SWREG_PRD); 457 AR_WRITE_BARRIER(sc); 458 } 459 460 int 461 ar9485_pmu_write(struct athn_softc *sc, uint32_t addr, uint32_t val) 462 { 463 int ntries; 464 465 AR_WRITE(sc, addr, val); 466 /* Wait for write to complete. */ 467 for (ntries = 0; ntries < 100; ntries++) { 468 if (AR_READ(sc, addr) == val) 469 return (0); 470 AR_WRITE(sc, addr, val); /* Insist. */ 471 AR_WRITE_BARRIER(sc); 472 DELAY(10); 473 } 474 return (ETIMEDOUT); 475 } 476 477 #define ar9486_pmu_read AR_READ 478 479 void 480 ar9485_init_swreg(struct athn_softc *sc) 481 { 482 const struct ar9380_eeprom *eep = sc->eep; 483 uint32_t reg; 484 485 ar9485_pmu_write(sc, AR_PHY_PMU2, 486 ar9486_pmu_read(sc, AR_PHY_PMU2) & ~AR_PHY_PMU2_PGM); 487 488 if (eep->baseEepHeader.featureEnable & AR_EEP_INTERNAL_REGULATOR) { 489 ar9485_pmu_write(sc, AR_PHY_PMU1, 0x131dc17a); 490 491 reg = ar9486_pmu_read(sc, AR_PHY_PMU2); 492 reg = (reg & ~0xffc00000) | 0x10000000; 493 ar9485_pmu_write(sc, AR_PHY_PMU2, reg); 494 } else { 495 ar9485_pmu_write(sc, AR_PHY_PMU1, 496 ar9486_pmu_read(sc, AR_PHY_PMU1) | AR_PHY_PMU1_PWD); 497 } 498 499 ar9485_pmu_write(sc, AR_PHY_PMU2, 500 ar9486_pmu_read(sc, AR_PHY_PMU2) | AR_PHY_PMU2_PGM); 501 } 502 503 void 504 ar9380_spur_mitigate_cck(struct athn_softc *sc, struct ieee80211_channel *c, 505 struct ieee80211_channel *extc) 506 { 507 /* NB: It is safe to call this function for 5GHz channels. */ 508 static const int16_t freqs[] = { 2420, 2440, 2464, 2480 }; 509 int i, spur, freq; 510 uint32_t reg; 511 512 for (i = 0; i < nitems(freqs); i++) { 513 spur = freqs[i] - c->ic_freq; 514 if (abs(spur) < 10) /* +/- 10MHz range. */ 515 break; 516 } 517 if (i == nitems(freqs)) { 518 /* Disable CCK spur mitigation. */ 519 reg = AR_READ(sc, AR_PHY_AGC_CONTROL); 520 reg = RW(reg, AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5); 521 AR_WRITE(sc, AR_PHY_AGC_CONTROL, reg); 522 reg = AR_READ(sc, AR_PHY_CCK_SPUR_MIT); 523 reg = RW(reg, AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0); 524 reg &= ~AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT; 525 AR_WRITE(sc, AR_PHY_CCK_SPUR_MIT, reg); 526 AR_WRITE_BARRIER(sc); 527 return; 528 } 529 freq = (spur * 524288) / 11; 530 531 reg = AR_READ(sc, AR_PHY_AGC_CONTROL); 532 reg = RW(reg, AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7); 533 AR_WRITE(sc, AR_PHY_AGC_CONTROL, reg); 534 535 reg = AR_READ(sc, AR_PHY_CCK_SPUR_MIT); 536 reg = RW(reg, AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, freq); 537 reg = RW(reg, AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f); 538 reg = RW(reg, AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE, 0x2); 539 reg |= AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT; 540 AR_WRITE(sc, AR_PHY_CCK_SPUR_MIT, reg); 541 AR_WRITE_BARRIER(sc); 542 } 543 544 void 545 ar9380_spur_mitigate_ofdm(struct athn_softc *sc, struct ieee80211_channel *c, 546 struct ieee80211_channel *extc) 547 { 548 const struct ar9380_eeprom *eep = sc->eep; 549 const uint8_t *spurchans; 550 uint32_t reg; 551 int idx, spur_delta_phase, spur_off, range, i; 552 int freq, spur, spur_freq_sd, spur_subchannel_sd; 553 554 if (IEEE80211_IS_CHAN_2GHZ(c)) 555 spurchans = eep->modalHeader2G.spurChans; 556 else 557 spurchans = eep->modalHeader5G.spurChans; 558 if (spurchans[0] == 0) 559 return; 560 561 /* Disable OFDM spur mitigation. */ 562 AR_CLRBITS(sc, AR_PHY_TIMING4, AR_PHY_TIMING4_ENABLE_SPUR_FILTER); 563 564 reg = AR_READ(sc, AR_PHY_TIMING11); 565 reg = RW(reg, AR_PHY_TIMING11_SPUR_FREQ_SD, 0); 566 reg = RW(reg, AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0); 567 reg &= ~AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC; 568 reg &= ~AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR; 569 AR_WRITE(sc, AR_PHY_TIMING11, reg); 570 571 AR_CLRBITS(sc, AR_PHY_SFCORR_EXT, 572 AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD); 573 574 AR_CLRBITS(sc, AR_PHY_TIMING4, AR_PHY_TIMING4_ENABLE_SPUR_RSSI); 575 576 reg = AR_READ(sc, AR_PHY_SPUR_REG); 577 reg = RW(reg, AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0); 578 reg &= ~AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI; 579 reg &= ~AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT; 580 reg &= ~AR_PHY_SPUR_REG_ENABLE_MASK_PPM; 581 AR_WRITE(sc, AR_PHY_SPUR_REG, reg); 582 AR_WRITE_BARRIER(sc); 583 584 freq = c->ic_freq; 585 if (extc != NULL) { 586 range = 19; /* +/- 19MHz range. */ 587 if (AR_READ(sc, AR_PHY_GEN_CTRL) & AR_PHY_GC_DYN2040_PRI_CH) 588 freq += 10; 589 else 590 freq -= 10; 591 } else 592 range = 10; /* +/- 10MHz range. */ 593 for (i = 0; i < AR9380_EEPROM_MODAL_SPURS; i++) { 594 spur = spurchans[i]; 595 if (spur == 0) 596 return; 597 /* Convert to frequency. */ 598 if (IEEE80211_IS_CHAN_2GHZ(c)) 599 spur = 2300 + spur; 600 else 601 spur = 4900 + (spur * 5); 602 spur -= freq; 603 if (abs(spur) < range) 604 break; 605 } 606 if (i == AR9380_EEPROM_MODAL_SPURS) 607 return; 608 609 /* Enable OFDM spur mitigation. */ 610 if (extc != NULL) { 611 spur_delta_phase = (spur * 131072) / 5; 612 reg = AR_READ(sc, AR_PHY_GEN_CTRL); 613 if (spur < 0) { 614 spur_subchannel_sd = 615 (reg & AR_PHY_GC_DYN2040_PRI_CH) == 0; 616 spur_off = spur + 10; 617 } else { 618 spur_subchannel_sd = 619 (reg & AR_PHY_GC_DYN2040_PRI_CH) != 0; 620 spur_off = spur - 10; 621 } 622 } else { 623 spur_delta_phase = (spur * 262144) / 5; 624 spur_subchannel_sd = 0; 625 spur_off = spur; 626 } 627 spur_freq_sd = (spur_off * 512) / 11; 628 629 AR_SETBITS(sc, AR_PHY_TIMING4, AR_PHY_TIMING4_ENABLE_SPUR_FILTER); 630 631 reg = AR_READ(sc, AR_PHY_TIMING11); 632 reg = RW(reg, AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd); 633 reg = RW(reg, AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase); 634 reg |= AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC; 635 reg |= AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR; 636 AR_WRITE(sc, AR_PHY_TIMING11, reg); 637 638 reg = AR_READ(sc, AR_PHY_SFCORR_EXT); 639 if (spur_subchannel_sd) 640 reg |= AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD; 641 else 642 reg &= ~AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD; 643 AR_WRITE(sc, AR_PHY_SFCORR_EXT, reg); 644 645 AR_SETBITS(sc, AR_PHY_TIMING4, AR_PHY_TIMING4_ENABLE_SPUR_RSSI); 646 647 reg = AR_READ(sc, AR_PHY_SPUR_REG); 648 reg = RW(reg, AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff); 649 reg = RW(reg, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, 34); 650 reg |= AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI; 651 if (AR_READ(sc, AR_PHY_MODE) & AR_PHY_MODE_DYNAMIC) 652 reg |= AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT; 653 reg |= AR_PHY_SPUR_REG_ENABLE_MASK_PPM; 654 AR_WRITE(sc, AR_PHY_SPUR_REG, reg); 655 656 idx = (spur * 16) / 5; 657 if (idx < 0) 658 idx--; 659 660 /* Write pilot mask. */ 661 AR_SETBITS(sc, AR_PHY_TIMING4, 662 AR_PHY_TIMING4_ENABLE_PILOT_MASK | 663 AR_PHY_TIMING4_ENABLE_CHAN_MASK); 664 665 reg = AR_READ(sc, AR_PHY_PILOT_SPUR_MASK); 666 reg = RW(reg, AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, idx); 667 reg = RW(reg, AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0x0c); 668 AR_WRITE(sc, AR_PHY_PILOT_SPUR_MASK, reg); 669 670 reg = AR_READ(sc, AR_PHY_SPUR_MASK_A); 671 reg = RW(reg, AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, idx); 672 reg = RW(reg, AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0); 673 AR_WRITE(sc, AR_PHY_SPUR_MASK_A, reg); 674 675 reg = AR_READ(sc, AR_PHY_CHAN_SPUR_MASK); 676 reg = RW(reg, AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, idx); 677 reg = RW(reg, AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0x0c); 678 AR_WRITE(sc, AR_PHY_CHAN_SPUR_MASK, reg); 679 AR_WRITE_BARRIER(sc); 680 } 681 682 void 683 ar9380_spur_mitigate(struct athn_softc *sc, struct ieee80211_channel *c, 684 struct ieee80211_channel *extc) 685 { 686 /* NB: We call spur_mitigate_cck for 5GHz too, just to disable it. */ 687 ar9380_spur_mitigate_cck(sc, c, extc); 688 ar9380_spur_mitigate_ofdm(sc, c, extc); 689 } 690 691 void 692 ar9380_set_txpower(struct athn_softc *sc, struct ieee80211_channel *c, 693 struct ieee80211_channel *extc) 694 { 695 const struct ar9380_eeprom *eep = sc->eep; 696 uint8_t tpow_cck[4], tpow_ofdm[4]; 697 uint8_t tpow_ht20[14], tpow_ht40[14]; 698 int16_t power[ATHN_POWER_COUNT]; 699 700 if (IEEE80211_IS_CHAN_2GHZ(c)) { 701 /* Get CCK target powers. */ 702 ar9003_get_lg_tpow(sc, c, AR_CTL_11B, 703 eep->calTargetFbinCck, eep->calTargetPowerCck, 704 AR9380_NUM_2G_CCK_TARGET_POWERS, tpow_cck); 705 706 /* Get OFDM target powers. */ 707 ar9003_get_lg_tpow(sc, c, AR_CTL_11G, 708 eep->calTargetFbin2G, eep->calTargetPower2G, 709 AR9380_NUM_2G_20_TARGET_POWERS, tpow_ofdm); 710 711 /* Get HT-20 target powers. */ 712 ar9003_get_ht_tpow(sc, c, AR_CTL_2GHT20, 713 eep->calTargetFbin2GHT20, eep->calTargetPower2GHT20, 714 AR9380_NUM_2G_20_TARGET_POWERS, tpow_ht20); 715 716 if (extc != NULL) { 717 /* Get HT-40 target powers. */ 718 ar9003_get_ht_tpow(sc, c, AR_CTL_2GHT40, 719 eep->calTargetFbin2GHT40, 720 eep->calTargetPower2GHT40, 721 AR9380_NUM_2G_40_TARGET_POWERS, tpow_ht40); 722 } 723 } else { 724 /* Get OFDM target powers. */ 725 ar9003_get_lg_tpow(sc, c, AR_CTL_11A, 726 eep->calTargetFbin5G, eep->calTargetPower5G, 727 AR9380_NUM_5G_20_TARGET_POWERS, tpow_ofdm); 728 729 /* Get HT-20 target powers. */ 730 ar9003_get_ht_tpow(sc, c, AR_CTL_5GHT20, 731 eep->calTargetFbin5GHT20, eep->calTargetPower5GHT20, 732 AR9380_NUM_5G_20_TARGET_POWERS, tpow_ht20); 733 734 if (extc != NULL) { 735 /* Get HT-40 target powers. */ 736 ar9003_get_ht_tpow(sc, c, AR_CTL_5GHT40, 737 eep->calTargetFbin5GHT40, 738 eep->calTargetPower5GHT40, 739 AR9380_NUM_5G_40_TARGET_POWERS, tpow_ht40); 740 } 741 } 742 743 memset(power, 0, sizeof(power)); 744 /* Shuffle target powers accross transmit rates. */ 745 power[ATHN_POWER_OFDM6 ] = 746 power[ATHN_POWER_OFDM9 ] = 747 power[ATHN_POWER_OFDM12] = 748 power[ATHN_POWER_OFDM18] = 749 power[ATHN_POWER_OFDM24] = tpow_ofdm[0]; 750 power[ATHN_POWER_OFDM36] = tpow_ofdm[1]; 751 power[ATHN_POWER_OFDM48] = tpow_ofdm[2]; 752 power[ATHN_POWER_OFDM54] = tpow_ofdm[3]; 753 if (IEEE80211_IS_CHAN_2GHZ(c)) { 754 power[ATHN_POWER_CCK1_LP ] = 755 power[ATHN_POWER_CCK2_LP ] = 756 power[ATHN_POWER_CCK2_SP ] = 757 power[ATHN_POWER_CCK55_LP] = tpow_cck[0]; 758 power[ATHN_POWER_CCK55_SP] = tpow_cck[1]; 759 power[ATHN_POWER_CCK11_LP] = tpow_cck[2]; 760 power[ATHN_POWER_CCK11_SP] = tpow_cck[3]; 761 } 762 /* Next entry covers MCS0, MCS8 and MCS16. */ 763 power[ATHN_POWER_HT20( 0)] = tpow_ht20[ 0]; 764 /* Next entry covers MCS1-3, MCS9-11 and MCS17-19. */ 765 power[ATHN_POWER_HT20( 1)] = tpow_ht20[ 1]; 766 power[ATHN_POWER_HT20( 4)] = tpow_ht20[ 2]; 767 power[ATHN_POWER_HT20( 5)] = tpow_ht20[ 3]; 768 power[ATHN_POWER_HT20( 6)] = tpow_ht20[ 4]; 769 power[ATHN_POWER_HT20( 7)] = tpow_ht20[ 5]; 770 power[ATHN_POWER_HT20(12)] = tpow_ht20[ 6]; 771 power[ATHN_POWER_HT20(13)] = tpow_ht20[ 7]; 772 power[ATHN_POWER_HT20(14)] = tpow_ht20[ 8]; 773 power[ATHN_POWER_HT20(15)] = tpow_ht20[ 9]; 774 power[ATHN_POWER_HT20(20)] = tpow_ht20[10]; 775 power[ATHN_POWER_HT20(21)] = tpow_ht20[11]; 776 power[ATHN_POWER_HT20(22)] = tpow_ht20[12]; 777 power[ATHN_POWER_HT20(23)] = tpow_ht20[13]; 778 if (extc != NULL) { 779 /* Next entry covers MCS0, MCS8 and MCS16. */ 780 power[ATHN_POWER_HT40( 0)] = tpow_ht40[ 0]; 781 /* Next entry covers MCS1-3, MCS9-11 and MCS17-19. */ 782 power[ATHN_POWER_HT40( 1)] = tpow_ht40[ 1]; 783 power[ATHN_POWER_HT40( 4)] = tpow_ht40[ 2]; 784 power[ATHN_POWER_HT40( 5)] = tpow_ht40[ 3]; 785 power[ATHN_POWER_HT40( 6)] = tpow_ht40[ 4]; 786 power[ATHN_POWER_HT40( 7)] = tpow_ht40[ 5]; 787 power[ATHN_POWER_HT40(12)] = tpow_ht40[ 6]; 788 power[ATHN_POWER_HT40(13)] = tpow_ht40[ 7]; 789 power[ATHN_POWER_HT40(14)] = tpow_ht40[ 8]; 790 power[ATHN_POWER_HT40(15)] = tpow_ht40[ 9]; 791 power[ATHN_POWER_HT40(20)] = tpow_ht40[10]; 792 power[ATHN_POWER_HT40(21)] = tpow_ht40[11]; 793 power[ATHN_POWER_HT40(22)] = tpow_ht40[12]; 794 power[ATHN_POWER_HT40(23)] = tpow_ht40[13]; 795 } 796 797 /* Write transmit power values to hardware. */ 798 ar9003_write_txpower(sc, power); 799 800 /* Apply transmit power correction. */ 801 ar9380_set_correction(sc, c); 802 } 803 804 void 805 ar9380_get_correction(struct athn_softc *sc, struct ieee80211_channel *c, 806 int chain, int *corr, int *temp) 807 { 808 const struct ar9380_eeprom *eep = sc->eep; 809 const struct ar9380_cal_data_per_freq_op_loop *pierdata; 810 const uint8_t *pierfreq; 811 uint8_t fbin; 812 int lo, hi, npiers; 813 814 if (IEEE80211_IS_CHAN_2GHZ(c)) { 815 pierfreq = eep->calFreqPier2G; 816 pierdata = eep->calPierData2G[chain]; 817 npiers = AR9380_NUM_2G_CAL_PIERS; 818 } else { 819 pierfreq = eep->calFreqPier5G; 820 pierdata = eep->calPierData5G[chain]; 821 npiers = AR9380_NUM_5G_CAL_PIERS; 822 } 823 /* Find channel in ROM pier table. */ 824 fbin = athn_chan2fbin(c); 825 athn_get_pier_ival(fbin, pierfreq, npiers, &lo, &hi); 826 827 *corr = athn_interpolate(fbin, 828 pierfreq[lo], pierdata[lo].refPower, 829 pierfreq[hi], pierdata[hi].refPower); 830 *temp = athn_interpolate(fbin, 831 pierfreq[lo], pierdata[lo].tempMeas, 832 pierfreq[hi], pierdata[hi].tempMeas); 833 } 834 835 void 836 ar9380_set_correction(struct athn_softc *sc, struct ieee80211_channel *c) 837 { 838 const struct ar9380_eeprom *eep = sc->eep; 839 const struct ar9380_modal_eep_header *modal; 840 uint32_t reg; 841 int8_t slope; 842 int i, corr, temp, temp0; 843 844 if (IEEE80211_IS_CHAN_2GHZ(c)) 845 modal = &eep->modalHeader2G; 846 else 847 modal = &eep->modalHeader5G; 848 849 for (i = 0; i < AR9380_MAX_CHAINS; i++) { 850 ar9380_get_correction(sc, c, i, &corr, &temp); 851 if (i == 0) 852 temp0 = temp; 853 854 reg = AR_READ(sc, AR_PHY_TPC_11_B(i)); 855 reg = RW(reg, AR_PHY_TPC_11_OLPC_GAIN_DELTA, corr); 856 AR_WRITE(sc, AR_PHY_TPC_11_B(i), reg); 857 858 /* Enable open loop power control. */ 859 reg = AR_READ(sc, AR_PHY_TPC_6_B(i)); 860 reg = RW(reg, AR_PHY_TPC_6_ERROR_EST_MODE, 3); 861 AR_WRITE(sc, AR_PHY_TPC_6_B(i), reg); 862 } 863 864 /* Enable temperature compensation. */ 865 if (IEEE80211_IS_CHAN_5GHZ(c) && 866 eep->base_ext2.tempSlopeLow != 0) { 867 if (c->ic_freq <= 5500) { 868 slope = athn_interpolate(c->ic_freq, 869 5180, eep->base_ext2.tempSlopeLow, 870 5500, modal->tempSlope); 871 } else { 872 slope = athn_interpolate(c->ic_freq, 873 5500, modal->tempSlope, 874 5785, eep->base_ext2.tempSlopeHigh); 875 } 876 } else 877 slope = modal->tempSlope; 878 879 reg = AR_READ(sc, AR_PHY_TPC_19); 880 reg = RW(reg, AR_PHY_TPC_19_ALPHA_THERM, slope); 881 AR_WRITE(sc, AR_PHY_TPC_19, reg); 882 883 reg = AR_READ(sc, AR_PHY_TPC_18); 884 reg = RW(reg, AR_PHY_TPC_18_THERM_CAL, temp0); 885 AR_WRITE(sc, AR_PHY_TPC_18, reg); 886 AR_WRITE_BARRIER(sc); 887 } 888