1 /* $OpenBSD: ar9285.c,v 1.26 2016/01/05 18:41:15 stsp Exp $ */ 2 3 /*- 4 * Copyright (c) 2009-2010 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2008-2010 Atheros Communications Inc. 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Driver for Atheros 802.11a/g/n chipsets. 22 * Routines for AR9285 and AR9271 chipsets. 23 */ 24 25 #include "athn_usb.h" 26 #include "bpfilter.h" 27 28 #include <sys/param.h> 29 #include <sys/sockio.h> 30 #include <sys/mbuf.h> 31 #include <sys/kernel.h> 32 #include <sys/socket.h> 33 #include <sys/systm.h> 34 #include <sys/malloc.h> 35 #include <sys/queue.h> 36 #include <sys/timeout.h> 37 #include <sys/conf.h> 38 #include <sys/device.h> 39 #include <sys/endian.h> 40 41 #include <machine/bus.h> 42 #include <machine/intr.h> 43 44 #if NBPFILTER > 0 45 #include <net/bpf.h> 46 #endif 47 #include <net/if.h> 48 #include <net/if_media.h> 49 50 #include <netinet/in.h> 51 #include <netinet/if_ether.h> 52 53 #include <net80211/ieee80211_var.h> 54 #include <net80211/ieee80211_amrr.h> 55 #include <net80211/ieee80211_radiotap.h> 56 57 #include <dev/ic/athnreg.h> 58 #include <dev/ic/athnvar.h> 59 60 #include <dev/ic/ar5008reg.h> 61 #include <dev/ic/ar9280reg.h> 62 #include <dev/ic/ar9285reg.h> 63 64 int ar9285_attach(struct athn_softc *); 65 void ar9285_setup(struct athn_softc *); 66 void ar9285_swap_rom(struct athn_softc *); 67 const struct ar_spur_chan *ar9285_get_spur_chans(struct athn_softc *, int); 68 void ar9285_init_from_rom(struct athn_softc *, struct ieee80211_channel *, 69 struct ieee80211_channel *); 70 void ar9285_pa_calib(struct athn_softc *); 71 void ar9271_pa_calib(struct athn_softc *); 72 int ar9285_cl_cal(struct athn_softc *, struct ieee80211_channel *, 73 struct ieee80211_channel *); 74 void ar9271_load_ani(struct athn_softc *); 75 int ar9285_init_calib(struct athn_softc *, struct ieee80211_channel *, 76 struct ieee80211_channel *); 77 void ar9285_get_pdadcs(struct athn_softc *, struct ieee80211_channel *, 78 int, uint8_t, uint8_t *, uint8_t *); 79 void ar9285_set_power_calib(struct athn_softc *, 80 struct ieee80211_channel *); 81 void ar9285_set_txpower(struct athn_softc *, struct ieee80211_channel *, 82 struct ieee80211_channel *); 83 84 /* Extern functions. */ 85 uint8_t athn_chan2fbin(struct ieee80211_channel *); 86 void athn_get_pier_ival(uint8_t, const uint8_t *, int, int *, int *); 87 int ar5008_attach(struct athn_softc *); 88 void ar5008_write_txpower(struct athn_softc *, int16_t power[]); 89 void ar5008_get_pdadcs(struct athn_softc *, uint8_t, struct athn_pier *, 90 struct athn_pier *, int, int, uint8_t, uint8_t *, uint8_t *); 91 void ar5008_get_lg_tpow(struct athn_softc *, struct ieee80211_channel *, 92 uint8_t, const struct ar_cal_target_power_leg *, int, uint8_t[]); 93 void ar5008_get_ht_tpow(struct athn_softc *, struct ieee80211_channel *, 94 uint8_t, const struct ar_cal_target_power_ht *, int, uint8_t[]); 95 int ar9280_set_synth(struct athn_softc *, struct ieee80211_channel *, 96 struct ieee80211_channel *); 97 void ar9280_spur_mitigate(struct athn_softc *, struct ieee80211_channel *, 98 struct ieee80211_channel *); 99 100 101 int 102 ar9285_attach(struct athn_softc *sc) 103 { 104 sc->eep_base = AR9285_EEP_START_LOC; 105 sc->eep_size = sizeof(struct ar9285_eeprom); 106 sc->def_nf = AR9285_PHY_CCA_MAX_GOOD_VALUE; 107 sc->ngpiopins = (sc->flags & ATHN_FLAG_USB) ? 16 : 12; 108 sc->led_pin = (sc->flags & ATHN_FLAG_USB) ? 15 : 1; 109 sc->workaround = AR9285_WA_DEFAULT; 110 sc->ops.setup = ar9285_setup; 111 sc->ops.swap_rom = ar9285_swap_rom; 112 sc->ops.init_from_rom = ar9285_init_from_rom; 113 sc->ops.set_txpower = ar9285_set_txpower; 114 sc->ops.set_synth = ar9280_set_synth; 115 sc->ops.spur_mitigate = ar9280_spur_mitigate; 116 sc->ops.get_spur_chans = ar9285_get_spur_chans; 117 #if NATHN_USB > 0 118 if (AR_SREV_9271(sc)) 119 sc->ini = &ar9271_ini; 120 else 121 #endif 122 sc->ini = &ar9285_1_2_ini; 123 sc->serdes = &ar9280_2_0_serdes; 124 125 return (ar5008_attach(sc)); 126 } 127 128 void 129 ar9285_setup(struct athn_softc *sc) 130 { 131 const struct ar9285_eeprom *eep = sc->eep; 132 uint8_t type; 133 134 /* Select initialization values based on ROM. */ 135 type = eep->baseEepHeader.txGainType; 136 DPRINTF(("Tx gain type=0x%x\n", type)); 137 #if NATHN_USB > 0 138 if (AR_SREV_9271(sc)) { 139 if (type == AR_EEP_TXGAIN_HIGH_POWER) 140 sc->tx_gain = &ar9271_tx_gain_high_power; 141 else 142 sc->tx_gain = &ar9271_tx_gain; 143 } else 144 #endif /* NATHN_USB */ 145 if ((AR_READ(sc, AR_AN_SYNTH9) & 0x7) == 0x1) { /* XE rev. */ 146 if (type == AR_EEP_TXGAIN_HIGH_POWER) 147 sc->tx_gain = &ar9285_2_0_tx_gain_high_power; 148 else 149 sc->tx_gain = &ar9285_2_0_tx_gain; 150 } else { 151 if (type == AR_EEP_TXGAIN_HIGH_POWER) 152 sc->tx_gain = &ar9285_1_2_tx_gain_high_power; 153 else 154 sc->tx_gain = &ar9285_1_2_tx_gain; 155 } 156 } 157 158 void 159 ar9285_swap_rom(struct athn_softc *sc) 160 { 161 struct ar9285_eeprom *eep = sc->eep; 162 int i; 163 164 eep->modalHeader.antCtrlCommon = 165 swap32(eep->modalHeader.antCtrlCommon); 166 eep->modalHeader.antCtrlChain = 167 swap32(eep->modalHeader.antCtrlChain); 168 169 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 170 eep->modalHeader.spurChans[i].spurChan = 171 swap16(eep->modalHeader.spurChans[i].spurChan); 172 } 173 } 174 175 const struct ar_spur_chan * 176 ar9285_get_spur_chans(struct athn_softc *sc, int is2ghz) 177 { 178 const struct ar9285_eeprom *eep = sc->eep; 179 180 KASSERT(is2ghz); 181 return (eep->modalHeader.spurChans); 182 } 183 184 void 185 ar9285_init_from_rom(struct athn_softc *sc, struct ieee80211_channel *c, 186 struct ieee80211_channel *extc) 187 { 188 const struct ar9285_eeprom *eep = sc->eep; 189 const struct ar9285_modal_eep_header *modal = &eep->modalHeader; 190 uint32_t reg, offset = 0x1000; 191 uint8_t ob[5], db1[5], db2[5]; 192 uint8_t txRxAtten; 193 194 AR_WRITE(sc, AR_PHY_SWITCH_COM, modal->antCtrlCommon); 195 AR_WRITE(sc, AR_PHY_SWITCH_CHAIN_0, modal->antCtrlChain); 196 197 reg = AR_READ(sc, AR_PHY_TIMING_CTRL4_0); 198 reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, modal->iqCalI); 199 reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, modal->iqCalQ); 200 AR_WRITE(sc, AR_PHY_TIMING_CTRL4_0, reg); 201 202 if (sc->eep_rev >= AR_EEP_MINOR_VER_3) { 203 reg = AR_READ(sc, AR_PHY_GAIN_2GHZ); 204 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, 205 modal->bswMargin); 206 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_DB, 207 modal->bswAtten); 208 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN, 209 modal->xatten2Margin); 210 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_DB, 211 modal->xatten2Db); 212 AR_WRITE(sc, AR_PHY_GAIN_2GHZ, reg); 213 214 /* Duplicate values of chain 0 for chain 1. */ 215 reg = AR_READ(sc, AR_PHY_GAIN_2GHZ + offset); 216 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, 217 modal->bswMargin); 218 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_DB, 219 modal->bswAtten); 220 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN, 221 modal->xatten2Margin); 222 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_DB, 223 modal->xatten2Db); 224 AR_WRITE(sc, AR_PHY_GAIN_2GHZ + offset, reg); 225 } 226 if (sc->eep_rev >= AR_EEP_MINOR_VER_3) 227 txRxAtten = modal->txRxAtten; 228 else /* Workaround for ROM versions < 14.3. */ 229 txRxAtten = 23; 230 reg = AR_READ(sc, AR_PHY_RXGAIN); 231 reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAtten); 232 reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_MARGIN, modal->rxTxMargin); 233 AR_WRITE(sc, AR_PHY_RXGAIN, reg); 234 235 /* Duplicate values of chain 0 for chain 1. */ 236 reg = AR_READ(sc, AR_PHY_RXGAIN + offset); 237 reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAtten); 238 reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_MARGIN, modal->rxTxMargin); 239 AR_WRITE(sc, AR_PHY_RXGAIN + offset, reg); 240 241 if (modal->version >= 3) { 242 /* Setup antenna diversity from ROM. */ 243 reg = AR_READ(sc, AR_PHY_MULTICHAIN_GAIN_CTL); 244 reg = RW(reg, AR9285_PHY_ANT_DIV_CTL_ALL, 0); 245 reg = RW(reg, AR9285_PHY_ANT_DIV_CTL, 246 (modal->ob_234 >> 12) & 0x1); 247 reg = RW(reg, AR9285_PHY_ANT_DIV_ALT_LNACONF, 248 (modal->db1_234 >> 12) & 0x3); 249 reg = RW(reg, AR9285_PHY_ANT_DIV_MAIN_LNACONF, 250 (modal->db1_234 >> 14) & 0x3); 251 reg = RW(reg, AR9285_PHY_ANT_DIV_ALT_GAINTB, 252 (modal->ob_234 >> 13) & 0x1); 253 reg = RW(reg, AR9285_PHY_ANT_DIV_MAIN_GAINTB, 254 (modal->ob_234 >> 14) & 0x1); 255 AR_WRITE(sc, AR_PHY_MULTICHAIN_GAIN_CTL, reg); 256 reg = AR_READ(sc, AR_PHY_MULTICHAIN_GAIN_CTL); /* Flush. */ 257 258 reg = AR_READ(sc, AR_PHY_CCK_DETECT); 259 if (modal->ob_234 & (1 << 15)) 260 reg |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV; 261 else 262 reg &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV; 263 AR_WRITE(sc, AR_PHY_CCK_DETECT, reg); 264 reg = AR_READ(sc, AR_PHY_CCK_DETECT); /* Flush. */ 265 } 266 if (modal->version >= 2) { 267 ob [0] = (modal->ob_01 >> 0) & 0xf; 268 ob [1] = (modal->ob_01 >> 4) & 0xf; 269 ob [2] = (modal->ob_234 >> 0) & 0xf; 270 ob [3] = (modal->ob_234 >> 4) & 0xf; 271 ob [4] = (modal->ob_234 >> 8) & 0xf; 272 273 db1[0] = (modal->db1_01 >> 0) & 0xf; 274 db1[1] = (modal->db1_01 >> 4) & 0xf; 275 db1[2] = (modal->db1_234 >> 0) & 0xf; 276 db1[3] = (modal->db1_234 >> 4) & 0xf; 277 db1[4] = (modal->db1_234 >> 8) & 0xf; 278 279 db2[0] = (modal->db2_01 >> 0) & 0xf; 280 db2[1] = (modal->db2_01 >> 4) & 0xf; 281 db2[2] = (modal->db2_234 >> 0) & 0xf; 282 db2[3] = (modal->db2_234 >> 4) & 0xf; 283 db2[4] = (modal->db2_234 >> 8) & 0xf; 284 285 } else if (modal->version == 1) { 286 ob [0] = (modal->ob_01 >> 0) & 0xf; 287 ob [1] = (modal->ob_01 >> 4) & 0xf; 288 /* Field ob_234 does not exist, use ob_01. */ 289 ob [2] = ob [3] = ob [4] = ob [1]; 290 291 db1[0] = (modal->db1_01 >> 0) & 0xf; 292 db1[1] = (modal->db1_01 >> 4) & 0xf; 293 /* Field db1_234 does not exist, use db1_01. */ 294 db1[2] = db1[3] = db1[4] = db1[1]; 295 296 db2[0] = (modal->db2_01 >> 0) & 0xf; 297 db2[1] = (modal->db2_01 >> 4) & 0xf; 298 /* Field db2_234 does not exist, use db2_01. */ 299 db2[2] = db2[3] = db2[4] = db2[1]; 300 301 } else { 302 ob [0] = modal->ob_01; 303 ob [1] = ob [2] = ob [3] = ob [4] = ob [0]; 304 305 db1[0] = modal->db1_01; 306 db1[1] = db1[2] = db1[3] = db1[4] = db1[0]; 307 308 /* Field db2_01 does not exist, use db1_01. */ 309 db2[0] = modal->db1_01; 310 db2[1] = db2[2] = db2[3] = db2[4] = db2[0]; 311 } 312 #if NATHN_USB > 0 313 if (AR_SREV_9271(sc)) { 314 reg = AR_READ(sc, AR9285_AN_RF2G3); 315 reg = RW(reg, AR9271_AN_RF2G3_OB_CCK, ob [0]); 316 reg = RW(reg, AR9271_AN_RF2G3_OB_PSK, ob [1]); 317 reg = RW(reg, AR9271_AN_RF2G3_OB_QAM, ob [2]); 318 reg = RW(reg, AR9271_AN_RF2G3_DB1, db1[0]); 319 AR_WRITE(sc, AR9285_AN_RF2G3, reg); 320 AR_WRITE_BARRIER(sc); 321 DELAY(100); 322 reg = AR_READ(sc, AR9285_AN_RF2G4); 323 reg = RW(reg, AR9271_AN_RF2G4_DB2, db2[0]); 324 AR_WRITE(sc, AR9285_AN_RF2G4, reg); 325 AR_WRITE_BARRIER(sc); 326 DELAY(100); 327 } else 328 #endif /* ATHN_USB */ 329 { 330 reg = AR_READ(sc, AR9285_AN_RF2G3); 331 reg = RW(reg, AR9285_AN_RF2G3_OB_0, ob [0]); 332 reg = RW(reg, AR9285_AN_RF2G3_OB_1, ob [1]); 333 reg = RW(reg, AR9285_AN_RF2G3_OB_2, ob [2]); 334 reg = RW(reg, AR9285_AN_RF2G3_OB_3, ob [3]); 335 reg = RW(reg, AR9285_AN_RF2G3_OB_4, ob [4]); 336 reg = RW(reg, AR9285_AN_RF2G3_DB1_0, db1[0]); 337 reg = RW(reg, AR9285_AN_RF2G3_DB1_1, db1[1]); 338 reg = RW(reg, AR9285_AN_RF2G3_DB1_2, db1[2]); 339 AR_WRITE(sc, AR9285_AN_RF2G3, reg); 340 AR_WRITE_BARRIER(sc); 341 DELAY(100); 342 reg = AR_READ(sc, AR9285_AN_RF2G4); 343 reg = RW(reg, AR9285_AN_RF2G4_DB1_3, db1[3]); 344 reg = RW(reg, AR9285_AN_RF2G4_DB1_4, db1[4]); 345 reg = RW(reg, AR9285_AN_RF2G4_DB2_0, db2[0]); 346 reg = RW(reg, AR9285_AN_RF2G4_DB2_1, db2[1]); 347 reg = RW(reg, AR9285_AN_RF2G4_DB2_2, db2[2]); 348 reg = RW(reg, AR9285_AN_RF2G4_DB2_3, db2[3]); 349 reg = RW(reg, AR9285_AN_RF2G4_DB2_4, db2[4]); 350 AR_WRITE(sc, AR9285_AN_RF2G4, reg); 351 AR_WRITE_BARRIER(sc); 352 DELAY(100); 353 } 354 355 reg = AR_READ(sc, AR_PHY_SETTLING); 356 reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->switchSettling); 357 AR_WRITE(sc, AR_PHY_SETTLING, reg); 358 359 reg = AR_READ(sc, AR_PHY_DESIRED_SZ); 360 reg = RW(reg, AR_PHY_DESIRED_SZ_ADC, modal->adcDesiredSize); 361 AR_WRITE(sc, AR_PHY_DESIRED_SZ, reg); 362 363 reg = SM(AR_PHY_RF_CTL4_TX_END_XPAA_OFF, modal->txEndToXpaOff); 364 reg |= SM(AR_PHY_RF_CTL4_TX_END_XPAB_OFF, modal->txEndToXpaOff); 365 reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAA_ON, modal->txFrameToXpaOn); 366 reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAB_ON, modal->txFrameToXpaOn); 367 AR_WRITE(sc, AR_PHY_RF_CTL4, reg); 368 369 reg = AR_READ(sc, AR_PHY_RF_CTL3); 370 reg = RW(reg, AR_PHY_TX_END_TO_A2_RX_ON, modal->txEndToRxOn); 371 AR_WRITE(sc, AR_PHY_RF_CTL3, reg); 372 373 reg = AR_READ(sc, AR_PHY_CCA(0)); 374 reg = RW(reg, AR9280_PHY_CCA_THRESH62, modal->thresh62); 375 AR_WRITE(sc, AR_PHY_CCA(0), reg); 376 377 reg = AR_READ(sc, AR_PHY_EXT_CCA0); 378 reg = RW(reg, AR_PHY_EXT_CCA0_THRESH62, modal->thresh62); 379 AR_WRITE(sc, AR_PHY_EXT_CCA0, reg); 380 381 if (sc->eep_rev >= AR_EEP_MINOR_VER_2) { 382 reg = AR_READ(sc, AR_PHY_RF_CTL2); 383 reg = RW(reg, AR_PHY_TX_END_PA_ON, 384 modal->txFrameToPaOn); 385 reg = RW(reg, AR_PHY_TX_END_DATA_START, 386 modal->txFrameToDataStart); 387 AR_WRITE(sc, AR_PHY_RF_CTL2, reg); 388 } 389 if (sc->eep_rev >= AR_EEP_MINOR_VER_3 && extc != NULL) { 390 reg = AR_READ(sc, AR_PHY_SETTLING); 391 reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->swSettleHt40); 392 AR_WRITE(sc, AR_PHY_SETTLING, reg); 393 } 394 AR_WRITE_BARRIER(sc); 395 } 396 397 void 398 ar9285_pa_calib(struct athn_softc *sc) 399 { 400 /* List of registers that need to be saved/restored. */ 401 static const uint16_t regs[] = { 402 AR9285_AN_TOP3, 403 AR9285_AN_RXTXBB1, 404 AR9285_AN_RF2G1, 405 AR9285_AN_RF2G2, 406 AR9285_AN_TOP2, 407 AR9285_AN_RF2G8, 408 AR9285_AN_RF2G7 409 }; 410 uint32_t svg[7], reg, ccomp_svg; 411 int i; 412 413 /* No PA calibration needed for high power solutions. */ 414 if (AR_SREV_9285(sc) && 415 ((struct ar9285_base_eep_header *)sc->eep)->txGainType == 416 AR_EEP_TXGAIN_HIGH_POWER) /* XXX AR9287? */ 417 return; 418 419 /* Save registers. */ 420 for (i = 0; i < nitems(regs); i++) 421 svg[i] = AR_READ(sc, regs[i]); 422 423 AR_CLRBITS(sc, AR9285_AN_RF2G6, 1); 424 AR_SETBITS(sc, AR_PHY(2), 1 << 27); 425 426 AR_SETBITS(sc, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC); 427 AR_SETBITS(sc, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1); 428 AR_SETBITS(sc, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I); 429 AR_SETBITS(sc, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF); 430 AR_CLRBITS(sc, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL); 431 AR_CLRBITS(sc, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB); 432 AR_CLRBITS(sc, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL); 433 /* Power down PA drivers. */ 434 AR_CLRBITS(sc, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1); 435 AR_CLRBITS(sc, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2); 436 AR_CLRBITS(sc, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT); 437 438 reg = AR_READ(sc, AR9285_AN_RF2G8); 439 reg = RW(reg, AR9285_AN_RF2G8_PADRVGN2TAB0, 7); 440 AR_WRITE(sc, AR9285_AN_RF2G8, reg); 441 442 reg = AR_READ(sc, AR9285_AN_RF2G7); 443 reg = RW(reg, AR9285_AN_RF2G7_PADRVGN2TAB0, 0); 444 AR_WRITE(sc, AR9285_AN_RF2G7, reg); 445 446 reg = AR_READ(sc, AR9285_AN_RF2G6); 447 /* Save compensation capacitor value. */ 448 ccomp_svg = MS(reg, AR9285_AN_RF2G6_CCOMP); 449 /* Program compensation capacitor for dynamic PA. */ 450 reg = RW(reg, AR9285_AN_RF2G6_CCOMP, 0xf); 451 AR_WRITE(sc, AR9285_AN_RF2G6, reg); 452 453 AR_WRITE(sc, AR9285_AN_TOP2, AR9285_AN_TOP2_DEFAULT); 454 AR_WRITE_BARRIER(sc); 455 DELAY(30); 456 457 /* Clear offsets 6-1. */ 458 AR_CLRBITS(sc, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS_6_1); 459 /* Clear offset 0. */ 460 AR_CLRBITS(sc, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP); 461 /* Set offsets 6-1. */ 462 for (i = 6; i >= 1; i--) { 463 AR_SETBITS(sc, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS(i)); 464 AR_WRITE_BARRIER(sc); 465 DELAY(1); 466 if (AR_READ(sc, AR9285_AN_RF2G9) & AR9285_AN_RXTXBB1_SPARE9) { 467 AR_SETBITS(sc, AR9285_AN_RF2G6, 468 AR9285_AN_RF2G6_OFFS(i)); 469 } else { 470 AR_CLRBITS(sc, AR9285_AN_RF2G6, 471 AR9285_AN_RF2G6_OFFS(i)); 472 } 473 } 474 /* Set offset 0. */ 475 AR_SETBITS(sc, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP); 476 AR_WRITE_BARRIER(sc); 477 DELAY(1); 478 if (AR_READ(sc, AR9285_AN_RF2G9) & AR9285_AN_RXTXBB1_SPARE9) 479 AR_SETBITS(sc, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP); 480 else 481 AR_CLRBITS(sc, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP); 482 483 AR_WRITE_BARRIER(sc); 484 485 AR_SETBITS(sc, AR9285_AN_RF2G6, 1); 486 AR_CLRBITS(sc, AR_PHY(2), 1 << 27); 487 488 /* Restore registers. */ 489 for (i = 0; i < nitems(regs); i++) 490 AR_WRITE(sc, regs[i], svg[i]); 491 492 /* Restore compensation capacitor value. */ 493 reg = AR_READ(sc, AR9285_AN_RF2G6); 494 reg = RW(reg, AR9285_AN_RF2G6_CCOMP, ccomp_svg); 495 AR_WRITE(sc, AR9285_AN_RF2G6, reg); 496 AR_WRITE_BARRIER(sc); 497 } 498 499 void 500 ar9271_pa_calib(struct athn_softc *sc) 501 { 502 #if NATHN_USB > 0 503 /* List of registers that need to be saved/restored. */ 504 static const uint16_t regs[] = { 505 AR9285_AN_TOP3, 506 AR9285_AN_RXTXBB1, 507 AR9285_AN_RF2G1, 508 AR9285_AN_RF2G2, 509 AR9285_AN_TOP2, 510 AR9285_AN_RF2G8, 511 AR9285_AN_RF2G7 512 }; 513 uint32_t svg[7], reg, rf2g3_svg; 514 int i; 515 516 /* Save registers. */ 517 for (i = 0; i < nitems(regs); i++) 518 svg[i] = AR_READ(sc, regs[i]); 519 520 AR_CLRBITS(sc, AR9285_AN_RF2G6, 1); 521 AR_SETBITS(sc, AR_PHY(2), 1 << 27); 522 523 AR_SETBITS(sc, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC); 524 AR_SETBITS(sc, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1); 525 AR_SETBITS(sc, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I); 526 AR_SETBITS(sc, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF); 527 AR_CLRBITS(sc, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL); 528 AR_CLRBITS(sc, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB); 529 AR_CLRBITS(sc, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL); 530 /* Power down PA drivers. */ 531 AR_CLRBITS(sc, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1); 532 AR_CLRBITS(sc, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2); 533 AR_CLRBITS(sc, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT); 534 535 reg = AR_READ(sc, AR9285_AN_RF2G8); 536 reg = RW(reg, AR9285_AN_RF2G8_PADRVGN2TAB0, 7); 537 AR_WRITE(sc, AR9285_AN_RF2G8, reg); 538 539 reg = AR_READ(sc, AR9285_AN_RF2G7); 540 reg = RW(reg, AR9285_AN_RF2G7_PADRVGN2TAB0, 0); 541 AR_WRITE(sc, AR9285_AN_RF2G7, reg); 542 543 /* Save compensation capacitor value. */ 544 reg = rf2g3_svg = AR_READ(sc, AR9285_AN_RF2G3); 545 /* Program compensation capacitor for dynamic PA. */ 546 reg = RW(reg, AR9271_AN_RF2G3_CCOMP, 0xfff); 547 AR_WRITE(sc, AR9285_AN_RF2G3, reg); 548 549 AR_WRITE(sc, AR9285_AN_TOP2, AR9285_AN_TOP2_DEFAULT); 550 AR_WRITE_BARRIER(sc); 551 DELAY(30); 552 553 /* Clear offsets 6-0. */ 554 AR_CLRBITS(sc, AR9285_AN_RF2G6, AR9271_AN_RF2G6_OFFS_6_0); 555 /* Set offsets 6-1. */ 556 for (i = 6; i >= 1; i--) { 557 reg = AR_READ(sc, AR9285_AN_RF2G6); 558 reg |= AR9271_AN_RF2G6_OFFS(i); 559 AR_WRITE(sc, AR9285_AN_RF2G6, reg); 560 AR_WRITE_BARRIER(sc); 561 DELAY(1); 562 if (!(AR_READ(sc, AR9285_AN_RF2G9) & AR9285_AN_RXTXBB1_SPARE9)) 563 reg &= ~AR9271_AN_RF2G6_OFFS(i); 564 AR_WRITE(sc, AR9285_AN_RF2G6, reg); 565 } 566 AR_WRITE_BARRIER(sc); 567 568 AR_SETBITS(sc, AR9285_AN_RF2G6, 1); 569 AR_CLRBITS(sc, AR_PHY(2), 1 << 27); 570 571 /* Restore registers. */ 572 for (i = 0; i < nitems(regs); i++) 573 AR_WRITE(sc, regs[i], svg[i]); 574 575 /* Restore compensation capacitor value. */ 576 AR_WRITE(sc, AR9285_AN_RF2G3, rf2g3_svg); 577 AR_WRITE_BARRIER(sc); 578 #endif /* NATHN_USB */ 579 } 580 581 /* 582 * Carrier Leakage Calibration. 583 */ 584 int 585 ar9285_cl_cal(struct athn_softc *sc, struct ieee80211_channel *c, 586 struct ieee80211_channel *extc) 587 { 588 int ntries; 589 590 AR_SETBITS(sc, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE); 591 if (0 && extc == NULL) { /* XXX IS_CHAN_HT20!! */ 592 AR_SETBITS(sc, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE); 593 AR_SETBITS(sc, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN); 594 AR_CLRBITS(sc, AR_PHY_AGC_CONTROL, 595 AR_PHY_AGC_CONTROL_FLTR_CAL); 596 AR_CLRBITS(sc, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE); 597 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL); 598 for (ntries = 0; ntries < 10000; ntries++) { 599 if (!(AR_READ(sc, AR_PHY_AGC_CONTROL) & 600 AR_PHY_AGC_CONTROL_CAL)) 601 break; 602 DELAY(10); 603 } 604 if (ntries == 10000) 605 return (ETIMEDOUT); 606 AR_CLRBITS(sc, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN); 607 AR_CLRBITS(sc, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE); 608 AR_CLRBITS(sc, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE); 609 } 610 AR_CLRBITS(sc, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC); 611 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL); 612 AR_SETBITS(sc, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE); 613 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL); 614 for (ntries = 0; ntries < 10000; ntries++) { 615 if (!(AR_READ(sc, AR_PHY_AGC_CONTROL) & 616 AR_PHY_AGC_CONTROL_CAL)) 617 break; 618 DELAY(10); 619 } 620 if (ntries == 10000) 621 return (ETIMEDOUT); 622 AR_SETBITS(sc, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC); 623 AR_CLRBITS(sc, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE); 624 AR_CLRBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL); 625 AR_WRITE_BARRIER(sc); 626 return (0); 627 } 628 629 void 630 ar9271_load_ani(struct athn_softc *sc) 631 { 632 #if NATHN_USB > 0 633 /* Write ANI registers. */ 634 AR_WRITE(sc, AR_PHY_DESIRED_SZ, 0x6d4000e2); 635 AR_WRITE(sc, AR_PHY_AGC_CTL1, 0x3139605e); 636 AR_WRITE(sc, AR_PHY_FIND_SIG, 0x7ec84d2e); 637 AR_WRITE(sc, AR_PHY_SFCORR_LOW, 0x06903881); 638 AR_WRITE(sc, AR_PHY_SFCORR, 0x5ac640d0); 639 AR_WRITE(sc, AR_PHY_CCK_DETECT, 0x803e68c8); 640 AR_WRITE(sc, AR_PHY_TIMING5, 0xd00a8007); 641 AR_WRITE(sc, AR_PHY_SFCORR_EXT, 0x05eea6d4); 642 AR_WRITE_BARRIER(sc); 643 #endif /* NATHN_USB */ 644 } 645 646 int 647 ar9285_init_calib(struct athn_softc *sc, struct ieee80211_channel *c, 648 struct ieee80211_channel *extc) 649 { 650 uint32_t reg, mask, clcgain, rf2g5_svg; 651 int i, maxgain, nclcs, thresh, error; 652 653 /* Do carrier leakage calibration. */ 654 if ((error = ar9285_cl_cal(sc, c, extc)) != 0) 655 return (error); 656 657 /* Workaround for high temperature is not applicable on AR9271. */ 658 if (AR_SREV_9271(sc)) 659 return (0); 660 661 mask = 0; 662 nclcs = 0; 663 reg = AR_READ(sc, AR_PHY_TX_PWRCTRL7); 664 maxgain = MS(reg, AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX); 665 for (i = 0; i <= maxgain; i++) { 666 reg = AR_READ(sc, AR_PHY_TX_GAIN_TBL(i)); 667 clcgain = MS(reg, AR_PHY_TX_GAIN_CLC); 668 /* NB: clcgain <= 0xf. */ 669 if (!(mask & (1 << clcgain))) { 670 mask |= 1 << clcgain; 671 nclcs++; 672 } 673 } 674 thresh = 0; 675 for (i = 0; i < nclcs; i++) { 676 reg = AR_READ(sc, AR_PHY_CLC_TBL(i)); 677 if (MS(reg, AR_PHY_CLC_I0) == 0) 678 thresh++; 679 if (MS(reg, AR_PHY_CLC_Q0) == 0) 680 thresh++; 681 } 682 if (thresh <= AR9285_CL_CAL_REDO_THRESH) 683 return (0); /* No need to redo. */ 684 685 /* Threshold reached, redo carrier leakage calibration. */ 686 DPRINTFN(2, ("CLC threshold=%d\n", thresh)); 687 rf2g5_svg = reg = AR_READ(sc, AR9285_AN_RF2G5); 688 if ((AR_READ(sc, AR_AN_SYNTH9) & 0x7) == 0x1) /* XE rev. */ 689 reg = RW(reg, AR9285_AN_RF2G5_IC50TX, 0x5); 690 else 691 reg = RW(reg, AR9285_AN_RF2G5_IC50TX, 0x4); 692 AR_WRITE(sc, AR9285_AN_RF2G5, reg); 693 AR_WRITE_BARRIER(sc); 694 error = ar9285_cl_cal(sc, c, extc); 695 AR_WRITE(sc, AR9285_AN_RF2G5, rf2g5_svg); 696 AR_WRITE_BARRIER(sc); 697 return (error); 698 } 699 700 void 701 ar9285_get_pdadcs(struct athn_softc *sc, struct ieee80211_channel *c, 702 int nxpdgains, uint8_t overlap, uint8_t *boundaries, uint8_t *pdadcs) 703 { 704 const struct ar9285_eeprom *eep = sc->eep; 705 const struct ar9285_cal_data_per_freq *pierdata; 706 const uint8_t *pierfreq; 707 struct athn_pier lopier, hipier; 708 uint8_t fbin; 709 int i, lo, hi, npiers; 710 711 pierfreq = eep->calFreqPier2G; 712 pierdata = eep->calPierData2G; 713 npiers = AR9285_NUM_2G_CAL_PIERS; 714 715 /* Find channel in ROM pier table. */ 716 fbin = athn_chan2fbin(c); 717 athn_get_pier_ival(fbin, pierfreq, npiers, &lo, &hi); 718 719 lopier.fbin = pierfreq[lo]; 720 hipier.fbin = pierfreq[hi]; 721 for (i = 0; i < nxpdgains; i++) { 722 lopier.pwr[i] = pierdata[lo].pwrPdg[i]; 723 lopier.vpd[i] = pierdata[lo].vpdPdg[i]; 724 hipier.pwr[i] = pierdata[lo].pwrPdg[i]; 725 hipier.vpd[i] = pierdata[lo].vpdPdg[i]; 726 } 727 ar5008_get_pdadcs(sc, fbin, &lopier, &hipier, nxpdgains, 728 AR9285_PD_GAIN_ICEPTS, overlap, boundaries, pdadcs); 729 } 730 731 void 732 ar9285_set_power_calib(struct athn_softc *sc, struct ieee80211_channel *c) 733 { 734 const struct ar9285_eeprom *eep = sc->eep; 735 uint8_t boundaries[AR_PD_GAINS_IN_MASK]; 736 uint8_t pdadcs[AR_NUM_PDADC_VALUES]; 737 uint8_t xpdgains[AR9285_NUM_PD_GAINS]; 738 uint8_t overlap; 739 uint32_t reg; 740 int i, nxpdgains; 741 742 if (sc->eep_rev < AR_EEP_MINOR_VER_2) { 743 overlap = MS(AR_READ(sc, AR_PHY_TPCRG5), 744 AR_PHY_TPCRG5_PD_GAIN_OVERLAP); 745 } else 746 overlap = eep->modalHeader.pdGainOverlap; 747 748 nxpdgains = 0; 749 memset(xpdgains, 0, sizeof(xpdgains)); 750 for (i = AR9285_PD_GAINS_IN_MASK - 1; i >= 0; i--) { 751 if (nxpdgains >= AR9285_NUM_PD_GAINS) 752 break; 753 if (eep->modalHeader.xpdGain & (1 << i)) 754 xpdgains[nxpdgains++] = i; 755 } 756 reg = AR_READ(sc, AR_PHY_TPCRG1); 757 reg = RW(reg, AR_PHY_TPCRG1_NUM_PD_GAIN, nxpdgains - 1); 758 reg = RW(reg, AR_PHY_TPCRG1_PD_GAIN_1, xpdgains[0]); 759 reg = RW(reg, AR_PHY_TPCRG1_PD_GAIN_2, xpdgains[1]); 760 AR_WRITE(sc, AR_PHY_TPCRG1, reg); 761 762 /* NB: No open loop power control for AR9285. */ 763 ar9285_get_pdadcs(sc, c, nxpdgains, overlap, boundaries, pdadcs); 764 765 /* Write boundaries. */ 766 reg = SM(AR_PHY_TPCRG5_PD_GAIN_OVERLAP, overlap); 767 reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1, boundaries[0]); 768 reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2, boundaries[1]); 769 reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3, boundaries[2]); 770 reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4, boundaries[3]); 771 AR_WRITE(sc, AR_PHY_TPCRG5, reg); 772 773 /* Write PDADC values. */ 774 for (i = 0; i < AR_NUM_PDADC_VALUES; i += 4) { 775 AR_WRITE(sc, AR_PHY_PDADC_TBL_BASE + i, 776 pdadcs[i + 0] << 0 | 777 pdadcs[i + 1] << 8 | 778 pdadcs[i + 2] << 16 | 779 pdadcs[i + 3] << 24); 780 } 781 AR_WRITE_BARRIER(sc); 782 } 783 784 void 785 ar9285_set_txpower(struct athn_softc *sc, struct ieee80211_channel *c, 786 struct ieee80211_channel *extc) 787 { 788 const struct ar9285_eeprom *eep = sc->eep; 789 const struct ar9285_modal_eep_header *modal = &eep->modalHeader; 790 uint8_t tpow_cck[4], tpow_ofdm[4]; 791 uint8_t tpow_cck_ext[4], tpow_ofdm_ext[4]; 792 uint8_t tpow_ht20[8], tpow_ht40[8]; 793 uint8_t ht40inc; 794 int16_t max_ant_gain, power[ATHN_POWER_COUNT]; 795 int i; 796 797 ar9285_set_power_calib(sc, c); 798 799 /* Compute transmit power reduction due to antenna gain. */ 800 max_ant_gain = modal->antennaGain; 801 /* XXX */ 802 803 /* Get CCK target powers. */ 804 ar5008_get_lg_tpow(sc, c, AR_CTL_11B, eep->calTargetPowerCck, 805 AR9285_NUM_2G_CCK_TARGET_POWERS, tpow_cck); 806 807 /* Get OFDM target powers. */ 808 ar5008_get_lg_tpow(sc, c, AR_CTL_11G, eep->calTargetPower2G, 809 AR9285_NUM_2G_20_TARGET_POWERS, tpow_ofdm); 810 811 /* Get HT-20 target powers. */ 812 ar5008_get_ht_tpow(sc, c, AR_CTL_2GHT20, eep->calTargetPower2GHT20, 813 AR9285_NUM_2G_20_TARGET_POWERS, tpow_ht20); 814 815 if (extc != NULL) { 816 /* Get HT-40 target powers. */ 817 ar5008_get_ht_tpow(sc, c, AR_CTL_2GHT40, 818 eep->calTargetPower2GHT40, AR9285_NUM_2G_40_TARGET_POWERS, 819 tpow_ht40); 820 821 /* Get secondary channel CCK target powers. */ 822 ar5008_get_lg_tpow(sc, extc, AR_CTL_11B, 823 eep->calTargetPowerCck, AR9285_NUM_2G_CCK_TARGET_POWERS, 824 tpow_cck_ext); 825 826 /* Get secondary channel OFDM target powers. */ 827 ar5008_get_lg_tpow(sc, extc, AR_CTL_11G, 828 eep->calTargetPower2G, AR9285_NUM_2G_20_TARGET_POWERS, 829 tpow_ofdm_ext); 830 } 831 832 memset(power, 0, sizeof(power)); 833 /* Shuffle target powers accross transmit rates. */ 834 power[ATHN_POWER_OFDM6 ] = 835 power[ATHN_POWER_OFDM9 ] = 836 power[ATHN_POWER_OFDM12 ] = 837 power[ATHN_POWER_OFDM18 ] = 838 power[ATHN_POWER_OFDM24 ] = tpow_ofdm[0]; 839 power[ATHN_POWER_OFDM36 ] = tpow_ofdm[1]; 840 power[ATHN_POWER_OFDM48 ] = tpow_ofdm[2]; 841 power[ATHN_POWER_OFDM54 ] = tpow_ofdm[3]; 842 power[ATHN_POWER_XR ] = tpow_ofdm[0]; 843 power[ATHN_POWER_CCK1_LP ] = tpow_cck[0]; 844 power[ATHN_POWER_CCK2_LP ] = 845 power[ATHN_POWER_CCK2_SP ] = tpow_cck[1]; 846 power[ATHN_POWER_CCK55_LP] = 847 power[ATHN_POWER_CCK55_SP] = tpow_cck[2]; 848 power[ATHN_POWER_CCK11_LP] = 849 power[ATHN_POWER_CCK11_SP] = tpow_cck[3]; 850 for (i = 0; i < nitems(tpow_ht20); i++) 851 power[ATHN_POWER_HT20(i)] = tpow_ht20[i]; 852 if (extc != NULL) { 853 /* Correct PAR difference between HT40 and HT20/Legacy. */ 854 if (sc->eep_rev >= AR_EEP_MINOR_VER_2) 855 ht40inc = modal->ht40PowerIncForPdadc; 856 else 857 ht40inc = AR_HT40_POWER_INC_FOR_PDADC; 858 for (i = 0; i < nitems(tpow_ht40); i++) 859 power[ATHN_POWER_HT40(i)] = tpow_ht40[i] + ht40inc; 860 power[ATHN_POWER_OFDM_DUP] = tpow_ht40[0]; 861 power[ATHN_POWER_CCK_DUP ] = tpow_ht40[0]; 862 power[ATHN_POWER_OFDM_EXT] = tpow_ofdm_ext[0]; 863 power[ATHN_POWER_CCK_EXT ] = tpow_cck_ext[0]; 864 } 865 866 for (i = 0; i < ATHN_POWER_COUNT; i++) { 867 power[i] -= AR_PWR_TABLE_OFFSET_DB * 2; /* In half dB. */ 868 if (power[i] > AR_MAX_RATE_POWER) 869 power[i] = AR_MAX_RATE_POWER; 870 } 871 872 /* Commit transmit power values to hardware. */ 873 ar5008_write_txpower(sc, power); 874 } 875