1 /* $OpenBSD: ar9003.c,v 1.39 2016/01/05 18:41:15 stsp Exp $ */ 2 3 /*- 4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2010 Atheros Communications Inc. 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Driver for Atheros 802.11a/g/n chipsets. 22 * Routines for AR9003 family. 23 */ 24 25 #include "bpfilter.h" 26 27 #include <sys/param.h> 28 #include <sys/sockio.h> 29 #include <sys/mbuf.h> 30 #include <sys/kernel.h> 31 #include <sys/socket.h> 32 #include <sys/systm.h> 33 #include <sys/malloc.h> 34 #include <sys/queue.h> 35 #include <sys/timeout.h> 36 #include <sys/conf.h> 37 #include <sys/device.h> 38 #include <sys/stdint.h> /* uintptr_t */ 39 #include <sys/endian.h> 40 41 #include <machine/bus.h> 42 43 #if NBPFILTER > 0 44 #include <net/bpf.h> 45 #endif 46 #include <net/if.h> 47 #include <net/if_media.h> 48 49 #include <netinet/in.h> 50 #include <netinet/if_ether.h> 51 52 #include <net80211/ieee80211_var.h> 53 #include <net80211/ieee80211_amrr.h> 54 #include <net80211/ieee80211_radiotap.h> 55 56 #include <dev/ic/athnreg.h> 57 #include <dev/ic/athnvar.h> 58 59 #include <dev/ic/ar9003reg.h> 60 61 int ar9003_attach(struct athn_softc *); 62 int ar9003_read_eep_word(struct athn_softc *, uint32_t, uint16_t *); 63 int ar9003_read_eep_data(struct athn_softc *, uint32_t, void *, int); 64 int ar9003_read_otp_word(struct athn_softc *, uint32_t, uint32_t *); 65 int ar9003_read_otp_data(struct athn_softc *, uint32_t, void *, int); 66 int ar9003_find_rom(struct athn_softc *); 67 int ar9003_restore_rom_block(struct athn_softc *, uint8_t, uint8_t, 68 const uint8_t *, int); 69 int ar9003_read_rom(struct athn_softc *); 70 int ar9003_gpio_read(struct athn_softc *, int); 71 void ar9003_gpio_write(struct athn_softc *, int, int); 72 void ar9003_gpio_config_input(struct athn_softc *, int); 73 void ar9003_gpio_config_output(struct athn_softc *, int, int); 74 void ar9003_rfsilent_init(struct athn_softc *); 75 int ar9003_dma_alloc(struct athn_softc *); 76 void ar9003_dma_free(struct athn_softc *); 77 int ar9003_tx_alloc(struct athn_softc *); 78 void ar9003_tx_free(struct athn_softc *); 79 int ar9003_rx_alloc(struct athn_softc *, int, int); 80 void ar9003_rx_free(struct athn_softc *, int); 81 void ar9003_reset_txsring(struct athn_softc *); 82 void ar9003_rx_enable(struct athn_softc *); 83 void ar9003_rx_radiotap(struct athn_softc *, struct mbuf *, 84 struct ar_rx_status *); 85 int ar9003_rx_process(struct athn_softc *, int); 86 void ar9003_rx_intr(struct athn_softc *, int); 87 int ar9003_tx_process(struct athn_softc *); 88 void ar9003_tx_intr(struct athn_softc *); 89 int ar9003_swba_intr(struct athn_softc *); 90 int ar9003_intr(struct athn_softc *); 91 int ar9003_tx(struct athn_softc *, struct mbuf *, struct ieee80211_node *, 92 int); 93 void ar9003_set_rf_mode(struct athn_softc *, struct ieee80211_channel *); 94 int ar9003_rf_bus_request(struct athn_softc *); 95 void ar9003_rf_bus_release(struct athn_softc *); 96 void ar9003_set_phy(struct athn_softc *, struct ieee80211_channel *, 97 struct ieee80211_channel *); 98 void ar9003_set_delta_slope(struct athn_softc *, struct ieee80211_channel *, 99 struct ieee80211_channel *); 100 void ar9003_enable_antenna_diversity(struct athn_softc *); 101 void ar9003_init_baseband(struct athn_softc *); 102 void ar9003_disable_phy(struct athn_softc *); 103 void ar9003_init_chains(struct athn_softc *); 104 void ar9003_set_rxchains(struct athn_softc *); 105 void ar9003_read_noisefloor(struct athn_softc *, int16_t *, int16_t *); 106 void ar9003_write_noisefloor(struct athn_softc *, int16_t *, int16_t *); 107 void ar9003_get_noisefloor(struct athn_softc *, struct ieee80211_channel *); 108 void ar9003_bb_load_noisefloor(struct athn_softc *); 109 void ar9300_noisefloor_calib(struct athn_softc *); 110 void ar9003_do_noisefloor_calib(struct athn_softc *); 111 int ar9003_init_calib(struct athn_softc *); 112 void ar9003_do_calib(struct athn_softc *); 113 void ar9003_next_calib(struct athn_softc *); 114 void ar9003_calib_iq(struct athn_softc *); 115 int ar9003_get_iq_corr(struct athn_softc *, int32_t[], int32_t[]); 116 int ar9003_calib_tx_iq(struct athn_softc *); 117 void ar9003_paprd_calib(struct athn_softc *, struct ieee80211_channel *); 118 int ar9003_get_desired_txgain(struct athn_softc *, int, int); 119 void ar9003_force_txgain(struct athn_softc *, uint32_t); 120 void ar9003_set_training_gain(struct athn_softc *, int); 121 int ar9003_paprd_tx_tone(struct athn_softc *); 122 int ar9003_compute_predistortion(struct athn_softc *, const uint32_t *, 123 const uint32_t *); 124 void ar9003_enable_predistorter(struct athn_softc *, int); 125 void ar9003_paprd_enable(struct athn_softc *); 126 void ar9003_paprd_tx_tone_done(struct athn_softc *); 127 void ar9003_write_txpower(struct athn_softc *, int16_t power[]); 128 void ar9003_reset_rx_gain(struct athn_softc *, struct ieee80211_channel *); 129 void ar9003_reset_tx_gain(struct athn_softc *, struct ieee80211_channel *); 130 void ar9003_hw_init(struct athn_softc *, struct ieee80211_channel *, 131 struct ieee80211_channel *); 132 void ar9003_get_lg_tpow(struct athn_softc *, struct ieee80211_channel *, 133 uint8_t, const uint8_t *, const struct ar_cal_target_power_leg *, 134 int, uint8_t[]); 135 void ar9003_get_ht_tpow(struct athn_softc *, struct ieee80211_channel *, 136 uint8_t, const uint8_t *, const struct ar_cal_target_power_ht *, 137 int, uint8_t[]); 138 void ar9003_set_noise_immunity_level(struct athn_softc *, int); 139 void ar9003_enable_ofdm_weak_signal(struct athn_softc *); 140 void ar9003_disable_ofdm_weak_signal(struct athn_softc *); 141 void ar9003_set_cck_weak_signal(struct athn_softc *, int); 142 void ar9003_set_firstep_level(struct athn_softc *, int); 143 void ar9003_set_spur_immunity_level(struct athn_softc *, int); 144 145 /* Extern functions. */ 146 void athn_stop(struct ifnet *, int); 147 int athn_interpolate(int, int, int, int, int); 148 int athn_txtime(struct athn_softc *, int, int, u_int); 149 void athn_inc_tx_trigger_level(struct athn_softc *); 150 int athn_tx_pending(struct athn_softc *, int); 151 void athn_stop_tx_dma(struct athn_softc *, int); 152 void athn_get_delta_slope(uint32_t, uint32_t *, uint32_t *); 153 void athn_config_pcie(struct athn_softc *); 154 void athn_config_nonpcie(struct athn_softc *); 155 uint8_t athn_chan2fbin(struct ieee80211_channel *); 156 157 158 int 159 ar9003_attach(struct athn_softc *sc) 160 { 161 struct athn_ops *ops = &sc->ops; 162 int error; 163 164 /* Set callbacks for AR9003 family. */ 165 ops->gpio_read = ar9003_gpio_read; 166 ops->gpio_write = ar9003_gpio_write; 167 ops->gpio_config_input = ar9003_gpio_config_input; 168 ops->gpio_config_output = ar9003_gpio_config_output; 169 ops->rfsilent_init = ar9003_rfsilent_init; 170 171 ops->dma_alloc = ar9003_dma_alloc; 172 ops->dma_free = ar9003_dma_free; 173 ops->rx_enable = ar9003_rx_enable; 174 ops->intr = ar9003_intr; 175 ops->tx = ar9003_tx; 176 177 ops->set_rf_mode = ar9003_set_rf_mode; 178 ops->rf_bus_request = ar9003_rf_bus_request; 179 ops->rf_bus_release = ar9003_rf_bus_release; 180 ops->set_phy = ar9003_set_phy; 181 ops->set_delta_slope = ar9003_set_delta_slope; 182 ops->enable_antenna_diversity = ar9003_enable_antenna_diversity; 183 ops->init_baseband = ar9003_init_baseband; 184 ops->disable_phy = ar9003_disable_phy; 185 ops->set_rxchains = ar9003_set_rxchains; 186 ops->noisefloor_calib = ar9003_do_noisefloor_calib; 187 ops->do_calib = ar9003_do_calib; 188 ops->next_calib = ar9003_next_calib; 189 ops->hw_init = ar9003_hw_init; 190 191 ops->set_noise_immunity_level = ar9003_set_noise_immunity_level; 192 ops->enable_ofdm_weak_signal = ar9003_enable_ofdm_weak_signal; 193 ops->disable_ofdm_weak_signal = ar9003_disable_ofdm_weak_signal; 194 ops->set_cck_weak_signal = ar9003_set_cck_weak_signal; 195 ops->set_firstep_level = ar9003_set_firstep_level; 196 ops->set_spur_immunity_level = ar9003_set_spur_immunity_level; 197 198 /* Set MAC registers offsets. */ 199 sc->obs_off = AR_OBS; 200 sc->gpio_input_en_off = AR_GPIO_INPUT_EN_VAL; 201 202 if (!(sc->flags & ATHN_FLAG_PCIE)) 203 athn_config_nonpcie(sc); 204 else 205 athn_config_pcie(sc); 206 207 /* Determine ROM type and location. */ 208 if ((error = ar9003_find_rom(sc)) != 0) { 209 printf("%s: could not find ROM\n", sc->sc_dev.dv_xname); 210 return (error); 211 } 212 /* Read entire ROM content in memory. */ 213 if ((error = ar9003_read_rom(sc)) != 0) { 214 printf("%s: could not read ROM\n", sc->sc_dev.dv_xname); 215 return (error); 216 } 217 218 /* Determine if it is a non-enterprise AR9003 card. */ 219 if (AR_READ(sc, AR_ENT_OTP) & AR_ENT_OTP_MPSD) 220 sc->flags |= ATHN_FLAG_NON_ENTERPRISE; 221 222 ops->setup(sc); 223 return (0); 224 } 225 226 /* 227 * Read 16-bit word from EEPROM. 228 */ 229 int 230 ar9003_read_eep_word(struct athn_softc *sc, uint32_t addr, uint16_t *val) 231 { 232 uint32_t reg; 233 int ntries; 234 235 reg = AR_READ(sc, AR_EEPROM_OFFSET(addr)); 236 for (ntries = 0; ntries < 1000; ntries++) { 237 reg = AR_READ(sc, AR_EEPROM_STATUS_DATA); 238 if (!(reg & (AR_EEPROM_STATUS_DATA_BUSY | 239 AR_EEPROM_STATUS_DATA_PROT_ACCESS))) { 240 *val = MS(reg, AR_EEPROM_STATUS_DATA_VAL); 241 return (0); 242 } 243 DELAY(10); 244 } 245 *val = 0xffff; 246 return (ETIMEDOUT); 247 } 248 249 /* 250 * Read an arbitrary number of bytes at a specified address in EEPROM. 251 * NB: The address may not be 16-bit aligned. 252 */ 253 int 254 ar9003_read_eep_data(struct athn_softc *sc, uint32_t addr, void *buf, int len) 255 { 256 uint8_t *dst = buf; 257 uint16_t val; 258 int error; 259 260 if (len > 0 && (addr & 1)) { 261 /* Deal with non-aligned reads. */ 262 addr >>= 1; 263 error = ar9003_read_eep_word(sc, addr, &val); 264 if (error != 0) 265 return (error); 266 *dst++ = val & 0xff; 267 addr--; 268 len--; 269 } else 270 addr >>= 1; 271 for (; len >= 2; addr--, len -= 2) { 272 error = ar9003_read_eep_word(sc, addr, &val); 273 if (error != 0) 274 return (error); 275 *dst++ = val >> 8; 276 *dst++ = val & 0xff; 277 } 278 if (len > 0) { 279 error = ar9003_read_eep_word(sc, addr, &val); 280 if (error != 0) 281 return (error); 282 *dst++ = val >> 8; 283 } 284 return (0); 285 } 286 287 /* 288 * Read 32-bit word from OTPROM. 289 */ 290 int 291 ar9003_read_otp_word(struct athn_softc *sc, uint32_t addr, uint32_t *val) 292 { 293 uint32_t reg; 294 int ntries; 295 296 reg = AR_READ(sc, AR_OTP_BASE(addr)); 297 for (ntries = 0; ntries < 1000; ntries++) { 298 reg = AR_READ(sc, AR_OTP_STATUS); 299 if (MS(reg, AR_OTP_STATUS_TYPE) == AR_OTP_STATUS_VALID) { 300 *val = AR_READ(sc, AR_OTP_READ_DATA); 301 return (0); 302 } 303 DELAY(10); 304 } 305 return (ETIMEDOUT); 306 } 307 308 /* 309 * Read an arbitrary number of bytes at a specified address in OTPROM. 310 * NB: The address may not be 32-bit aligned. 311 */ 312 int 313 ar9003_read_otp_data(struct athn_softc *sc, uint32_t addr, void *buf, int len) 314 { 315 uint8_t *dst = buf; 316 uint32_t val; 317 int error; 318 319 /* NB: not optimal for non-aligned reads, but correct. */ 320 for (; len > 0; addr--, len--) { 321 error = ar9003_read_otp_word(sc, addr >> 2, &val); 322 if (error != 0) 323 return (error); 324 *dst++ = (val >> ((addr & 3) * 8)) & 0xff; 325 } 326 return (0); 327 } 328 329 /* 330 * Determine if the chip has an external EEPROM or an OTPROM and its size. 331 */ 332 int 333 ar9003_find_rom(struct athn_softc *sc) 334 { 335 struct athn_ops *ops = &sc->ops; 336 uint32_t hdr; 337 int error; 338 339 /* Try EEPROM. */ 340 ops->read_rom_data = ar9003_read_eep_data; 341 342 sc->eep_size = AR_SREV_9485(sc) ? 4096 : 1024; 343 sc->eep_base = sc->eep_size - 1; 344 error = ops->read_rom_data(sc, sc->eep_base, &hdr, sizeof(hdr)); 345 if (error == 0 && hdr != 0 && hdr != 0xffffffff) 346 return (0); 347 348 sc->eep_size = 512; 349 sc->eep_base = sc->eep_size - 1; 350 error = ops->read_rom_data(sc, sc->eep_base, &hdr, sizeof(hdr)); 351 if (error == 0 && hdr != 0 && hdr != 0xffffffff) 352 return (0); 353 354 /* Try OTPROM. */ 355 ops->read_rom_data = ar9003_read_otp_data; 356 357 sc->eep_size = 1024; 358 sc->eep_base = sc->eep_size - 1; 359 error = ops->read_rom_data(sc, sc->eep_base, &hdr, sizeof(hdr)); 360 if (error == 0 && hdr != 0 && hdr != 0xffffffff) 361 return (0); 362 363 sc->eep_size = 512; 364 sc->eep_base = sc->eep_size - 1; 365 error = ops->read_rom_data(sc, sc->eep_base, &hdr, sizeof(hdr)); 366 if (error == 0 && hdr != 0 && hdr != 0xffffffff) 367 return (0); 368 369 return (EIO); /* Not found. */ 370 } 371 372 int 373 ar9003_restore_rom_block(struct athn_softc *sc, uint8_t alg, uint8_t ref, 374 const uint8_t *buf, int len) 375 { 376 const uint8_t *def, *ptr, *end; 377 uint8_t *eep = sc->eep; 378 int off, clen; 379 380 if (alg == AR_EEP_COMPRESS_BLOCK) { 381 /* Block contains chunks that shadow ROM template. */ 382 def = sc->ops.get_rom_template(sc, ref); 383 if (def == NULL) { 384 DPRINTF(("unknown template image %d\n", ref)); 385 return (EINVAL); 386 } 387 /* Start with template. */ 388 memcpy(eep, def, sc->eep_size); 389 /* Shadow template with chunks. */ 390 off = 0; /* Offset in ROM image. */ 391 ptr = buf; /* Offset in block. */ 392 end = buf + len; 393 /* Process chunks. */ 394 while (ptr + 2 <= end) { 395 off += *ptr++; /* Gap with previous chunk. */ 396 clen = *ptr++; /* Chunk length. */ 397 /* Make sure block is large enough. */ 398 if (ptr + clen > end) 399 return (EINVAL); 400 /* Make sure chunk fits in ROM image. */ 401 if (off + clen > sc->eep_size) 402 return (EINVAL); 403 /* Restore chunk. */ 404 DPRINTFN(2, ("ROM chunk @%d/%d\n", off, clen)); 405 memcpy(&eep[off], ptr, clen); 406 ptr += clen; 407 off += clen; 408 } 409 } else if (alg == AR_EEP_COMPRESS_NONE) { 410 /* Block contains full ROM image. */ 411 if (len != sc->eep_size) { 412 DPRINTF(("block length mismatch %d\n", len)); 413 return (EINVAL); 414 } 415 memcpy(eep, buf, len); 416 } 417 return (0); 418 } 419 420 int 421 ar9003_read_rom(struct athn_softc *sc) 422 { 423 struct athn_ops *ops = &sc->ops; 424 uint8_t *buf, *ptr, alg, ref; 425 uint16_t sum, rsum; 426 uint32_t hdr; 427 int error, addr, len, i, j; 428 429 /* Allocate space to store ROM in host memory. */ 430 sc->eep = malloc(sc->eep_size, M_DEVBUF, M_NOWAIT); 431 if (sc->eep == NULL) 432 return (ENOMEM); 433 434 /* Allocate temporary buffer to store ROM blocks. */ 435 buf = malloc(2048, M_DEVBUF, M_NOWAIT); 436 if (buf == NULL) 437 return (ENOMEM); 438 439 /* Restore vendor-specified ROM blocks. */ 440 addr = sc->eep_base; 441 for (i = 0; i < 100; i++) { 442 /* Read block header. */ 443 error = ops->read_rom_data(sc, addr, &hdr, sizeof(hdr)); 444 if (error != 0) 445 break; 446 if (hdr == 0 || hdr == 0xffffffff) 447 break; 448 addr -= sizeof(hdr); 449 450 /* Extract bits from header. */ 451 ptr = (uint8_t *)&hdr; 452 alg = (ptr[0] & 0xe0) >> 5; 453 ref = (ptr[1] & 0x80) >> 2 | (ptr[0] & 0x1f); 454 len = (ptr[1] & 0x7f) << 4 | (ptr[2] & 0xf0) >> 4; 455 DPRINTFN(2, ("ROM block %d: alg=%d ref=%d len=%d\n", 456 i, alg, ref, len)); 457 458 /* Read block data (len <= 0x7ff). */ 459 error = ops->read_rom_data(sc, addr, buf, len); 460 if (error != 0) 461 break; 462 addr -= len; 463 464 /* Read block checksum. */ 465 error = ops->read_rom_data(sc, addr, &sum, sizeof(sum)); 466 if (error != 0) 467 break; 468 addr -= sizeof(sum); 469 470 /* Compute block checksum. */ 471 rsum = 0; 472 for (j = 0; j < len; j++) 473 rsum += buf[j]; 474 /* Compare to that in ROM. */ 475 if (letoh16(sum) != rsum) { 476 DPRINTF(("bad block checksum 0x%x/0x%x\n", 477 letoh16(sum), rsum)); 478 continue; /* Skip bad block. */ 479 } 480 /* Checksum is correct, restore block. */ 481 ar9003_restore_rom_block(sc, alg, ref, buf, len); 482 } 483 #if BYTE_ORDER == BIG_ENDIAN 484 /* NB: ROM is always little endian. */ 485 if (error == 0) 486 ops->swap_rom(sc); 487 #endif 488 free(buf, M_DEVBUF, 0); 489 return (error); 490 } 491 492 /* 493 * Access to General Purpose Input/Output ports. 494 */ 495 int 496 ar9003_gpio_read(struct athn_softc *sc, int pin) 497 { 498 KASSERT(pin < sc->ngpiopins); 499 return (((AR_READ(sc, AR_GPIO_IN) & AR9300_GPIO_IN_VAL) & 500 (1 << pin)) != 0); 501 } 502 503 void 504 ar9003_gpio_write(struct athn_softc *sc, int pin, int set) 505 { 506 uint32_t reg; 507 508 KASSERT(pin < sc->ngpiopins); 509 reg = AR_READ(sc, AR_GPIO_IN_OUT); 510 if (set) 511 reg |= 1 << pin; 512 else 513 reg &= ~(1 << pin); 514 AR_WRITE(sc, AR_GPIO_IN_OUT, reg); 515 AR_WRITE_BARRIER(sc); 516 } 517 518 void 519 ar9003_gpio_config_input(struct athn_softc *sc, int pin) 520 { 521 uint32_t reg; 522 523 reg = AR_READ(sc, AR_GPIO_OE_OUT); 524 reg &= ~(AR_GPIO_OE_OUT_DRV_M << (pin * 2)); 525 reg |= AR_GPIO_OE_OUT_DRV_NO << (pin * 2); 526 AR_WRITE(sc, AR_GPIO_OE_OUT, reg); 527 AR_WRITE_BARRIER(sc); 528 } 529 530 void 531 ar9003_gpio_config_output(struct athn_softc *sc, int pin, int type) 532 { 533 uint32_t reg; 534 int mux, off; 535 536 mux = pin / 6; 537 off = pin % 6; 538 539 reg = AR_READ(sc, AR_GPIO_OUTPUT_MUX(mux)); 540 reg &= ~(0x1f << (off * 5)); 541 reg |= (type & 0x1f) << (off * 5); 542 AR_WRITE(sc, AR_GPIO_OUTPUT_MUX(mux), reg); 543 544 reg = AR_READ(sc, AR_GPIO_OE_OUT); 545 reg &= ~(AR_GPIO_OE_OUT_DRV_M << (pin * 2)); 546 reg |= AR_GPIO_OE_OUT_DRV_ALL << (pin * 2); 547 AR_WRITE(sc, AR_GPIO_OE_OUT, reg); 548 AR_WRITE_BARRIER(sc); 549 } 550 551 void 552 ar9003_rfsilent_init(struct athn_softc *sc) 553 { 554 uint32_t reg; 555 556 /* Configure hardware radio switch. */ 557 AR_SETBITS(sc, AR_GPIO_INPUT_EN_VAL, AR_GPIO_INPUT_EN_VAL_RFSILENT_BB); 558 reg = AR_READ(sc, AR_GPIO_INPUT_MUX2); 559 reg = RW(reg, AR_GPIO_INPUT_MUX2_RFSILENT, 0); 560 AR_WRITE(sc, AR_GPIO_INPUT_MUX2, reg); 561 ar9003_gpio_config_input(sc, sc->rfsilent_pin); 562 AR_SETBITS(sc, AR_PHY_TEST, AR_PHY_TEST_RFSILENT_BB); 563 if (!(sc->flags & ATHN_FLAG_RFSILENT_REVERSED)) { 564 AR_SETBITS(sc, AR_GPIO_INTR_POL, 565 AR_GPIO_INTR_POL_PIN(sc->rfsilent_pin)); 566 } 567 AR_WRITE_BARRIER(sc); 568 } 569 570 int 571 ar9003_dma_alloc(struct athn_softc *sc) 572 { 573 int error; 574 575 error = ar9003_tx_alloc(sc); 576 if (error != 0) 577 return (error); 578 579 error = ar9003_rx_alloc(sc, ATHN_QID_LP, AR9003_RX_LP_QDEPTH); 580 if (error != 0) 581 return (error); 582 583 error = ar9003_rx_alloc(sc, ATHN_QID_HP, AR9003_RX_HP_QDEPTH); 584 if (error != 0) 585 return (error); 586 587 return (0); 588 } 589 590 void 591 ar9003_dma_free(struct athn_softc *sc) 592 { 593 ar9003_tx_free(sc); 594 ar9003_rx_free(sc, ATHN_QID_LP); 595 ar9003_rx_free(sc, ATHN_QID_HP); 596 } 597 598 int 599 ar9003_tx_alloc(struct athn_softc *sc) 600 { 601 struct athn_tx_buf *bf; 602 bus_size_t size; 603 int error, nsegs, i; 604 605 /* 606 * Allocate Tx status ring. 607 */ 608 size = AR9003_NTXSTATUS * sizeof(struct ar_tx_status); 609 610 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 611 BUS_DMA_NOWAIT, &sc->txsmap); 612 if (error != 0) 613 goto fail; 614 615 error = bus_dmamem_alloc(sc->sc_dmat, size, 4, 0, &sc->txsseg, 1, 616 &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 617 if (error != 0) 618 goto fail; 619 620 error = bus_dmamem_map(sc->sc_dmat, &sc->txsseg, 1, size, 621 (caddr_t *)&sc->txsring, BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 622 if (error != 0) 623 goto fail; 624 625 error = bus_dmamap_load_raw(sc->sc_dmat, sc->txsmap, &sc->txsseg, 626 1, size, BUS_DMA_NOWAIT | BUS_DMA_READ); 627 if (error != 0) 628 goto fail; 629 630 /* 631 * Allocate a pool of Tx descriptors shared between all Tx queues. 632 */ 633 size = ATHN_NTXBUFS * sizeof(struct ar_tx_desc); 634 635 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 636 BUS_DMA_NOWAIT, &sc->map); 637 if (error != 0) 638 goto fail; 639 640 error = bus_dmamem_alloc(sc->sc_dmat, size, 4, 0, &sc->seg, 1, 641 &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 642 if (error != 0) 643 goto fail; 644 645 error = bus_dmamem_map(sc->sc_dmat, &sc->seg, 1, size, 646 (caddr_t *)&sc->descs, BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 647 if (error != 0) 648 goto fail; 649 650 error = bus_dmamap_load_raw(sc->sc_dmat, sc->map, &sc->seg, 1, size, 651 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 652 if (error != 0) 653 goto fail; 654 655 SIMPLEQ_INIT(&sc->txbufs); 656 for (i = 0; i < ATHN_NTXBUFS; i++) { 657 bf = &sc->txpool[i]; 658 659 error = bus_dmamap_create(sc->sc_dmat, ATHN_TXBUFSZ, 660 AR9003_MAX_SCATTER, ATHN_TXBUFSZ, 0, BUS_DMA_NOWAIT, 661 &bf->bf_map); 662 if (error != 0) { 663 printf("%s: could not create Tx buf DMA map\n", 664 sc->sc_dev.dv_xname); 665 goto fail; 666 } 667 668 bf->bf_descs = &((struct ar_tx_desc *)sc->descs)[i]; 669 bf->bf_daddr = sc->map->dm_segs[0].ds_addr + 670 i * sizeof(struct ar_tx_desc); 671 672 SIMPLEQ_INSERT_TAIL(&sc->txbufs, bf, bf_list); 673 } 674 return (0); 675 fail: 676 ar9003_tx_free(sc); 677 return (error); 678 } 679 680 void 681 ar9003_tx_free(struct athn_softc *sc) 682 { 683 struct athn_tx_buf *bf; 684 int i; 685 686 for (i = 0; i < ATHN_NTXBUFS; i++) { 687 bf = &sc->txpool[i]; 688 689 if (bf->bf_map != NULL) 690 bus_dmamap_destroy(sc->sc_dmat, bf->bf_map); 691 } 692 /* Free Tx descriptors. */ 693 if (sc->map != NULL) { 694 if (sc->descs != NULL) { 695 bus_dmamap_unload(sc->sc_dmat, sc->map); 696 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->descs, 697 ATHN_NTXBUFS * sizeof(struct ar_tx_desc)); 698 bus_dmamem_free(sc->sc_dmat, &sc->seg, 1); 699 } 700 bus_dmamap_destroy(sc->sc_dmat, sc->map); 701 } 702 /* Free Tx status ring. */ 703 if (sc->txsmap != NULL) { 704 if (sc->txsring != NULL) { 705 bus_dmamap_unload(sc->sc_dmat, sc->txsmap); 706 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->txsring, 707 AR9003_NTXSTATUS * sizeof(struct ar_tx_status)); 708 bus_dmamem_free(sc->sc_dmat, &sc->txsseg, 1); 709 } 710 bus_dmamap_destroy(sc->sc_dmat, sc->txsmap); 711 } 712 } 713 714 int 715 ar9003_rx_alloc(struct athn_softc *sc, int qid, int count) 716 { 717 struct athn_rxq *rxq = &sc->rxq[qid]; 718 struct athn_rx_buf *bf; 719 struct ar_rx_status *ds; 720 int error, i; 721 722 rxq->bf = mallocarray(count, sizeof(*bf), M_DEVBUF, 723 M_NOWAIT | M_ZERO); 724 if (rxq->bf == NULL) 725 return (ENOMEM); 726 727 rxq->count = count; 728 729 for (i = 0; i < rxq->count; i++) { 730 bf = &rxq->bf[i]; 731 732 error = bus_dmamap_create(sc->sc_dmat, ATHN_RXBUFSZ, 1, 733 ATHN_RXBUFSZ, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 734 &bf->bf_map); 735 if (error != 0) { 736 printf("%s: could not create Rx buf DMA map\n", 737 sc->sc_dev.dv_xname); 738 goto fail; 739 } 740 /* 741 * Assumes MCLGETI returns cache-line-size aligned buffers. 742 */ 743 bf->bf_m = MCLGETI(NULL, M_DONTWAIT, NULL, ATHN_RXBUFSZ); 744 if (bf->bf_m == NULL) { 745 printf("%s: could not allocate Rx mbuf\n", 746 sc->sc_dev.dv_xname); 747 error = ENOBUFS; 748 goto fail; 749 } 750 751 error = bus_dmamap_load(sc->sc_dmat, bf->bf_map, 752 mtod(bf->bf_m, void *), ATHN_RXBUFSZ, NULL, 753 BUS_DMA_NOWAIT); 754 if (error != 0) { 755 printf("%s: could not DMA map Rx buffer\n", 756 sc->sc_dev.dv_xname); 757 goto fail; 758 } 759 760 ds = mtod(bf->bf_m, struct ar_rx_status *); 761 memset(ds, 0, sizeof(*ds)); 762 bf->bf_desc = ds; 763 bf->bf_daddr = bf->bf_map->dm_segs[0].ds_addr; 764 765 bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, ATHN_RXBUFSZ, 766 BUS_DMASYNC_PREREAD); 767 } 768 return (0); 769 fail: 770 ar9003_rx_free(sc, qid); 771 return (error); 772 } 773 774 void 775 ar9003_rx_free(struct athn_softc *sc, int qid) 776 { 777 struct athn_rxq *rxq = &sc->rxq[qid]; 778 struct athn_rx_buf *bf; 779 int i; 780 781 if (rxq->bf == NULL) 782 return; 783 for (i = 0; i < rxq->count; i++) { 784 bf = &rxq->bf[i]; 785 786 if (bf->bf_map != NULL) 787 bus_dmamap_destroy(sc->sc_dmat, bf->bf_map); 788 if (bf->bf_m != NULL) 789 m_freem(bf->bf_m); 790 } 791 free(rxq->bf, M_DEVBUF, 0); 792 } 793 794 void 795 ar9003_reset_txsring(struct athn_softc *sc) 796 { 797 sc->txscur = 0; 798 memset(sc->txsring, 0, AR9003_NTXSTATUS * sizeof(struct ar_tx_status)); 799 AR_WRITE(sc, AR_Q_STATUS_RING_START, 800 sc->txsmap->dm_segs[0].ds_addr); 801 AR_WRITE(sc, AR_Q_STATUS_RING_END, 802 sc->txsmap->dm_segs[0].ds_addr + sc->txsmap->dm_segs[0].ds_len); 803 AR_WRITE_BARRIER(sc); 804 } 805 806 void 807 ar9003_rx_enable(struct athn_softc *sc) 808 { 809 struct athn_rxq *rxq; 810 struct athn_rx_buf *bf; 811 struct ar_rx_status *ds; 812 uint32_t reg; 813 int qid, i; 814 815 reg = AR_READ(sc, AR_RXBP_THRESH); 816 reg = RW(reg, AR_RXBP_THRESH_HP, 1); 817 reg = RW(reg, AR_RXBP_THRESH_LP, 1); 818 AR_WRITE(sc, AR_RXBP_THRESH, reg); 819 820 /* Set Rx buffer size. */ 821 AR_WRITE(sc, AR_DATABUF_SIZE, ATHN_RXBUFSZ - sizeof(*ds)); 822 823 for (qid = 0; qid < 2; qid++) { 824 rxq = &sc->rxq[qid]; 825 826 /* Setup Rx status descriptors. */ 827 SIMPLEQ_INIT(&rxq->head); 828 for (i = 0; i < rxq->count; i++) { 829 bf = &rxq->bf[i]; 830 ds = bf->bf_desc; 831 832 memset(ds, 0, sizeof(*ds)); 833 if (qid == ATHN_QID_LP) 834 AR_WRITE(sc, AR_LP_RXDP, bf->bf_daddr); 835 else 836 AR_WRITE(sc, AR_HP_RXDP, bf->bf_daddr); 837 AR_WRITE_BARRIER(sc); 838 SIMPLEQ_INSERT_TAIL(&rxq->head, bf, bf_list); 839 } 840 } 841 /* Enable Rx. */ 842 AR_WRITE(sc, AR_CR, 0); 843 AR_WRITE_BARRIER(sc); 844 } 845 846 #if NBPFILTER > 0 847 void 848 ar9003_rx_radiotap(struct athn_softc *sc, struct mbuf *m, 849 struct ar_rx_status *ds) 850 { 851 #define IEEE80211_RADIOTAP_F_SHORTGI 0x80 /* XXX from FBSD */ 852 853 struct athn_rx_radiotap_header *tap = &sc->sc_rxtap; 854 struct ieee80211com *ic = &sc->sc_ic; 855 struct mbuf mb; 856 uint64_t tsf; 857 uint32_t tstamp; 858 uint8_t rate; 859 860 /* Extend the 15-bit timestamp from Rx status to 64-bit TSF. */ 861 tstamp = ds->ds_status3; 862 tsf = AR_READ(sc, AR_TSF_U32); 863 tsf = tsf << 32 | AR_READ(sc, AR_TSF_L32); 864 if ((tsf & 0x7fff) < tstamp) 865 tsf -= 0x8000; 866 tsf = (tsf & ~0x7fff) | tstamp; 867 868 tap->wr_flags = IEEE80211_RADIOTAP_F_FCS; 869 tap->wr_tsft = htole64(tsf); 870 tap->wr_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 871 tap->wr_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 872 tap->wr_dbm_antsignal = MS(ds->ds_status5, AR_RXS5_RSSI_COMBINED); 873 /* XXX noise. */ 874 tap->wr_antenna = MS(ds->ds_status4, AR_RXS4_ANTENNA); 875 tap->wr_rate = 0; /* In case it can't be found below. */ 876 rate = MS(ds->ds_status1, AR_RXS1_RATE); 877 if (rate & 0x80) { /* HT. */ 878 /* Bit 7 set means HT MCS instead of rate. */ 879 tap->wr_rate = rate; 880 if (!(ds->ds_status4 & AR_RXS4_GI)) 881 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTGI; 882 883 } else if (rate & 0x10) { /* CCK. */ 884 if (rate & 0x04) 885 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 886 switch (rate & ~0x14) { 887 case 0xb: tap->wr_rate = 2; break; 888 case 0xa: tap->wr_rate = 4; break; 889 case 0x9: tap->wr_rate = 11; break; 890 case 0x8: tap->wr_rate = 22; break; 891 } 892 } else { /* OFDM. */ 893 switch (rate) { 894 case 0xb: tap->wr_rate = 12; break; 895 case 0xf: tap->wr_rate = 18; break; 896 case 0xa: tap->wr_rate = 24; break; 897 case 0xe: tap->wr_rate = 36; break; 898 case 0x9: tap->wr_rate = 48; break; 899 case 0xd: tap->wr_rate = 72; break; 900 case 0x8: tap->wr_rate = 96; break; 901 case 0xc: tap->wr_rate = 108; break; 902 } 903 } 904 mb.m_data = (caddr_t)tap; 905 mb.m_len = sc->sc_rxtap_len; 906 mb.m_next = m; 907 mb.m_nextpkt = NULL; 908 mb.m_type = 0; 909 mb.m_flags = 0; 910 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_IN); 911 } 912 #endif 913 914 int 915 ar9003_rx_process(struct athn_softc *sc, int qid) 916 { 917 struct ieee80211com *ic = &sc->sc_ic; 918 struct ifnet *ifp = &ic->ic_if; 919 struct athn_rxq *rxq = &sc->rxq[qid]; 920 struct athn_rx_buf *bf; 921 struct ar_rx_status *ds; 922 struct ieee80211_frame *wh; 923 struct ieee80211_rxinfo rxi; 924 struct ieee80211_node *ni; 925 struct mbuf *m, *m1; 926 int error, len; 927 928 bf = SIMPLEQ_FIRST(&rxq->head); 929 if (__predict_false(bf == NULL)) { /* Should not happen. */ 930 printf("%s: Rx queue is empty!\n", sc->sc_dev.dv_xname); 931 return (ENOENT); 932 } 933 bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, ATHN_RXBUFSZ, 934 BUS_DMASYNC_POSTREAD); 935 936 ds = mtod(bf->bf_m, struct ar_rx_status *); 937 if (!(ds->ds_status1 & AR_RXS1_DONE)) 938 return (EBUSY); 939 940 /* Check that it is a valid Rx status descriptor. */ 941 if ((ds->ds_info & (AR_RXI_DESC_ID_M | AR_RXI_DESC_TX | 942 AR_RXI_CTRL_STAT)) != SM(AR_RXI_DESC_ID, AR_VENDOR_ATHEROS)) 943 goto skip; 944 945 if (!(ds->ds_status11 & AR_RXS11_FRAME_OK)) { 946 if (ds->ds_status11 & AR_RXS11_CRC_ERR) 947 DPRINTFN(6, ("CRC error\n")); 948 else if (ds->ds_status11 & AR_RXS11_PHY_ERR) 949 DPRINTFN(6, ("PHY error=0x%x\n", 950 MS(ds->ds_status11, AR_RXS11_PHY_ERR_CODE))); 951 else if (ds->ds_status11 & AR_RXS11_DECRYPT_CRC_ERR) 952 DPRINTFN(6, ("Decryption CRC error\n")); 953 else if (ds->ds_status11 & AR_RXS11_MICHAEL_ERR) { 954 DPRINTFN(2, ("Michael MIC failure\n")); 955 /* Report Michael MIC failures to net80211. */ 956 ic->ic_stats.is_rx_locmicfail++; 957 ieee80211_michael_mic_failure(ic, 0); 958 /* 959 * XXX Check that it is not a control frame 960 * (invalid MIC failures on valid ctl frames). 961 */ 962 } 963 ifp->if_ierrors++; 964 goto skip; 965 } 966 967 len = MS(ds->ds_status2, AR_RXS2_DATA_LEN); 968 if (__predict_false(len < IEEE80211_MIN_LEN || 969 len > ATHN_RXBUFSZ - sizeof(*ds))) { 970 DPRINTF(("corrupted descriptor length=%d\n", len)); 971 ifp->if_ierrors++; 972 goto skip; 973 } 974 975 /* Allocate a new Rx buffer. */ 976 m1 = MCLGETI(NULL, M_DONTWAIT, NULL, ATHN_RXBUFSZ); 977 if (__predict_false(m1 == NULL)) { 978 ic->ic_stats.is_rx_nombuf++; 979 ifp->if_ierrors++; 980 goto skip; 981 } 982 983 /* Unmap the old Rx buffer. */ 984 bus_dmamap_unload(sc->sc_dmat, bf->bf_map); 985 986 /* Map the new Rx buffer. */ 987 error = bus_dmamap_load(sc->sc_dmat, bf->bf_map, mtod(m1, void *), 988 ATHN_RXBUFSZ, NULL, BUS_DMA_NOWAIT | BUS_DMA_READ); 989 if (__predict_false(error != 0)) { 990 m_freem(m1); 991 992 /* Remap the old Rx buffer or panic. */ 993 error = bus_dmamap_load(sc->sc_dmat, bf->bf_map, 994 mtod(bf->bf_m, void *), ATHN_RXBUFSZ, NULL, 995 BUS_DMA_NOWAIT | BUS_DMA_READ); 996 KASSERT(error != 0); 997 bf->bf_daddr = bf->bf_map->dm_segs[0].ds_addr; 998 ifp->if_ierrors++; 999 goto skip; 1000 } 1001 bf->bf_desc = mtod(m1, struct ar_rx_status *); 1002 bf->bf_daddr = bf->bf_map->dm_segs[0].ds_addr; 1003 1004 m = bf->bf_m; 1005 bf->bf_m = m1; 1006 1007 /* Finalize mbuf. */ 1008 /* Strip Rx status descriptor from head. */ 1009 m->m_data = (caddr_t)&ds[1]; 1010 m->m_pkthdr.len = m->m_len = len; 1011 1012 /* Grab a reference to the source node. */ 1013 wh = mtod(m, struct ieee80211_frame *); 1014 ni = ieee80211_find_rxnode(ic, wh); 1015 1016 /* Remove any HW padding after the 802.11 header. */ 1017 if (!(wh->i_fc[0] & IEEE80211_FC0_TYPE_CTL)) { 1018 u_int hdrlen = ieee80211_get_hdrlen(wh); 1019 if (hdrlen & 3) { 1020 memmove((caddr_t)wh + 2, wh, hdrlen); 1021 m_adj(m, 2); 1022 } 1023 } 1024 #if NBPFILTER > 0 1025 if (__predict_false(sc->sc_drvbpf != NULL)) 1026 ar9003_rx_radiotap(sc, m, ds); 1027 #endif 1028 /* Trim 802.11 FCS after radiotap. */ 1029 m_adj(m, -IEEE80211_CRC_LEN); 1030 1031 /* Send the frame to the 802.11 layer. */ 1032 rxi.rxi_flags = 0; /* XXX */ 1033 rxi.rxi_rssi = MS(ds->ds_status5, AR_RXS5_RSSI_COMBINED); 1034 rxi.rxi_tstamp = ds->ds_status3; 1035 ieee80211_input(ifp, m, ni, &rxi); 1036 1037 /* Node is no longer needed. */ 1038 ieee80211_release_node(ic, ni); 1039 1040 skip: 1041 /* Unlink this descriptor from head. */ 1042 SIMPLEQ_REMOVE_HEAD(&rxq->head, bf_list); 1043 memset(bf->bf_desc, 0, sizeof(*ds)); 1044 1045 /* Re-use this descriptor and link it to tail. */ 1046 bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, ATHN_RXBUFSZ, 1047 BUS_DMASYNC_PREREAD); 1048 1049 if (qid == ATHN_QID_LP) 1050 AR_WRITE(sc, AR_LP_RXDP, bf->bf_daddr); 1051 else 1052 AR_WRITE(sc, AR_HP_RXDP, bf->bf_daddr); 1053 AR_WRITE_BARRIER(sc); 1054 SIMPLEQ_INSERT_TAIL(&rxq->head, bf, bf_list); 1055 1056 /* Re-enable Rx. */ 1057 AR_WRITE(sc, AR_CR, 0); 1058 AR_WRITE_BARRIER(sc); 1059 return (0); 1060 } 1061 1062 void 1063 ar9003_rx_intr(struct athn_softc *sc, int qid) 1064 { 1065 while (ar9003_rx_process(sc, qid) == 0); 1066 } 1067 1068 int 1069 ar9003_tx_process(struct athn_softc *sc) 1070 { 1071 struct ieee80211com *ic = &sc->sc_ic; 1072 struct ifnet *ifp = &ic->ic_if; 1073 struct athn_txq *txq; 1074 struct athn_node *an; 1075 struct athn_tx_buf *bf; 1076 struct ar_tx_status *ds; 1077 uint8_t qid, failcnt; 1078 1079 ds = &((struct ar_tx_status *)sc->txsring)[sc->txscur]; 1080 if (!(ds->ds_status8 & AR_TXS8_DONE)) 1081 return (EBUSY); 1082 1083 sc->txscur = (sc->txscur + 1) % AR9003_NTXSTATUS; 1084 1085 /* Check that it is a valid Tx status descriptor. */ 1086 if ((ds->ds_info & (AR_TXI_DESC_ID_M | AR_TXI_DESC_TX)) != 1087 (SM(AR_TXI_DESC_ID, AR_VENDOR_ATHEROS) | AR_TXI_DESC_TX)) { 1088 memset(ds, 0, sizeof(*ds)); 1089 return (0); 1090 } 1091 /* Retrieve the queue that was used to send this PDU. */ 1092 qid = MS(ds->ds_info, AR_TXI_QCU_NUM); 1093 txq = &sc->txq[qid]; 1094 1095 bf = SIMPLEQ_FIRST(&txq->head); 1096 if (bf == NULL || bf == txq->wait) { 1097 memset(ds, 0, sizeof(*ds)); 1098 return (0); 1099 } 1100 SIMPLEQ_REMOVE_HEAD(&txq->head, bf_list); 1101 ifp->if_opackets++; 1102 1103 sc->sc_tx_timer = 0; 1104 1105 if (ds->ds_status3 & AR_TXS3_EXCESSIVE_RETRIES) 1106 ifp->if_oerrors++; 1107 1108 if (ds->ds_status3 & AR_TXS3_UNDERRUN) 1109 athn_inc_tx_trigger_level(sc); 1110 1111 /* Wakeup PA predistortion state machine. */ 1112 if (bf->bf_txflags & ATHN_TXFLAG_PAPRD) 1113 ar9003_paprd_tx_tone_done(sc); 1114 1115 an = (struct athn_node *)bf->bf_ni; 1116 /* 1117 * NB: the data fail count contains the number of un-acked tries 1118 * for the final series used. We must add the number of tries for 1119 * each series that was fully processed. 1120 */ 1121 failcnt = MS(ds->ds_status3, AR_TXS3_DATA_FAIL_CNT); 1122 /* NB: Assume two tries per series. */ 1123 failcnt += MS(ds->ds_status8, AR_TXS8_FINAL_IDX) * 2; 1124 1125 /* Update rate control statistics. */ 1126 an->amn.amn_txcnt++; 1127 if (failcnt > 0) 1128 an->amn.amn_retrycnt++; 1129 1130 DPRINTFN(5, ("Tx done qid=%d status3=%d fail count=%d\n", 1131 qid, ds->ds_status3, failcnt)); 1132 1133 /* Reset Tx status descriptor. */ 1134 memset(ds, 0, sizeof(*ds)); 1135 1136 /* Unmap Tx buffer. */ 1137 bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, bf->bf_map->dm_mapsize, 1138 BUS_DMASYNC_POSTWRITE); 1139 bus_dmamap_unload(sc->sc_dmat, bf->bf_map); 1140 1141 m_freem(bf->bf_m); 1142 bf->bf_m = NULL; 1143 ieee80211_release_node(ic, bf->bf_ni); 1144 bf->bf_ni = NULL; 1145 1146 /* Link Tx buffer back to global free list. */ 1147 SIMPLEQ_INSERT_TAIL(&sc->txbufs, bf, bf_list); 1148 1149 /* Queue buffers that are waiting if there is new room. */ 1150 if (--txq->queued < AR9003_TX_QDEPTH && txq->wait != NULL) { 1151 AR_WRITE(sc, AR_QTXDP(qid), txq->wait->bf_daddr); 1152 AR_WRITE_BARRIER(sc); 1153 txq->wait = SIMPLEQ_NEXT(txq->wait, bf_list); 1154 } 1155 return (0); 1156 } 1157 1158 void 1159 ar9003_tx_intr(struct athn_softc *sc) 1160 { 1161 struct ieee80211com *ic = &sc->sc_ic; 1162 struct ifnet *ifp = &ic->ic_if; 1163 1164 while (ar9003_tx_process(sc) == 0); 1165 1166 if (!SIMPLEQ_EMPTY(&sc->txbufs)) { 1167 ifq_clr_oactive(&ifp->if_snd); 1168 ifp->if_start(ifp); 1169 } 1170 } 1171 1172 #ifndef IEEE80211_STA_ONLY 1173 /* 1174 * Process Software Beacon Alert interrupts. 1175 */ 1176 int 1177 ar9003_swba_intr(struct athn_softc *sc) 1178 { 1179 struct ieee80211com *ic = &sc->sc_ic; 1180 struct ifnet *ifp = &ic->ic_if; 1181 struct ieee80211_node *ni = ic->ic_bss; 1182 struct athn_tx_buf *bf = sc->bcnbuf; 1183 struct ieee80211_frame *wh; 1184 struct ar_tx_desc *ds; 1185 struct mbuf *m; 1186 uint32_t sum; 1187 uint8_t ridx, hwrate; 1188 int error, totlen; 1189 1190 if (ic->ic_tim_mcast_pending && 1191 mq_empty(&ni->ni_savedq) && 1192 SIMPLEQ_EMPTY(&sc->txq[ATHN_QID_CAB].head)) 1193 ic->ic_tim_mcast_pending = 0; 1194 1195 if (ic->ic_dtim_count == 0) 1196 ic->ic_dtim_count = ic->ic_dtim_period - 1; 1197 else 1198 ic->ic_dtim_count--; 1199 1200 /* Make sure previous beacon has been sent. */ 1201 if (athn_tx_pending(sc, ATHN_QID_BEACON)) { 1202 DPRINTF(("beacon stuck\n")); 1203 return (EBUSY); 1204 } 1205 /* Get new beacon. */ 1206 m = ieee80211_beacon_alloc(ic, ic->ic_bss); 1207 if (__predict_false(m == NULL)) 1208 return (ENOBUFS); 1209 /* Assign sequence number. */ 1210 wh = mtod(m, struct ieee80211_frame *); 1211 *(uint16_t *)&wh->i_seq[0] = 1212 htole16(ic->ic_bss->ni_txseq << IEEE80211_SEQ_SEQ_SHIFT); 1213 ic->ic_bss->ni_txseq++; 1214 1215 /* Unmap and free old beacon if any. */ 1216 if (__predict_true(bf->bf_m != NULL)) { 1217 bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, 1218 bf->bf_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1219 bus_dmamap_unload(sc->sc_dmat, bf->bf_map); 1220 m_freem(bf->bf_m); 1221 bf->bf_m = NULL; 1222 } 1223 /* DMA map new beacon. */ 1224 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_map, m, 1225 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 1226 if (__predict_false(error != 0)) { 1227 m_freem(m); 1228 return (error); 1229 } 1230 bf->bf_m = m; 1231 1232 /* Setup Tx descriptor (simplified ar9003_tx()). */ 1233 ds = bf->bf_descs; 1234 memset(ds, 0, sizeof(*ds)); 1235 1236 ds->ds_info = 1237 SM(AR_TXI_DESC_ID, AR_VENDOR_ATHEROS) | 1238 SM(AR_TXI_DESC_NDWORDS, 23) | 1239 SM(AR_TXI_QCU_NUM, ATHN_QID_BEACON) | 1240 AR_TXI_DESC_TX | AR_TXI_CTRL_STAT; 1241 1242 totlen = m->m_pkthdr.len + IEEE80211_CRC_LEN; 1243 ds->ds_ctl11 = SM(AR_TXC11_FRAME_LEN, totlen); 1244 ds->ds_ctl11 |= SM(AR_TXC11_XMIT_POWER, AR_MAX_RATE_POWER); 1245 ds->ds_ctl12 = SM(AR_TXC12_FRAME_TYPE, AR_FRAME_TYPE_BEACON); 1246 ds->ds_ctl12 |= AR_TXC12_NO_ACK; 1247 ds->ds_ctl17 = SM(AR_TXC17_ENCR_TYPE, AR_ENCR_TYPE_CLEAR); 1248 1249 /* Write number of tries. */ 1250 ds->ds_ctl13 = SM(AR_TXC13_XMIT_DATA_TRIES0, 1); 1251 1252 /* Write Tx rate. */ 1253 ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? 1254 ATHN_RIDX_OFDM6 : ATHN_RIDX_CCK1; 1255 hwrate = athn_rates[ridx].hwrate; 1256 ds->ds_ctl14 = SM(AR_TXC14_XMIT_RATE0, hwrate); 1257 1258 /* Write Tx chains. */ 1259 ds->ds_ctl18 = SM(AR_TXC18_CHAIN_SEL0, sc->txchainmask); 1260 1261 ds->ds_segs[0].ds_data = bf->bf_map->dm_segs[0].ds_addr; 1262 /* Segment length must be a multiple of 4. */ 1263 ds->ds_segs[0].ds_ctl |= SM(AR_TXC_BUF_LEN, 1264 (bf->bf_map->dm_segs[0].ds_len + 3) & ~3); 1265 /* Compute Tx descriptor checksum. */ 1266 sum = ds->ds_info; 1267 sum += ds->ds_segs[0].ds_data; 1268 sum += ds->ds_segs[0].ds_ctl; 1269 sum = (sum >> 16) + (sum & 0xffff); 1270 ds->ds_ctl10 = SM(AR_TXC10_PTR_CHK_SUM, sum); 1271 1272 bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, bf->bf_map->dm_mapsize, 1273 BUS_DMASYNC_PREWRITE); 1274 1275 /* Stop Tx DMA before putting the new beacon on the queue. */ 1276 athn_stop_tx_dma(sc, ATHN_QID_BEACON); 1277 1278 AR_WRITE(sc, AR_QTXDP(ATHN_QID_BEACON), bf->bf_daddr); 1279 1280 for(;;) { 1281 if (SIMPLEQ_EMPTY(&sc->txbufs)) 1282 break; 1283 1284 m = mq_dequeue(&ni->ni_savedq); 1285 if (m == NULL) 1286 break; 1287 if (!mq_empty(&ni->ni_savedq)) { 1288 /* more queued frames, set the more data bit */ 1289 wh = mtod(m, struct ieee80211_frame *); 1290 wh->i_fc[1] |= IEEE80211_FC1_MORE_DATA; 1291 } 1292 1293 if (sc->ops.tx(sc, m, ni, ATHN_TXFLAG_CAB) != 0) { 1294 ieee80211_release_node(ic, ni); 1295 ifp->if_oerrors++; 1296 break; 1297 } 1298 } 1299 1300 /* Kick Tx. */ 1301 AR_WRITE(sc, AR_Q_TXE, 1 << ATHN_QID_BEACON); 1302 AR_WRITE_BARRIER(sc); 1303 return (0); 1304 } 1305 #endif 1306 1307 int 1308 ar9003_intr(struct athn_softc *sc) 1309 { 1310 uint32_t intr, intr2, intr5, sync; 1311 1312 /* Get pending interrupts. */ 1313 intr = AR_READ(sc, AR_INTR_ASYNC_CAUSE); 1314 if (!(intr & AR_INTR_MAC_IRQ) || intr == AR_INTR_SPURIOUS) { 1315 intr = AR_READ(sc, AR_INTR_SYNC_CAUSE); 1316 if (intr == AR_INTR_SPURIOUS || (intr & sc->isync) == 0) 1317 return (0); /* Not for us. */ 1318 } 1319 1320 if ((AR_READ(sc, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) && 1321 (AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) == AR_RTC_STATUS_ON) 1322 intr = AR_READ(sc, AR_ISR); 1323 else 1324 intr = 0; 1325 sync = AR_READ(sc, AR_INTR_SYNC_CAUSE) & sc->isync; 1326 if (intr == 0 && sync == 0) 1327 return (0); /* Not for us. */ 1328 1329 if (intr != 0) { 1330 if (intr & AR_ISR_BCNMISC) { 1331 intr2 = AR_READ(sc, AR_ISR_S2); 1332 if (intr2 & AR_ISR_S2_TIM) 1333 /* TBD */; 1334 if (intr2 & AR_ISR_S2_TSFOOR) 1335 /* TBD */; 1336 if (intr2 & AR_ISR_S2_BB_WATCHDOG) 1337 /* TBD */; 1338 } 1339 intr = AR_READ(sc, AR_ISR_RAC); 1340 if (intr == AR_INTR_SPURIOUS) 1341 return (1); 1342 1343 #ifndef IEEE80211_STA_ONLY 1344 if (intr & AR_ISR_SWBA) 1345 ar9003_swba_intr(sc); 1346 #endif 1347 if (intr & (AR_ISR_RXMINTR | AR_ISR_RXINTM)) 1348 ar9003_rx_intr(sc, ATHN_QID_LP); 1349 if (intr & (AR_ISR_LP_RXOK | AR_ISR_RXERR)) 1350 ar9003_rx_intr(sc, ATHN_QID_LP); 1351 if (intr & AR_ISR_HP_RXOK) 1352 ar9003_rx_intr(sc, ATHN_QID_HP); 1353 1354 if (intr & (AR_ISR_TXMINTR | AR_ISR_TXINTM)) 1355 ar9003_tx_intr(sc); 1356 if (intr & (AR_ISR_TXOK | AR_ISR_TXERR | AR_ISR_TXEOL)) 1357 ar9003_tx_intr(sc); 1358 1359 if (intr & AR_ISR_GENTMR) { 1360 intr5 = AR_READ(sc, AR_ISR_S5_S); 1361 DPRINTF(("GENTMR trigger=%d thresh=%d\n", 1362 MS(intr5, AR_ISR_S5_GENTIMER_TRIG), 1363 MS(intr5, AR_ISR_S5_GENTIMER_THRESH))); 1364 } 1365 } 1366 if (sync != 0) { 1367 if (sync & AR_INTR_SYNC_RADM_CPL_TIMEOUT) { 1368 AR_WRITE(sc, AR_RC, AR_RC_HOSTIF); 1369 AR_WRITE(sc, AR_RC, 0); 1370 } 1371 1372 if ((sc->flags & ATHN_FLAG_RFSILENT) && 1373 (sync & AR_INTR_SYNC_GPIO_PIN(sc->rfsilent_pin))) { 1374 struct ifnet *ifp = &sc->sc_ic.ic_if; 1375 1376 printf("%s: radio switch turned off\n", 1377 sc->sc_dev.dv_xname); 1378 /* Turn the interface down. */ 1379 ifp->if_flags &= ~IFF_UP; 1380 athn_stop(ifp, 1); 1381 return (1); 1382 } 1383 1384 AR_WRITE(sc, AR_INTR_SYNC_CAUSE, sync); 1385 (void)AR_READ(sc, AR_INTR_SYNC_CAUSE); 1386 } 1387 return (1); 1388 } 1389 1390 int 1391 ar9003_tx(struct athn_softc *sc, struct mbuf *m, struct ieee80211_node *ni, 1392 int txflags) 1393 { 1394 struct ieee80211com *ic = &sc->sc_ic; 1395 struct ieee80211_key *k = NULL; 1396 struct ieee80211_frame *wh; 1397 struct athn_series series[4]; 1398 struct ar_tx_desc *ds; 1399 struct athn_txq *txq; 1400 struct athn_tx_buf *bf; 1401 struct athn_node *an = (void *)ni; 1402 struct mbuf *m1; 1403 uintptr_t entry; 1404 uint32_t sum; 1405 uint16_t qos = 0; 1406 uint8_t txpower, type, encrtype, tid, ridx[4]; 1407 int i, error, totlen, hasqos, qid; 1408 1409 /* Grab a Tx buffer from our global free list. */ 1410 bf = SIMPLEQ_FIRST(&sc->txbufs); 1411 KASSERT(bf != NULL); 1412 1413 /* Map 802.11 frame type to hardware frame type. */ 1414 wh = mtod(m, struct ieee80211_frame *); 1415 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == 1416 IEEE80211_FC0_TYPE_MGT) { 1417 /* NB: Beacons do not use ar9003_tx(). */ 1418 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 1419 IEEE80211_FC0_SUBTYPE_PROBE_RESP) 1420 type = AR_FRAME_TYPE_PROBE_RESP; 1421 else if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 1422 IEEE80211_FC0_SUBTYPE_ATIM) 1423 type = AR_FRAME_TYPE_ATIM; 1424 else 1425 type = AR_FRAME_TYPE_NORMAL; 1426 } else if ((wh->i_fc[0] & 1427 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1428 (IEEE80211_FC0_TYPE_CTL | IEEE80211_FC0_SUBTYPE_PS_POLL)) { 1429 type = AR_FRAME_TYPE_PSPOLL; 1430 } else 1431 type = AR_FRAME_TYPE_NORMAL; 1432 1433 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1434 k = ieee80211_get_txkey(ic, wh, ni); 1435 if ((m = ieee80211_encrypt(ic, m, k)) == NULL) 1436 return (ENOBUFS); 1437 wh = mtod(m, struct ieee80211_frame *); 1438 } 1439 1440 /* XXX 2-byte padding for QoS and 4-addr headers. */ 1441 1442 /* Select the HW Tx queue to use for this frame. */ 1443 if ((hasqos = ieee80211_has_qos(wh))) { 1444 qos = ieee80211_get_qos(wh); 1445 tid = qos & IEEE80211_QOS_TID; 1446 qid = athn_ac2qid[ieee80211_up_to_ac(ic, tid)]; 1447 } else if (type == AR_FRAME_TYPE_PSPOLL) { 1448 qid = ATHN_QID_PSPOLL; 1449 } else if (txflags & ATHN_TXFLAG_CAB) { 1450 qid = ATHN_QID_CAB; 1451 } else 1452 qid = ATHN_QID_AC_BE; 1453 txq = &sc->txq[qid]; 1454 1455 /* Select the transmit rates to use for this frame. */ 1456 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 1457 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != 1458 IEEE80211_FC0_TYPE_DATA) { 1459 /* Use lowest rate for all tries. */ 1460 ridx[0] = ridx[1] = ridx[2] = ridx[3] = 1461 (ic->ic_curmode == IEEE80211_MODE_11A) ? 1462 ATHN_RIDX_OFDM6 : ATHN_RIDX_CCK1; 1463 } else if (ic->ic_fixed_rate != -1) { 1464 /* Use same fixed rate for all tries. */ 1465 ridx[0] = ridx[1] = ridx[2] = ridx[3] = 1466 sc->fixed_ridx; 1467 } else { 1468 int txrate = ni->ni_txrate; 1469 /* Use fallback table of the node. */ 1470 for (i = 0; i < 4; i++) { 1471 ridx[i] = an->ridx[txrate]; 1472 txrate = an->fallback[txrate]; 1473 } 1474 } 1475 1476 #if NBPFILTER > 0 1477 if (__predict_false(sc->sc_drvbpf != NULL)) { 1478 struct athn_tx_radiotap_header *tap = &sc->sc_txtap; 1479 struct mbuf mb; 1480 1481 tap->wt_flags = 0; 1482 /* Use initial transmit rate. */ 1483 tap->wt_rate = athn_rates[ridx[0]].rate; 1484 tap->wt_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 1485 tap->wt_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 1486 tap->wt_hwqueue = qid; 1487 if (ridx[0] != ATHN_RIDX_CCK1 && 1488 (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1489 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1490 mb.m_data = (caddr_t)tap; 1491 mb.m_len = sc->sc_txtap_len; 1492 mb.m_next = m; 1493 mb.m_nextpkt = NULL; 1494 mb.m_type = 0; 1495 mb.m_flags = 0; 1496 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_OUT); 1497 } 1498 #endif 1499 1500 /* DMA map mbuf. */ 1501 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_map, m, 1502 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 1503 if (__predict_false(error != 0)) { 1504 if (error != EFBIG) { 1505 printf("%s: can't map mbuf (error %d)\n", 1506 sc->sc_dev.dv_xname, error); 1507 m_freem(m); 1508 return (error); 1509 } 1510 /* 1511 * DMA mapping requires too many DMA segments; linearize 1512 * mbuf in kernel virtual address space and retry. 1513 */ 1514 MGETHDR(m1, M_DONTWAIT, MT_DATA); 1515 if (m1 == NULL) { 1516 m_freem(m); 1517 return (ENOBUFS); 1518 } 1519 if (m->m_pkthdr.len > MHLEN) { 1520 MCLGET(m1, M_DONTWAIT); 1521 if (!(m1->m_flags & M_EXT)) { 1522 m_freem(m); 1523 m_freem(m1); 1524 return (ENOBUFS); 1525 } 1526 } 1527 m_copydata(m, 0, m->m_pkthdr.len, mtod(m1, caddr_t)); 1528 m1->m_pkthdr.len = m1->m_len = m->m_pkthdr.len; 1529 m_freem(m); 1530 m = m1; 1531 1532 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_map, m, 1533 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 1534 if (error != 0) { 1535 printf("%s: can't map mbuf (error %d)\n", 1536 sc->sc_dev.dv_xname, error); 1537 m_freem(m); 1538 return (error); 1539 } 1540 } 1541 bf->bf_m = m; 1542 bf->bf_ni = ni; 1543 bf->bf_txflags = txflags; 1544 1545 wh = mtod(m, struct ieee80211_frame *); 1546 1547 totlen = m->m_pkthdr.len + IEEE80211_CRC_LEN; 1548 1549 /* Setup Tx descriptor. */ 1550 ds = bf->bf_descs; 1551 memset(ds, 0, sizeof(*ds)); 1552 1553 ds->ds_info = 1554 SM(AR_TXI_DESC_ID, AR_VENDOR_ATHEROS) | 1555 SM(AR_TXI_DESC_NDWORDS, 23) | 1556 SM(AR_TXI_QCU_NUM, qid) | 1557 AR_TXI_DESC_TX | AR_TXI_CTRL_STAT; 1558 1559 ds->ds_ctl11 = AR_TXC11_CLR_DEST_MASK; 1560 txpower = AR_MAX_RATE_POWER; /* Get from per-rate registers. */ 1561 ds->ds_ctl11 |= SM(AR_TXC11_XMIT_POWER, txpower); 1562 1563 ds->ds_ctl12 = SM(AR_TXC12_FRAME_TYPE, type); 1564 1565 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 1566 (hasqos && (qos & IEEE80211_QOS_ACK_POLICY_MASK) == 1567 IEEE80211_QOS_ACK_POLICY_NOACK)) 1568 ds->ds_ctl12 |= AR_TXC12_NO_ACK; 1569 1570 if (0 && k != NULL) { 1571 /* 1572 * Map 802.11 cipher to hardware encryption type and 1573 * compute MIC+ICV overhead. 1574 */ 1575 switch (k->k_cipher) { 1576 case IEEE80211_CIPHER_WEP40: 1577 case IEEE80211_CIPHER_WEP104: 1578 encrtype = AR_ENCR_TYPE_WEP; 1579 totlen += 4; 1580 break; 1581 case IEEE80211_CIPHER_TKIP: 1582 encrtype = AR_ENCR_TYPE_TKIP; 1583 totlen += 12; 1584 break; 1585 case IEEE80211_CIPHER_CCMP: 1586 encrtype = AR_ENCR_TYPE_AES; 1587 totlen += 8; 1588 break; 1589 default: 1590 panic("unsupported cipher"); 1591 } 1592 /* 1593 * NB: The key cache entry index is stored in the key 1594 * private field when the key is installed. 1595 */ 1596 entry = (uintptr_t)k->k_priv; 1597 ds->ds_ctl12 |= SM(AR_TXC12_DEST_IDX, entry); 1598 ds->ds_ctl11 |= AR_TXC11_DEST_IDX_VALID; 1599 } else 1600 encrtype = AR_ENCR_TYPE_CLEAR; 1601 ds->ds_ctl17 = SM(AR_TXC17_ENCR_TYPE, encrtype); 1602 1603 /* Check if frame must be protected using RTS/CTS or CTS-to-self. */ 1604 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1605 /* NB: Group frames are sent using CCK in 802.11b/g. */ 1606 if (totlen > ic->ic_rtsthreshold) { 1607 ds->ds_ctl11 |= AR_TXC11_RTS_ENABLE; 1608 } else if ((ic->ic_flags & IEEE80211_F_USEPROT) && 1609 athn_rates[ridx[0]].phy == IEEE80211_T_OFDM) { 1610 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 1611 ds->ds_ctl11 |= AR_TXC11_RTS_ENABLE; 1612 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 1613 ds->ds_ctl11 |= AR_TXC11_CTS_ENABLE; 1614 } 1615 } 1616 if (ds->ds_ctl11 & (AR_TXC11_RTS_ENABLE | AR_TXC11_CTS_ENABLE)) { 1617 /* Disable multi-rate retries when protection is used. */ 1618 ridx[1] = ridx[2] = ridx[3] = ridx[0]; 1619 } 1620 /* Setup multi-rate retries. */ 1621 for (i = 0; i < 4; i++) { 1622 series[i].hwrate = athn_rates[ridx[i]].hwrate; 1623 if (athn_rates[ridx[i]].phy == IEEE80211_T_DS && 1624 ridx[i] != ATHN_RIDX_CCK1 && 1625 (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1626 series[i].hwrate |= 0x04; 1627 series[i].dur = 0; 1628 } 1629 if (!(ds->ds_ctl12 & AR_TXC12_NO_ACK)) { 1630 /* Compute duration for each series. */ 1631 for (i = 0; i < 4; i++) { 1632 series[i].dur = athn_txtime(sc, IEEE80211_ACK_LEN, 1633 athn_rates[ridx[i]].rspridx, ic->ic_flags); 1634 } 1635 } 1636 /* If this is a PA training frame, select the Tx chain to use. */ 1637 if (__predict_false(txflags & ATHN_TXFLAG_PAPRD)) { 1638 ds->ds_ctl12 |= SM(AR_TXC12_PAPRD_CHAIN_MASK, 1639 1 << sc->paprd_curchain); 1640 } 1641 1642 /* Write number of tries for each series. */ 1643 ds->ds_ctl13 = 1644 SM(AR_TXC13_XMIT_DATA_TRIES0, 2) | 1645 SM(AR_TXC13_XMIT_DATA_TRIES1, 2) | 1646 SM(AR_TXC13_XMIT_DATA_TRIES2, 2) | 1647 SM(AR_TXC13_XMIT_DATA_TRIES3, 4); 1648 1649 /* Tell HW to update duration field in 802.11 header. */ 1650 if (type != AR_FRAME_TYPE_PSPOLL) 1651 ds->ds_ctl13 |= AR_TXC13_DUR_UPDATE_ENA; 1652 1653 /* Write Tx rate for each series. */ 1654 ds->ds_ctl14 = 1655 SM(AR_TXC14_XMIT_RATE0, series[0].hwrate) | 1656 SM(AR_TXC14_XMIT_RATE1, series[1].hwrate) | 1657 SM(AR_TXC14_XMIT_RATE2, series[2].hwrate) | 1658 SM(AR_TXC14_XMIT_RATE3, series[3].hwrate); 1659 1660 /* Write duration for each series. */ 1661 ds->ds_ctl15 = 1662 SM(AR_TXC15_PACKET_DUR0, series[0].dur) | 1663 SM(AR_TXC15_PACKET_DUR1, series[1].dur); 1664 ds->ds_ctl16 = 1665 SM(AR_TXC16_PACKET_DUR2, series[2].dur) | 1666 SM(AR_TXC16_PACKET_DUR3, series[3].dur); 1667 1668 if ((sc->flags & ATHN_FLAG_3TREDUCE_CHAIN) && 1669 ic->ic_curmode == IEEE80211_MODE_11A) { 1670 /* 1671 * In order to not exceed PCIe power requirements, we only 1672 * use two Tx chains for MCS0~15 on 5GHz band on these chips. 1673 */ 1674 ds->ds_ctl18 = 1675 SM(AR_TXC18_CHAIN_SEL0, 1676 (ridx[0] <= ATHN_RIDX_MCS15) ? 0x3 : sc->txchainmask) | 1677 SM(AR_TXC18_CHAIN_SEL1, 1678 (ridx[1] <= ATHN_RIDX_MCS15) ? 0x3 : sc->txchainmask) | 1679 SM(AR_TXC18_CHAIN_SEL2, 1680 (ridx[2] <= ATHN_RIDX_MCS15) ? 0x3 : sc->txchainmask) | 1681 SM(AR_TXC18_CHAIN_SEL3, 1682 (ridx[3] <= ATHN_RIDX_MCS15) ? 0x3 : sc->txchainmask); 1683 } else { 1684 /* Use the same Tx chains for all tries. */ 1685 ds->ds_ctl18 = 1686 SM(AR_TXC18_CHAIN_SEL0, sc->txchainmask) | 1687 SM(AR_TXC18_CHAIN_SEL1, sc->txchainmask) | 1688 SM(AR_TXC18_CHAIN_SEL2, sc->txchainmask) | 1689 SM(AR_TXC18_CHAIN_SEL3, sc->txchainmask); 1690 } 1691 #ifdef notyet 1692 /* Use the same short GI setting for all tries. */ 1693 if (ic->ic_flags & IEEE80211_F_SHGI) 1694 ds->ds_ctl18 |= AR_TXC18_GI0123; 1695 /* Use the same channel width for all tries. */ 1696 if (ic->ic_flags & IEEE80211_F_CBW40) 1697 ds->ds_ctl18 |= AR_TXC18_2040_0123; 1698 #endif 1699 1700 if (ds->ds_ctl11 & (AR_TXC11_RTS_ENABLE | AR_TXC11_CTS_ENABLE)) { 1701 uint8_t protridx, hwrate; 1702 uint16_t dur = 0; 1703 1704 /* Use the same protection mode for all tries. */ 1705 if (ds->ds_ctl11 & AR_TXC11_RTS_ENABLE) { 1706 ds->ds_ctl15 |= AR_TXC15_RTSCTS_QUAL01; 1707 ds->ds_ctl16 |= AR_TXC16_RTSCTS_QUAL23; 1708 } 1709 /* Select protection rate (suboptimal but ok). */ 1710 protridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? 1711 ATHN_RIDX_OFDM6 : ATHN_RIDX_CCK2; 1712 if (ds->ds_ctl11 & AR_TXC11_RTS_ENABLE) { 1713 /* Account for CTS duration. */ 1714 dur += athn_txtime(sc, IEEE80211_ACK_LEN, 1715 athn_rates[protridx].rspridx, ic->ic_flags); 1716 } 1717 dur += athn_txtime(sc, totlen, ridx[0], ic->ic_flags); 1718 if (!(ds->ds_ctl12 & AR_TXC12_NO_ACK)) { 1719 /* Account for ACK duration. */ 1720 dur += athn_txtime(sc, IEEE80211_ACK_LEN, 1721 athn_rates[ridx[0]].rspridx, ic->ic_flags); 1722 } 1723 /* Write protection frame duration and rate. */ 1724 ds->ds_ctl13 |= SM(AR_TXC13_BURST_DUR, dur); 1725 hwrate = athn_rates[protridx].hwrate; 1726 if (protridx == ATHN_RIDX_CCK2 && 1727 (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1728 hwrate |= 0x04; 1729 ds->ds_ctl18 |= SM(AR_TXC18_RTSCTS_RATE, hwrate); 1730 } 1731 1732 ds->ds_ctl11 |= SM(AR_TXC11_FRAME_LEN, totlen); 1733 ds->ds_ctl19 = AR_TXC19_NOT_SOUNDING; 1734 1735 for (i = 0; i < bf->bf_map->dm_nsegs; i++) { 1736 ds->ds_segs[i].ds_data = bf->bf_map->dm_segs[i].ds_addr; 1737 ds->ds_segs[i].ds_ctl = SM(AR_TXC_BUF_LEN, 1738 bf->bf_map->dm_segs[i].ds_len); 1739 } 1740 /* Compute Tx descriptor checksum. */ 1741 sum = ds->ds_info + ds->ds_link; 1742 for (i = 0; i < 4; i++) { 1743 sum += ds->ds_segs[i].ds_data; 1744 sum += ds->ds_segs[i].ds_ctl; 1745 } 1746 sum = (sum >> 16) + (sum & 0xffff); 1747 ds->ds_ctl10 = SM(AR_TXC10_PTR_CHK_SUM, sum); 1748 1749 bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, bf->bf_map->dm_mapsize, 1750 BUS_DMASYNC_PREWRITE); 1751 1752 DPRINTFN(6, ("Tx qid=%d nsegs=%d ctl11=0x%x ctl12=0x%x ctl14=0x%x\n", 1753 qid, bf->bf_map->dm_nsegs, ds->ds_ctl11, ds->ds_ctl12, 1754 ds->ds_ctl14)); 1755 1756 SIMPLEQ_REMOVE_HEAD(&sc->txbufs, bf_list); 1757 SIMPLEQ_INSERT_TAIL(&txq->head, bf, bf_list); 1758 1759 /* Queue buffer unless hardware FIFO is already full. */ 1760 if (++txq->queued <= AR9003_TX_QDEPTH) { 1761 AR_WRITE(sc, AR_QTXDP(qid), bf->bf_daddr); 1762 AR_WRITE_BARRIER(sc); 1763 } else if (txq->wait == NULL) 1764 txq->wait = bf; 1765 return (0); 1766 } 1767 1768 void 1769 ar9003_set_rf_mode(struct athn_softc *sc, struct ieee80211_channel *c) 1770 { 1771 uint32_t reg; 1772 1773 reg = IEEE80211_IS_CHAN_2GHZ(c) ? 1774 AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM; 1775 if (IEEE80211_IS_CHAN_5GHZ(c) && 1776 (sc->flags & ATHN_FLAG_FAST_PLL_CLOCK)) { 1777 reg |= AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE; 1778 } 1779 AR_WRITE(sc, AR_PHY_MODE, reg); 1780 AR_WRITE_BARRIER(sc); 1781 } 1782 1783 static __inline uint32_t 1784 ar9003_synth_delay(struct athn_softc *sc) 1785 { 1786 uint32_t delay; 1787 1788 delay = MS(AR_READ(sc, AR_PHY_RX_DELAY), AR_PHY_RX_DELAY_DELAY); 1789 if (sc->sc_ic.ic_curmode == IEEE80211_MODE_11B) 1790 delay = (delay * 4) / 22; 1791 else 1792 delay = delay / 10; /* in 100ns steps */ 1793 return (delay); 1794 } 1795 1796 int 1797 ar9003_rf_bus_request(struct athn_softc *sc) 1798 { 1799 int ntries; 1800 1801 /* Request RF Bus grant. */ 1802 AR_WRITE(sc, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN); 1803 for (ntries = 0; ntries < 10000; ntries++) { 1804 if (AR_READ(sc, AR_PHY_RFBUS_GRANT) & AR_PHY_RFBUS_GRANT_EN) 1805 return (0); 1806 DELAY(10); 1807 } 1808 DPRINTF(("could not kill baseband Rx")); 1809 return (ETIMEDOUT); 1810 } 1811 1812 void 1813 ar9003_rf_bus_release(struct athn_softc *sc) 1814 { 1815 /* Wait for the synthesizer to settle. */ 1816 DELAY(AR_BASE_PHY_ACTIVE_DELAY + ar9003_synth_delay(sc)); 1817 1818 /* Release the RF Bus grant. */ 1819 AR_WRITE(sc, AR_PHY_RFBUS_REQ, 0); 1820 AR_WRITE_BARRIER(sc); 1821 } 1822 1823 void 1824 ar9003_set_phy(struct athn_softc *sc, struct ieee80211_channel *c, 1825 struct ieee80211_channel *extc) 1826 { 1827 uint32_t phy; 1828 1829 phy = AR_READ(sc, AR_PHY_GEN_CTRL); 1830 phy |= AR_PHY_GC_HT_EN | AR_PHY_GC_SHORT_GI_40 | 1831 AR_PHY_GC_SINGLE_HT_LTF1 | AR_PHY_GC_WALSH; 1832 if (extc != NULL) { 1833 phy |= AR_PHY_GC_DYN2040_EN; 1834 if (extc > c) /* XXX */ 1835 phy |= AR_PHY_GC_DYN2040_PRI_CH; 1836 } 1837 /* Turn off Green Field detection for now. */ 1838 phy &= ~AR_PHY_GC_GF_DETECT_EN; 1839 AR_WRITE(sc, AR_PHY_GEN_CTRL, phy); 1840 1841 AR_WRITE(sc, AR_2040_MODE, 1842 (extc != NULL) ? AR_2040_JOINED_RX_CLEAR : 0); 1843 1844 /* Set global transmit timeout. */ 1845 AR_WRITE(sc, AR_GTXTO, SM(AR_GTXTO_TIMEOUT_LIMIT, 25)); 1846 /* Set carrier sense timeout. */ 1847 AR_WRITE(sc, AR_CST, SM(AR_CST_TIMEOUT_LIMIT, 15)); 1848 AR_WRITE_BARRIER(sc); 1849 } 1850 1851 void 1852 ar9003_set_delta_slope(struct athn_softc *sc, struct ieee80211_channel *c, 1853 struct ieee80211_channel *extc) 1854 { 1855 uint32_t coeff, exp, man, reg; 1856 1857 /* Set Delta Slope (exponent and mantissa). */ 1858 coeff = (100 << 24) / c->ic_freq; 1859 athn_get_delta_slope(coeff, &exp, &man); 1860 DPRINTFN(5, ("delta slope coeff exp=%u man=%u\n", exp, man)); 1861 1862 reg = AR_READ(sc, AR_PHY_TIMING3); 1863 reg = RW(reg, AR_PHY_TIMING3_DSC_EXP, exp); 1864 reg = RW(reg, AR_PHY_TIMING3_DSC_MAN, man); 1865 AR_WRITE(sc, AR_PHY_TIMING3, reg); 1866 1867 /* For Short GI, coeff is 9/10 that of normal coeff. */ 1868 coeff = (9 * coeff) / 10; 1869 athn_get_delta_slope(coeff, &exp, &man); 1870 DPRINTFN(5, ("delta slope coeff exp=%u man=%u\n", exp, man)); 1871 1872 reg = AR_READ(sc, AR_PHY_SGI_DELTA); 1873 reg = RW(reg, AR_PHY_SGI_DSC_EXP, exp); 1874 reg = RW(reg, AR_PHY_SGI_DSC_MAN, man); 1875 AR_WRITE(sc, AR_PHY_SGI_DELTA, reg); 1876 AR_WRITE_BARRIER(sc); 1877 } 1878 1879 void 1880 ar9003_enable_antenna_diversity(struct athn_softc *sc) 1881 { 1882 AR_SETBITS(sc, AR_PHY_CCK_DETECT, 1883 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV); 1884 AR_WRITE_BARRIER(sc); 1885 } 1886 1887 void 1888 ar9003_init_baseband(struct athn_softc *sc) 1889 { 1890 uint32_t synth_delay; 1891 1892 synth_delay = ar9003_synth_delay(sc); 1893 /* Activate the PHY (includes baseband activate and synthesizer on). */ 1894 AR_WRITE(sc, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); 1895 AR_WRITE_BARRIER(sc); 1896 DELAY(AR_BASE_PHY_ACTIVE_DELAY + synth_delay); 1897 } 1898 1899 void 1900 ar9003_disable_phy(struct athn_softc *sc) 1901 { 1902 AR_WRITE(sc, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); 1903 AR_WRITE_BARRIER(sc); 1904 } 1905 1906 void 1907 ar9003_init_chains(struct athn_softc *sc) 1908 { 1909 if (sc->rxchainmask == 0x5 || sc->txchainmask == 0x5) 1910 AR_SETBITS(sc, AR_PHY_ANALOG_SWAP, AR_PHY_SWAP_ALT_CHAIN); 1911 1912 /* Setup chain masks. */ 1913 AR_WRITE(sc, AR_PHY_RX_CHAINMASK, sc->rxchainmask); 1914 AR_WRITE(sc, AR_PHY_CAL_CHAINMASK, sc->rxchainmask); 1915 1916 if (sc->flags & ATHN_FLAG_3TREDUCE_CHAIN) { 1917 /* 1918 * All self-generated frames are sent using two Tx chains 1919 * on these chips to not exceed PCIe power requirements. 1920 */ 1921 AR_WRITE(sc, AR_SELFGEN_MASK, 0x3); 1922 } else 1923 AR_WRITE(sc, AR_SELFGEN_MASK, sc->txchainmask); 1924 AR_WRITE_BARRIER(sc); 1925 } 1926 1927 void 1928 ar9003_set_rxchains(struct athn_softc *sc) 1929 { 1930 if (sc->rxchainmask == 0x3 || sc->rxchainmask == 0x5) { 1931 AR_WRITE(sc, AR_PHY_RX_CHAINMASK, sc->rxchainmask); 1932 AR_WRITE(sc, AR_PHY_CAL_CHAINMASK, sc->rxchainmask); 1933 AR_WRITE_BARRIER(sc); 1934 } 1935 } 1936 1937 void 1938 ar9003_read_noisefloor(struct athn_softc *sc, int16_t *nf, int16_t *nf_ext) 1939 { 1940 /* Sign-extends 9-bit value (assumes upper bits are zeroes). */ 1941 #define SIGN_EXT(v) (((v) ^ 0x100) - 0x100) 1942 uint32_t reg; 1943 int i; 1944 1945 for (i = 0; i < sc->nrxchains; i++) { 1946 reg = AR_READ(sc, AR_PHY_CCA(i)); 1947 nf[i] = MS(reg, AR_PHY_MINCCA_PWR); 1948 nf[i] = SIGN_EXT(nf[i]); 1949 1950 reg = AR_READ(sc, AR_PHY_EXT_CCA(i)); 1951 nf_ext[i] = MS(reg, AR_PHY_EXT_MINCCA_PWR); 1952 nf_ext[i] = SIGN_EXT(nf_ext[i]); 1953 } 1954 #undef SIGN_EXT 1955 } 1956 1957 void 1958 ar9003_write_noisefloor(struct athn_softc *sc, int16_t *nf, int16_t *nf_ext) 1959 { 1960 uint32_t reg; 1961 int i; 1962 1963 for (i = 0; i < sc->nrxchains; i++) { 1964 reg = AR_READ(sc, AR_PHY_CCA(i)); 1965 reg = RW(reg, AR_PHY_MAXCCA_PWR, nf[i]); 1966 AR_WRITE(sc, AR_PHY_CCA(i), reg); 1967 1968 reg = AR_READ(sc, AR_PHY_EXT_CCA(i)); 1969 reg = RW(reg, AR_PHY_EXT_MAXCCA_PWR, nf_ext[i]); 1970 AR_WRITE(sc, AR_PHY_EXT_CCA(i), reg); 1971 } 1972 AR_WRITE_BARRIER(sc); 1973 } 1974 1975 void 1976 ar9003_get_noisefloor(struct athn_softc *sc, struct ieee80211_channel *c) 1977 { 1978 int16_t nf[AR_MAX_CHAINS], nf_ext[AR_MAX_CHAINS]; 1979 int16_t min, max; 1980 int i; 1981 1982 if (AR_READ(sc, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) { 1983 /* Noisefloor calibration not finished. */ 1984 return; 1985 } 1986 /* Noisefloor calibration is finished. */ 1987 ar9003_read_noisefloor(sc, nf, nf_ext); 1988 1989 if (IEEE80211_IS_CHAN_2GHZ(c)) { 1990 min = sc->cca_min_2g; 1991 max = sc->cca_max_2g; 1992 } else { 1993 min = sc->cca_min_5g; 1994 max = sc->cca_max_5g; 1995 } 1996 /* Update noisefloor history. */ 1997 for (i = 0; i < sc->nrxchains; i++) { 1998 if (nf[i] < min) 1999 nf[i] = min; 2000 else if (nf[i] > max) 2001 nf[i] = max; 2002 if (nf_ext[i] < min) 2003 nf_ext[i] = min; 2004 else if (nf_ext[i] > max) 2005 nf_ext[i] = max; 2006 2007 sc->nf_hist[sc->nf_hist_cur].nf[i] = nf[i]; 2008 sc->nf_hist[sc->nf_hist_cur].nf_ext[i] = nf_ext[i]; 2009 } 2010 if (++sc->nf_hist_cur >= ATHN_NF_CAL_HIST_MAX) 2011 sc->nf_hist_cur = 0; 2012 } 2013 2014 void 2015 ar9003_bb_load_noisefloor(struct athn_softc *sc) 2016 { 2017 int16_t nf[AR_MAX_CHAINS], nf_ext[AR_MAX_CHAINS]; 2018 int i, ntries; 2019 2020 /* Write filtered noisefloor values. */ 2021 for (i = 0; i < sc->nrxchains; i++) { 2022 nf[i] = sc->nf_priv[i] * 2; 2023 nf_ext[i] = sc->nf_ext_priv[i] * 2; 2024 } 2025 ar9003_write_noisefloor(sc, nf, nf_ext); 2026 2027 /* Load filtered noisefloor values into baseband. */ 2028 AR_CLRBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF); 2029 AR_CLRBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF); 2030 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); 2031 /* Wait for load to complete. */ 2032 for (ntries = 0; ntries < 1000; ntries++) { 2033 if (!(AR_READ(sc, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF)) 2034 break; 2035 DELAY(10); 2036 } 2037 if (ntries == 1000) { 2038 DPRINTF(("failed to load noisefloor values\n")); 2039 return; 2040 } 2041 2042 /* Restore noisefloor values to initial (max) values. */ 2043 for (i = 0; i < AR_MAX_CHAINS; i++) 2044 nf[i] = nf_ext[i] = -50 * 2; 2045 ar9003_write_noisefloor(sc, nf, nf_ext); 2046 } 2047 2048 void 2049 ar9300_noisefloor_calib(struct athn_softc *sc) 2050 { 2051 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF); 2052 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF); 2053 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); 2054 } 2055 2056 void 2057 ar9003_do_noisefloor_calib(struct athn_softc *sc) 2058 { 2059 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); 2060 } 2061 2062 int 2063 ar9003_init_calib(struct athn_softc *sc) 2064 { 2065 uint8_t txchainmask, rxchainmask; 2066 uint32_t reg; 2067 int ntries; 2068 2069 /* Save chains masks. */ 2070 txchainmask = sc->txchainmask; 2071 rxchainmask = sc->rxchainmask; 2072 /* Configure hardware before calibration. */ 2073 if (AR_READ(sc, AR_ENT_OTP) & AR_ENT_OTP_CHAIN2_DISABLE) 2074 txchainmask = rxchainmask = 0x3; 2075 else 2076 txchainmask = rxchainmask = 0x7; 2077 ar9003_init_chains(sc); 2078 2079 /* Perform Tx IQ calibration. */ 2080 ar9003_calib_tx_iq(sc); 2081 /* Disable and re-enable the PHY chips. */ 2082 AR_WRITE(sc, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); 2083 AR_WRITE_BARRIER(sc); 2084 DELAY(5); 2085 AR_WRITE(sc, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); 2086 2087 /* Calibrate the AGC. */ 2088 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL); 2089 /* Poll for offset calibration completion. */ 2090 for (ntries = 0; ntries < 10000; ntries++) { 2091 reg = AR_READ(sc, AR_PHY_AGC_CONTROL); 2092 if (!(reg & AR_PHY_AGC_CONTROL_CAL)) 2093 break; 2094 DELAY(10); 2095 } 2096 if (ntries == 10000) 2097 return (ETIMEDOUT); 2098 2099 /* Restore chains masks. */ 2100 sc->txchainmask = txchainmask; 2101 sc->rxchainmask = rxchainmask; 2102 ar9003_init_chains(sc); 2103 2104 return (0); 2105 } 2106 2107 void 2108 ar9003_do_calib(struct athn_softc *sc) 2109 { 2110 uint32_t reg; 2111 2112 if (sc->cur_calib_mask & ATHN_CAL_IQ) { 2113 reg = AR_READ(sc, AR_PHY_TIMING4); 2114 reg = RW(reg, AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX, 10); 2115 AR_WRITE(sc, AR_PHY_TIMING4, reg); 2116 AR_WRITE(sc, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ); 2117 AR_SETBITS(sc, AR_PHY_TIMING4, AR_PHY_TIMING4_DO_CAL); 2118 AR_WRITE_BARRIER(sc); 2119 } else if (sc->cur_calib_mask & ATHN_CAL_TEMP) { 2120 AR_SETBITS(sc, AR_PHY_65NM_CH0_THERM, 2121 AR_PHY_65NM_CH0_THERM_LOCAL); 2122 AR_SETBITS(sc, AR_PHY_65NM_CH0_THERM, 2123 AR_PHY_65NM_CH0_THERM_START); 2124 AR_WRITE_BARRIER(sc); 2125 } 2126 } 2127 2128 void 2129 ar9003_next_calib(struct athn_softc *sc) 2130 { 2131 /* Check if we have any calibration in progress. */ 2132 if (sc->cur_calib_mask != 0) { 2133 if (!(AR_READ(sc, AR_PHY_TIMING4) & AR_PHY_TIMING4_DO_CAL)) { 2134 /* Calibration completed for current sample. */ 2135 ar9003_calib_iq(sc); 2136 } 2137 } 2138 } 2139 2140 void 2141 ar9003_calib_iq(struct athn_softc *sc) 2142 { 2143 struct athn_iq_cal *cal; 2144 uint32_t reg, i_coff_denom, q_coff_denom; 2145 int32_t i_coff, q_coff; 2146 int i, iq_corr_neg; 2147 2148 for (i = 0; i < AR_MAX_CHAINS; i++) { 2149 cal = &sc->calib.iq[i]; 2150 2151 /* Read IQ calibration measures (clear on read). */ 2152 cal->pwr_meas_i = AR_READ(sc, AR_PHY_IQ_ADC_MEAS_0_B(i)); 2153 cal->pwr_meas_q = AR_READ(sc, AR_PHY_IQ_ADC_MEAS_1_B(i)); 2154 cal->iq_corr_meas = 2155 (int32_t)AR_READ(sc, AR_PHY_IQ_ADC_MEAS_2_B(i)); 2156 } 2157 2158 for (i = 0; i < sc->nrxchains; i++) { 2159 cal = &sc->calib.iq[i]; 2160 2161 if (cal->pwr_meas_q == 0) 2162 continue; 2163 2164 if ((iq_corr_neg = cal->iq_corr_meas < 0)) 2165 cal->iq_corr_meas = -cal->iq_corr_meas; 2166 2167 i_coff_denom = 2168 (cal->pwr_meas_i / 2 + cal->pwr_meas_q / 2) / 256; 2169 q_coff_denom = cal->pwr_meas_q / 64; 2170 2171 if (i_coff_denom == 0 || q_coff_denom == 0) 2172 continue; /* Prevents division by zero. */ 2173 2174 i_coff = cal->iq_corr_meas / i_coff_denom; 2175 q_coff = (cal->pwr_meas_i / q_coff_denom) - 64; 2176 2177 if (i_coff > 63) 2178 i_coff = 63; 2179 else if (i_coff < -63) 2180 i_coff = -63; 2181 /* Negate i_coff if iq_corr_meas is positive. */ 2182 if (!iq_corr_neg) 2183 i_coff = -i_coff; 2184 if (q_coff > 63) 2185 q_coff = 63; 2186 else if (q_coff < -63) 2187 q_coff = -63; 2188 2189 DPRINTFN(2, ("IQ calibration for chain %d\n", i)); 2190 reg = AR_READ(sc, AR_PHY_RX_IQCAL_CORR_B(i)); 2191 reg = RW(reg, AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF, i_coff); 2192 reg = RW(reg, AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF, q_coff); 2193 AR_WRITE(sc, AR_PHY_RX_IQCAL_CORR_B(i), reg); 2194 } 2195 2196 /* Apply new settings. */ 2197 AR_SETBITS(sc, AR_PHY_RX_IQCAL_CORR_B(0), 2198 AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE); 2199 AR_WRITE_BARRIER(sc); 2200 2201 /* IQ calibration done. */ 2202 sc->cur_calib_mask &= ~ATHN_CAL_IQ; 2203 memset(&sc->calib, 0, sizeof(sc->calib)); 2204 } 2205 2206 #define DELPT 32 2207 int 2208 ar9003_get_iq_corr(struct athn_softc *sc, int32_t res[6], int32_t coeff[2]) 2209 { 2210 /* Sign-extends 12-bit value (assumes upper bits are zeroes). */ 2211 #define SIGN_EXT(v) (((v) ^ 0x800) - 0x800) 2212 #define SCALE (1 << 15) 2213 #define SHIFT (1 << 8) 2214 struct { 2215 int32_t m, p, c; 2216 } val[2][2]; 2217 int32_t mag[2][2], phs[2][2], cos[2], sin[2]; 2218 int32_t min, max, div, f1, f2, f3, m, p, c; 2219 int32_t txmag, txphs, rxmag, rxphs; 2220 int32_t q_coff, i_coff; 2221 int i, j; 2222 2223 /* Extract our twelve signed 12-bit values from res[] array. */ 2224 val[0][0].m = res[0] & 0xfff; 2225 val[0][0].p = (res[0] >> 12) & 0xfff; 2226 val[0][0].c = ((res[0] >> 24) & 0xff) | (res[1] & 0xf) << 8; 2227 2228 val[0][1].m = (res[1] >> 4) & 0xfff; 2229 val[0][1].p = res[2] & 0xfff; 2230 val[0][1].c = (res[2] >> 12) & 0xfff; 2231 2232 val[1][0].m = ((res[2] >> 24) & 0xff) | (res[3] & 0xf) << 8; 2233 val[1][0].p = (res[3] >> 4) & 0xfff; 2234 val[1][0].c = res[4] & 0xfff; 2235 2236 val[1][1].m = (res[4] >> 12) & 0xfff; 2237 val[1][1].p = ((res[4] >> 24) & 0xff) | (res[5] & 0xf) << 8; 2238 val[1][1].c = (res[5] >> 4) & 0xfff; 2239 2240 for (i = 0; i < 2; i++) { 2241 for (j = 0; j < 2; j++) { 2242 m = SIGN_EXT(val[i][j].m); 2243 p = SIGN_EXT(val[i][j].p); 2244 c = SIGN_EXT(val[i][j].c); 2245 2246 if (p == 0) 2247 return (1); /* Prevent division by 0. */ 2248 2249 mag[i][j] = (m * SCALE) / p; 2250 phs[i][j] = (c * SCALE) / p; 2251 } 2252 sin[i] = ((mag[i][0] - mag[i][1]) * SHIFT) / DELPT; 2253 cos[i] = ((phs[i][0] - phs[i][1]) * SHIFT) / DELPT; 2254 /* Find magnitude by approximation. */ 2255 min = MIN(abs(sin[i]), abs(cos[i])); 2256 max = MAX(abs(sin[i]), abs(cos[i])); 2257 div = max - (max / 32) + (min / 8) + (min / 4); 2258 if (div == 0) 2259 return (1); /* Prevent division by 0. */ 2260 /* Normalize sin and cos by magnitude. */ 2261 sin[i] = (sin[i] * SCALE) / div; 2262 cos[i] = (cos[i] * SCALE) / div; 2263 } 2264 2265 /* Compute IQ mismatch (solve 4x4 linear equation). */ 2266 f1 = cos[0] - cos[1]; 2267 f3 = sin[0] - sin[1]; 2268 f2 = (f1 * f1 + f3 * f3) / SCALE; 2269 if (f2 == 0) 2270 return (1); /* Prevent division by 0. */ 2271 2272 /* Compute Tx magnitude mismatch. */ 2273 txmag = (f1 * ( mag[0][0] - mag[1][0]) + 2274 f3 * ( phs[0][0] - phs[1][0])) / f2; 2275 /* Compute Tx phase mismatch. */ 2276 txphs = (f3 * (-mag[0][0] + mag[1][0]) + 2277 f1 * ( phs[0][0] - phs[1][0])) / f2; 2278 2279 if (txmag == SCALE) 2280 return (1); /* Prevent division by 0. */ 2281 2282 /* Compute Rx magnitude mismatch. */ 2283 rxmag = mag[0][0] - (cos[0] * txmag + sin[0] * txphs) / SCALE; 2284 /* Compute Rx phase mismatch. */ 2285 rxphs = phs[0][0] + (sin[0] * txmag - cos[0] * txphs) / SCALE; 2286 2287 if (-rxmag == SCALE) 2288 return (1); /* Prevent division by 0. */ 2289 2290 txmag = (txmag * SCALE) / (SCALE - txmag); 2291 txphs = -txphs; 2292 2293 q_coff = (txmag * 128) / SCALE; 2294 if (q_coff < -63) 2295 q_coff = -63; 2296 else if (q_coff > 63) 2297 q_coff = 63; 2298 i_coff = (txphs * 256) / SCALE; 2299 if (i_coff < -63) 2300 i_coff = -63; 2301 else if (i_coff > 63) 2302 i_coff = 63; 2303 coeff[0] = q_coff * 128 + i_coff; 2304 2305 rxmag = (-rxmag * SCALE) / (SCALE + rxmag); 2306 rxphs = -rxphs; 2307 2308 q_coff = (rxmag * 128) / SCALE; 2309 if (q_coff < -63) 2310 q_coff = -63; 2311 else if (q_coff > 63) 2312 q_coff = 63; 2313 i_coff = (rxphs * 256) / SCALE; 2314 if (i_coff < -63) 2315 i_coff = -63; 2316 else if (i_coff > 63) 2317 i_coff = 63; 2318 coeff[1] = q_coff * 128 + i_coff; 2319 2320 return (0); 2321 #undef SHIFT 2322 #undef SCALE 2323 #undef SIGN_EXT 2324 } 2325 2326 int 2327 ar9003_calib_tx_iq(struct athn_softc *sc) 2328 { 2329 uint32_t reg; 2330 int32_t res[6], coeff[2]; 2331 int i, j, ntries; 2332 2333 reg = AR_READ(sc, AR_PHY_TX_IQCAL_CONTROL_1); 2334 reg = RW(reg, AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT, DELPT); 2335 AR_WRITE(sc, AR_PHY_TX_IQCAL_CONTROL_1, reg); 2336 2337 /* Start Tx IQ calibration. */ 2338 AR_SETBITS(sc, AR_PHY_TX_IQCAL_START, AR_PHY_TX_IQCAL_START_DO_CAL); 2339 /* Wait for completion. */ 2340 for (ntries = 0; ntries < 10000; ntries++) { 2341 reg = AR_READ(sc, AR_PHY_TX_IQCAL_START); 2342 if (!(reg & AR_PHY_TX_IQCAL_START_DO_CAL)) 2343 break; 2344 DELAY(10); 2345 } 2346 if (ntries == 10000) 2347 return (ETIMEDOUT); 2348 2349 for (i = 0; i < sc->ntxchains; i++) { 2350 /* Read Tx IQ calibration status for this chain. */ 2351 reg = AR_READ(sc, AR_PHY_TX_IQCAL_STATUS_B(i)); 2352 if (reg & AR_PHY_TX_IQCAL_STATUS_FAILED) 2353 return (EIO); 2354 /* 2355 * Read Tx IQ calibration results for this chain. 2356 * This consists in twelve signed 12-bit values. 2357 */ 2358 for (j = 0; j < 3; j++) { 2359 AR_CLRBITS(sc, AR_PHY_CHAN_INFO_MEMORY, 2360 AR_PHY_CHAN_INFO_TAB_S2_READ); 2361 reg = AR_READ(sc, AR_PHY_CHAN_INFO_TAB(i, j)); 2362 res[j * 2 + 0] = reg; 2363 2364 AR_SETBITS(sc, AR_PHY_CHAN_INFO_MEMORY, 2365 AR_PHY_CHAN_INFO_TAB_S2_READ); 2366 reg = AR_READ(sc, AR_PHY_CHAN_INFO_TAB(i, j)); 2367 res[j * 2 + 1] = reg & 0xffff; 2368 } 2369 2370 /* Compute Tx IQ correction. */ 2371 if (ar9003_get_iq_corr(sc, res, coeff) != 0) 2372 return (EIO); 2373 2374 /* Write Tx IQ correction coefficients. */ 2375 reg = AR_READ(sc, AR_PHY_TX_IQCAL_CORR_COEFF_01_B(i)); 2376 reg = RW(reg, AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE, 2377 coeff[0]); 2378 AR_WRITE(sc, AR_PHY_TX_IQCAL_CORR_COEFF_01_B(i), reg); 2379 2380 reg = AR_READ(sc, AR_PHY_RX_IQCAL_CORR_B(i)); 2381 reg = RW(reg, AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF, 2382 coeff[1] >> 7); 2383 reg = RW(reg, AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF, 2384 coeff[1]); 2385 AR_WRITE(sc, AR_PHY_RX_IQCAL_CORR_B(i), reg); 2386 AR_WRITE_BARRIER(sc); 2387 } 2388 2389 /* Enable Tx IQ correction. */ 2390 AR_SETBITS(sc, AR_PHY_TX_IQCAL_CONTROL_3, 2391 AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN); 2392 AR_SETBITS(sc, AR_PHY_RX_IQCAL_CORR_B(0), 2393 AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN); 2394 AR_WRITE_BARRIER(sc); 2395 return (0); 2396 } 2397 #undef DELPT 2398 2399 /*- 2400 * The power amplifier predistortion state machine works as follows: 2401 * 1) Disable digital predistorters for all Tx chains 2402 * 2) Repeat steps 3~7 for all Tx chains 2403 * 3) Force Tx gain to that of training signal 2404 * 4) Send training signal (asynchronous) 2405 * 5) Wait for training signal to complete (asynchronous) 2406 * 6) Read PA measurements (input power, output power, output phase) 2407 * 7) Compute the predistortion function that linearizes PA output 2408 * 8) Write predistortion functions to hardware tables for all Tx chains 2409 * 9) Enable digital predistorters for all Tx chains 2410 */ 2411 void 2412 ar9003_paprd_calib(struct athn_softc *sc, struct ieee80211_channel *c) 2413 { 2414 static const int scaling[] = { 2415 261376, 248079, 233759, 220464, 2416 208194, 196949, 185706, 175487 2417 }; 2418 struct athn_ops *ops = &sc->ops; 2419 uint32_t reg, ht20mask, ht40mask; 2420 int i; 2421 2422 /* Read PA predistortion masks from ROM. */ 2423 ops->get_paprd_masks(sc, c, &ht20mask, &ht40mask); 2424 2425 /* AM-to-AM: amplifier's amplitude characteristic. */ 2426 reg = AR_READ(sc, AR_PHY_PAPRD_AM2AM); 2427 reg = RW(reg, AR_PHY_PAPRD_AM2AM_MASK, ht20mask); 2428 AR_WRITE(sc, AR_PHY_PAPRD_AM2AM, reg); 2429 2430 /* AM-to-PM: amplifier's phase transfer characteristic. */ 2431 reg = AR_READ(sc, AR_PHY_PAPRD_AM2PM); 2432 reg = RW(reg, AR_PHY_PAPRD_AM2PM_MASK, ht20mask); 2433 AR_WRITE(sc, AR_PHY_PAPRD_AM2PM, reg); 2434 2435 reg = AR_READ(sc, AR_PHY_PAPRD_HT40); 2436 reg = RW(reg, AR_PHY_PAPRD_HT40_MASK, ht40mask); 2437 AR_WRITE(sc, AR_PHY_PAPRD_HT40, reg); 2438 2439 for (i = 0; i < AR9003_MAX_CHAINS; i++) { 2440 AR_SETBITS(sc, AR_PHY_PAPRD_CTRL0_B(i), 2441 AR_PHY_PAPRD_CTRL0_USE_SINGLE_TABLE); 2442 2443 reg = AR_READ(sc, AR_PHY_PAPRD_CTRL1_B(i)); 2444 reg = RW(reg, AR_PHY_PAPRD_CTRL1_PA_GAIN_SCALE_FACT, 181); 2445 reg = RW(reg, AR_PHY_PAPRD_CTRL1_MAG_SCALE_FACT, 361); 2446 reg &= ~AR_PHY_PAPRD_CTRL1_ADAPTIVE_SCALING_ENA; 2447 reg |= AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2AM_ENA; 2448 reg |= AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2PM_ENA; 2449 AR_WRITE(sc, AR_PHY_PAPRD_CTRL1_B(i), reg); 2450 2451 reg = AR_READ(sc, AR_PHY_PAPRD_CTRL0_B(i)); 2452 reg = RW(reg, AR_PHY_PAPRD_CTRL0_PAPRD_MAG_THRSH, 3); 2453 AR_WRITE(sc, AR_PHY_PAPRD_CTRL0_B(i), reg); 2454 } 2455 2456 /* Disable all digital predistorters during calibration. */ 2457 for (i = 0; i < AR9003_MAX_CHAINS; i++) { 2458 AR_CLRBITS(sc, AR_PHY_PAPRD_CTRL0_B(i), 2459 AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE); 2460 } 2461 AR_WRITE_BARRIER(sc); 2462 2463 /* 2464 * Configure training signal. 2465 */ 2466 reg = AR_READ(sc, AR_PHY_PAPRD_TRAINER_CNTL1); 2467 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL1_AGC2_SETTLING, 28); 2468 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL1_LB_SKIP, 0x30); 2469 reg &= ~AR_PHY_PAPRD_TRAINER_CNTL1_RX_BB_GAIN_FORCE; 2470 reg &= ~AR_PHY_PAPRD_TRAINER_CNTL1_IQCORR_ENABLE; 2471 reg |= AR_PHY_PAPRD_TRAINER_CNTL1_LB_ENABLE; 2472 reg |= AR_PHY_PAPRD_TRAINER_CNTL1_TX_GAIN_FORCE; 2473 reg |= AR_PHY_PAPRD_TRAINER_CNTL1_TRAIN_ENABLE; 2474 AR_WRITE(sc, AR_PHY_PAPRD_TRAINER_CNTL1, reg); 2475 2476 AR_WRITE(sc, AR_PHY_PAPRD_TRAINER_CNTL2, 147); 2477 2478 reg = AR_READ(sc, AR_PHY_PAPRD_TRAINER_CNTL3); 2479 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_FINE_CORR_LEN, 4); 2480 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_COARSE_CORR_LEN, 4); 2481 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_NUM_CORR_STAGES, 7); 2482 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_MIN_LOOPBACK_DEL, 1); 2483 if (AR_SREV_9485(sc)) 2484 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_QUICK_DROP, -3); 2485 else 2486 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_QUICK_DROP, -6); 2487 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_ADC_DESIRED_SIZE, -15); 2488 reg |= AR_PHY_PAPRD_TRAINER_CNTL3_BBTXMIX_DISABLE; 2489 AR_WRITE(sc, AR_PHY_PAPRD_TRAINER_CNTL3, reg); 2490 2491 reg = AR_READ(sc, AR_PHY_PAPRD_TRAINER_CNTL4); 2492 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL4_SAFETY_DELTA, 0); 2493 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL4_MIN_CORR, 400); 2494 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL4_NUM_TRAIN_SAMPLES, 100); 2495 AR_WRITE(sc, AR_PHY_PAPRD_TRAINER_CNTL4, reg); 2496 2497 for (i = 0; i < nitems(scaling); i++) { 2498 reg = AR_READ(sc, AR_PHY_PAPRD_PRE_POST_SCALE_B0(i)); 2499 reg = RW(reg, AR_PHY_PAPRD_PRE_POST_SCALING, scaling[i]); 2500 AR_WRITE(sc, AR_PHY_PAPRD_PRE_POST_SCALE_B0(i), reg); 2501 } 2502 2503 /* Save Tx gain table. */ 2504 for (i = 0; i < AR9003_TX_GAIN_TABLE_SIZE; i++) 2505 sc->txgain[i] = AR_READ(sc, AR_PHY_TXGAIN_TABLE(i)); 2506 2507 /* Set Tx power of training signal (use setting for MCS0). */ 2508 sc->trainpow = MS(AR_READ(sc, AR_PHY_PWRTX_RATE5), 2509 AR_PHY_PWRTX_RATE5_POWERTXHT20_0) - 4; 2510 2511 /* 2512 * Start PA predistortion calibration state machine. 2513 */ 2514 /* Find first available Tx chain. */ 2515 sc->paprd_curchain = 0; 2516 while (!(sc->txchainmask & (1 << sc->paprd_curchain))) 2517 sc->paprd_curchain++; 2518 2519 /* Make sure training done bit is clear. */ 2520 AR_CLRBITS(sc, AR_PHY_PAPRD_TRAINER_STAT1, 2521 AR_PHY_PAPRD_TRAINER_STAT1_TRAIN_DONE); 2522 AR_WRITE_BARRIER(sc); 2523 2524 /* Transmit training signal. */ 2525 ar9003_paprd_tx_tone(sc); 2526 } 2527 2528 int 2529 ar9003_get_desired_txgain(struct athn_softc *sc, int chain, int pow) 2530 { 2531 int32_t scale, atemp, avolt, tempcal, voltcal, temp, volt; 2532 int32_t tempcorr, voltcorr; 2533 uint32_t reg; 2534 int8_t delta; 2535 2536 scale = MS(AR_READ(sc, AR_PHY_TPC_12), 2537 AR_PHY_TPC_12_DESIRED_SCALE_HT40_5); 2538 2539 reg = AR_READ(sc, AR_PHY_TPC_19); 2540 atemp = MS(reg, AR_PHY_TPC_19_ALPHA_THERM); 2541 avolt = MS(reg, AR_PHY_TPC_19_ALPHA_VOLT); 2542 2543 reg = AR_READ(sc, AR_PHY_TPC_18); 2544 tempcal = MS(reg, AR_PHY_TPC_18_THERM_CAL); 2545 voltcal = MS(reg, AR_PHY_TPC_18_VOLT_CAL); 2546 2547 reg = AR_READ(sc, AR_PHY_BB_THERM_ADC_4); 2548 temp = MS(reg, AR_PHY_BB_THERM_ADC_4_LATEST_THERM); 2549 volt = MS(reg, AR_PHY_BB_THERM_ADC_4_LATEST_VOLT); 2550 2551 delta = (int8_t)MS(AR_READ(sc, AR_PHY_TPC_11_B(chain)), 2552 AR_PHY_TPC_11_OLPC_GAIN_DELTA); 2553 2554 /* Compute temperature and voltage correction. */ 2555 tempcorr = (atemp * (temp - tempcal) + 128) / 256; 2556 voltcorr = (avolt * (volt - voltcal) + 64) / 128; 2557 2558 /* Compute desired Tx gain. */ 2559 return (pow - delta - tempcorr - voltcorr + scale); 2560 } 2561 2562 void 2563 ar9003_force_txgain(struct athn_softc *sc, uint32_t txgain) 2564 { 2565 uint32_t reg; 2566 2567 reg = AR_READ(sc, AR_PHY_TX_FORCED_GAIN); 2568 reg = RW(reg, AR_PHY_TX_FORCED_GAIN_TXBB1DBGAIN, 2569 MS(txgain, AR_PHY_TXGAIN_TXBB1DBGAIN)); 2570 reg = RW(reg, AR_PHY_TX_FORCED_GAIN_TXBB6DBGAIN, 2571 MS(txgain, AR_PHY_TXGAIN_TXBB6DBGAIN)); 2572 reg = RW(reg, AR_PHY_TX_FORCED_GAIN_TXMXRGAIN, 2573 MS(txgain, AR_PHY_TXGAIN_TXMXRGAIN)); 2574 reg = RW(reg, AR_PHY_TX_FORCED_GAIN_PADRVGNA, 2575 MS(txgain, AR_PHY_TXGAIN_PADRVGNA)); 2576 reg = RW(reg, AR_PHY_TX_FORCED_GAIN_PADRVGNB, 2577 MS(txgain, AR_PHY_TXGAIN_PADRVGNB)); 2578 reg = RW(reg, AR_PHY_TX_FORCED_GAIN_PADRVGNC, 2579 MS(txgain, AR_PHY_TXGAIN_PADRVGNC)); 2580 reg = RW(reg, AR_PHY_TX_FORCED_GAIN_PADRVGND, 2581 MS(txgain, AR_PHY_TXGAIN_PADRVGND)); 2582 reg &= ~AR_PHY_TX_FORCED_GAIN_ENABLE_PAL; 2583 reg &= ~AR_PHY_TX_FORCED_GAIN_FORCE_TX_GAIN; 2584 AR_WRITE(sc, AR_PHY_TX_FORCED_GAIN, reg); 2585 2586 reg = AR_READ(sc, AR_PHY_TPC_1); 2587 reg = RW(reg, AR_PHY_TPC_1_FORCED_DAC_GAIN, 0); 2588 reg &= ~AR_PHY_TPC_1_FORCE_DAC_GAIN; 2589 AR_WRITE(sc, AR_PHY_TPC_1, reg); 2590 AR_WRITE_BARRIER(sc); 2591 } 2592 2593 void 2594 ar9003_set_training_gain(struct athn_softc *sc, int chain) 2595 { 2596 int i, gain; 2597 2598 /* 2599 * Get desired gain for training signal power (take into account 2600 * current temperature/voltage). 2601 */ 2602 gain = ar9003_get_desired_txgain(sc, chain, sc->trainpow); 2603 /* Find entry in table. */ 2604 for (i = 0; i < AR9003_TX_GAIN_TABLE_SIZE - 1; i++) 2605 if (MS(sc->txgain[i], AR_PHY_TXGAIN_INDEX) >= gain) 2606 break; 2607 ar9003_force_txgain(sc, sc->txgain[i]); 2608 } 2609 2610 int 2611 ar9003_paprd_tx_tone(struct athn_softc *sc) 2612 { 2613 #define TONE_LEN 1800 2614 struct ieee80211com *ic = &sc->sc_ic; 2615 struct ieee80211_frame *wh; 2616 struct ieee80211_node *ni; 2617 struct mbuf *m; 2618 int error; 2619 2620 /* Build a Null (no data) frame of TONE_LEN bytes. */ 2621 m = MCLGETI(NULL, M_DONTWAIT, NULL, TONE_LEN); 2622 if (m == NULL) 2623 return (ENOBUFS); 2624 memset(mtod(m, caddr_t), 0, TONE_LEN); 2625 wh = mtod(m, struct ieee80211_frame *); 2626 wh->i_fc[0] = IEEE80211_FC0_TYPE_DATA | IEEE80211_FC0_SUBTYPE_NODATA; 2627 wh->i_fc[1] = IEEE80211_FC1_DIR_NODS; 2628 *(uint16_t *)wh->i_dur = htole16(10); /* XXX */ 2629 IEEE80211_ADDR_COPY(wh->i_addr1, ic->ic_myaddr); 2630 IEEE80211_ADDR_COPY(wh->i_addr2, ic->ic_myaddr); 2631 IEEE80211_ADDR_COPY(wh->i_addr3, ic->ic_myaddr); 2632 m->m_pkthdr.len = m->m_len = TONE_LEN; 2633 2634 /* Set gain of training signal. */ 2635 ar9003_set_training_gain(sc, sc->paprd_curchain); 2636 2637 /* Transmit training signal. */ 2638 ni = ieee80211_ref_node(ic->ic_bss); 2639 if ((error = ar9003_tx(sc, m, ni, ATHN_TXFLAG_PAPRD)) != 0) 2640 ieee80211_release_node(ic, ni); 2641 return (error); 2642 #undef TONE_LEN 2643 } 2644 2645 static __inline int 2646 get_scale(int val) 2647 { 2648 int log = 0; 2649 2650 /* Find the log base 2 (position of highest bit set). */ 2651 while (val >>= 1) 2652 log++; 2653 2654 return ((log > 10) ? log - 10 : 0); 2655 } 2656 2657 /* 2658 * Compute predistortion function to linearize power amplifier output based 2659 * on feedback from training signal. 2660 */ 2661 int 2662 ar9003_compute_predistortion(struct athn_softc *sc, const uint32_t *lo, 2663 const uint32_t *hi) 2664 { 2665 #define NBINS 23 2666 int chain = sc->paprd_curchain; 2667 int x[NBINS + 1], y[NBINS + 1], t[NBINS + 1]; 2668 int b1[NBINS + 1], b2[NBINS + 1], xtilde[NBINS + 1]; 2669 int nsamples, txsum, rxsum, rosum, maxidx; 2670 int order, order5x, order5xrem, order3x, order3xrem, y5, y3; 2671 int icept, G, I, L, M, angle, xnonlin, y2, y4, sumy2, sumy4; 2672 int alpha, beta, scale, Qalpha, Qbeta, Qscale, Qx, Qb1, Qb2; 2673 int tavg, ttilde, maxb1abs, maxb2abs, maxxtildeabs, in; 2674 int tmp, i; 2675 2676 /* Set values at origin. */ 2677 x[0] = y[0] = t[0] = 0; 2678 2679 #define SCALE 32 2680 maxidx = 0; 2681 for (i = 0; i < NBINS; i++) { 2682 nsamples = lo[i] & 0xffff; 2683 /* Skip bins that contain 16 or less samples. */ 2684 if (nsamples <= 16) { 2685 x[i + 1] = y[i + 1] = t[i + 1] = 0; 2686 continue; 2687 } 2688 txsum = (hi[i] & 0x7ff) << 16 | lo[i] >> 16; 2689 rxsum = (lo[i + NBINS] & 0xffff) << 5 | 2690 ((hi[i] >> 11) & 0x1f); 2691 rosum = (hi[i + NBINS] & 0x7ff) << 16 | hi[i + NBINS] >> 16; 2692 /* Sign-extend 27-bit value. */ 2693 rosum = (rosum ^ 0x4000000) - 0x4000000; 2694 2695 txsum *= SCALE; 2696 rxsum *= SCALE; 2697 rosum *= SCALE; 2698 2699 x[i + 1] = ((txsum + nsamples) / nsamples + SCALE) / SCALE; 2700 y[i + 1] = ((rxsum + nsamples) / nsamples + SCALE) / SCALE + 2701 SCALE * maxidx + SCALE / 2; 2702 t[i + 1] = (rosum + nsamples) / nsamples; 2703 maxidx++; 2704 } 2705 #undef SCALE 2706 2707 #define SCALE_LOG 8 2708 #define SCALE (1 << SCALE_LOG) 2709 if (x[6] == x[3]) 2710 return (1); /* Prevent division by 0. */ 2711 G = ((y[6] - y[3]) * SCALE + (x[6] - x[3])) / (x[6] - x[3]); 2712 if (G == 0) 2713 return (1); /* Prevent division by 0. */ 2714 2715 sc->gain1[chain] = G; /* Save low signal gain. */ 2716 2717 /* Find interception point. */ 2718 icept = (G * (x[0] - x[3]) + SCALE) / SCALE + y[3]; 2719 for (i = 0; i <= 3; i++) { 2720 y[i] = i * 32; 2721 x[i] = (y[i] * SCALE + G) / G; 2722 } 2723 for (i = 4; i <= maxidx; i++) 2724 y[i] -= icept; 2725 2726 xnonlin = x[maxidx] - (y[maxidx] * SCALE + G) / G; 2727 order = (xnonlin + y[maxidx]) / y[maxidx]; 2728 if (order == 0) 2729 M = 10; 2730 else if (order == 1) 2731 M = 9; 2732 else 2733 M = 8; 2734 2735 I = (maxidx >= 16) ? 7 : maxidx / 2; 2736 L = maxidx - I; 2737 2738 sumy2 = sumy4 = y2 = y4 = 0; 2739 for (i = 0; i <= L; i++) { 2740 if (y[i + I] == 0) 2741 return (1); /* Prevent division by 0. */ 2742 2743 xnonlin = x[i + I] - ((y[i + I] * SCALE) + G) / G; 2744 xtilde[i] = ((xnonlin << M) + y[i + I]) / y[i + I]; 2745 xtilde[i] = ((xtilde[i] << M) + y[i + I]) / y[i + I]; 2746 xtilde[i] = ((xtilde[i] << M) + y[i + I]) / y[i + I]; 2747 2748 y2 = (y[i + I] * y[i + I] + SCALE * SCALE) / (SCALE * SCALE); 2749 2750 sumy2 += y2; 2751 sumy4 += y2 * y2; 2752 2753 b1[i] = y2 * (L + 1); 2754 b2[i] = y2; 2755 } 2756 for (i = 0; i <= L; i++) { 2757 b1[i] -= sumy2; 2758 b2[i] = sumy4 - sumy2 * b2[i]; 2759 } 2760 2761 maxxtildeabs = maxb1abs = maxb2abs = 0; 2762 for (i = 0; i <= L; i++) { 2763 tmp = abs(xtilde[i]); 2764 if (tmp > maxxtildeabs) 2765 maxxtildeabs = tmp; 2766 2767 tmp = abs(b1[i]); 2768 if (tmp > maxb1abs) 2769 maxb1abs = tmp; 2770 2771 tmp = abs(b2[i]); 2772 if (tmp > maxb2abs) 2773 maxb2abs = tmp; 2774 } 2775 Qx = get_scale(maxxtildeabs); 2776 Qb1 = get_scale(maxb1abs); 2777 Qb2 = get_scale(maxb2abs); 2778 for (i = 0; i <= L; i++) { 2779 xtilde[i] /= 1 << Qx; 2780 b1[i] /= 1 << Qb1; 2781 b2[i] /= 1 << Qb2; 2782 } 2783 2784 alpha = beta = 0; 2785 for (i = 0; i <= L; i++) { 2786 alpha += b1[i] * xtilde[i]; 2787 beta += b2[i] * xtilde[i]; 2788 } 2789 2790 scale = ((y4 / SCALE_LOG) * (L + 1) - 2791 (y2 / SCALE_LOG) * sumy2) * SCALE_LOG; 2792 2793 Qscale = get_scale(abs(scale)); 2794 scale /= 1 << Qscale; 2795 Qalpha = get_scale(abs(alpha)); 2796 alpha /= 1 << Qalpha; 2797 Qbeta = get_scale(abs(beta)); 2798 beta /= 1 << Qbeta; 2799 2800 order = 3 * M - Qx - Qb1 - Qbeta + 10 + Qscale; 2801 order5x = 1 << (order / 5); 2802 order5xrem = 1 << (order % 5); 2803 2804 order = 3 * M - Qx - Qb2 - Qalpha + 10 + Qscale; 2805 order3x = 1 << (order / 3); 2806 order3xrem = 1 << (order % 3); 2807 2808 for (i = 0; i < AR9003_PAPRD_MEM_TAB_SIZE; i++) { 2809 tmp = i * 32; 2810 2811 /* Fifth order. */ 2812 y5 = ((beta * tmp) / 64) / order5x; 2813 y5 = (y5 * tmp) / order5x; 2814 y5 = (y5 * tmp) / order5x; 2815 y5 = (y5 * tmp) / order5x; 2816 y5 = (y5 * tmp) / order5x; 2817 y5 = y5 / order5xrem; 2818 2819 /* Third oder. */ 2820 y3 = (alpha * tmp) / order3x; 2821 y3 = (y3 * tmp) / order3x; 2822 y3 = (y3 * tmp) / order3x; 2823 y3 = y3 / order3xrem; 2824 2825 in = y5 + y3 + (SCALE * tmp) / G; 2826 if (i >= 2 && in < sc->pa_in[chain][i - 1]) { 2827 in = sc->pa_in[chain][i - 1] + 2828 (sc->pa_in[chain][i - 1] - 2829 sc->pa_in[chain][i - 2]); 2830 } 2831 if (in > 1400) 2832 in = 1400; 2833 sc->pa_in[chain][i] = in; 2834 } 2835 2836 /* Compute average theta of first 5 bins (linear region). */ 2837 tavg = 0; 2838 for (i = 1; i <= 5; i++) 2839 tavg += t[i]; 2840 tavg /= 5; 2841 for (i = 1; i <= 5; i++) 2842 t[i] = 0; 2843 for (i = 6; i <= maxidx; i++) 2844 t[i] -= tavg; 2845 2846 alpha = beta = 0; 2847 for (i = 0; i <= L; i++) { 2848 ttilde = ((t[i + I] << M) + y[i + I]) / y[i + I]; 2849 ttilde = ((ttilde << M) + y[i + I]) / y[i + I]; 2850 ttilde = ((ttilde << M) + y[i + I]) / y[i + I]; 2851 2852 alpha += b2[i] * ttilde; 2853 beta += b1[i] * ttilde; 2854 } 2855 2856 Qalpha = get_scale(abs(alpha)); 2857 alpha /= 1 << Qalpha; 2858 Qbeta = get_scale(abs(beta)); 2859 beta /= 1 << Qbeta; 2860 2861 order = 3 * M - Qx - Qb1 - Qbeta + 10 + Qscale + 5; 2862 order5x = 1 << (order / 5); 2863 order5xrem = 1 << (order % 5); 2864 2865 order = 3 * M - Qx - Qb2 - Qalpha + 10 + Qscale + 5; 2866 order3x = 1 << (order / 3); 2867 order3xrem = 1 << (order % 3); 2868 2869 for (i = 0; i <= 4; i++) 2870 sc->angle[chain][i] = 0; /* Linear at that range. */ 2871 for (i = 5; i < AR9003_PAPRD_MEM_TAB_SIZE; i++) { 2872 tmp = i * 32; 2873 2874 /* Fifth order. */ 2875 if (beta > 0) 2876 y5 = (((beta * tmp - 64) / 64) - order5x) / order5x; 2877 else 2878 y5 = (((beta * tmp - 64) / 64) + order5x) / order5x; 2879 y5 = (y5 * tmp) / order5x; 2880 y5 = (y5 * tmp) / order5x; 2881 y5 = (y5 * tmp) / order5x; 2882 y5 = (y5 * tmp) / order5x; 2883 y5 = y5 / order5xrem; 2884 2885 /* Third oder. */ 2886 if (beta > 0) /* XXX alpha? */ 2887 y3 = (alpha * tmp - order3x) / order3x; 2888 else 2889 y3 = (alpha * tmp + order3x) / order3x; 2890 y3 = (y3 * tmp) / order3x; 2891 y3 = (y3 * tmp) / order3x; 2892 y3 = y3 / order3xrem; 2893 2894 angle = y5 + y3; 2895 if (angle < -150) 2896 angle = -150; 2897 else if (angle > 150) 2898 angle = 150; 2899 sc->angle[chain][i] = angle; 2900 } 2901 /* Angle for entry 4 is derived from angle for entry 5. */ 2902 sc->angle[chain][4] = (sc->angle[chain][5] + 2) / 2; 2903 2904 return (0); 2905 #undef SCALE 2906 #undef SCALE_LOG 2907 #undef NBINS 2908 } 2909 2910 void 2911 ar9003_enable_predistorter(struct athn_softc *sc, int chain) 2912 { 2913 uint32_t reg; 2914 int i; 2915 2916 /* Write digital predistorter lookup table. */ 2917 for (i = 0; i < AR9003_PAPRD_MEM_TAB_SIZE; i++) { 2918 AR_WRITE(sc, AR_PHY_PAPRD_MEM_TAB_B(chain, i), 2919 SM(AR_PHY_PAPRD_PA_IN, sc->pa_in[chain][i]) | 2920 SM(AR_PHY_PAPRD_ANGLE, sc->angle[chain][i])); 2921 } 2922 2923 reg = AR_READ(sc, AR_PHY_PA_GAIN123_B(chain)); 2924 reg = RW(reg, AR_PHY_PA_GAIN123_PA_GAIN1, sc->gain1[chain]); 2925 AR_WRITE(sc, AR_PHY_PA_GAIN123_B(chain), reg); 2926 2927 /* Indicate Tx power used for calibration (training signal). */ 2928 reg = AR_READ(sc, AR_PHY_PAPRD_CTRL1_B(chain)); 2929 reg = RW(reg, AR_PHY_PAPRD_CTRL1_POWER_AT_AM2AM_CAL, sc->trainpow); 2930 AR_WRITE(sc, AR_PHY_PAPRD_CTRL1_B(chain), reg); 2931 2932 /* Enable digital predistorter for this chain. */ 2933 AR_SETBITS(sc, AR_PHY_PAPRD_CTRL0_B(chain), 2934 AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE); 2935 AR_WRITE_BARRIER(sc); 2936 } 2937 2938 void 2939 ar9003_paprd_enable(struct athn_softc *sc) 2940 { 2941 int i; 2942 2943 /* Enable digital predistorters for all Tx chains. */ 2944 for (i = 0; i < AR9003_MAX_CHAINS; i++) 2945 if (sc->txchainmask & (1 << i)) 2946 ar9003_enable_predistorter(sc, i); 2947 } 2948 2949 /* 2950 * This function is called when our training signal has been sent. 2951 */ 2952 void 2953 ar9003_paprd_tx_tone_done(struct athn_softc *sc) 2954 { 2955 uint32_t lo[48], hi[48]; 2956 int i; 2957 2958 /* Make sure training is complete. */ 2959 if (!(AR_READ(sc, AR_PHY_PAPRD_TRAINER_STAT1) & 2960 AR_PHY_PAPRD_TRAINER_STAT1_TRAIN_DONE)) 2961 return; 2962 2963 /* Read feedback from training signal. */ 2964 AR_CLRBITS(sc, AR_PHY_CHAN_INFO_MEMORY, AR_PHY_CHAN_INFO_TAB_S2_READ); 2965 for (i = 0; i < nitems(lo); i++) 2966 lo[i] = AR_READ(sc, AR_PHY_CHAN_INFO_TAB(0, i)); 2967 AR_SETBITS(sc, AR_PHY_CHAN_INFO_MEMORY, AR_PHY_CHAN_INFO_TAB_S2_READ); 2968 for (i = 0; i < nitems(hi); i++) 2969 hi[i] = AR_READ(sc, AR_PHY_CHAN_INFO_TAB(0, i)); 2970 2971 AR_CLRBITS(sc, AR_PHY_PAPRD_TRAINER_STAT1, 2972 AR_PHY_PAPRD_TRAINER_STAT1_TRAIN_DONE); 2973 2974 /* Compute predistortion function based on this feedback. */ 2975 if (ar9003_compute_predistortion(sc, lo, hi) != 0) 2976 return; 2977 2978 /* Get next available Tx chain. */ 2979 while (++sc->paprd_curchain < AR9003_MAX_CHAINS) 2980 if (sc->txchainmask & (1 << sc->paprd_curchain)) 2981 break; 2982 if (sc->paprd_curchain == AR9003_MAX_CHAINS) { 2983 /* All Tx chains measured; enable digital predistortion. */ 2984 ar9003_paprd_enable(sc); 2985 } else /* Measure next Tx chain. */ 2986 ar9003_paprd_tx_tone(sc); 2987 } 2988 2989 void 2990 ar9003_write_txpower(struct athn_softc *sc, int16_t power[ATHN_POWER_COUNT]) 2991 { 2992 /* Make sure forced gain is disabled. */ 2993 AR_WRITE(sc, AR_PHY_TX_FORCED_GAIN, 0); 2994 2995 AR_WRITE(sc, AR_PHY_PWRTX_RATE1, 2996 (power[ATHN_POWER_OFDM18 ] & 0x3f) << 24 | 2997 (power[ATHN_POWER_OFDM12 ] & 0x3f) << 16 | 2998 (power[ATHN_POWER_OFDM9 ] & 0x3f) << 8 | 2999 (power[ATHN_POWER_OFDM6 ] & 0x3f)); 3000 AR_WRITE(sc, AR_PHY_PWRTX_RATE2, 3001 (power[ATHN_POWER_OFDM54 ] & 0x3f) << 24 | 3002 (power[ATHN_POWER_OFDM48 ] & 0x3f) << 16 | 3003 (power[ATHN_POWER_OFDM36 ] & 0x3f) << 8 | 3004 (power[ATHN_POWER_OFDM24 ] & 0x3f)); 3005 AR_WRITE(sc, AR_PHY_PWRTX_RATE3, 3006 (power[ATHN_POWER_CCK2_SP ] & 0x3f) << 24 | 3007 (power[ATHN_POWER_CCK2_LP ] & 0x3f) << 16 | 3008 /* NB: No eXtended Range for AR9003. */ 3009 (power[ATHN_POWER_CCK1_LP ] & 0x3f)); 3010 AR_WRITE(sc, AR_PHY_PWRTX_RATE4, 3011 (power[ATHN_POWER_CCK11_SP] & 0x3f) << 24 | 3012 (power[ATHN_POWER_CCK11_LP] & 0x3f) << 16 | 3013 (power[ATHN_POWER_CCK55_SP] & 0x3f) << 8 | 3014 (power[ATHN_POWER_CCK55_LP] & 0x3f)); 3015 /* 3016 * NB: AR_PHY_PWRTX_RATE5 needs to be written even if HT is disabled 3017 * because it is read by PA predistortion functions. 3018 */ 3019 AR_WRITE(sc, AR_PHY_PWRTX_RATE5, 3020 (power[ATHN_POWER_HT20( 5)] & 0x3f) << 24 | 3021 (power[ATHN_POWER_HT20( 4)] & 0x3f) << 16 | 3022 (power[ATHN_POWER_HT20( 1)] & 0x3f) << 8 | 3023 (power[ATHN_POWER_HT20( 0)] & 0x3f)); 3024 AR_WRITE(sc, AR_PHY_PWRTX_RATE6, 3025 (power[ATHN_POWER_HT20(13)] & 0x3f) << 24 | 3026 (power[ATHN_POWER_HT20(12)] & 0x3f) << 16 | 3027 (power[ATHN_POWER_HT20( 7)] & 0x3f) << 8 | 3028 (power[ATHN_POWER_HT20( 6)] & 0x3f)); 3029 AR_WRITE(sc, AR_PHY_PWRTX_RATE7, 3030 (power[ATHN_POWER_HT40( 5)] & 0x3f) << 24 | 3031 (power[ATHN_POWER_HT40( 4)] & 0x3f) << 16 | 3032 (power[ATHN_POWER_HT40( 1)] & 0x3f) << 8 | 3033 (power[ATHN_POWER_HT40( 0)] & 0x3f)); 3034 AR_WRITE(sc, AR_PHY_PWRTX_RATE8, 3035 (power[ATHN_POWER_HT40(13)] & 0x3f) << 24 | 3036 (power[ATHN_POWER_HT40(12)] & 0x3f) << 16 | 3037 (power[ATHN_POWER_HT40( 7)] & 0x3f) << 8 | 3038 (power[ATHN_POWER_HT40( 6)] & 0x3f)); 3039 AR_WRITE(sc, AR_PHY_PWRTX_RATE10, 3040 (power[ATHN_POWER_HT20(21)] & 0x3f) << 24 | 3041 (power[ATHN_POWER_HT20(20)] & 0x3f) << 16 | 3042 (power[ATHN_POWER_HT20(15)] & 0x3f) << 8 | 3043 (power[ATHN_POWER_HT20(14)] & 0x3f)); 3044 AR_WRITE(sc, AR_PHY_PWRTX_RATE11, 3045 (power[ATHN_POWER_HT40(23)] & 0x3f) << 24 | 3046 (power[ATHN_POWER_HT40(22)] & 0x3f) << 16 | 3047 (power[ATHN_POWER_HT20(23)] & 0x3f) << 8 | 3048 (power[ATHN_POWER_HT20(22)] & 0x3f)); 3049 AR_WRITE(sc, AR_PHY_PWRTX_RATE12, 3050 (power[ATHN_POWER_HT40(21)] & 0x3f) << 24 | 3051 (power[ATHN_POWER_HT40(20)] & 0x3f) << 16 | 3052 (power[ATHN_POWER_HT40(15)] & 0x3f) << 8 | 3053 (power[ATHN_POWER_HT40(14)] & 0x3f)); 3054 AR_WRITE_BARRIER(sc); 3055 } 3056 3057 void 3058 ar9003_reset_rx_gain(struct athn_softc *sc, struct ieee80211_channel *c) 3059 { 3060 #define X(x) ((uint32_t)(x) << 2) 3061 const struct athn_gain *prog = sc->rx_gain; 3062 const uint32_t *pvals; 3063 int i; 3064 3065 if (IEEE80211_IS_CHAN_2GHZ(c)) 3066 pvals = prog->vals_2g; 3067 else 3068 pvals = prog->vals_5g; 3069 for (i = 0; i < prog->nregs; i++) 3070 AR_WRITE(sc, X(prog->regs[i]), pvals[i]); 3071 AR_WRITE_BARRIER(sc); 3072 #undef X 3073 } 3074 3075 void 3076 ar9003_reset_tx_gain(struct athn_softc *sc, struct ieee80211_channel *c) 3077 { 3078 #define X(x) ((uint32_t)(x) << 2) 3079 const struct athn_gain *prog = sc->tx_gain; 3080 const uint32_t *pvals; 3081 int i; 3082 3083 if (IEEE80211_IS_CHAN_2GHZ(c)) 3084 pvals = prog->vals_2g; 3085 else 3086 pvals = prog->vals_5g; 3087 for (i = 0; i < prog->nregs; i++) 3088 AR_WRITE(sc, X(prog->regs[i]), pvals[i]); 3089 AR_WRITE_BARRIER(sc); 3090 #undef X 3091 } 3092 3093 void 3094 ar9003_hw_init(struct athn_softc *sc, struct ieee80211_channel *c, 3095 struct ieee80211_channel *extc) 3096 { 3097 #define X(x) ((uint32_t)(x) << 2) 3098 struct athn_ops *ops = &sc->ops; 3099 const struct athn_ini *ini = sc->ini; 3100 const uint32_t *pvals; 3101 uint32_t reg; 3102 int i; 3103 3104 /* 3105 * The common init values include the pre and core phases for the 3106 * SoC, MAC, BB and Radio subsystems. 3107 */ 3108 DPRINTFN(4, ("writing pre and core init vals\n")); 3109 for (i = 0; i < ini->ncmregs; i++) { 3110 AR_WRITE(sc, X(ini->cmregs[i]), ini->cmvals[i]); 3111 if (AR_IS_ANALOG_REG(X(ini->cmregs[i]))) 3112 DELAY(100); 3113 if ((i & 0x1f) == 0) 3114 DELAY(1); 3115 } 3116 3117 /* 3118 * The modal init values include the post phase for the SoC, MAC, 3119 * BB and Radio subsystems. 3120 */ 3121 if (extc != NULL) { 3122 if (IEEE80211_IS_CHAN_2GHZ(c)) 3123 pvals = ini->vals_2g40; 3124 else 3125 pvals = ini->vals_5g40; 3126 } else { 3127 if (IEEE80211_IS_CHAN_2GHZ(c)) 3128 pvals = ini->vals_2g20; 3129 else 3130 pvals = ini->vals_5g20; 3131 } 3132 DPRINTFN(4, ("writing post init vals\n")); 3133 for (i = 0; i < ini->nregs; i++) { 3134 AR_WRITE(sc, X(ini->regs[i]), pvals[i]); 3135 if (AR_IS_ANALOG_REG(X(ini->regs[i]))) 3136 DELAY(100); 3137 if ((i & 0x1f) == 0) 3138 DELAY(1); 3139 } 3140 3141 if (sc->rx_gain != NULL) 3142 ar9003_reset_rx_gain(sc, c); 3143 if (sc->tx_gain != NULL) 3144 ar9003_reset_tx_gain(sc, c); 3145 3146 if (IEEE80211_IS_CHAN_5GHZ(c) && 3147 (sc->flags & ATHN_FLAG_FAST_PLL_CLOCK)) { 3148 /* Update modal values for fast PLL clock. */ 3149 if (extc != NULL) 3150 pvals = ini->fastvals_5g40; 3151 else 3152 pvals = ini->fastvals_5g20; 3153 DPRINTFN(4, ("writing fast pll clock init vals\n")); 3154 for (i = 0; i < ini->nfastregs; i++) { 3155 AR_WRITE(sc, X(ini->fastregs[i]), pvals[i]); 3156 if (AR_IS_ANALOG_REG(X(ini->fastregs[i]))) 3157 DELAY(100); 3158 if ((i & 0x1f) == 0) 3159 DELAY(1); 3160 } 3161 } 3162 3163 /* 3164 * Set the RX_ABORT and RX_DIS bits to prevent frames with corrupted 3165 * descriptor status. 3166 */ 3167 AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 3168 3169 reg = AR_READ(sc, AR_PCU_MISC_MODE2); 3170 reg &= ~AR_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE; 3171 reg |= AR_PCU_MISC_MODE2_AGG_WEP_ENABLE_FIX; 3172 reg |= AR_PCU_MISC_MODE2_ENABLE_AGGWEP; 3173 AR_WRITE(sc, AR_PCU_MISC_MODE2, reg); 3174 AR_WRITE_BARRIER(sc); 3175 3176 ar9003_set_phy(sc, c, extc); 3177 ar9003_init_chains(sc); 3178 3179 ops->set_txpower(sc, c, extc); 3180 #undef X 3181 } 3182 3183 void 3184 ar9003_get_lg_tpow(struct athn_softc *sc, struct ieee80211_channel *c, 3185 uint8_t ctl, const uint8_t *fbins, 3186 const struct ar_cal_target_power_leg *tgt, int nchans, uint8_t tpow[4]) 3187 { 3188 uint8_t fbin; 3189 int i, delta, lo, hi; 3190 3191 lo = hi = -1; 3192 fbin = athn_chan2fbin(c); 3193 for (i = 0; i < nchans; i++) { 3194 delta = fbin - fbins[i]; 3195 /* Find the largest sample that is <= our frequency. */ 3196 if (delta >= 0 && (lo == -1 || delta < fbin - fbins[lo])) 3197 lo = i; 3198 /* Find the smallest sample that is >= our frequency. */ 3199 if (delta <= 0 && (hi == -1 || delta > fbin - fbins[hi])) 3200 hi = i; 3201 } 3202 if (lo == -1) 3203 lo = hi; 3204 else if (hi == -1) 3205 hi = lo; 3206 /* Interpolate values. */ 3207 for (i = 0; i < 4; i++) { 3208 tpow[i] = athn_interpolate(fbin, 3209 fbins[lo], tgt[lo].tPow2x[i], 3210 fbins[hi], tgt[hi].tPow2x[i]); 3211 } 3212 /* XXX Apply conformance test limit. */ 3213 } 3214 3215 void 3216 ar9003_get_ht_tpow(struct athn_softc *sc, struct ieee80211_channel *c, 3217 uint8_t ctl, const uint8_t *fbins, 3218 const struct ar_cal_target_power_ht *tgt, int nchans, uint8_t tpow[14]) 3219 { 3220 uint8_t fbin; 3221 int i, delta, lo, hi; 3222 3223 lo = hi = -1; 3224 fbin = athn_chan2fbin(c); 3225 for (i = 0; i < nchans; i++) { 3226 delta = fbin - fbins[i]; 3227 /* Find the largest sample that is <= our frequency. */ 3228 if (delta >= 0 && (lo == -1 || delta < fbin - fbins[lo])) 3229 lo = i; 3230 /* Find the smallest sample that is >= our frequency. */ 3231 if (delta <= 0 && (hi == -1 || delta > fbin - fbins[hi])) 3232 hi = i; 3233 } 3234 if (lo == -1) 3235 lo = hi; 3236 else if (hi == -1) 3237 hi = lo; 3238 /* Interpolate values. */ 3239 for (i = 0; i < 14; i++) { 3240 tpow[i] = athn_interpolate(fbin, 3241 fbins[lo], tgt[lo].tPow2x[i], 3242 fbins[hi], tgt[hi].tPow2x[i]); 3243 } 3244 /* XXX Apply conformance test limit. */ 3245 } 3246 3247 /* 3248 * Adaptive noise immunity. 3249 */ 3250 void 3251 ar9003_set_noise_immunity_level(struct athn_softc *sc, int level) 3252 { 3253 int high = level == 4; 3254 uint32_t reg; 3255 3256 reg = AR_READ(sc, AR_PHY_DESIRED_SZ); 3257 reg = RW(reg, AR_PHY_DESIRED_SZ_TOT_DES, high ? -62 : -55); 3258 AR_WRITE(sc, AR_PHY_DESIRED_SZ, reg); 3259 3260 reg = AR_READ(sc, AR_PHY_AGC); 3261 reg = RW(reg, AR_PHY_AGC_COARSE_LOW, high ? -70 : -64); 3262 reg = RW(reg, AR_PHY_AGC_COARSE_HIGH, high ? -12 : -14); 3263 AR_WRITE(sc, AR_PHY_AGC, reg); 3264 3265 reg = AR_READ(sc, AR_PHY_FIND_SIG); 3266 reg = RW(reg, AR_PHY_FIND_SIG_FIRPWR, high ? -80 : -78); 3267 AR_WRITE(sc, AR_PHY_FIND_SIG, reg); 3268 AR_WRITE_BARRIER(sc); 3269 } 3270 3271 void 3272 ar9003_enable_ofdm_weak_signal(struct athn_softc *sc) 3273 { 3274 uint32_t reg; 3275 3276 reg = AR_READ(sc, AR_PHY_SFCORR_LOW); 3277 reg = RW(reg, AR_PHY_SFCORR_LOW_M1_THRESH_LOW, 50); 3278 reg = RW(reg, AR_PHY_SFCORR_LOW_M2_THRESH_LOW, 40); 3279 reg = RW(reg, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, 48); 3280 AR_WRITE(sc, AR_PHY_SFCORR_LOW, reg); 3281 3282 reg = AR_READ(sc, AR_PHY_SFCORR); 3283 reg = RW(reg, AR_PHY_SFCORR_M1_THRESH, 77); 3284 reg = RW(reg, AR_PHY_SFCORR_M2_THRESH, 64); 3285 reg = RW(reg, AR_PHY_SFCORR_M2COUNT_THR, 16); 3286 AR_WRITE(sc, AR_PHY_SFCORR, reg); 3287 3288 reg = AR_READ(sc, AR_PHY_SFCORR_EXT); 3289 reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH_LOW, 50); 3290 reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH_LOW, 40); 3291 reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH, 77); 3292 reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH, 64); 3293 AR_WRITE(sc, AR_PHY_SFCORR_EXT, reg); 3294 3295 AR_SETBITS(sc, AR_PHY_SFCORR_LOW, 3296 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); 3297 AR_WRITE_BARRIER(sc); 3298 } 3299 3300 void 3301 ar9003_disable_ofdm_weak_signal(struct athn_softc *sc) 3302 { 3303 uint32_t reg; 3304 3305 reg = AR_READ(sc, AR_PHY_SFCORR_LOW); 3306 reg = RW(reg, AR_PHY_SFCORR_LOW_M1_THRESH_LOW, 127); 3307 reg = RW(reg, AR_PHY_SFCORR_LOW_M2_THRESH_LOW, 127); 3308 reg = RW(reg, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, 63); 3309 AR_WRITE(sc, AR_PHY_SFCORR_LOW, reg); 3310 3311 reg = AR_READ(sc, AR_PHY_SFCORR); 3312 reg = RW(reg, AR_PHY_SFCORR_M1_THRESH, 127); 3313 reg = RW(reg, AR_PHY_SFCORR_M2_THRESH, 127); 3314 reg = RW(reg, AR_PHY_SFCORR_M2COUNT_THR, 31); 3315 AR_WRITE(sc, AR_PHY_SFCORR, reg); 3316 3317 reg = AR_READ(sc, AR_PHY_SFCORR_EXT); 3318 reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH_LOW, 127); 3319 reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH_LOW, 127); 3320 reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH, 127); 3321 reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH, 127); 3322 AR_WRITE(sc, AR_PHY_SFCORR_EXT, reg); 3323 3324 AR_CLRBITS(sc, AR_PHY_SFCORR_LOW, 3325 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); 3326 AR_WRITE_BARRIER(sc); 3327 } 3328 3329 void 3330 ar9003_set_cck_weak_signal(struct athn_softc *sc, int high) 3331 { 3332 uint32_t reg; 3333 3334 reg = AR_READ(sc, AR_PHY_CCK_DETECT); 3335 reg = RW(reg, AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK, high ? 6 : 8); 3336 AR_WRITE(sc, AR_PHY_CCK_DETECT, reg); 3337 AR_WRITE_BARRIER(sc); 3338 } 3339 3340 void 3341 ar9003_set_firstep_level(struct athn_softc *sc, int level) 3342 { 3343 uint32_t reg; 3344 3345 reg = AR_READ(sc, AR_PHY_FIND_SIG); 3346 reg = RW(reg, AR_PHY_FIND_SIG_FIRSTEP, level * 4); 3347 AR_WRITE(sc, AR_PHY_FIND_SIG, reg); 3348 AR_WRITE_BARRIER(sc); 3349 } 3350 3351 void 3352 ar9003_set_spur_immunity_level(struct athn_softc *sc, int level) 3353 { 3354 uint32_t reg; 3355 3356 reg = AR_READ(sc, AR_PHY_TIMING5); 3357 reg = RW(reg, AR_PHY_TIMING5_CYCPWR_THR1, (level + 1) * 2); 3358 AR_WRITE(sc, AR_PHY_TIMING5, reg); 3359 AR_WRITE_BARRIER(sc); 3360 } 3361