1 /* $OpenBSD: ar5xxx.c,v 1.59 2016/01/12 09:28:09 stsp Exp $ */ 2 3 /* 4 * Copyright (c) 2004, 2005, 2006, 2007 Reyk Floeter <reyk@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * HAL interface for Atheros Wireless LAN devices. 21 * (Please have a look at ar5xxx.h for further information) 22 */ 23 24 #include <dev/pci/pcidevs.h> 25 #include <dev/ic/ar5xxx.h> 26 27 extern ar5k_attach_t ar5k_ar5210_attach; 28 extern ar5k_attach_t ar5k_ar5211_attach; 29 extern ar5k_attach_t ar5k_ar5212_attach; 30 31 static const struct { 32 u_int16_t vendor; 33 u_int16_t device; 34 ar5k_attach_t (*attach); 35 } ar5k_known_products[] = { 36 /* 37 * From pcidevs_data.h 38 */ 39 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5210, 40 ar5k_ar5210_attach }, 41 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5210_AP, 42 ar5k_ar5210_attach }, 43 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5210_DEFAULT, 44 ar5k_ar5210_attach }, 45 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5211, 46 ar5k_ar5211_attach }, 47 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5211_DEFAULT, 48 ar5k_ar5211_attach }, 49 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5311, 50 ar5k_ar5211_attach }, 51 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5211_FPGA11B, 52 ar5k_ar5211_attach }, 53 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5211_LEGACY, 54 ar5k_ar5211_attach }, 55 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5212, 56 ar5k_ar5212_attach }, 57 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5212_DEFAULT, 58 ar5k_ar5212_attach }, 59 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5212_FPGA, 60 ar5k_ar5212_attach }, 61 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5212_IBM, 62 ar5k_ar5212_attach }, 63 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR2413, 64 ar5k_ar5212_attach }, 65 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5413, 66 ar5k_ar5212_attach }, 67 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5424, 68 ar5k_ar5212_attach }, 69 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CRDAG675, 70 ar5k_ar5212_attach }, 71 { PCI_VENDOR_3COM2, PCI_PRODUCT_3COM2_3CRPAG175, 72 ar5k_ar5212_attach } 73 }; 74 75 static const HAL_RATE_TABLE ar5k_rt_11a = AR5K_RATES_11A; 76 static const HAL_RATE_TABLE ar5k_rt_11b = AR5K_RATES_11B; 77 static const HAL_RATE_TABLE ar5k_rt_11g = AR5K_RATES_11G; 78 static const HAL_RATE_TABLE ar5k_rt_xr = AR5K_RATES_XR; 79 80 int ar5k_eeprom_read_ants(struct ath_hal *, u_int32_t *, u_int); 81 int ar5k_eeprom_read_modes(struct ath_hal *, u_int32_t *, u_int); 82 u_int16_t ar5k_eeprom_bin2freq(struct ath_hal *, u_int16_t, u_int); 83 84 HAL_BOOL ar5k_ar5110_channel(struct ath_hal *, HAL_CHANNEL *); 85 u_int32_t ar5k_ar5110_chan2athchan(HAL_CHANNEL *); 86 HAL_BOOL ar5k_ar5111_channel(struct ath_hal *, HAL_CHANNEL *); 87 HAL_BOOL ar5k_ar5111_chan2athchan(u_int, struct ar5k_athchan_2ghz *); 88 HAL_BOOL ar5k_ar5112_channel(struct ath_hal *, HAL_CHANNEL *); 89 HAL_BOOL ar5k_check_channel(struct ath_hal *, u_int16_t, u_int flags); 90 91 HAL_BOOL ar5k_ar5111_rfregs(struct ath_hal *, HAL_CHANNEL *, u_int); 92 HAL_BOOL ar5k_ar5112_rfregs(struct ath_hal *, HAL_CHANNEL *, u_int); 93 HAL_BOOL ar5k_arxxxx_rfregs(struct ath_hal *, HAL_CHANNEL *, u_int); 94 u_int ar5k_rfregs_op(u_int32_t *, u_int32_t, u_int32_t, u_int32_t, 95 u_int32_t, u_int32_t, HAL_BOOL); 96 97 /* 98 * Supported channels 99 */ 100 static const struct 101 ieee80211_regchannel ar5k_5ghz_channels[] = IEEE80211_CHANNELS_5GHZ; 102 static const struct 103 ieee80211_regchannel ar5k_2ghz_channels[] = IEEE80211_CHANNELS_2GHZ; 104 105 /* 106 * Initial gain optimization values 107 */ 108 static const struct ar5k_gain_opt ar5111_gain_opt = AR5K_AR5111_GAIN_OPT; 109 static const struct ar5k_gain_opt ar5112_gain_opt = AR5K_AR5112_GAIN_OPT; 110 111 /* 112 * Initial register for the radio chipsets 113 */ 114 static const struct ar5k_ini_rf ar5111_rf[] = AR5K_AR5111_INI_RF; 115 static const struct ar5k_ini_rf ar5112_rf[] = AR5K_AR5112_INI_RF; 116 static const struct ar5k_ini_rf ar5112a_rf[] = AR5K_AR5112A_INI_RF; 117 static const struct ar5k_ini_rf ar5413_rf[] = AR5K_AR5413_INI_RF; 118 static const struct ar5k_ini_rf ar2413_rf[] = AR5K_AR2413_INI_RF; 119 static const struct ar5k_ini_rf ar2425_rf[] = AR5K_AR2425_INI_RF; 120 static const struct ar5k_ini_rfgain ar5111_rfg[] = AR5K_AR5111_INI_RFGAIN; 121 static const struct ar5k_ini_rfgain ar5112_rfg[] = AR5K_AR5112_INI_RFGAIN; 122 static const struct ar5k_ini_rfgain ar5413_rfg[] = AR5K_AR5413_INI_RFGAIN; 123 static const struct ar5k_ini_rfgain ar2413_rfg[] = AR5K_AR2413_INI_RFGAIN; 124 125 /* 126 * Enable to overwrite the country code (use "00" for debug) 127 */ 128 #if 0 129 #define COUNTRYCODE "00" 130 #endif 131 132 /* 133 * Perform a lookup if the device is supported by the HAL 134 */ 135 const char * 136 ath_hal_probe(u_int16_t vendor, u_int16_t device) 137 { 138 int i; 139 140 /* 141 * Perform a linear search on the table of supported devices 142 */ 143 for (i = 0; i < nitems(ar5k_known_products); i++) { 144 if (vendor == ar5k_known_products[i].vendor && 145 device == ar5k_known_products[i].device) 146 return (""); 147 } 148 149 return (NULL); 150 } 151 152 /* 153 * Fills in the HAL structure and initialises the device 154 */ 155 struct ath_hal * 156 ath_hal_attach(u_int16_t device, void *arg, bus_space_tag_t st, 157 bus_space_handle_t sh, u_int is_pcie, int *status) 158 { 159 struct ath_softc *sc = (struct ath_softc *)arg; 160 struct ath_hal *hal = NULL; 161 ar5k_attach_t *attach = NULL; 162 u_int8_t mac[IEEE80211_ADDR_LEN]; 163 int i; 164 165 *status = EINVAL; 166 167 /* 168 * Call the chipset-dependent attach routine by device id 169 */ 170 for (i = 0; i < nitems(ar5k_known_products); i++) { 171 if (device == ar5k_known_products[i].device && 172 ar5k_known_products[i].attach != NULL) 173 attach = ar5k_known_products[i].attach; 174 } 175 176 if (attach == NULL) { 177 *status = ENXIO; 178 AR5K_PRINTF("device not supported: 0x%04x\n", device); 179 return (NULL); 180 } 181 182 if ((hal = malloc(sizeof(struct ath_hal), 183 M_DEVBUF, M_NOWAIT | M_ZERO)) == NULL) { 184 *status = ENOMEM; 185 AR5K_PRINT("out of memory\n"); 186 return (NULL); 187 } 188 189 hal->ah_sc = sc; 190 hal->ah_st = st; 191 hal->ah_sh = sh; 192 hal->ah_device = device; 193 hal->ah_sub_vendor = 0; /* XXX unknown?! */ 194 195 /* 196 * HAL information 197 */ 198 hal->ah_abi = HAL_ABI_VERSION; 199 hal->ah_op_mode = HAL_M_STA; 200 hal->ah_radar.r_enabled = AR5K_TUNE_RADAR_ALERT; 201 hal->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER; 202 hal->ah_imr = 0; 203 hal->ah_atim_window = 0; 204 hal->ah_aifs = AR5K_TUNE_AIFS; 205 hal->ah_cw_min = AR5K_TUNE_CWMIN; 206 hal->ah_limit_tx_retries = AR5K_INIT_TX_RETRY; 207 hal->ah_software_retry = AH_FALSE; 208 hal->ah_ant_diversity = AR5K_TUNE_ANT_DIVERSITY; 209 hal->ah_pci_express = is_pcie ? AH_TRUE : AH_FALSE; 210 211 switch (device) { 212 case PCI_PRODUCT_ATHEROS_AR2413: 213 case PCI_PRODUCT_ATHEROS_AR5413: 214 case PCI_PRODUCT_ATHEROS_AR5424: 215 /* 216 * Known single chip solutions 217 */ 218 hal->ah_single_chip = AH_TRUE; 219 break; 220 default: 221 /* 222 * Multi chip solutions 223 */ 224 hal->ah_single_chip = AH_FALSE; 225 break; 226 } 227 228 if ((attach)(device, hal, st, sh, status) == NULL) 229 goto failed; 230 231 #ifdef AR5K_DEBUG 232 hal->ah_dump_state(hal); 233 #endif 234 235 /* 236 * Get card capabilities, values, ... 237 */ 238 239 if (ar5k_eeprom_init(hal) != 0) { 240 AR5K_PRINT("unable to init EEPROM\n"); 241 goto failed; 242 } 243 244 /* Get misc capabilities */ 245 if (hal->ah_get_capabilities(hal) != AH_TRUE) { 246 AR5K_PRINTF("unable to get device capabilities: 0x%04x\n", 247 device); 248 goto failed; 249 } 250 251 /* Get MAC address */ 252 if ((*status = ar5k_eeprom_read_mac(hal, mac)) != 0) { 253 AR5K_PRINTF("unable to read address from EEPROM: 0x%04x\n", 254 device); 255 goto failed; 256 } 257 258 hal->ah_set_lladdr(hal, mac); 259 260 /* Get rate tables */ 261 if (hal->ah_capabilities.cap_mode & HAL_MODE_11A) 262 ar5k_rt_copy(&hal->ah_rt_11a, &ar5k_rt_11a); 263 if (hal->ah_capabilities.cap_mode & HAL_MODE_11B) 264 ar5k_rt_copy(&hal->ah_rt_11b, &ar5k_rt_11b); 265 if (hal->ah_capabilities.cap_mode & HAL_MODE_11G) 266 ar5k_rt_copy(&hal->ah_rt_11g, &ar5k_rt_11g); 267 if (hal->ah_capabilities.cap_mode & HAL_MODE_XR) 268 ar5k_rt_copy(&hal->ah_rt_xr, &ar5k_rt_xr); 269 270 /* Initialize the gain optimization values */ 271 if (hal->ah_radio == AR5K_AR5111) { 272 hal->ah_gain.g_step_idx = ar5111_gain_opt.go_default; 273 hal->ah_gain.g_step = 274 &ar5111_gain_opt.go_step[hal->ah_gain.g_step_idx]; 275 hal->ah_gain.g_low = 20; 276 hal->ah_gain.g_high = 35; 277 hal->ah_gain.g_active = 1; 278 } else if (hal->ah_radio == AR5K_AR5112) { 279 hal->ah_gain.g_step_idx = ar5112_gain_opt.go_default; 280 hal->ah_gain.g_step = 281 &ar5111_gain_opt.go_step[hal->ah_gain.g_step_idx]; 282 hal->ah_gain.g_low = 20; 283 hal->ah_gain.g_high = 85; 284 hal->ah_gain.g_active = 1; 285 } else { 286 /* XXX not needed for newer chipsets? */ 287 } 288 289 *status = HAL_OK; 290 291 return (hal); 292 293 failed: 294 free(hal, M_DEVBUF, 0); 295 return (NULL); 296 } 297 298 u_int16_t 299 ath_hal_computetxtime(struct ath_hal *hal, const HAL_RATE_TABLE *rates, 300 u_int32_t frame_length, u_int16_t rate_index, HAL_BOOL short_preamble) 301 { 302 const HAL_RATE *rate; 303 u_int32_t value; 304 305 AR5K_ASSERT_ENTRY(rate_index, rates->rateCount); 306 307 /* 308 * Get rate by index 309 */ 310 rate = &rates->info[rate_index]; 311 312 /* 313 * Calculate the transmission time by operation (PHY) mode 314 */ 315 switch (rate->phy) { 316 case IEEE80211_T_CCK: 317 /* 318 * CCK / DS mode (802.11b) 319 */ 320 value = AR5K_CCK_TX_TIME(rate->rateKbps, frame_length, 321 (short_preamble && rate->shortPreamble)); 322 break; 323 324 case IEEE80211_T_OFDM: 325 /* 326 * Orthogonal Frequency Division Multiplexing 327 */ 328 if (AR5K_OFDM_NUM_BITS_PER_SYM(rate->rateKbps) == 0) 329 return (0); 330 value = AR5K_OFDM_TX_TIME(rate->rateKbps, frame_length); 331 break; 332 333 case IEEE80211_T_XR: 334 /* 335 * Orthogonal Frequency Division Multiplexing 336 * Atheros "eXtended Range" (XR) 337 */ 338 if (AR5K_XR_NUM_BITS_PER_SYM(rate->rateKbps) == 0) 339 return (0); 340 value = AR5K_XR_TX_TIME(rate->rateKbps, frame_length); 341 break; 342 343 default: 344 return (0); 345 } 346 347 return (value); 348 } 349 350 HAL_BOOL 351 ar5k_check_channel(struct ath_hal *hal, u_int16_t freq, u_int flags) 352 { 353 /* Check if the channel is in our supported range */ 354 if (flags & IEEE80211_CHAN_2GHZ) { 355 if ((freq >= hal->ah_capabilities.cap_range.range_2ghz_min) && 356 (freq <= hal->ah_capabilities.cap_range.range_2ghz_max)) 357 return (AH_TRUE); 358 } else if (flags & IEEE80211_CHAN_5GHZ) { 359 if ((freq >= hal->ah_capabilities.cap_range.range_5ghz_min) && 360 (freq <= hal->ah_capabilities.cap_range.range_5ghz_max)) 361 return (AH_TRUE); 362 } 363 364 return (AH_FALSE); 365 } 366 367 HAL_BOOL 368 ath_hal_init_channels(struct ath_hal *hal, HAL_CHANNEL *channels, 369 u_int max_channels, u_int *channels_size, u_int16_t mode, 370 HAL_BOOL outdoor, HAL_BOOL extended) 371 { 372 u_int i, c; 373 u_int32_t domain_current; 374 u_int domain_5ghz, domain_2ghz; 375 HAL_CHANNEL *all_channels; 376 377 if ((all_channels = mallocarray(max_channels, sizeof(HAL_CHANNEL), 378 M_TEMP, M_NOWAIT | M_ZERO)) == NULL) 379 return (AH_FALSE); 380 381 i = c = 0; 382 domain_current = hal->ah_regdomain; 383 384 /* 385 * In debugging mode, enable all channels supported by the chipset 386 */ 387 if (domain_current == DMN_DEFAULT) { 388 int min, max, freq; 389 u_int flags; 390 391 min = ieee80211_mhz2ieee(IEEE80211_CHANNELS_2GHZ_MIN, 392 IEEE80211_CHAN_2GHZ); 393 max = ieee80211_mhz2ieee(IEEE80211_CHANNELS_2GHZ_MAX, 394 IEEE80211_CHAN_2GHZ); 395 flags = CHANNEL_B | 396 (hal->ah_version == AR5K_AR5211 ? 397 CHANNEL_PUREG : CHANNEL_G); 398 399 debugchan: 400 for (i = min; i <= max && c < max_channels; i++) { 401 freq = ieee80211_ieee2mhz(i, flags); 402 if (ar5k_check_channel(hal, freq, flags) == AH_FALSE) 403 continue; 404 all_channels[c].c_channel = freq; 405 all_channels[c++].c_channel_flags = flags; 406 } 407 408 if (flags & IEEE80211_CHAN_2GHZ) { 409 min = ieee80211_mhz2ieee(IEEE80211_CHANNELS_5GHZ_MIN, 410 IEEE80211_CHAN_5GHZ); 411 max = ieee80211_mhz2ieee(IEEE80211_CHANNELS_5GHZ_MAX, 412 IEEE80211_CHAN_5GHZ); 413 flags = CHANNEL_A | CHANNEL_XR; 414 goto debugchan; 415 } 416 417 goto done; 418 } 419 420 domain_5ghz = ieee80211_regdomain2flag(domain_current, 421 IEEE80211_CHANNELS_5GHZ_MIN); 422 domain_2ghz = ieee80211_regdomain2flag(domain_current, 423 IEEE80211_CHANNELS_2GHZ_MIN); 424 425 /* 426 * Create channel list based on chipset capabilities, regulation domain 427 * and mode. 5GHz... 428 */ 429 for (i = 0; (hal->ah_capabilities.cap_range.range_5ghz_max > 0) && 430 (i < nitems(ar5k_5ghz_channels)) && 431 (c < max_channels); i++) { 432 /* Check if channel is supported by the chipset */ 433 if (ar5k_check_channel(hal, 434 ar5k_5ghz_channels[i].rc_channel, 435 IEEE80211_CHAN_5GHZ) == AH_FALSE) 436 continue; 437 438 /* Match regulation domain */ 439 if ((IEEE80211_DMN(ar5k_5ghz_channels[i].rc_domain) & 440 IEEE80211_DMN(domain_5ghz)) == 0) 441 continue; 442 443 /* Match modes */ 444 if (ar5k_5ghz_channels[i].rc_mode & IEEE80211_CHAN_OFDM) 445 all_channels[c].c_channel_flags = CHANNEL_A; 446 else 447 continue; 448 449 /* Write channel and increment counter */ 450 all_channels[c++].channel = ar5k_5ghz_channels[i].rc_channel; 451 } 452 453 /* 454 * ...and 2GHz. 455 */ 456 for (i = 0; (hal->ah_capabilities.cap_range.range_2ghz_max > 0) && 457 (i < nitems(ar5k_2ghz_channels)) && 458 (c < max_channels); i++) { 459 /* Check if channel is supported by the chipset */ 460 if (ar5k_check_channel(hal, 461 ar5k_2ghz_channels[i].rc_channel, 462 IEEE80211_CHAN_2GHZ) == AH_FALSE) 463 continue; 464 465 /* Match regulation domain */ 466 if ((IEEE80211_DMN(ar5k_2ghz_channels[i].rc_domain) & 467 IEEE80211_DMN(domain_2ghz)) == 0) 468 continue; 469 470 /* Match modes */ 471 if ((hal->ah_capabilities.cap_mode & HAL_MODE_11B) && 472 (ar5k_2ghz_channels[i].rc_mode & IEEE80211_CHAN_CCK)) 473 all_channels[c].c_channel_flags = CHANNEL_B; 474 475 if ((hal->ah_capabilities.cap_mode & HAL_MODE_11G) && 476 (ar5k_2ghz_channels[i].rc_mode & IEEE80211_CHAN_OFDM)) { 477 all_channels[c].c_channel_flags |= 478 hal->ah_version == AR5K_AR5211 ? 479 CHANNEL_PUREG : CHANNEL_G; 480 } 481 482 /* Write channel and increment counter */ 483 all_channels[c++].channel = ar5k_2ghz_channels[i].rc_channel; 484 } 485 486 done: 487 bcopy(all_channels, channels, sizeof(HAL_CHANNEL) * max_channels); 488 *channels_size = c; 489 free(all_channels, M_TEMP, 0); 490 return (AH_TRUE); 491 } 492 493 /* 494 * Common internal functions 495 */ 496 497 const char * 498 ar5k_printver(enum ar5k_srev_type type, u_int32_t val) 499 { 500 struct ar5k_srev_name names[] = AR5K_SREV_NAME; 501 const char *name = "xxxx"; 502 int i; 503 504 for (i = 0; i < nitems(names); i++) { 505 if (type == AR5K_VERSION_DEV) { 506 if (names[i].sr_type == type && 507 names[i].sr_val == val) { 508 name = names[i].sr_name; 509 break; 510 } 511 continue; 512 } 513 if (names[i].sr_type != type || 514 names[i].sr_val == AR5K_SREV_UNKNOWN) 515 continue; 516 if ((val & 0xff) < names[i + 1].sr_val) { 517 name = names[i].sr_name; 518 break; 519 } 520 } 521 522 return (name); 523 } 524 525 void 526 ar5k_radar_alert(struct ath_hal *hal) 527 { 528 /* 529 * Limit ~1/s 530 */ 531 if (hal->ah_radar.r_last_channel.channel == 532 hal->ah_current_channel.channel && 533 tick < (hal->ah_radar.r_last_alert + hz)) 534 return; 535 536 hal->ah_radar.r_last_channel.channel = 537 hal->ah_current_channel.channel; 538 hal->ah_radar.r_last_channel.c_channel_flags = 539 hal->ah_current_channel.c_channel_flags; 540 hal->ah_radar.r_last_alert = tick; 541 542 AR5K_PRINTF("Possible radar activity detected at %u MHz (tick %u)\n", 543 hal->ah_radar.r_last_alert, hal->ah_current_channel.channel); 544 } 545 546 u_int16_t 547 ar5k_regdomain_from_ieee(ieee80211_regdomain_t ieee) 548 { 549 u_int32_t regdomain = (u_int32_t)ieee; 550 551 /* 552 * Use the default regulation domain if the value is empty 553 * or not supported by the net80211 regulation code. 554 */ 555 if (ieee80211_regdomain2flag(regdomain, 556 IEEE80211_CHANNELS_5GHZ_MIN) == DMN_DEBUG) 557 return ((u_int16_t)AR5K_TUNE_REGDOMAIN); 558 559 /* It is supported, just return the value */ 560 return (regdomain); 561 } 562 563 ieee80211_regdomain_t 564 ar5k_regdomain_to_ieee(u_int16_t regdomain) 565 { 566 ieee80211_regdomain_t ieee = (ieee80211_regdomain_t)regdomain; 567 568 return (ieee); 569 } 570 571 u_int16_t 572 ar5k_get_regdomain(struct ath_hal *hal) 573 { 574 u_int16_t regdomain; 575 ieee80211_regdomain_t ieee_regdomain; 576 #ifdef COUNTRYCODE 577 u_int16_t code; 578 #endif 579 580 ar5k_eeprom_regulation_domain(hal, AH_FALSE, &ieee_regdomain); 581 hal->ah_capabilities.cap_regdomain.reg_hw = ieee_regdomain; 582 583 #ifdef COUNTRYCODE 584 /* 585 * Get the regulation domain by country code. This will ignore 586 * the settings found in the EEPROM. 587 */ 588 code = ieee80211_name2countrycode(COUNTRYCODE); 589 ieee_regdomain = ieee80211_countrycode2regdomain(code); 590 #endif 591 592 regdomain = ar5k_regdomain_from_ieee(ieee_regdomain); 593 hal->ah_capabilities.cap_regdomain.reg_current = regdomain; 594 595 return (regdomain); 596 } 597 598 u_int32_t 599 ar5k_bitswap(u_int32_t val, u_int bits) 600 { 601 if (bits == 8) { 602 val = ((val & 0xF0) >> 4) | ((val & 0x0F) << 4); 603 val = ((val & 0xCC) >> 2) | ((val & 0x33) << 2); 604 val = ((val & 0xAA) >> 1) | ((val & 0x55) << 1); 605 606 return val; 607 } else { 608 u_int32_t retval = 0, bit, i; 609 610 for (i = 0; i < bits; i++) { 611 bit = (val >> i) & 1; 612 retval = (retval << 1) | bit; 613 } 614 615 return retval; 616 } 617 } 618 619 u_int 620 ar5k_htoclock(u_int usec) 621 { 622 return (usec * 40); 623 } 624 625 u_int 626 ar5k_clocktoh(u_int clock) 627 { 628 return (clock / 40); 629 } 630 631 void 632 ar5k_rt_copy(HAL_RATE_TABLE *dst, const HAL_RATE_TABLE *src) 633 { 634 bzero(dst, sizeof(HAL_RATE_TABLE)); 635 dst->rateCount = src->rateCount; 636 bcopy(src->rateCodeToIndex, dst->rateCodeToIndex, 637 sizeof(dst->rateCodeToIndex)); 638 bcopy(src->info, dst->info, sizeof(dst->info)); 639 } 640 641 HAL_BOOL 642 ar5k_register_timeout(struct ath_hal *hal, u_int32_t reg, u_int32_t flag, 643 u_int32_t val, HAL_BOOL is_set) 644 { 645 int i; 646 u_int32_t data; 647 648 for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) { 649 data = AR5K_REG_READ(reg); 650 if ((is_set == AH_TRUE) && (data & flag)) 651 break; 652 else if ((data & flag) == val) 653 break; 654 AR5K_DELAY(15); 655 } 656 657 if (i <= 0) 658 return (AH_FALSE); 659 660 return (AH_TRUE); 661 } 662 663 /* 664 * Common ar5xx EEPROM access functions 665 */ 666 667 u_int16_t 668 ar5k_eeprom_bin2freq(struct ath_hal *hal, u_int16_t bin, u_int mode) 669 { 670 u_int16_t val; 671 672 if (bin == AR5K_EEPROM_CHANNEL_DIS) 673 return (bin); 674 675 if (mode == AR5K_EEPROM_MODE_11A) { 676 if (hal->ah_ee_version > AR5K_EEPROM_VERSION_3_2) 677 val = (5 * bin) + 4800; 678 else 679 val = bin > 62 ? 680 (10 * 62) + (5 * (bin - 62)) + 5100 : 681 (bin * 10) + 5100; 682 } else { 683 if (hal->ah_ee_version > AR5K_EEPROM_VERSION_3_2) 684 val = bin + 2300; 685 else 686 val = bin + 2400; 687 } 688 689 return (val); 690 } 691 692 int 693 ar5k_eeprom_read_ants(struct ath_hal *hal, u_int32_t *offset, u_int mode) 694 { 695 struct ar5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; 696 u_int32_t o = *offset; 697 u_int16_t val; 698 int ret, i = 0; 699 700 AR5K_EEPROM_READ(o++, val); 701 ee->ee_switch_settling[mode] = (val >> 8) & 0x7f; 702 ee->ee_ant_tx_rx[mode] = (val >> 2) & 0x3f; 703 ee->ee_ant_control[mode][i] = (val << 4) & 0x3f; 704 705 AR5K_EEPROM_READ(o++, val); 706 ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf; 707 ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f; 708 ee->ee_ant_control[mode][i++] = val & 0x3f; 709 710 AR5K_EEPROM_READ(o++, val); 711 ee->ee_ant_control[mode][i++] = (val >> 10) & 0x3f; 712 ee->ee_ant_control[mode][i++] = (val >> 4) & 0x3f; 713 ee->ee_ant_control[mode][i] = (val << 2) & 0x3f; 714 715 AR5K_EEPROM_READ(o++, val); 716 ee->ee_ant_control[mode][i++] |= (val >> 14) & 0x3; 717 ee->ee_ant_control[mode][i++] = (val >> 8) & 0x3f; 718 ee->ee_ant_control[mode][i++] = (val >> 2) & 0x3f; 719 ee->ee_ant_control[mode][i] = (val << 4) & 0x3f; 720 721 AR5K_EEPROM_READ(o++, val); 722 ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf; 723 ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f; 724 ee->ee_ant_control[mode][i++] = val & 0x3f; 725 726 /* Get antenna modes */ 727 hal->ah_antenna[mode][0] = 728 (ee->ee_ant_control[mode][0] << 4) | 0x1; 729 hal->ah_antenna[mode][HAL_ANT_FIXED_A] = 730 ee->ee_ant_control[mode][1] | 731 (ee->ee_ant_control[mode][2] << 6) | 732 (ee->ee_ant_control[mode][3] << 12) | 733 (ee->ee_ant_control[mode][4] << 18) | 734 (ee->ee_ant_control[mode][5] << 24); 735 hal->ah_antenna[mode][HAL_ANT_FIXED_B] = 736 ee->ee_ant_control[mode][6] | 737 (ee->ee_ant_control[mode][7] << 6) | 738 (ee->ee_ant_control[mode][8] << 12) | 739 (ee->ee_ant_control[mode][9] << 18) | 740 (ee->ee_ant_control[mode][10] << 24); 741 742 /* return new offset */ 743 *offset = o; 744 745 return (0); 746 } 747 748 int 749 ar5k_eeprom_read_modes(struct ath_hal *hal, u_int32_t *offset, u_int mode) 750 { 751 struct ar5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; 752 u_int32_t o = *offset; 753 u_int16_t val; 754 int ret; 755 756 AR5K_EEPROM_READ(o++, val); 757 ee->ee_tx_end2xlna_enable[mode] = (val >> 8) & 0xff; 758 ee->ee_thr_62[mode] = val & 0xff; 759 760 if (hal->ah_ee_version <= AR5K_EEPROM_VERSION_3_2) 761 ee->ee_thr_62[mode] = 762 mode == AR5K_EEPROM_MODE_11A ? 15 : 28; 763 764 AR5K_EEPROM_READ(o++, val); 765 ee->ee_tx_end2xpa_disable[mode] = (val >> 8) & 0xff; 766 ee->ee_tx_frm2xpa_enable[mode] = val & 0xff; 767 768 AR5K_EEPROM_READ(o++, val); 769 ee->ee_pga_desired_size[mode] = (val >> 8) & 0xff; 770 771 if ((val & 0xff) & 0x80) 772 ee->ee_noise_floor_thr[mode] = -((((val & 0xff) ^ 0xff)) + 1); 773 else 774 ee->ee_noise_floor_thr[mode] = val & 0xff; 775 776 if (hal->ah_ee_version <= AR5K_EEPROM_VERSION_3_2) 777 ee->ee_noise_floor_thr[mode] = 778 mode == AR5K_EEPROM_MODE_11A ? -54 : -1; 779 780 AR5K_EEPROM_READ(o++, val); 781 ee->ee_xlna_gain[mode] = (val >> 5) & 0xff; 782 ee->ee_x_gain[mode] = (val >> 1) & 0xf; 783 ee->ee_xpd[mode] = val & 0x1; 784 785 if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) 786 ee->ee_fixed_bias[mode] = (val >> 13) & 0x1; 787 788 if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_3_3) { 789 AR5K_EEPROM_READ(o++, val); 790 ee->ee_false_detect[mode] = (val >> 6) & 0x7f; 791 792 if (mode == AR5K_EEPROM_MODE_11A) 793 ee->ee_xr_power[mode] = val & 0x3f; 794 else { 795 ee->ee_ob[mode][0] = val & 0x7; 796 ee->ee_db[mode][0] = (val >> 3) & 0x7; 797 } 798 } 799 800 if (hal->ah_ee_version < AR5K_EEPROM_VERSION_3_4) { 801 ee->ee_i_gain[mode] = AR5K_EEPROM_I_GAIN; 802 ee->ee_cck_ofdm_power_delta = AR5K_EEPROM_CCK_OFDM_DELTA; 803 } else { 804 ee->ee_i_gain[mode] = (val >> 13) & 0x7; 805 806 AR5K_EEPROM_READ(o++, val); 807 ee->ee_i_gain[mode] |= (val << 3) & 0x38; 808 809 if (mode == AR5K_EEPROM_MODE_11G) 810 ee->ee_cck_ofdm_power_delta = (val >> 3) & 0xff; 811 } 812 813 if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0 && 814 mode == AR5K_EEPROM_MODE_11A) { 815 ee->ee_i_cal[mode] = (val >> 8) & 0x3f; 816 ee->ee_q_cal[mode] = (val >> 3) & 0x1f; 817 } 818 819 if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_6 && 820 mode == AR5K_EEPROM_MODE_11G) 821 ee->ee_scaled_cck_delta = (val >> 11) & 0x1f; 822 823 /* return new offset */ 824 *offset = o; 825 826 return (0); 827 } 828 829 int 830 ar5k_eeprom_init(struct ath_hal *hal) 831 { 832 struct ar5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; 833 u_int32_t offset; 834 u_int16_t val; 835 int ret, i; 836 u_int mode; 837 838 /* Initial TX thermal adjustment values */ 839 ee->ee_tx_clip = 4; 840 ee->ee_pwd_84 = ee->ee_pwd_90 = 1; 841 ee->ee_gain_select = 1; 842 843 /* 844 * Read values from EEPROM and store them in the capability structure 845 */ 846 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MAGIC, ee_magic); 847 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_PROTECT, ee_protect); 848 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_REG_DOMAIN, ee_regdomain); 849 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_VERSION, ee_version); 850 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_HDR, ee_header); 851 852 /* Return if we have an old EEPROM */ 853 if (hal->ah_ee_version < AR5K_EEPROM_VERSION_3_0) 854 return (0); 855 856 #ifdef notyet 857 /* 858 * Validate the checksum of the EEPROM date. There are some 859 * devices with invalid EEPROMs. 860 */ 861 for (cksum = 0, offset = 0; offset < AR5K_EEPROM_INFO_MAX; offset++) { 862 AR5K_EEPROM_READ(AR5K_EEPROM_INFO(offset), val); 863 cksum ^= val; 864 } 865 if (cksum != AR5K_EEPROM_INFO_CKSUM) { 866 AR5K_PRINTF("Invalid EEPROM checksum 0x%04x\n", cksum); 867 return (EINVAL); 868 } 869 #endif 870 871 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_ANT_GAIN(hal->ah_ee_version), 872 ee_ant_gain); 873 874 if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) { 875 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC0, ee_misc0); 876 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC1, ee_misc1); 877 } 878 879 if (hal->ah_ee_version < AR5K_EEPROM_VERSION_3_3) { 880 AR5K_EEPROM_READ(AR5K_EEPROM_OBDB0_2GHZ, val); 881 ee->ee_ob[AR5K_EEPROM_MODE_11B][0] = val & 0x7; 882 ee->ee_db[AR5K_EEPROM_MODE_11B][0] = (val >> 3) & 0x7; 883 884 AR5K_EEPROM_READ(AR5K_EEPROM_OBDB1_2GHZ, val); 885 ee->ee_ob[AR5K_EEPROM_MODE_11G][0] = val & 0x7; 886 ee->ee_db[AR5K_EEPROM_MODE_11G][0] = (val >> 3) & 0x7; 887 } 888 889 /* 890 * Get conformance test limit values 891 */ 892 offset = AR5K_EEPROM_CTL(hal->ah_ee_version); 893 ee->ee_ctls = AR5K_EEPROM_N_CTLS(hal->ah_ee_version); 894 895 for (i = 0; i < ee->ee_ctls; i++) { 896 AR5K_EEPROM_READ(offset++, val); 897 ee->ee_ctl[i] = (val >> 8) & 0xff; 898 ee->ee_ctl[i + 1] = val & 0xff; 899 } 900 901 /* 902 * Get values for 802.11a (5GHz) 903 */ 904 mode = AR5K_EEPROM_MODE_11A; 905 906 offset = AR5K_EEPROM_MODES_11A(hal->ah_ee_version); 907 908 if ((ret = ar5k_eeprom_read_ants(hal, &offset, mode)) != 0) 909 return (ret); 910 911 AR5K_EEPROM_READ(offset++, val); 912 ee->ee_adc_desired_size[mode] = (int8_t)((val >> 8) & 0xff); 913 ee->ee_ob[mode][3] = (val >> 5) & 0x7; 914 ee->ee_db[mode][3] = (val >> 2) & 0x7; 915 ee->ee_ob[mode][2] = (val << 1) & 0x7; 916 917 AR5K_EEPROM_READ(offset++, val); 918 ee->ee_ob[mode][2] |= (val >> 15) & 0x1; 919 ee->ee_db[mode][2] = (val >> 12) & 0x7; 920 ee->ee_ob[mode][1] = (val >> 9) & 0x7; 921 ee->ee_db[mode][1] = (val >> 6) & 0x7; 922 ee->ee_ob[mode][0] = (val >> 3) & 0x7; 923 ee->ee_db[mode][0] = val & 0x7; 924 925 if ((ret = ar5k_eeprom_read_modes(hal, &offset, mode)) != 0) 926 return (ret); 927 928 if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) { 929 AR5K_EEPROM_READ(offset++, val); 930 ee->ee_margin_tx_rx[mode] = val & 0x3f; 931 } 932 933 /* 934 * Get values for 802.11b (2.4GHz) 935 */ 936 mode = AR5K_EEPROM_MODE_11B; 937 offset = AR5K_EEPROM_MODES_11B(hal->ah_ee_version); 938 939 if ((ret = ar5k_eeprom_read_ants(hal, &offset, mode)) != 0) 940 return (ret); 941 942 AR5K_EEPROM_READ(offset++, val); 943 ee->ee_adc_desired_size[mode] = (int8_t)((val >> 8) & 0xff); 944 ee->ee_ob[mode][1] = (val >> 4) & 0x7; 945 ee->ee_db[mode][1] = val & 0x7; 946 947 if ((ret = ar5k_eeprom_read_modes(hal, &offset, mode)) != 0) 948 return (ret); 949 950 if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) { 951 AR5K_EEPROM_READ(offset++, val); 952 ee->ee_cal_pier[mode][0] = 953 ar5k_eeprom_bin2freq(hal, val & 0xff, mode); 954 ee->ee_cal_pier[mode][1] = 955 ar5k_eeprom_bin2freq(hal, (val >> 8) & 0xff, mode); 956 957 AR5K_EEPROM_READ(offset++, val); 958 ee->ee_cal_pier[mode][2] = 959 ar5k_eeprom_bin2freq(hal, val & 0xff, mode); 960 } 961 962 if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) { 963 ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f; 964 } 965 966 /* 967 * Get values for 802.11g (2.4GHz) 968 */ 969 mode = AR5K_EEPROM_MODE_11G; 970 offset = AR5K_EEPROM_MODES_11G(hal->ah_ee_version); 971 972 if ((ret = ar5k_eeprom_read_ants(hal, &offset, mode)) != 0) 973 return (ret); 974 975 AR5K_EEPROM_READ(offset++, val); 976 ee->ee_adc_desired_size[mode] = (int8_t)((val >> 8) & 0xff); 977 ee->ee_ob[mode][1] = (val >> 4) & 0x7; 978 ee->ee_db[mode][1] = val & 0x7; 979 980 if ((ret = ar5k_eeprom_read_modes(hal, &offset, mode)) != 0) 981 return (ret); 982 983 if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) { 984 AR5K_EEPROM_READ(offset++, val); 985 ee->ee_cal_pier[mode][0] = 986 ar5k_eeprom_bin2freq(hal, val & 0xff, mode); 987 ee->ee_cal_pier[mode][1] = 988 ar5k_eeprom_bin2freq(hal, (val >> 8) & 0xff, mode); 989 990 AR5K_EEPROM_READ(offset++, val); 991 ee->ee_xr_power[mode] = (val >> 7) & 0x3f; 992 993 AR5K_EEPROM_READ(offset++, val); 994 ee->ee_cal_pier[mode][2] = 995 ar5k_eeprom_bin2freq(hal, val & 0xff, mode); 996 997 if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) { 998 ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f; 999 } 1000 1001 AR5K_EEPROM_READ(offset++, val); 1002 ee->ee_i_cal[mode] = (val >> 8) & 0x3f; 1003 ee->ee_q_cal[mode] = (val >> 3) & 0x1f; 1004 1005 if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_2) { 1006 AR5K_EEPROM_READ(offset++, val); 1007 ee->ee_cck_ofdm_gain_delta = val & 0xff; 1008 } 1009 } 1010 1011 /* 1012 * Read 5GHz EEPROM channels 1013 */ 1014 1015 return (0); 1016 } 1017 1018 int 1019 ar5k_eeprom_read_mac(struct ath_hal *hal, u_int8_t *mac) 1020 { 1021 u_int32_t total, offset; 1022 u_int16_t data; 1023 int octet; 1024 u_int8_t mac_d[IEEE80211_ADDR_LEN]; 1025 1026 bzero(mac, IEEE80211_ADDR_LEN); 1027 bzero(&mac_d, IEEE80211_ADDR_LEN); 1028 1029 if (hal->ah_eeprom_read(hal, 0x20, &data) != 0) 1030 return (EIO); 1031 1032 for (offset = 0x1f, octet = 0, total = 0; 1033 offset >= 0x1d; offset--) { 1034 if (hal->ah_eeprom_read(hal, offset, &data) != 0) 1035 return (EIO); 1036 1037 total += data; 1038 mac_d[octet + 1] = data & 0xff; 1039 mac_d[octet] = data >> 8; 1040 octet += 2; 1041 } 1042 1043 bcopy(mac_d, mac, IEEE80211_ADDR_LEN); 1044 1045 if ((!total) || total == (3 * 0xffff)) 1046 return (EINVAL); 1047 1048 return (0); 1049 } 1050 1051 HAL_BOOL 1052 ar5k_eeprom_regulation_domain(struct ath_hal *hal, HAL_BOOL write, 1053 ieee80211_regdomain_t *regdomain) 1054 { 1055 u_int16_t ee_regdomain; 1056 1057 /* Read current value */ 1058 if (write != AH_TRUE) { 1059 ee_regdomain = hal->ah_capabilities.cap_eeprom.ee_regdomain; 1060 *regdomain = ar5k_regdomain_to_ieee(ee_regdomain); 1061 return (AH_TRUE); 1062 } 1063 1064 ee_regdomain = ar5k_regdomain_from_ieee(*regdomain); 1065 1066 /* Try to write a new value */ 1067 if (hal->ah_capabilities.cap_eeprom.ee_protect & 1068 AR5K_EEPROM_PROTECT_WR_128_191) 1069 return (AH_FALSE); 1070 if (hal->ah_eeprom_write(hal, AR5K_EEPROM_REG_DOMAIN, 1071 ee_regdomain) != 0) 1072 return (AH_FALSE); 1073 1074 hal->ah_capabilities.cap_eeprom.ee_regdomain = ee_regdomain; 1075 1076 return (AH_TRUE); 1077 } 1078 1079 /* 1080 * PHY/RF access functions 1081 */ 1082 1083 HAL_BOOL 1084 ar5k_channel(struct ath_hal *hal, HAL_CHANNEL *channel) 1085 { 1086 HAL_BOOL ret; 1087 1088 /* 1089 * Check bounds supported by the PHY 1090 * (don't care about regulation restrictions at this point) 1091 */ 1092 if ((channel->channel < hal->ah_capabilities.cap_range.range_2ghz_min || 1093 channel->channel > hal->ah_capabilities.cap_range.range_2ghz_max) && 1094 (channel->channel < hal->ah_capabilities.cap_range.range_5ghz_min || 1095 channel->channel > hal->ah_capabilities.cap_range.range_5ghz_max)) { 1096 AR5K_PRINTF("channel out of supported range (%u MHz)\n", 1097 channel->channel); 1098 return (AH_FALSE); 1099 } 1100 1101 /* 1102 * Set the channel and wait 1103 */ 1104 if (hal->ah_radio == AR5K_AR5110) 1105 ret = ar5k_ar5110_channel(hal, channel); 1106 else if (hal->ah_radio == AR5K_AR5111) 1107 ret = ar5k_ar5111_channel(hal, channel); 1108 else 1109 ret = ar5k_ar5112_channel(hal, channel); 1110 1111 if (ret == AH_FALSE) 1112 return (ret); 1113 1114 hal->ah_current_channel.c_channel = channel->c_channel; 1115 hal->ah_current_channel.c_channel_flags = channel->c_channel_flags; 1116 1117 return (AH_TRUE); 1118 } 1119 1120 u_int32_t 1121 ar5k_ar5110_chan2athchan(HAL_CHANNEL *channel) 1122 { 1123 u_int32_t athchan; 1124 1125 /* 1126 * Convert IEEE channel/MHz to an internal channel value used 1127 * by the AR5210 chipset. This has not been verified with 1128 * newer chipsets like the AR5212A who have a completely 1129 * different RF/PHY part. 1130 */ 1131 athchan = (ar5k_bitswap((ieee80211_mhz2ieee(channel->c_channel, 1132 channel->c_channel_flags) - 24) / 2, 5) << 1) | 1133 (1 << 6) | 0x1; 1134 1135 return (athchan); 1136 } 1137 1138 HAL_BOOL 1139 ar5k_ar5110_channel(struct ath_hal *hal, HAL_CHANNEL *channel) 1140 { 1141 u_int32_t data; 1142 1143 /* 1144 * Set the channel and wait 1145 */ 1146 data = ar5k_ar5110_chan2athchan(channel); 1147 AR5K_PHY_WRITE(0x27, data); 1148 AR5K_PHY_WRITE(0x30, 0); 1149 AR5K_DELAY(1000); 1150 1151 return (AH_TRUE); 1152 } 1153 1154 HAL_BOOL 1155 ar5k_ar5111_chan2athchan(u_int ieee, struct ar5k_athchan_2ghz *athchan) 1156 { 1157 int channel; 1158 1159 /* Cast this value to catch negative channel numbers (>= -19) */ 1160 channel = (int)ieee; 1161 1162 /* 1163 * Map 2GHz IEEE channel to 5GHz Atheros channel 1164 */ 1165 if (channel <= 13) { 1166 athchan->a2_athchan = 115 + channel; 1167 athchan->a2_flags = 0x46; 1168 } else if (channel == 14) { 1169 athchan->a2_athchan = 124; 1170 athchan->a2_flags = 0x44; 1171 } else if (channel >= 15 && channel <= 26) { 1172 athchan->a2_athchan = ((channel - 14) * 4) + 132; 1173 athchan->a2_flags = 0x46; 1174 } else 1175 return (AH_FALSE); 1176 1177 return (AH_TRUE); 1178 } 1179 1180 HAL_BOOL 1181 ar5k_ar5111_channel(struct ath_hal *hal, HAL_CHANNEL *channel) 1182 { 1183 u_int ieee_channel, ath_channel; 1184 u_int32_t data0, data1, clock; 1185 struct ar5k_athchan_2ghz ath_channel_2ghz; 1186 1187 /* 1188 * Set the channel on the AR5111 radio 1189 */ 1190 data0 = data1 = 0; 1191 ath_channel = ieee_channel = ieee80211_mhz2ieee(channel->c_channel, 1192 channel->c_channel_flags); 1193 1194 if (channel->c_channel_flags & IEEE80211_CHAN_2GHZ) { 1195 /* Map 2GHz channel to 5GHz Atheros channel ID */ 1196 if (ar5k_ar5111_chan2athchan(ieee_channel, 1197 &ath_channel_2ghz) == AH_FALSE) 1198 return (AH_FALSE); 1199 1200 ath_channel = ath_channel_2ghz.a2_athchan; 1201 data0 = ((ar5k_bitswap(ath_channel_2ghz.a2_flags, 8) & 0xff) 1202 << 5) | (1 << 4); 1203 } 1204 1205 if (ath_channel < 145 || !(ath_channel & 1)) { 1206 clock = 1; 1207 data1 = ((ar5k_bitswap(ath_channel - 24, 8) & 0xff) << 2) 1208 | (clock << 1) | (1 << 10) | 1; 1209 } else { 1210 clock = 0; 1211 data1 = ((ar5k_bitswap((ath_channel - 24) / 2, 8) & 0xff) << 2) 1212 | (clock << 1) | (1 << 10) | 1; 1213 } 1214 1215 AR5K_PHY_WRITE(0x27, (data1 & 0xff) | ((data0 & 0xff) << 8)); 1216 AR5K_PHY_WRITE(0x34, ((data1 >> 8) & 0xff) | (data0 & 0xff00)); 1217 1218 return (AH_TRUE); 1219 } 1220 1221 HAL_BOOL 1222 ar5k_ar5112_channel(struct ath_hal *hal, HAL_CHANNEL *channel) 1223 { 1224 u_int32_t data, data0, data1, data2; 1225 u_int16_t c; 1226 1227 data = data0 = data1 = data2 = 0; 1228 c = channel->c_channel + hal->ah_chanoff; 1229 1230 /* 1231 * Set the channel on the AR5112 or newer 1232 */ 1233 if (c < 4800) { 1234 if (!((c - 2224) % 5)) { 1235 data0 = ((2 * (c - 704)) - 3040) / 10; 1236 data1 = 1; 1237 } else if (!((c - 2192) % 5)) { 1238 data0 = ((2 * (c - 672)) - 3040) / 10; 1239 data1 = 0; 1240 } else 1241 return (AH_FALSE); 1242 1243 data0 = ar5k_bitswap((data0 << 2) & 0xff, 8); 1244 } else { 1245 if (!(c % 20) && c >= 5120) { 1246 data0 = ar5k_bitswap(((c - 4800) / 20 << 2), 8); 1247 data2 = ar5k_bitswap(3, 2); 1248 } else if (!(c % 10)) { 1249 data0 = ar5k_bitswap(((c - 4800) / 10 << 1), 8); 1250 data2 = ar5k_bitswap(2, 2); 1251 } else if (!(c % 5)) { 1252 data0 = ar5k_bitswap((c - 4800) / 5, 8); 1253 data2 = ar5k_bitswap(1, 2); 1254 } else 1255 return (AH_FALSE); 1256 } 1257 1258 data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001; 1259 1260 AR5K_PHY_WRITE(0x27, data & 0xff); 1261 AR5K_PHY_WRITE(0x36, (data >> 8) & 0x7f); 1262 1263 return (AH_TRUE); 1264 } 1265 1266 u_int 1267 ar5k_rfregs_op(u_int32_t *rf, u_int32_t offset, u_int32_t reg, u_int32_t bits, 1268 u_int32_t first, u_int32_t col, HAL_BOOL set) 1269 { 1270 u_int32_t mask, entry, last, data, shift, position; 1271 int32_t left; 1272 int i; 1273 1274 if (rf == NULL) { 1275 /* should not happen */ 1276 return (0); 1277 } 1278 1279 if (!(col <= 3 && bits <= 32 && first + bits <= 319)) { 1280 AR5K_PRINTF("invalid values at offset %u\n", offset); 1281 return (0); 1282 } 1283 1284 entry = ((first - 1) / 8) + offset; 1285 position = (first - 1) % 8; 1286 1287 if (set == AH_TRUE) 1288 data = ar5k_bitswap(reg, bits); 1289 1290 for (i = shift = 0, left = bits; left > 0; position = 0, entry++, i++) { 1291 last = (position + left > 8) ? 8 : position + left; 1292 mask = (((1 << last) - 1) ^ ((1 << position) - 1)) << 1293 (col * 8); 1294 1295 if (set == AH_TRUE) { 1296 rf[entry] &= ~mask; 1297 rf[entry] |= ((data << position) << (col * 8)) & mask; 1298 data >>= (8 - position); 1299 } else { 1300 data = (((rf[entry] & mask) >> (col * 8)) >> 1301 position) << shift; 1302 shift += last - position; 1303 } 1304 1305 left -= 8 - position; 1306 } 1307 1308 data = set == AH_TRUE ? 1 : ar5k_bitswap(data, bits); 1309 1310 return (data); 1311 } 1312 1313 u_int32_t 1314 ar5k_rfregs_gainf_corr(struct ath_hal *hal) 1315 { 1316 u_int32_t mix, step; 1317 u_int32_t *rf; 1318 1319 if (hal->ah_rf_banks == NULL) 1320 return (0); 1321 1322 rf = hal->ah_rf_banks; 1323 hal->ah_gain.g_f_corr = 0; 1324 1325 if (ar5k_rfregs_op(rf, hal->ah_offset[7], 0, 1, 36, 0, AH_FALSE) != 1) 1326 return (0); 1327 1328 step = ar5k_rfregs_op(rf, hal->ah_offset[7], 0, 4, 32, 0, AH_FALSE); 1329 mix = hal->ah_gain.g_step->gos_param[0]; 1330 1331 switch (mix) { 1332 case 3: 1333 hal->ah_gain.g_f_corr = step * 2; 1334 break; 1335 case 2: 1336 hal->ah_gain.g_f_corr = (step - 5) * 2; 1337 break; 1338 case 1: 1339 hal->ah_gain.g_f_corr = step; 1340 break; 1341 default: 1342 hal->ah_gain.g_f_corr = 0; 1343 break; 1344 } 1345 1346 return (hal->ah_gain.g_f_corr); 1347 } 1348 1349 HAL_BOOL 1350 ar5k_rfregs_gain_readback(struct ath_hal *hal) 1351 { 1352 u_int32_t step, mix, level[4]; 1353 u_int32_t *rf; 1354 1355 if (hal->ah_rf_banks == NULL) 1356 return (0); 1357 1358 rf = hal->ah_rf_banks; 1359 1360 if (hal->ah_radio == AR5K_AR5111) { 1361 step = ar5k_rfregs_op(rf, hal->ah_offset[7], 1362 0, 6, 37, 0, AH_FALSE); 1363 level[0] = 0; 1364 level[1] = (step == 0x3f) ? 0x32 : step + 4; 1365 level[2] = (step != 0x3f) ? 0x40 : level[0]; 1366 level[3] = level[2] + 0x32; 1367 1368 hal->ah_gain.g_high = level[3] - 1369 (step == 0x3f ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5); 1370 hal->ah_gain.g_low = level[0] + 1371 (step == 0x3f ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0); 1372 } else { 1373 mix = ar5k_rfregs_op(rf, hal->ah_offset[7], 1374 0, 1, 36, 0, AH_FALSE); 1375 level[0] = level[2] = 0; 1376 1377 if (mix == 1) { 1378 level[1] = level[3] = 83; 1379 } else { 1380 level[1] = level[3] = 107; 1381 hal->ah_gain.g_high = 55; 1382 } 1383 } 1384 1385 return ((hal->ah_gain.g_current >= level[0] && 1386 hal->ah_gain.g_current <= level[1]) || 1387 (hal->ah_gain.g_current >= level[2] && 1388 hal->ah_gain.g_current <= level[3])); 1389 } 1390 1391 int32_t 1392 ar5k_rfregs_gain_adjust(struct ath_hal *hal) 1393 { 1394 int ret = 0; 1395 const struct ar5k_gain_opt *go; 1396 1397 go = hal->ah_radio == AR5K_AR5111 ? 1398 &ar5111_gain_opt : &ar5112_gain_opt; 1399 1400 hal->ah_gain.g_step = &go->go_step[hal->ah_gain.g_step_idx]; 1401 1402 if (hal->ah_gain.g_current >= hal->ah_gain.g_high) { 1403 if (hal->ah_gain.g_step_idx == 0) 1404 return (-1); 1405 for (hal->ah_gain.g_target = hal->ah_gain.g_current; 1406 hal->ah_gain.g_target >= hal->ah_gain.g_high && 1407 hal->ah_gain.g_step_idx > 0; 1408 hal->ah_gain.g_step = 1409 &go->go_step[hal->ah_gain.g_step_idx]) { 1410 hal->ah_gain.g_target -= 2 * 1411 (go->go_step[--(hal->ah_gain.g_step_idx)].gos_gain - 1412 hal->ah_gain.g_step->gos_gain); 1413 } 1414 1415 ret = 1; 1416 goto done; 1417 } 1418 1419 if (hal->ah_gain.g_current <= hal->ah_gain.g_low) { 1420 if (hal->ah_gain.g_step_idx == (go->go_steps_count - 1)) 1421 return (-2); 1422 for (hal->ah_gain.g_target = hal->ah_gain.g_current; 1423 hal->ah_gain.g_target <= hal->ah_gain.g_low && 1424 hal->ah_gain.g_step_idx < (go->go_steps_count - 1); 1425 hal->ah_gain.g_step = 1426 &go->go_step[hal->ah_gain.g_step_idx]) { 1427 hal->ah_gain.g_target -= 2 * 1428 (go->go_step[++(hal->ah_gain.g_step_idx)].gos_gain - 1429 hal->ah_gain.g_step->gos_gain); 1430 } 1431 1432 ret = 2; 1433 goto done; 1434 } 1435 1436 done: 1437 #ifdef AR5K_DEBUG 1438 AR5K_PRINTF("ret %d, gain step %u, current gain %u, target gain %u\n", 1439 ret, 1440 hal->ah_gain.g_step_idx, 1441 hal->ah_gain.g_current, 1442 hal->ah_gain.g_target); 1443 #endif 1444 1445 return (ret); 1446 } 1447 1448 HAL_BOOL 1449 ar5k_rfregs(struct ath_hal *hal, HAL_CHANNEL *channel, u_int mode) 1450 { 1451 ar5k_rfgain_t *func = NULL; 1452 HAL_BOOL ret; 1453 1454 switch (hal->ah_radio) { 1455 case AR5K_AR5111: 1456 hal->ah_rf_banks_size = sizeof(ar5111_rf); 1457 func = ar5k_ar5111_rfregs; 1458 break; 1459 case AR5K_AR5112: 1460 if (hal->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) 1461 hal->ah_rf_banks_size = sizeof(ar5112a_rf); 1462 else 1463 hal->ah_rf_banks_size = sizeof(ar5112_rf); 1464 func = ar5k_ar5112_rfregs; 1465 break; 1466 case AR5K_AR5413: 1467 hal->ah_rf_banks_size = sizeof(ar5413_rf); 1468 func = ar5k_arxxxx_rfregs; 1469 break; 1470 case AR5K_AR2413: 1471 hal->ah_rf_banks_size = sizeof(ar2413_rf); 1472 func = ar5k_arxxxx_rfregs; 1473 break; 1474 case AR5K_AR2425: 1475 hal->ah_rf_banks_size = sizeof(ar2425_rf); 1476 func = ar5k_arxxxx_rfregs; 1477 break; 1478 default: 1479 return (AH_FALSE); 1480 } 1481 1482 if (hal->ah_rf_banks == NULL) { 1483 /* XXX do extra checks? */ 1484 if ((hal->ah_rf_banks = malloc(hal->ah_rf_banks_size, 1485 M_DEVBUF, M_NOWAIT | M_ZERO)) == NULL) { 1486 AR5K_PRINT("out of memory\n"); 1487 return (AH_FALSE); 1488 } 1489 } 1490 1491 ret = (func)(hal, channel, mode); 1492 1493 if (ret == AH_TRUE) 1494 hal->ah_rf_gain = HAL_RFGAIN_INACTIVE; 1495 1496 return (ret); 1497 } 1498 1499 HAL_BOOL 1500 ar5k_ar5111_rfregs(struct ath_hal *hal, HAL_CHANNEL *channel, u_int mode) 1501 { 1502 struct ar5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; 1503 const u_int rf_size = nitems(ar5111_rf); 1504 u_int32_t *rf; 1505 int i, obdb = -1, bank = -1; 1506 u_int32_t ee_mode; 1507 1508 AR5K_ASSERT_ENTRY(mode, AR5K_INI_VAL_MAX); 1509 1510 rf = hal->ah_rf_banks; 1511 1512 /* Copy values to modify them */ 1513 for (i = 0; i < rf_size; i++) { 1514 if (ar5111_rf[i].rf_bank >= 1515 AR5K_AR5111_INI_RF_MAX_BANKS) { 1516 AR5K_PRINT("invalid bank\n"); 1517 return (AH_FALSE); 1518 } 1519 1520 if (bank != ar5111_rf[i].rf_bank) { 1521 bank = ar5111_rf[i].rf_bank; 1522 hal->ah_offset[bank] = i; 1523 } 1524 1525 rf[i] = ar5111_rf[i].rf_value[mode]; 1526 } 1527 1528 if (channel->c_channel_flags & IEEE80211_CHAN_2GHZ) { 1529 if ((channel->c_channel_flags & IEEE80211_CHAN_G) == 1530 IEEE80211_CHAN_G) 1531 ee_mode = AR5K_EEPROM_MODE_11G; 1532 else 1533 ee_mode = AR5K_EEPROM_MODE_11B; 1534 obdb = 0; 1535 1536 if (!ar5k_rfregs_op(rf, hal->ah_offset[0], 1537 ee->ee_ob[ee_mode][obdb], 3, 119, 0, AH_TRUE)) 1538 return (AH_FALSE); 1539 1540 if (!ar5k_rfregs_op(rf, hal->ah_offset[0], 1541 ee->ee_ob[ee_mode][obdb], 3, 122, 0, AH_TRUE)) 1542 return (AH_FALSE); 1543 1544 obdb = 1; 1545 } else { 1546 /* For 11a, Turbo and XR */ 1547 ee_mode = AR5K_EEPROM_MODE_11A; 1548 obdb = channel->c_channel >= 5725 ? 3 : 1549 (channel->c_channel >= 5500 ? 2 : 1550 (channel->c_channel >= 5260 ? 1 : 1551 (channel->c_channel > 4000 ? 0 : -1))); 1552 1553 if (!ar5k_rfregs_op(rf, hal->ah_offset[6], 1554 ee->ee_pwd_84, 1, 51, 3, AH_TRUE)) 1555 return (AH_FALSE); 1556 1557 if (!ar5k_rfregs_op(rf, hal->ah_offset[6], 1558 ee->ee_pwd_90, 1, 45, 3, AH_TRUE)) 1559 return (AH_FALSE); 1560 } 1561 1562 if (!ar5k_rfregs_op(rf, hal->ah_offset[6], 1563 !ee->ee_xpd[ee_mode], 1, 95, 0, AH_TRUE)) 1564 return (AH_FALSE); 1565 1566 if (!ar5k_rfregs_op(rf, hal->ah_offset[6], 1567 ee->ee_x_gain[ee_mode], 4, 96, 0, AH_TRUE)) 1568 return (AH_FALSE); 1569 1570 if (!ar5k_rfregs_op(rf, hal->ah_offset[6], 1571 obdb >= 0 ? ee->ee_ob[ee_mode][obdb] : 0, 3, 104, 0, AH_TRUE)) 1572 return (AH_FALSE); 1573 1574 if (!ar5k_rfregs_op(rf, hal->ah_offset[6], 1575 obdb >= 0 ? ee->ee_db[ee_mode][obdb] : 0, 3, 107, 0, AH_TRUE)) 1576 return (AH_FALSE); 1577 1578 if (!ar5k_rfregs_op(rf, hal->ah_offset[7], 1579 ee->ee_i_gain[ee_mode], 6, 29, 0, AH_TRUE)) 1580 return (AH_FALSE); 1581 1582 if (!ar5k_rfregs_op(rf, hal->ah_offset[7], 1583 ee->ee_xpd[ee_mode], 1, 4, 0, AH_TRUE)) 1584 return (AH_FALSE); 1585 1586 /* Write RF values */ 1587 for (i = 0; i < rf_size; i++) { 1588 AR5K_REG_WAIT(i); 1589 AR5K_REG_WRITE(ar5111_rf[i].rf_register, rf[i]); 1590 } 1591 1592 return (AH_TRUE); 1593 } 1594 1595 HAL_BOOL 1596 ar5k_ar5112_rfregs(struct ath_hal *hal, HAL_CHANNEL *channel, u_int mode) 1597 { 1598 struct ar5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; 1599 u_int rf_size; 1600 u_int32_t *rf; 1601 int i, obdb = -1, bank = -1; 1602 u_int32_t ee_mode; 1603 const struct ar5k_ini_rf *rf_ini; 1604 1605 AR5K_ASSERT_ENTRY(mode, AR5K_INI_VAL_MAX); 1606 1607 rf = hal->ah_rf_banks; 1608 1609 if (hal->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) { 1610 rf_ini = ar5112a_rf; 1611 rf_size = nitems(ar5112a_rf); 1612 } else { 1613 rf_ini = ar5112_rf; 1614 rf_size = nitems(ar5112_rf); 1615 } 1616 1617 /* Copy values to modify them */ 1618 for (i = 0; i < rf_size; i++) { 1619 if (rf_ini[i].rf_bank >= 1620 AR5K_AR5112_INI_RF_MAX_BANKS) { 1621 AR5K_PRINT("invalid bank\n"); 1622 return (AH_FALSE); 1623 } 1624 1625 if (bank != rf_ini[i].rf_bank) { 1626 bank = rf_ini[i].rf_bank; 1627 hal->ah_offset[bank] = i; 1628 } 1629 1630 rf[i] = rf_ini[i].rf_value[mode]; 1631 } 1632 1633 if (channel->c_channel_flags & IEEE80211_CHAN_2GHZ) { 1634 if ((channel->c_channel_flags & IEEE80211_CHAN_G) == 1635 IEEE80211_CHAN_G) 1636 ee_mode = AR5K_EEPROM_MODE_11G; 1637 else 1638 ee_mode = AR5K_EEPROM_MODE_11B; 1639 obdb = 0; 1640 1641 if (!ar5k_rfregs_op(rf, hal->ah_offset[6], 1642 ee->ee_ob[ee_mode][obdb], 3, 287, 0, AH_TRUE)) 1643 return (AH_FALSE); 1644 1645 if (!ar5k_rfregs_op(rf, hal->ah_offset[6], 1646 ee->ee_ob[ee_mode][obdb], 3, 290, 0, AH_TRUE)) 1647 return (AH_FALSE); 1648 } else { 1649 /* For 11a, Turbo and XR */ 1650 ee_mode = AR5K_EEPROM_MODE_11A; 1651 obdb = channel->c_channel >= 5725 ? 3 : 1652 (channel->c_channel >= 5500 ? 2 : 1653 (channel->c_channel >= 5260 ? 1 : 1654 (channel->c_channel > 4000 ? 0 : -1))); 1655 1656 /* bogus channel: bad beacon? */ 1657 if (obdb < 0) 1658 return (AH_FALSE); 1659 1660 if (!ar5k_rfregs_op(rf, hal->ah_offset[6], 1661 ee->ee_ob[ee_mode][obdb], 3, 279, 0, AH_TRUE)) 1662 return (AH_FALSE); 1663 1664 if (!ar5k_rfregs_op(rf, hal->ah_offset[6], 1665 ee->ee_ob[ee_mode][obdb], 3, 282, 0, AH_TRUE)) 1666 return (AH_FALSE); 1667 } 1668 1669 #ifdef notyet 1670 ar5k_rfregs_op(rf, hal->ah_offset[6], 1671 ee->ee_x_gain[ee_mode], 2, 270, 0, AH_TRUE); 1672 ar5k_rfregs_op(rf, hal->ah_offset[6], 1673 ee->ee_x_gain[ee_mode], 2, 257, 0, AH_TRUE); 1674 #endif 1675 1676 if (!ar5k_rfregs_op(rf, hal->ah_offset[6], 1677 ee->ee_xpd[ee_mode], 1, 302, 0, AH_TRUE)) 1678 return (AH_FALSE); 1679 1680 if (!ar5k_rfregs_op(rf, hal->ah_offset[7], 1681 ee->ee_i_gain[ee_mode], 6, 14, 0, AH_TRUE)) 1682 return (AH_FALSE); 1683 1684 /* Write RF values */ 1685 for (i = 0; i < rf_size; i++) 1686 AR5K_REG_WRITE(rf_ini[i].rf_register, rf[i]); 1687 1688 return (AH_TRUE); 1689 } 1690 1691 HAL_BOOL 1692 ar5k_arxxxx_rfregs(struct ath_hal *hal, HAL_CHANNEL *channel, u_int mode) 1693 { 1694 const struct ar5k_ini_rf *rf_ini; 1695 u_int rf_size; 1696 u_int32_t *rf; 1697 int i, bank = -1; 1698 1699 AR5K_ASSERT_ENTRY(mode, AR5K_INI_VAL_MAX); 1700 1701 rf = hal->ah_rf_banks; 1702 1703 switch (hal->ah_radio) { 1704 case AR5K_AR5413: 1705 rf_ini = ar5413_rf; 1706 rf_size = nitems(ar5413_rf); 1707 break; 1708 case AR5K_AR2413: 1709 rf_ini = ar2413_rf; 1710 rf_size = nitems(ar2413_rf); 1711 break; 1712 case AR5K_AR2425: 1713 if (mode == AR5K_INI_VAL_11B) 1714 mode = AR5K_INI_VAL_11G; 1715 rf_ini = ar2425_rf; 1716 rf_size = nitems(ar2425_rf); 1717 break; 1718 default: 1719 return (AH_FALSE); 1720 } 1721 1722 /* Copy values to modify them */ 1723 for (i = 0; i < rf_size; i++) { 1724 if (rf_ini[i].rf_bank >= AR5K_MAX_RF_BANKS) { 1725 AR5K_PRINT("invalid bank\n"); 1726 return (AH_FALSE); 1727 } 1728 1729 if (bank != rf_ini[i].rf_bank) { 1730 bank = rf_ini[i].rf_bank; 1731 hal->ah_offset[bank] = i; 1732 } 1733 1734 rf[i] = rf_ini[i].rf_value[mode]; 1735 } 1736 1737 /* Write RF values */ 1738 for (i = 0; i < rf_size; i++) 1739 AR5K_REG_WRITE(rf_ini[i].rf_register, rf[i]); 1740 1741 return (AH_TRUE); 1742 } 1743 1744 HAL_BOOL 1745 ar5k_rfgain(struct ath_hal *hal, u_int freq) 1746 { 1747 const struct ar5k_ini_rfgain *rfg; 1748 size_t rfg_size; 1749 int i; 1750 1751 switch (hal->ah_radio) { 1752 case AR5K_AR5111: 1753 rfg = ar5111_rfg; 1754 rfg_size = nitems(ar5111_rfg); 1755 break; 1756 case AR5K_AR5112: 1757 rfg = ar5112_rfg; 1758 rfg_size = nitems(ar5112_rfg); 1759 break; 1760 case AR5K_AR5413: 1761 rfg = ar5413_rfg; 1762 rfg_size = nitems(ar5413_rfg); 1763 break; 1764 case AR5K_AR2413: 1765 case AR5K_AR2425: 1766 if (freq == AR5K_INI_RFGAIN_5GHZ) 1767 return (AH_FALSE); 1768 rfg = ar2413_rfg; 1769 rfg_size = nitems(ar2413_rfg); 1770 break; 1771 default: 1772 return (AH_FALSE); 1773 } 1774 1775 switch (freq) { 1776 case AR5K_INI_RFGAIN_2GHZ: 1777 case AR5K_INI_RFGAIN_5GHZ: 1778 break; 1779 default: 1780 return (AH_FALSE); 1781 } 1782 1783 for (i = 0; i < rfg_size; i++) { 1784 AR5K_REG_WAIT(i); 1785 AR5K_REG_WRITE((u_int32_t)rfg[i].rfg_register, 1786 rfg[i].rfg_value[freq]); 1787 } 1788 1789 return (AH_TRUE); 1790 } 1791 1792 /* 1793 * Common TX power setup 1794 */ 1795 void 1796 ar5k_txpower_table(struct ath_hal *hal, HAL_CHANNEL *channel, int16_t max_power) 1797 { 1798 u_int16_t txpower, *rates; 1799 int i, min, max, n; 1800 1801 rates = hal->ah_txpower.txp_rates; 1802 1803 txpower = AR5K_TUNE_DEFAULT_TXPOWER * 2; 1804 if (max_power > txpower) { 1805 txpower = max_power > AR5K_TUNE_MAX_TXPOWER ? 1806 AR5K_TUNE_MAX_TXPOWER : max_power; 1807 } 1808 1809 for (i = 0; i < AR5K_MAX_RATES; i++) 1810 rates[i] = txpower; 1811 1812 /* XXX setup target powers by rate */ 1813 1814 hal->ah_txpower.txp_min = rates[7]; 1815 hal->ah_txpower.txp_max = rates[0]; 1816 hal->ah_txpower.txp_ofdm = rates[0]; 1817 1818 /* Calculate the power table */ 1819 n = nitems(hal->ah_txpower.txp_pcdac); 1820 min = AR5K_EEPROM_PCDAC_START; 1821 max = AR5K_EEPROM_PCDAC_STOP; 1822 for (i = 0; i < n; i += AR5K_EEPROM_PCDAC_STEP) 1823 hal->ah_txpower.txp_pcdac[i] = 1824 #ifdef notyet 1825 min + ((i * (max - min)) / n); 1826 #else 1827 min; 1828 #endif 1829 } 1830 1831 void 1832 ar5k_write_ini(struct ath_hal *hal, const struct ar5k_ini *ini, 1833 size_t n, HAL_BOOL change_channel) 1834 { 1835 u_int i; 1836 1837 for (i = 0; i < n; i++) { 1838 if (change_channel == AH_TRUE && 1839 ini[i].ini_register >= AR5K_PCU_MIN && 1840 ini[i].ini_register <= AR5K_PCU_MAX) 1841 continue; 1842 switch (ini[i].ini_mode) { 1843 case AR5K_INI_READ: 1844 /* cleared on read */ 1845 AR5K_REG_READ((u_int32_t)ini[i].ini_register); 1846 break; 1847 case AR5K_INI_WRITE: 1848 AR5K_REG_WAIT(i); 1849 AR5K_REG_WRITE((u_int32_t)ini[i].ini_register, 1850 ini[i].ini_value); 1851 break; 1852 } 1853 } 1854 } 1855 1856 void 1857 ar5k_write_mode(struct ath_hal *hal, const struct ar5k_mode *ini, 1858 size_t n, u_int mode) 1859 { 1860 u_int i; 1861 1862 for (i = 0; i < n; i++) { 1863 AR5K_REG_WAIT(i); 1864 AR5K_REG_WRITE((u_int32_t)ini[i].mode_register, 1865 ini[i].mode_value[mode]); 1866 } 1867 } 1868