1 /* $OpenBSD: ar5xxx.c,v 1.55 2009/09/23 18:03:30 damien Exp $ */ 2 3 /* 4 * Copyright (c) 2004, 2005, 2006, 2007 Reyk Floeter <reyk@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * HAL interface for Atheros Wireless LAN devices. 21 * (Please have a look at ar5xxx.h for further information) 22 */ 23 24 #include <dev/pci/pcidevs.h> 25 #include <dev/ic/ar5xxx.h> 26 27 extern ar5k_attach_t ar5k_ar5210_attach; 28 extern ar5k_attach_t ar5k_ar5211_attach; 29 extern ar5k_attach_t ar5k_ar5212_attach; 30 31 static const struct { 32 u_int16_t vendor; 33 u_int16_t device; 34 ar5k_attach_t (*attach); 35 } ar5k_known_products[] = { 36 /* 37 * From pcidevs_data.h 38 */ 39 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5210, 40 ar5k_ar5210_attach }, 41 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5210_AP, 42 ar5k_ar5210_attach }, 43 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5210_DEFAULT, 44 ar5k_ar5210_attach }, 45 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5211, 46 ar5k_ar5211_attach }, 47 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5211_DEFAULT, 48 ar5k_ar5211_attach }, 49 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5311, 50 ar5k_ar5211_attach }, 51 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5211_FPGA11B, 52 ar5k_ar5211_attach }, 53 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5211_LEGACY, 54 ar5k_ar5211_attach }, 55 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5212, 56 ar5k_ar5212_attach }, 57 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5212_DEFAULT, 58 ar5k_ar5212_attach }, 59 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5212_FPGA, 60 ar5k_ar5212_attach }, 61 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5212_IBM, 62 ar5k_ar5212_attach }, 63 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR2413, 64 ar5k_ar5212_attach }, 65 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5413, 66 ar5k_ar5212_attach }, 67 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5424, 68 ar5k_ar5212_attach }, 69 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CRDAG675, 70 ar5k_ar5212_attach }, 71 { PCI_VENDOR_3COM2, PCI_PRODUCT_3COM2_3CRPAG175, 72 ar5k_ar5212_attach } 73 }; 74 75 static const HAL_RATE_TABLE ar5k_rt_11a = AR5K_RATES_11A; 76 static const HAL_RATE_TABLE ar5k_rt_11b = AR5K_RATES_11B; 77 static const HAL_RATE_TABLE ar5k_rt_11g = AR5K_RATES_11G; 78 static const HAL_RATE_TABLE ar5k_rt_turbo = AR5K_RATES_TURBO; 79 static const HAL_RATE_TABLE ar5k_rt_xr = AR5K_RATES_XR; 80 81 int ar5k_eeprom_read_ants(struct ath_hal *, u_int32_t *, u_int); 82 int ar5k_eeprom_read_modes(struct ath_hal *, u_int32_t *, u_int); 83 u_int16_t ar5k_eeprom_bin2freq(struct ath_hal *, u_int16_t, u_int); 84 85 HAL_BOOL ar5k_ar5110_channel(struct ath_hal *, HAL_CHANNEL *); 86 u_int32_t ar5k_ar5110_chan2athchan(HAL_CHANNEL *); 87 HAL_BOOL ar5k_ar5111_channel(struct ath_hal *, HAL_CHANNEL *); 88 HAL_BOOL ar5k_ar5111_chan2athchan(u_int, struct ar5k_athchan_2ghz *); 89 HAL_BOOL ar5k_ar5112_channel(struct ath_hal *, HAL_CHANNEL *); 90 HAL_BOOL ar5k_check_channel(struct ath_hal *, u_int16_t, u_int flags); 91 92 HAL_BOOL ar5k_ar5111_rfregs(struct ath_hal *, HAL_CHANNEL *, u_int); 93 HAL_BOOL ar5k_ar5112_rfregs(struct ath_hal *, HAL_CHANNEL *, u_int); 94 HAL_BOOL ar5k_arxxxx_rfregs(struct ath_hal *, HAL_CHANNEL *, u_int); 95 u_int ar5k_rfregs_op(u_int32_t *, u_int32_t, u_int32_t, u_int32_t, 96 u_int32_t, u_int32_t, HAL_BOOL); 97 98 /* 99 * Supported channels 100 */ 101 static const struct 102 ieee80211_regchannel ar5k_5ghz_channels[] = IEEE80211_CHANNELS_5GHZ; 103 static const struct 104 ieee80211_regchannel ar5k_2ghz_channels[] = IEEE80211_CHANNELS_2GHZ; 105 106 /* 107 * Initial gain optimization values 108 */ 109 static const struct ar5k_gain_opt ar5111_gain_opt = AR5K_AR5111_GAIN_OPT; 110 static const struct ar5k_gain_opt ar5112_gain_opt = AR5K_AR5112_GAIN_OPT; 111 112 /* 113 * Initial register for the radio chipsets 114 */ 115 static const struct ar5k_ini_rf ar5111_rf[] = AR5K_AR5111_INI_RF; 116 static const struct ar5k_ini_rf ar5112_rf[] = AR5K_AR5112_INI_RF; 117 static const struct ar5k_ini_rf ar5112a_rf[] = AR5K_AR5112A_INI_RF; 118 static const struct ar5k_ini_rf ar5413_rf[] = AR5K_AR5413_INI_RF; 119 static const struct ar5k_ini_rf ar2413_rf[] = AR5K_AR2413_INI_RF; 120 static const struct ar5k_ini_rf ar2425_rf[] = AR5K_AR2425_INI_RF; 121 static const struct ar5k_ini_rfgain ar5111_rfg[] = AR5K_AR5111_INI_RFGAIN; 122 static const struct ar5k_ini_rfgain ar5112_rfg[] = AR5K_AR5112_INI_RFGAIN; 123 static const struct ar5k_ini_rfgain ar5413_rfg[] = AR5K_AR5413_INI_RFGAIN; 124 static const struct ar5k_ini_rfgain ar2413_rfg[] = AR5K_AR2413_INI_RFGAIN; 125 126 /* 127 * Enable to overwrite the country code (use "00" for debug) 128 */ 129 #if 0 130 #define COUNTRYCODE "00" 131 #endif 132 133 /* 134 * Perform a lookup if the device is supported by the HAL 135 */ 136 const char * 137 ath_hal_probe(u_int16_t vendor, u_int16_t device) 138 { 139 int i; 140 141 /* 142 * Perform a linear search on the table of supported devices 143 */ 144 for (i = 0; i < nitems(ar5k_known_products); i++) { 145 if (vendor == ar5k_known_products[i].vendor && 146 device == ar5k_known_products[i].device) 147 return (""); 148 } 149 150 return (NULL); 151 } 152 153 /* 154 * Fills in the HAL structure and initialises the device 155 */ 156 struct ath_hal * 157 ath_hal_attach(u_int16_t device, void *arg, bus_space_tag_t st, 158 bus_space_handle_t sh, u_int is_pcie, int *status) 159 { 160 struct ath_softc *sc = (struct ath_softc *)arg; 161 struct ath_hal *hal = NULL; 162 ar5k_attach_t *attach = NULL; 163 u_int8_t mac[IEEE80211_ADDR_LEN]; 164 int i; 165 166 *status = EINVAL; 167 168 /* 169 * Call the chipset-dependent attach routine by device id 170 */ 171 for (i = 0; i < nitems(ar5k_known_products); i++) { 172 if (device == ar5k_known_products[i].device && 173 ar5k_known_products[i].attach != NULL) 174 attach = ar5k_known_products[i].attach; 175 } 176 177 if (attach == NULL) { 178 *status = ENXIO; 179 AR5K_PRINTF("device not supported: 0x%04x\n", device); 180 return (NULL); 181 } 182 183 if ((hal = malloc(sizeof(struct ath_hal), 184 M_DEVBUF, M_NOWAIT | M_ZERO)) == NULL) { 185 *status = ENOMEM; 186 AR5K_PRINT("out of memory\n"); 187 return (NULL); 188 } 189 190 hal->ah_sc = sc; 191 hal->ah_st = st; 192 hal->ah_sh = sh; 193 hal->ah_device = device; 194 hal->ah_sub_vendor = 0; /* XXX unknown?! */ 195 196 /* 197 * HAL information 198 */ 199 hal->ah_abi = HAL_ABI_VERSION; 200 hal->ah_op_mode = HAL_M_STA; 201 hal->ah_radar.r_enabled = AR5K_TUNE_RADAR_ALERT; 202 hal->ah_turbo = AH_FALSE; 203 hal->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER; 204 hal->ah_imr = 0; 205 hal->ah_atim_window = 0; 206 hal->ah_aifs = AR5K_TUNE_AIFS; 207 hal->ah_cw_min = AR5K_TUNE_CWMIN; 208 hal->ah_limit_tx_retries = AR5K_INIT_TX_RETRY; 209 hal->ah_software_retry = AH_FALSE; 210 hal->ah_ant_diversity = AR5K_TUNE_ANT_DIVERSITY; 211 hal->ah_pci_express = is_pcie ? AH_TRUE : AH_FALSE; 212 213 switch (device) { 214 case PCI_PRODUCT_ATHEROS_AR2413: 215 case PCI_PRODUCT_ATHEROS_AR5413: 216 case PCI_PRODUCT_ATHEROS_AR5424: 217 /* 218 * Known single chip solutions 219 */ 220 hal->ah_single_chip = AH_TRUE; 221 break; 222 default: 223 /* 224 * Multi chip solutions 225 */ 226 hal->ah_single_chip = AH_FALSE; 227 break; 228 } 229 230 if ((attach)(device, hal, st, sh, status) == NULL) 231 goto failed; 232 233 #ifdef AR5K_DEBUG 234 hal->ah_dump_state(hal); 235 #endif 236 237 /* 238 * Get card capabilities, values, ... 239 */ 240 241 if (ar5k_eeprom_init(hal) != 0) { 242 AR5K_PRINT("unable to init EEPROM\n"); 243 goto failed; 244 } 245 246 /* Get misc capabilities */ 247 if (hal->ah_get_capabilities(hal) != AH_TRUE) { 248 AR5K_PRINTF("unable to get device capabilities: 0x%04x\n", 249 device); 250 goto failed; 251 } 252 253 /* Get MAC address */ 254 if ((*status = ar5k_eeprom_read_mac(hal, mac)) != 0) { 255 AR5K_PRINTF("unable to read address from EEPROM: 0x%04x\n", 256 device); 257 goto failed; 258 } 259 260 hal->ah_set_lladdr(hal, mac); 261 262 /* Get rate tables */ 263 if (hal->ah_capabilities.cap_mode & HAL_MODE_11A) 264 ar5k_rt_copy(&hal->ah_rt_11a, &ar5k_rt_11a); 265 if (hal->ah_capabilities.cap_mode & HAL_MODE_11B) 266 ar5k_rt_copy(&hal->ah_rt_11b, &ar5k_rt_11b); 267 if (hal->ah_capabilities.cap_mode & HAL_MODE_11G) 268 ar5k_rt_copy(&hal->ah_rt_11g, &ar5k_rt_11g); 269 if (hal->ah_capabilities.cap_mode & HAL_MODE_TURBO) 270 ar5k_rt_copy(&hal->ah_rt_turbo, &ar5k_rt_turbo); 271 if (hal->ah_capabilities.cap_mode & HAL_MODE_XR) 272 ar5k_rt_copy(&hal->ah_rt_xr, &ar5k_rt_xr); 273 274 /* Initialize the gain optimization values */ 275 if (hal->ah_radio == AR5K_AR5111) { 276 hal->ah_gain.g_step_idx = ar5111_gain_opt.go_default; 277 hal->ah_gain.g_step = 278 &ar5111_gain_opt.go_step[hal->ah_gain.g_step_idx]; 279 hal->ah_gain.g_low = 20; 280 hal->ah_gain.g_high = 35; 281 hal->ah_gain.g_active = 1; 282 } else if (hal->ah_radio == AR5K_AR5112) { 283 hal->ah_gain.g_step_idx = ar5112_gain_opt.go_default; 284 hal->ah_gain.g_step = 285 &ar5111_gain_opt.go_step[hal->ah_gain.g_step_idx]; 286 hal->ah_gain.g_low = 20; 287 hal->ah_gain.g_high = 85; 288 hal->ah_gain.g_active = 1; 289 } else { 290 /* XXX not needed for newer chipsets? */ 291 } 292 293 *status = HAL_OK; 294 295 return (hal); 296 297 failed: 298 free(hal, M_DEVBUF); 299 return (NULL); 300 } 301 302 u_int16_t 303 ath_hal_computetxtime(struct ath_hal *hal, const HAL_RATE_TABLE *rates, 304 u_int32_t frame_length, u_int16_t rate_index, HAL_BOOL short_preamble) 305 { 306 const HAL_RATE *rate; 307 u_int32_t value; 308 309 AR5K_ASSERT_ENTRY(rate_index, rates->rateCount); 310 311 /* 312 * Get rate by index 313 */ 314 rate = &rates->info[rate_index]; 315 316 /* 317 * Calculate the transmission time by operation (PHY) mode 318 */ 319 switch (rate->phy) { 320 case IEEE80211_T_CCK: 321 /* 322 * CCK / DS mode (802.11b) 323 */ 324 value = AR5K_CCK_TX_TIME(rate->rateKbps, frame_length, 325 (short_preamble && rate->shortPreamble)); 326 break; 327 328 case IEEE80211_T_OFDM: 329 /* 330 * Orthogonal Frequency Division Multiplexing 331 */ 332 if (AR5K_OFDM_NUM_BITS_PER_SYM(rate->rateKbps) == 0) 333 return (0); 334 value = AR5K_OFDM_TX_TIME(rate->rateKbps, frame_length); 335 break; 336 337 case IEEE80211_T_TURBO: 338 /* 339 * Orthogonal Frequency Division Multiplexing 340 * Atheros "Turbo Mode" (doubled rates) 341 */ 342 if (AR5K_TURBO_NUM_BITS_PER_SYM(rate->rateKbps) == 0) 343 return (0); 344 value = AR5K_TURBO_TX_TIME(rate->rateKbps, frame_length); 345 break; 346 347 case IEEE80211_T_XR: 348 /* 349 * Orthogonal Frequency Division Multiplexing 350 * Atheros "eXtended Range" (XR) 351 */ 352 if (AR5K_XR_NUM_BITS_PER_SYM(rate->rateKbps) == 0) 353 return (0); 354 value = AR5K_XR_TX_TIME(rate->rateKbps, frame_length); 355 break; 356 357 default: 358 return (0); 359 } 360 361 return (value); 362 } 363 364 HAL_BOOL 365 ar5k_check_channel(struct ath_hal *hal, u_int16_t freq, u_int flags) 366 { 367 /* Check if the channel is in our supported range */ 368 if (flags & IEEE80211_CHAN_2GHZ) { 369 if ((freq >= hal->ah_capabilities.cap_range.range_2ghz_min) && 370 (freq <= hal->ah_capabilities.cap_range.range_2ghz_max)) 371 return (AH_TRUE); 372 } else if (flags & IEEE80211_CHAN_5GHZ) { 373 if ((freq >= hal->ah_capabilities.cap_range.range_5ghz_min) && 374 (freq <= hal->ah_capabilities.cap_range.range_5ghz_max)) 375 return (AH_TRUE); 376 } 377 378 return (AH_FALSE); 379 } 380 381 HAL_BOOL 382 ath_hal_init_channels(struct ath_hal *hal, HAL_CHANNEL *channels, 383 u_int max_channels, u_int *channels_size, u_int16_t mode, 384 HAL_BOOL outdoor, HAL_BOOL extended) 385 { 386 u_int i, c; 387 u_int32_t domain_current; 388 u_int domain_5ghz, domain_2ghz; 389 HAL_CHANNEL *all_channels; 390 391 if ((all_channels = malloc(sizeof(HAL_CHANNEL) * max_channels, 392 M_TEMP, M_NOWAIT | M_ZERO)) == NULL) 393 return (AH_FALSE); 394 395 i = c = 0; 396 domain_current = hal->ah_regdomain; 397 398 /* 399 * In debugging mode, enable all channels supported by the chipset 400 */ 401 if (domain_current == DMN_DEFAULT) { 402 int min, max, freq; 403 u_int flags; 404 405 min = ieee80211_mhz2ieee(IEEE80211_CHANNELS_2GHZ_MIN, 406 IEEE80211_CHAN_2GHZ); 407 max = ieee80211_mhz2ieee(IEEE80211_CHANNELS_2GHZ_MAX, 408 IEEE80211_CHAN_2GHZ); 409 flags = CHANNEL_B | CHANNEL_TG | 410 (hal->ah_version == AR5K_AR5211 ? 411 CHANNEL_PUREG : CHANNEL_G); 412 413 debugchan: 414 for (i = min; i <= max && c < max_channels; i++) { 415 freq = ieee80211_ieee2mhz(i, flags); 416 if (ar5k_check_channel(hal, freq, flags) == AH_FALSE) 417 continue; 418 all_channels[c].c_channel = freq; 419 all_channels[c++].c_channel_flags = flags; 420 } 421 422 if (flags & IEEE80211_CHAN_2GHZ) { 423 min = ieee80211_mhz2ieee(IEEE80211_CHANNELS_5GHZ_MIN, 424 IEEE80211_CHAN_5GHZ); 425 max = ieee80211_mhz2ieee(IEEE80211_CHANNELS_5GHZ_MAX, 426 IEEE80211_CHAN_5GHZ); 427 flags = CHANNEL_A | CHANNEL_T | CHANNEL_XR; 428 goto debugchan; 429 } 430 431 goto done; 432 } 433 434 domain_5ghz = ieee80211_regdomain2flag(domain_current, 435 IEEE80211_CHANNELS_5GHZ_MIN); 436 domain_2ghz = ieee80211_regdomain2flag(domain_current, 437 IEEE80211_CHANNELS_2GHZ_MIN); 438 439 /* 440 * Create channel list based on chipset capabilities, regulation domain 441 * and mode. 5GHz... 442 */ 443 for (i = 0; (hal->ah_capabilities.cap_range.range_5ghz_max > 0) && 444 (i < nitems(ar5k_5ghz_channels)) && 445 (c < max_channels); i++) { 446 /* Check if channel is supported by the chipset */ 447 if (ar5k_check_channel(hal, 448 ar5k_5ghz_channels[i].rc_channel, 449 IEEE80211_CHAN_5GHZ) == AH_FALSE) 450 continue; 451 452 /* Match regulation domain */ 453 if ((IEEE80211_DMN(ar5k_5ghz_channels[i].rc_domain) & 454 IEEE80211_DMN(domain_5ghz)) == 0) 455 continue; 456 457 /* Match modes */ 458 if (ar5k_5ghz_channels[i].rc_mode & IEEE80211_CHAN_TURBO) { 459 all_channels[c].c_channel_flags = CHANNEL_T; 460 } else if (ar5k_5ghz_channels[i].rc_mode & 461 IEEE80211_CHAN_OFDM) { 462 all_channels[c].c_channel_flags = CHANNEL_A; 463 } else 464 continue; 465 466 /* Write channel and increment counter */ 467 all_channels[c++].channel = ar5k_5ghz_channels[i].rc_channel; 468 } 469 470 /* 471 * ...and 2GHz. 472 */ 473 for (i = 0; (hal->ah_capabilities.cap_range.range_2ghz_max > 0) && 474 (i < nitems(ar5k_2ghz_channels)) && 475 (c < max_channels); i++) { 476 /* Check if channel is supported by the chipset */ 477 if (ar5k_check_channel(hal, 478 ar5k_2ghz_channels[i].rc_channel, 479 IEEE80211_CHAN_2GHZ) == AH_FALSE) 480 continue; 481 482 /* Match regulation domain */ 483 if ((IEEE80211_DMN(ar5k_2ghz_channels[i].rc_domain) & 484 IEEE80211_DMN(domain_2ghz)) == 0) 485 continue; 486 487 /* Match modes */ 488 if ((hal->ah_capabilities.cap_mode & HAL_MODE_11B) && 489 (ar5k_2ghz_channels[i].rc_mode & IEEE80211_CHAN_CCK)) 490 all_channels[c].c_channel_flags = CHANNEL_B; 491 492 if ((hal->ah_capabilities.cap_mode & HAL_MODE_11G) && 493 (ar5k_2ghz_channels[i].rc_mode & IEEE80211_CHAN_OFDM)) { 494 all_channels[c].c_channel_flags |= 495 hal->ah_version == AR5K_AR5211 ? 496 CHANNEL_PUREG : CHANNEL_G; 497 if (ar5k_2ghz_channels[i].rc_mode & 498 IEEE80211_CHAN_TURBO) 499 all_channels[c].c_channel_flags |= CHANNEL_TG; 500 } 501 502 /* Write channel and increment counter */ 503 all_channels[c++].channel = ar5k_2ghz_channels[i].rc_channel; 504 } 505 506 done: 507 bcopy(all_channels, channels, sizeof(HAL_CHANNEL) * max_channels); 508 *channels_size = c; 509 free(all_channels, M_TEMP); 510 return (AH_TRUE); 511 } 512 513 /* 514 * Common internal functions 515 */ 516 517 const char * 518 ar5k_printver(enum ar5k_srev_type type, u_int32_t val) 519 { 520 struct ar5k_srev_name names[] = AR5K_SREV_NAME; 521 const char *name = "xxxx"; 522 int i; 523 524 for (i = 0; i < nitems(names); i++) { 525 if (type == AR5K_VERSION_DEV) { 526 if (names[i].sr_type == type && 527 names[i].sr_val == val) { 528 name = names[i].sr_name; 529 break; 530 } 531 continue; 532 } 533 if (names[i].sr_type != type || 534 names[i].sr_val == AR5K_SREV_UNKNOWN) 535 continue; 536 if ((val & 0xff) < names[i + 1].sr_val) { 537 name = names[i].sr_name; 538 break; 539 } 540 } 541 542 return (name); 543 } 544 545 void 546 ar5k_radar_alert(struct ath_hal *hal) 547 { 548 /* 549 * Limit ~1/s 550 */ 551 if (hal->ah_radar.r_last_channel.channel == 552 hal->ah_current_channel.channel && 553 tick < (hal->ah_radar.r_last_alert + hz)) 554 return; 555 556 hal->ah_radar.r_last_channel.channel = 557 hal->ah_current_channel.channel; 558 hal->ah_radar.r_last_channel.c_channel_flags = 559 hal->ah_current_channel.c_channel_flags; 560 hal->ah_radar.r_last_alert = tick; 561 562 AR5K_PRINTF("Possible radar activity detected at %u MHz (tick %u)\n", 563 hal->ah_radar.r_last_alert, hal->ah_current_channel.channel); 564 } 565 566 u_int16_t 567 ar5k_regdomain_from_ieee(ieee80211_regdomain_t ieee) 568 { 569 u_int32_t regdomain = (u_int32_t)ieee; 570 571 /* 572 * Use the default regulation domain if the value is empty 573 * or not supported by the net80211 regulation code. 574 */ 575 if (ieee80211_regdomain2flag(regdomain, 576 IEEE80211_CHANNELS_5GHZ_MIN) == DMN_DEBUG) 577 return ((u_int16_t)AR5K_TUNE_REGDOMAIN); 578 579 /* It is supported, just return the value */ 580 return (regdomain); 581 } 582 583 ieee80211_regdomain_t 584 ar5k_regdomain_to_ieee(u_int16_t regdomain) 585 { 586 ieee80211_regdomain_t ieee = (ieee80211_regdomain_t)regdomain; 587 588 return (ieee); 589 } 590 591 u_int16_t 592 ar5k_get_regdomain(struct ath_hal *hal) 593 { 594 u_int16_t regdomain; 595 ieee80211_regdomain_t ieee_regdomain; 596 #ifdef COUNTRYCODE 597 u_int16_t code; 598 #endif 599 600 ar5k_eeprom_regulation_domain(hal, AH_FALSE, &ieee_regdomain); 601 hal->ah_capabilities.cap_regdomain.reg_hw = ieee_regdomain; 602 603 #ifdef COUNTRYCODE 604 /* 605 * Get the regulation domain by country code. This will ignore 606 * the settings found in the EEPROM. 607 */ 608 code = ieee80211_name2countrycode(COUNTRYCODE); 609 ieee_regdomain = ieee80211_countrycode2regdomain(code); 610 #endif 611 612 regdomain = ar5k_regdomain_from_ieee(ieee_regdomain); 613 hal->ah_capabilities.cap_regdomain.reg_current = regdomain; 614 615 return (regdomain); 616 } 617 618 u_int32_t 619 ar5k_bitswap(u_int32_t val, u_int bits) 620 { 621 if (bits == 8) { 622 val = ((val & 0xF0) >> 4) | ((val & 0x0F) << 4); 623 val = ((val & 0xCC) >> 2) | ((val & 0x33) << 2); 624 val = ((val & 0xAA) >> 1) | ((val & 0x55) << 1); 625 626 return val; 627 } else { 628 u_int32_t retval = 0, bit, i; 629 630 for (i = 0; i < bits; i++) { 631 bit = (val >> i) & 1; 632 retval = (retval << 1) | bit; 633 } 634 635 return retval; 636 } 637 } 638 639 u_int 640 ar5k_htoclock(u_int usec, HAL_BOOL turbo) 641 { 642 return (turbo == AH_TRUE ? (usec * 80) : (usec * 40)); 643 } 644 645 u_int 646 ar5k_clocktoh(u_int clock, HAL_BOOL turbo) 647 { 648 return (turbo == AH_TRUE ? (clock / 80) : (clock / 40)); 649 } 650 651 void 652 ar5k_rt_copy(HAL_RATE_TABLE *dst, const HAL_RATE_TABLE *src) 653 { 654 bzero(dst, sizeof(HAL_RATE_TABLE)); 655 dst->rateCount = src->rateCount; 656 bcopy(src->info, dst->info, sizeof(dst->info)); 657 } 658 659 HAL_BOOL 660 ar5k_register_timeout(struct ath_hal *hal, u_int32_t reg, u_int32_t flag, 661 u_int32_t val, HAL_BOOL is_set) 662 { 663 int i; 664 u_int32_t data; 665 666 for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) { 667 data = AR5K_REG_READ(reg); 668 if ((is_set == AH_TRUE) && (data & flag)) 669 break; 670 else if ((data & flag) == val) 671 break; 672 AR5K_DELAY(15); 673 } 674 675 if (i <= 0) 676 return (AH_FALSE); 677 678 return (AH_TRUE); 679 } 680 681 /* 682 * Common ar5xx EEPROM access functions 683 */ 684 685 u_int16_t 686 ar5k_eeprom_bin2freq(struct ath_hal *hal, u_int16_t bin, u_int mode) 687 { 688 u_int16_t val; 689 690 if (bin == AR5K_EEPROM_CHANNEL_DIS) 691 return (bin); 692 693 if (mode == AR5K_EEPROM_MODE_11A) { 694 if (hal->ah_ee_version > AR5K_EEPROM_VERSION_3_2) 695 val = (5 * bin) + 4800; 696 else 697 val = bin > 62 ? 698 (10 * 62) + (5 * (bin - 62)) + 5100 : 699 (bin * 10) + 5100; 700 } else { 701 if (hal->ah_ee_version > AR5K_EEPROM_VERSION_3_2) 702 val = bin + 2300; 703 else 704 val = bin + 2400; 705 } 706 707 return (val); 708 } 709 710 int 711 ar5k_eeprom_read_ants(struct ath_hal *hal, u_int32_t *offset, u_int mode) 712 { 713 struct ar5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; 714 u_int32_t o = *offset; 715 u_int16_t val; 716 int ret, i = 0; 717 718 AR5K_EEPROM_READ(o++, val); 719 ee->ee_switch_settling[mode] = (val >> 8) & 0x7f; 720 ee->ee_ant_tx_rx[mode] = (val >> 2) & 0x3f; 721 ee->ee_ant_control[mode][i] = (val << 4) & 0x3f; 722 723 AR5K_EEPROM_READ(o++, val); 724 ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf; 725 ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f; 726 ee->ee_ant_control[mode][i++] = val & 0x3f; 727 728 AR5K_EEPROM_READ(o++, val); 729 ee->ee_ant_control[mode][i++] = (val >> 10) & 0x3f; 730 ee->ee_ant_control[mode][i++] = (val >> 4) & 0x3f; 731 ee->ee_ant_control[mode][i] = (val << 2) & 0x3f; 732 733 AR5K_EEPROM_READ(o++, val); 734 ee->ee_ant_control[mode][i++] |= (val >> 14) & 0x3; 735 ee->ee_ant_control[mode][i++] = (val >> 8) & 0x3f; 736 ee->ee_ant_control[mode][i++] = (val >> 2) & 0x3f; 737 ee->ee_ant_control[mode][i] = (val << 4) & 0x3f; 738 739 AR5K_EEPROM_READ(o++, val); 740 ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf; 741 ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f; 742 ee->ee_ant_control[mode][i++] = val & 0x3f; 743 744 /* Get antenna modes */ 745 hal->ah_antenna[mode][0] = 746 (ee->ee_ant_control[mode][0] << 4) | 0x1; 747 hal->ah_antenna[mode][HAL_ANT_FIXED_A] = 748 ee->ee_ant_control[mode][1] | 749 (ee->ee_ant_control[mode][2] << 6) | 750 (ee->ee_ant_control[mode][3] << 12) | 751 (ee->ee_ant_control[mode][4] << 18) | 752 (ee->ee_ant_control[mode][5] << 24); 753 hal->ah_antenna[mode][HAL_ANT_FIXED_B] = 754 ee->ee_ant_control[mode][6] | 755 (ee->ee_ant_control[mode][7] << 6) | 756 (ee->ee_ant_control[mode][8] << 12) | 757 (ee->ee_ant_control[mode][9] << 18) | 758 (ee->ee_ant_control[mode][10] << 24); 759 760 /* return new offset */ 761 *offset = o; 762 763 return (0); 764 } 765 766 int 767 ar5k_eeprom_read_modes(struct ath_hal *hal, u_int32_t *offset, u_int mode) 768 { 769 struct ar5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; 770 u_int32_t o = *offset; 771 u_int16_t val; 772 int ret; 773 774 AR5K_EEPROM_READ(o++, val); 775 ee->ee_tx_end2xlna_enable[mode] = (val >> 8) & 0xff; 776 ee->ee_thr_62[mode] = val & 0xff; 777 778 if (hal->ah_ee_version <= AR5K_EEPROM_VERSION_3_2) 779 ee->ee_thr_62[mode] = 780 mode == AR5K_EEPROM_MODE_11A ? 15 : 28; 781 782 AR5K_EEPROM_READ(o++, val); 783 ee->ee_tx_end2xpa_disable[mode] = (val >> 8) & 0xff; 784 ee->ee_tx_frm2xpa_enable[mode] = val & 0xff; 785 786 AR5K_EEPROM_READ(o++, val); 787 ee->ee_pga_desired_size[mode] = (val >> 8) & 0xff; 788 789 if ((val & 0xff) & 0x80) 790 ee->ee_noise_floor_thr[mode] = -((((val & 0xff) ^ 0xff)) + 1); 791 else 792 ee->ee_noise_floor_thr[mode] = val & 0xff; 793 794 if (hal->ah_ee_version <= AR5K_EEPROM_VERSION_3_2) 795 ee->ee_noise_floor_thr[mode] = 796 mode == AR5K_EEPROM_MODE_11A ? -54 : -1; 797 798 AR5K_EEPROM_READ(o++, val); 799 ee->ee_xlna_gain[mode] = (val >> 5) & 0xff; 800 ee->ee_x_gain[mode] = (val >> 1) & 0xf; 801 ee->ee_xpd[mode] = val & 0x1; 802 803 if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) 804 ee->ee_fixed_bias[mode] = (val >> 13) & 0x1; 805 806 if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_3_3) { 807 AR5K_EEPROM_READ(o++, val); 808 ee->ee_false_detect[mode] = (val >> 6) & 0x7f; 809 810 if (mode == AR5K_EEPROM_MODE_11A) 811 ee->ee_xr_power[mode] = val & 0x3f; 812 else { 813 ee->ee_ob[mode][0] = val & 0x7; 814 ee->ee_db[mode][0] = (val >> 3) & 0x7; 815 } 816 } 817 818 if (hal->ah_ee_version < AR5K_EEPROM_VERSION_3_4) { 819 ee->ee_i_gain[mode] = AR5K_EEPROM_I_GAIN; 820 ee->ee_cck_ofdm_power_delta = AR5K_EEPROM_CCK_OFDM_DELTA; 821 } else { 822 ee->ee_i_gain[mode] = (val >> 13) & 0x7; 823 824 AR5K_EEPROM_READ(o++, val); 825 ee->ee_i_gain[mode] |= (val << 3) & 0x38; 826 827 if (mode == AR5K_EEPROM_MODE_11G) 828 ee->ee_cck_ofdm_power_delta = (val >> 3) & 0xff; 829 } 830 831 if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0 && 832 mode == AR5K_EEPROM_MODE_11A) { 833 ee->ee_i_cal[mode] = (val >> 8) & 0x3f; 834 ee->ee_q_cal[mode] = (val >> 3) & 0x1f; 835 } 836 837 if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_6 && 838 mode == AR5K_EEPROM_MODE_11G) 839 ee->ee_scaled_cck_delta = (val >> 11) & 0x1f; 840 841 /* return new offset */ 842 *offset = o; 843 844 return (0); 845 } 846 847 int 848 ar5k_eeprom_init(struct ath_hal *hal) 849 { 850 struct ar5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; 851 u_int32_t offset; 852 u_int16_t val; 853 int ret, i; 854 u_int mode; 855 856 /* Initial TX thermal adjustment values */ 857 ee->ee_tx_clip = 4; 858 ee->ee_pwd_84 = ee->ee_pwd_90 = 1; 859 ee->ee_gain_select = 1; 860 861 /* 862 * Read values from EEPROM and store them in the capability structure 863 */ 864 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MAGIC, ee_magic); 865 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_PROTECT, ee_protect); 866 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_REG_DOMAIN, ee_regdomain); 867 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_VERSION, ee_version); 868 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_HDR, ee_header); 869 870 /* Return if we have an old EEPROM */ 871 if (hal->ah_ee_version < AR5K_EEPROM_VERSION_3_0) 872 return (0); 873 874 #ifdef notyet 875 /* 876 * Validate the checksum of the EEPROM date. There are some 877 * devices with invalid EEPROMs. 878 */ 879 for (cksum = 0, offset = 0; offset < AR5K_EEPROM_INFO_MAX; offset++) { 880 AR5K_EEPROM_READ(AR5K_EEPROM_INFO(offset), val); 881 cksum ^= val; 882 } 883 if (cksum != AR5K_EEPROM_INFO_CKSUM) { 884 AR5K_PRINTF("Invalid EEPROM checksum 0x%04x\n", cksum); 885 return (EINVAL); 886 } 887 #endif 888 889 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_ANT_GAIN(hal->ah_ee_version), 890 ee_ant_gain); 891 892 if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) { 893 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC0, ee_misc0); 894 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC1, ee_misc1); 895 } 896 897 if (hal->ah_ee_version < AR5K_EEPROM_VERSION_3_3) { 898 AR5K_EEPROM_READ(AR5K_EEPROM_OBDB0_2GHZ, val); 899 ee->ee_ob[AR5K_EEPROM_MODE_11B][0] = val & 0x7; 900 ee->ee_db[AR5K_EEPROM_MODE_11B][0] = (val >> 3) & 0x7; 901 902 AR5K_EEPROM_READ(AR5K_EEPROM_OBDB1_2GHZ, val); 903 ee->ee_ob[AR5K_EEPROM_MODE_11G][0] = val & 0x7; 904 ee->ee_db[AR5K_EEPROM_MODE_11G][0] = (val >> 3) & 0x7; 905 } 906 907 /* 908 * Get conformance test limit values 909 */ 910 offset = AR5K_EEPROM_CTL(hal->ah_ee_version); 911 ee->ee_ctls = AR5K_EEPROM_N_CTLS(hal->ah_ee_version); 912 913 for (i = 0; i < ee->ee_ctls; i++) { 914 AR5K_EEPROM_READ(offset++, val); 915 ee->ee_ctl[i] = (val >> 8) & 0xff; 916 ee->ee_ctl[i + 1] = val & 0xff; 917 } 918 919 /* 920 * Get values for 802.11a (5GHz) 921 */ 922 mode = AR5K_EEPROM_MODE_11A; 923 924 ee->ee_turbo_max_power[mode] = 925 AR5K_EEPROM_HDR_T_5GHZ_DBM(ee->ee_header); 926 927 offset = AR5K_EEPROM_MODES_11A(hal->ah_ee_version); 928 929 if ((ret = ar5k_eeprom_read_ants(hal, &offset, mode)) != 0) 930 return (ret); 931 932 AR5K_EEPROM_READ(offset++, val); 933 ee->ee_adc_desired_size[mode] = (int8_t)((val >> 8) & 0xff); 934 ee->ee_ob[mode][3] = (val >> 5) & 0x7; 935 ee->ee_db[mode][3] = (val >> 2) & 0x7; 936 ee->ee_ob[mode][2] = (val << 1) & 0x7; 937 938 AR5K_EEPROM_READ(offset++, val); 939 ee->ee_ob[mode][2] |= (val >> 15) & 0x1; 940 ee->ee_db[mode][2] = (val >> 12) & 0x7; 941 ee->ee_ob[mode][1] = (val >> 9) & 0x7; 942 ee->ee_db[mode][1] = (val >> 6) & 0x7; 943 ee->ee_ob[mode][0] = (val >> 3) & 0x7; 944 ee->ee_db[mode][0] = val & 0x7; 945 946 if ((ret = ar5k_eeprom_read_modes(hal, &offset, mode)) != 0) 947 return (ret); 948 949 if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) { 950 AR5K_EEPROM_READ(offset++, val); 951 ee->ee_margin_tx_rx[mode] = val & 0x3f; 952 } 953 954 /* 955 * Get values for 802.11b (2.4GHz) 956 */ 957 mode = AR5K_EEPROM_MODE_11B; 958 offset = AR5K_EEPROM_MODES_11B(hal->ah_ee_version); 959 960 if ((ret = ar5k_eeprom_read_ants(hal, &offset, mode)) != 0) 961 return (ret); 962 963 AR5K_EEPROM_READ(offset++, val); 964 ee->ee_adc_desired_size[mode] = (int8_t)((val >> 8) & 0xff); 965 ee->ee_ob[mode][1] = (val >> 4) & 0x7; 966 ee->ee_db[mode][1] = val & 0x7; 967 968 if ((ret = ar5k_eeprom_read_modes(hal, &offset, mode)) != 0) 969 return (ret); 970 971 if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) { 972 AR5K_EEPROM_READ(offset++, val); 973 ee->ee_cal_pier[mode][0] = 974 ar5k_eeprom_bin2freq(hal, val & 0xff, mode); 975 ee->ee_cal_pier[mode][1] = 976 ar5k_eeprom_bin2freq(hal, (val >> 8) & 0xff, mode); 977 978 AR5K_EEPROM_READ(offset++, val); 979 ee->ee_cal_pier[mode][2] = 980 ar5k_eeprom_bin2freq(hal, val & 0xff, mode); 981 } 982 983 if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) { 984 ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f; 985 } 986 987 /* 988 * Get values for 802.11g (2.4GHz) 989 */ 990 mode = AR5K_EEPROM_MODE_11G; 991 offset = AR5K_EEPROM_MODES_11G(hal->ah_ee_version); 992 993 if ((ret = ar5k_eeprom_read_ants(hal, &offset, mode)) != 0) 994 return (ret); 995 996 AR5K_EEPROM_READ(offset++, val); 997 ee->ee_adc_desired_size[mode] = (int8_t)((val >> 8) & 0xff); 998 ee->ee_ob[mode][1] = (val >> 4) & 0x7; 999 ee->ee_db[mode][1] = val & 0x7; 1000 1001 if ((ret = ar5k_eeprom_read_modes(hal, &offset, mode)) != 0) 1002 return (ret); 1003 1004 if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) { 1005 AR5K_EEPROM_READ(offset++, val); 1006 ee->ee_cal_pier[mode][0] = 1007 ar5k_eeprom_bin2freq(hal, val & 0xff, mode); 1008 ee->ee_cal_pier[mode][1] = 1009 ar5k_eeprom_bin2freq(hal, (val >> 8) & 0xff, mode); 1010 1011 AR5K_EEPROM_READ(offset++, val); 1012 ee->ee_turbo_max_power[mode] = val & 0x7f; 1013 ee->ee_xr_power[mode] = (val >> 7) & 0x3f; 1014 1015 AR5K_EEPROM_READ(offset++, val); 1016 ee->ee_cal_pier[mode][2] = 1017 ar5k_eeprom_bin2freq(hal, val & 0xff, mode); 1018 1019 if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) { 1020 ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f; 1021 } 1022 1023 AR5K_EEPROM_READ(offset++, val); 1024 ee->ee_i_cal[mode] = (val >> 8) & 0x3f; 1025 ee->ee_q_cal[mode] = (val >> 3) & 0x1f; 1026 1027 if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_2) { 1028 AR5K_EEPROM_READ(offset++, val); 1029 ee->ee_cck_ofdm_gain_delta = val & 0xff; 1030 } 1031 } 1032 1033 /* 1034 * Read 5GHz EEPROM channels 1035 */ 1036 1037 return (0); 1038 } 1039 1040 int 1041 ar5k_eeprom_read_mac(struct ath_hal *hal, u_int8_t *mac) 1042 { 1043 u_int32_t total, offset; 1044 u_int16_t data; 1045 int octet; 1046 u_int8_t mac_d[IEEE80211_ADDR_LEN]; 1047 1048 bzero(mac, IEEE80211_ADDR_LEN); 1049 bzero(&mac_d, IEEE80211_ADDR_LEN); 1050 1051 if (hal->ah_eeprom_read(hal, 0x20, &data) != 0) 1052 return (EIO); 1053 1054 for (offset = 0x1f, octet = 0, total = 0; 1055 offset >= 0x1d; offset--) { 1056 if (hal->ah_eeprom_read(hal, offset, &data) != 0) 1057 return (EIO); 1058 1059 total += data; 1060 mac_d[octet + 1] = data & 0xff; 1061 mac_d[octet] = data >> 8; 1062 octet += 2; 1063 } 1064 1065 bcopy(mac_d, mac, IEEE80211_ADDR_LEN); 1066 1067 if ((!total) || total == (3 * 0xffff)) 1068 return (EINVAL); 1069 1070 return (0); 1071 } 1072 1073 HAL_BOOL 1074 ar5k_eeprom_regulation_domain(struct ath_hal *hal, HAL_BOOL write, 1075 ieee80211_regdomain_t *regdomain) 1076 { 1077 u_int16_t ee_regdomain; 1078 1079 /* Read current value */ 1080 if (write != AH_TRUE) { 1081 ee_regdomain = hal->ah_capabilities.cap_eeprom.ee_regdomain; 1082 *regdomain = ar5k_regdomain_to_ieee(ee_regdomain); 1083 return (AH_TRUE); 1084 } 1085 1086 ee_regdomain = ar5k_regdomain_from_ieee(*regdomain); 1087 1088 /* Try to write a new value */ 1089 if (hal->ah_capabilities.cap_eeprom.ee_protect & 1090 AR5K_EEPROM_PROTECT_WR_128_191) 1091 return (AH_FALSE); 1092 if (hal->ah_eeprom_write(hal, AR5K_EEPROM_REG_DOMAIN, 1093 ee_regdomain) != 0) 1094 return (AH_FALSE); 1095 1096 hal->ah_capabilities.cap_eeprom.ee_regdomain = ee_regdomain; 1097 1098 return (AH_TRUE); 1099 } 1100 1101 /* 1102 * PHY/RF access functions 1103 */ 1104 1105 HAL_BOOL 1106 ar5k_channel(struct ath_hal *hal, HAL_CHANNEL *channel) 1107 { 1108 HAL_BOOL ret; 1109 1110 /* 1111 * Check bounds supported by the PHY 1112 * (don't care about regulation restrictions at this point) 1113 */ 1114 if ((channel->channel < hal->ah_capabilities.cap_range.range_2ghz_min || 1115 channel->channel > hal->ah_capabilities.cap_range.range_2ghz_max) && 1116 (channel->channel < hal->ah_capabilities.cap_range.range_5ghz_min || 1117 channel->channel > hal->ah_capabilities.cap_range.range_5ghz_max)) { 1118 AR5K_PRINTF("channel out of supported range (%u MHz)\n", 1119 channel->channel); 1120 return (AH_FALSE); 1121 } 1122 1123 /* 1124 * Set the channel and wait 1125 */ 1126 if (hal->ah_radio == AR5K_AR5110) 1127 ret = ar5k_ar5110_channel(hal, channel); 1128 else if (hal->ah_radio == AR5K_AR5111) 1129 ret = ar5k_ar5111_channel(hal, channel); 1130 else 1131 ret = ar5k_ar5112_channel(hal, channel); 1132 1133 if (ret == AH_FALSE) 1134 return (ret); 1135 1136 hal->ah_current_channel.c_channel = channel->c_channel; 1137 hal->ah_current_channel.c_channel_flags = channel->c_channel_flags; 1138 hal->ah_turbo = channel->c_channel_flags == CHANNEL_T ? 1139 AH_TRUE : AH_FALSE; 1140 1141 return (AH_TRUE); 1142 } 1143 1144 u_int32_t 1145 ar5k_ar5110_chan2athchan(HAL_CHANNEL *channel) 1146 { 1147 u_int32_t athchan; 1148 1149 /* 1150 * Convert IEEE channel/MHz to an internal channel value used 1151 * by the AR5210 chipset. This has not been verified with 1152 * newer chipsets like the AR5212A who have a completely 1153 * different RF/PHY part. 1154 */ 1155 athchan = (ar5k_bitswap((ieee80211_mhz2ieee(channel->c_channel, 1156 channel->c_channel_flags) - 24) / 2, 5) << 1) | 1157 (1 << 6) | 0x1; 1158 1159 return (athchan); 1160 } 1161 1162 HAL_BOOL 1163 ar5k_ar5110_channel(struct ath_hal *hal, HAL_CHANNEL *channel) 1164 { 1165 u_int32_t data; 1166 1167 /* 1168 * Set the channel and wait 1169 */ 1170 data = ar5k_ar5110_chan2athchan(channel); 1171 AR5K_PHY_WRITE(0x27, data); 1172 AR5K_PHY_WRITE(0x30, 0); 1173 AR5K_DELAY(1000); 1174 1175 return (AH_TRUE); 1176 } 1177 1178 HAL_BOOL 1179 ar5k_ar5111_chan2athchan(u_int ieee, struct ar5k_athchan_2ghz *athchan) 1180 { 1181 int channel; 1182 1183 /* Cast this value to catch negative channel numbers (>= -19) */ 1184 channel = (int)ieee; 1185 1186 /* 1187 * Map 2GHz IEEE channel to 5GHz Atheros channel 1188 */ 1189 if (channel <= 13) { 1190 athchan->a2_athchan = 115 + channel; 1191 athchan->a2_flags = 0x46; 1192 } else if (channel == 14) { 1193 athchan->a2_athchan = 124; 1194 athchan->a2_flags = 0x44; 1195 } else if (channel >= 15 && channel <= 26) { 1196 athchan->a2_athchan = ((channel - 14) * 4) + 132; 1197 athchan->a2_flags = 0x46; 1198 } else 1199 return (AH_FALSE); 1200 1201 return (AH_TRUE); 1202 } 1203 1204 HAL_BOOL 1205 ar5k_ar5111_channel(struct ath_hal *hal, HAL_CHANNEL *channel) 1206 { 1207 u_int ieee_channel, ath_channel; 1208 u_int32_t data0, data1, clock; 1209 struct ar5k_athchan_2ghz ath_channel_2ghz; 1210 1211 /* 1212 * Set the channel on the AR5111 radio 1213 */ 1214 data0 = data1 = 0; 1215 ath_channel = ieee_channel = ieee80211_mhz2ieee(channel->c_channel, 1216 channel->c_channel_flags); 1217 1218 if (channel->c_channel_flags & IEEE80211_CHAN_2GHZ) { 1219 /* Map 2GHz channel to 5GHz Atheros channel ID */ 1220 if (ar5k_ar5111_chan2athchan(ieee_channel, 1221 &ath_channel_2ghz) == AH_FALSE) 1222 return (AH_FALSE); 1223 1224 ath_channel = ath_channel_2ghz.a2_athchan; 1225 data0 = ((ar5k_bitswap(ath_channel_2ghz.a2_flags, 8) & 0xff) 1226 << 5) | (1 << 4); 1227 } 1228 1229 if (ath_channel < 145 || !(ath_channel & 1)) { 1230 clock = 1; 1231 data1 = ((ar5k_bitswap(ath_channel - 24, 8) & 0xff) << 2) 1232 | (clock << 1) | (1 << 10) | 1; 1233 } else { 1234 clock = 0; 1235 data1 = ((ar5k_bitswap((ath_channel - 24) / 2, 8) & 0xff) << 2) 1236 | (clock << 1) | (1 << 10) | 1; 1237 } 1238 1239 AR5K_PHY_WRITE(0x27, (data1 & 0xff) | ((data0 & 0xff) << 8)); 1240 AR5K_PHY_WRITE(0x34, ((data1 >> 8) & 0xff) | (data0 & 0xff00)); 1241 1242 return (AH_TRUE); 1243 } 1244 1245 HAL_BOOL 1246 ar5k_ar5112_channel(struct ath_hal *hal, HAL_CHANNEL *channel) 1247 { 1248 u_int32_t data, data0, data1, data2; 1249 u_int16_t c; 1250 1251 data = data0 = data1 = data2 = 0; 1252 c = channel->c_channel + hal->ah_chanoff; 1253 1254 /* 1255 * Set the channel on the AR5112 or newer 1256 */ 1257 if (c < 4800) { 1258 if (!((c - 2224) % 5)) { 1259 data0 = ((2 * (c - 704)) - 3040) / 10; 1260 data1 = 1; 1261 } else if (!((c - 2192) % 5)) { 1262 data0 = ((2 * (c - 672)) - 3040) / 10; 1263 data1 = 0; 1264 } else 1265 return (AH_FALSE); 1266 1267 data0 = ar5k_bitswap((data0 << 2) & 0xff, 8); 1268 } else { 1269 if (!(c % 20) && c >= 5120) { 1270 data0 = ar5k_bitswap(((c - 4800) / 20 << 2), 8); 1271 data2 = ar5k_bitswap(3, 2); 1272 } else if (!(c % 10)) { 1273 data0 = ar5k_bitswap(((c - 4800) / 10 << 1), 8); 1274 data2 = ar5k_bitswap(2, 2); 1275 } else if (!(c % 5)) { 1276 data0 = ar5k_bitswap((c - 4800) / 5, 8); 1277 data2 = ar5k_bitswap(1, 2); 1278 } else 1279 return (AH_FALSE); 1280 } 1281 1282 data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001; 1283 1284 AR5K_PHY_WRITE(0x27, data & 0xff); 1285 AR5K_PHY_WRITE(0x36, (data >> 8) & 0x7f); 1286 1287 return (AH_TRUE); 1288 } 1289 1290 u_int 1291 ar5k_rfregs_op(u_int32_t *rf, u_int32_t offset, u_int32_t reg, u_int32_t bits, 1292 u_int32_t first, u_int32_t col, HAL_BOOL set) 1293 { 1294 u_int32_t mask, entry, last, data, shift, position; 1295 int32_t left; 1296 int i; 1297 1298 if (rf == NULL) { 1299 /* should not happen */ 1300 return (0); 1301 } 1302 1303 if (!(col <= 3 && bits <= 32 && first + bits <= 319)) { 1304 AR5K_PRINTF("invalid values at offset %u\n", offset); 1305 return (0); 1306 } 1307 1308 entry = ((first - 1) / 8) + offset; 1309 position = (first - 1) % 8; 1310 1311 if (set == AH_TRUE) 1312 data = ar5k_bitswap(reg, bits); 1313 1314 for (i = shift = 0, left = bits; left > 0; position = 0, entry++, i++) { 1315 last = (position + left > 8) ? 8 : position + left; 1316 mask = (((1 << last) - 1) ^ ((1 << position) - 1)) << 1317 (col * 8); 1318 1319 if (set == AH_TRUE) { 1320 rf[entry] &= ~mask; 1321 rf[entry] |= ((data << position) << (col * 8)) & mask; 1322 data >>= (8 - position); 1323 } else { 1324 data = (((rf[entry] & mask) >> (col * 8)) >> 1325 position) << shift; 1326 shift += last - position; 1327 } 1328 1329 left -= 8 - position; 1330 } 1331 1332 data = set == AH_TRUE ? 1 : ar5k_bitswap(data, bits); 1333 1334 return (data); 1335 } 1336 1337 u_int32_t 1338 ar5k_rfregs_gainf_corr(struct ath_hal *hal) 1339 { 1340 u_int32_t mix, step; 1341 u_int32_t *rf; 1342 1343 if (hal->ah_rf_banks == NULL) 1344 return (0); 1345 1346 rf = hal->ah_rf_banks; 1347 hal->ah_gain.g_f_corr = 0; 1348 1349 if (ar5k_rfregs_op(rf, hal->ah_offset[7], 0, 1, 36, 0, AH_FALSE) != 1) 1350 return (0); 1351 1352 step = ar5k_rfregs_op(rf, hal->ah_offset[7], 0, 4, 32, 0, AH_FALSE); 1353 mix = hal->ah_gain.g_step->gos_param[0]; 1354 1355 switch (mix) { 1356 case 3: 1357 hal->ah_gain.g_f_corr = step * 2; 1358 break; 1359 case 2: 1360 hal->ah_gain.g_f_corr = (step - 5) * 2; 1361 break; 1362 case 1: 1363 hal->ah_gain.g_f_corr = step; 1364 break; 1365 default: 1366 hal->ah_gain.g_f_corr = 0; 1367 break; 1368 } 1369 1370 return (hal->ah_gain.g_f_corr); 1371 } 1372 1373 HAL_BOOL 1374 ar5k_rfregs_gain_readback(struct ath_hal *hal) 1375 { 1376 u_int32_t step, mix, level[4]; 1377 u_int32_t *rf; 1378 1379 if (hal->ah_rf_banks == NULL) 1380 return (0); 1381 1382 rf = hal->ah_rf_banks; 1383 1384 if (hal->ah_radio == AR5K_AR5111) { 1385 step = ar5k_rfregs_op(rf, hal->ah_offset[7], 1386 0, 6, 37, 0, AH_FALSE); 1387 level[0] = 0; 1388 level[1] = (step == 0x3f) ? 0x32 : step + 4; 1389 level[2] = (step != 0x3f) ? 0x40 : level[0]; 1390 level[3] = level[2] + 0x32; 1391 1392 hal->ah_gain.g_high = level[3] - 1393 (step == 0x3f ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5); 1394 hal->ah_gain.g_low = level[0] + 1395 (step == 0x3f ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0); 1396 } else { 1397 mix = ar5k_rfregs_op(rf, hal->ah_offset[7], 1398 0, 1, 36, 0, AH_FALSE); 1399 level[0] = level[2] = 0; 1400 1401 if (mix == 1) { 1402 level[1] = level[3] = 83; 1403 } else { 1404 level[1] = level[3] = 107; 1405 hal->ah_gain.g_high = 55; 1406 } 1407 } 1408 1409 return ((hal->ah_gain.g_current >= level[0] && 1410 hal->ah_gain.g_current <= level[1]) || 1411 (hal->ah_gain.g_current >= level[2] && 1412 hal->ah_gain.g_current <= level[3])); 1413 } 1414 1415 int32_t 1416 ar5k_rfregs_gain_adjust(struct ath_hal *hal) 1417 { 1418 int ret = 0; 1419 const struct ar5k_gain_opt *go; 1420 1421 go = hal->ah_radio == AR5K_AR5111 ? 1422 &ar5111_gain_opt : &ar5112_gain_opt; 1423 1424 hal->ah_gain.g_step = &go->go_step[hal->ah_gain.g_step_idx]; 1425 1426 if (hal->ah_gain.g_current >= hal->ah_gain.g_high) { 1427 if (hal->ah_gain.g_step_idx == 0) 1428 return (-1); 1429 for (hal->ah_gain.g_target = hal->ah_gain.g_current; 1430 hal->ah_gain.g_target >= hal->ah_gain.g_high && 1431 hal->ah_gain.g_step_idx > 0; 1432 hal->ah_gain.g_step = 1433 &go->go_step[hal->ah_gain.g_step_idx]) { 1434 hal->ah_gain.g_target -= 2 * 1435 (go->go_step[--(hal->ah_gain.g_step_idx)].gos_gain - 1436 hal->ah_gain.g_step->gos_gain); 1437 } 1438 1439 ret = 1; 1440 goto done; 1441 } 1442 1443 if (hal->ah_gain.g_current <= hal->ah_gain.g_low) { 1444 if (hal->ah_gain.g_step_idx == (go->go_steps_count - 1)) 1445 return (-2); 1446 for (hal->ah_gain.g_target = hal->ah_gain.g_current; 1447 hal->ah_gain.g_target <= hal->ah_gain.g_low && 1448 hal->ah_gain.g_step_idx < (go->go_steps_count - 1); 1449 hal->ah_gain.g_step = 1450 &go->go_step[hal->ah_gain.g_step_idx]) { 1451 hal->ah_gain.g_target -= 2 * 1452 (go->go_step[++(hal->ah_gain.g_step_idx)].gos_gain - 1453 hal->ah_gain.g_step->gos_gain); 1454 } 1455 1456 ret = 2; 1457 goto done; 1458 } 1459 1460 done: 1461 #ifdef AR5K_DEBUG 1462 AR5K_PRINTF("ret %d, gain step %u, current gain %u, target gain %u\n", 1463 ret, 1464 hal->ah_gain.g_step_idx, 1465 hal->ah_gain.g_current, 1466 hal->ah_gain.g_target); 1467 #endif 1468 1469 return (ret); 1470 } 1471 1472 HAL_BOOL 1473 ar5k_rfregs(struct ath_hal *hal, HAL_CHANNEL *channel, u_int mode) 1474 { 1475 ar5k_rfgain_t *func = NULL; 1476 HAL_BOOL ret; 1477 1478 switch (hal->ah_radio) { 1479 case AR5K_AR5111: 1480 hal->ah_rf_banks_size = sizeof(ar5111_rf); 1481 func = ar5k_ar5111_rfregs; 1482 break; 1483 case AR5K_AR5112: 1484 if (hal->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) 1485 hal->ah_rf_banks_size = sizeof(ar5112a_rf); 1486 else 1487 hal->ah_rf_banks_size = sizeof(ar5112_rf); 1488 func = ar5k_ar5112_rfregs; 1489 break; 1490 case AR5K_AR5413: 1491 hal->ah_rf_banks_size = sizeof(ar5413_rf); 1492 func = ar5k_arxxxx_rfregs; 1493 break; 1494 case AR5K_AR2413: 1495 hal->ah_rf_banks_size = sizeof(ar2413_rf); 1496 func = ar5k_arxxxx_rfregs; 1497 break; 1498 case AR5K_AR2425: 1499 hal->ah_rf_banks_size = sizeof(ar2425_rf); 1500 func = ar5k_arxxxx_rfregs; 1501 break; 1502 default: 1503 return (AH_FALSE); 1504 } 1505 1506 if (hal->ah_rf_banks == NULL) { 1507 /* XXX do extra checks? */ 1508 if ((hal->ah_rf_banks = malloc(hal->ah_rf_banks_size, 1509 M_DEVBUF, M_NOWAIT | M_ZERO)) == NULL) { 1510 AR5K_PRINT("out of memory\n"); 1511 return (AH_FALSE); 1512 } 1513 } 1514 1515 ret = (func)(hal, channel, mode); 1516 1517 if (ret == AH_TRUE) 1518 hal->ah_rf_gain = HAL_RFGAIN_INACTIVE; 1519 1520 return (ret); 1521 } 1522 1523 HAL_BOOL 1524 ar5k_ar5111_rfregs(struct ath_hal *hal, HAL_CHANNEL *channel, u_int mode) 1525 { 1526 struct ar5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; 1527 const u_int rf_size = nitems(ar5111_rf); 1528 u_int32_t *rf; 1529 int i, obdb = -1, bank = -1; 1530 u_int32_t ee_mode; 1531 1532 AR5K_ASSERT_ENTRY(mode, AR5K_INI_VAL_MAX); 1533 1534 rf = hal->ah_rf_banks; 1535 1536 /* Copy values to modify them */ 1537 for (i = 0; i < rf_size; i++) { 1538 if (ar5111_rf[i].rf_bank >= 1539 AR5K_AR5111_INI_RF_MAX_BANKS) { 1540 AR5K_PRINT("invalid bank\n"); 1541 return (AH_FALSE); 1542 } 1543 1544 if (bank != ar5111_rf[i].rf_bank) { 1545 bank = ar5111_rf[i].rf_bank; 1546 hal->ah_offset[bank] = i; 1547 } 1548 1549 rf[i] = ar5111_rf[i].rf_value[mode]; 1550 } 1551 1552 if (channel->c_channel_flags & IEEE80211_CHAN_2GHZ) { 1553 if ((channel->c_channel_flags & IEEE80211_CHAN_G) == 1554 IEEE80211_CHAN_G) 1555 ee_mode = AR5K_EEPROM_MODE_11G; 1556 else 1557 ee_mode = AR5K_EEPROM_MODE_11B; 1558 obdb = 0; 1559 1560 if (!ar5k_rfregs_op(rf, hal->ah_offset[0], 1561 ee->ee_ob[ee_mode][obdb], 3, 119, 0, AH_TRUE)) 1562 return (AH_FALSE); 1563 1564 if (!ar5k_rfregs_op(rf, hal->ah_offset[0], 1565 ee->ee_ob[ee_mode][obdb], 3, 122, 0, AH_TRUE)) 1566 return (AH_FALSE); 1567 1568 obdb = 1; 1569 } else { 1570 /* For 11a, Turbo and XR */ 1571 ee_mode = AR5K_EEPROM_MODE_11A; 1572 obdb = channel->c_channel >= 5725 ? 3 : 1573 (channel->c_channel >= 5500 ? 2 : 1574 (channel->c_channel >= 5260 ? 1 : 1575 (channel->c_channel > 4000 ? 0 : -1))); 1576 1577 if (!ar5k_rfregs_op(rf, hal->ah_offset[6], 1578 ee->ee_pwd_84, 1, 51, 3, AH_TRUE)) 1579 return (AH_FALSE); 1580 1581 if (!ar5k_rfregs_op(rf, hal->ah_offset[6], 1582 ee->ee_pwd_90, 1, 45, 3, AH_TRUE)) 1583 return (AH_FALSE); 1584 } 1585 1586 if (!ar5k_rfregs_op(rf, hal->ah_offset[6], 1587 !ee->ee_xpd[ee_mode], 1, 95, 0, AH_TRUE)) 1588 return (AH_FALSE); 1589 1590 if (!ar5k_rfregs_op(rf, hal->ah_offset[6], 1591 ee->ee_x_gain[ee_mode], 4, 96, 0, AH_TRUE)) 1592 return (AH_FALSE); 1593 1594 if (!ar5k_rfregs_op(rf, hal->ah_offset[6], 1595 obdb >= 0 ? ee->ee_ob[ee_mode][obdb] : 0, 3, 104, 0, AH_TRUE)) 1596 return (AH_FALSE); 1597 1598 if (!ar5k_rfregs_op(rf, hal->ah_offset[6], 1599 obdb >= 0 ? ee->ee_db[ee_mode][obdb] : 0, 3, 107, 0, AH_TRUE)) 1600 return (AH_FALSE); 1601 1602 if (!ar5k_rfregs_op(rf, hal->ah_offset[7], 1603 ee->ee_i_gain[ee_mode], 6, 29, 0, AH_TRUE)) 1604 return (AH_FALSE); 1605 1606 if (!ar5k_rfregs_op(rf, hal->ah_offset[7], 1607 ee->ee_xpd[ee_mode], 1, 4, 0, AH_TRUE)) 1608 return (AH_FALSE); 1609 1610 /* Write RF values */ 1611 for (i = 0; i < rf_size; i++) { 1612 AR5K_REG_WAIT(i); 1613 AR5K_REG_WRITE(ar5111_rf[i].rf_register, rf[i]); 1614 } 1615 1616 return (AH_TRUE); 1617 } 1618 1619 HAL_BOOL 1620 ar5k_ar5112_rfregs(struct ath_hal *hal, HAL_CHANNEL *channel, u_int mode) 1621 { 1622 struct ar5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; 1623 u_int rf_size; 1624 u_int32_t *rf; 1625 int i, obdb = -1, bank = -1; 1626 u_int32_t ee_mode; 1627 const struct ar5k_ini_rf *rf_ini; 1628 1629 AR5K_ASSERT_ENTRY(mode, AR5K_INI_VAL_MAX); 1630 1631 rf = hal->ah_rf_banks; 1632 1633 if (hal->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) { 1634 rf_ini = ar5112a_rf; 1635 rf_size = nitems(ar5112a_rf); 1636 } else { 1637 rf_ini = ar5112_rf; 1638 rf_size = nitems(ar5112_rf); 1639 } 1640 1641 /* Copy values to modify them */ 1642 for (i = 0; i < rf_size; i++) { 1643 if (rf_ini[i].rf_bank >= 1644 AR5K_AR5112_INI_RF_MAX_BANKS) { 1645 AR5K_PRINT("invalid bank\n"); 1646 return (AH_FALSE); 1647 } 1648 1649 if (bank != rf_ini[i].rf_bank) { 1650 bank = rf_ini[i].rf_bank; 1651 hal->ah_offset[bank] = i; 1652 } 1653 1654 rf[i] = rf_ini[i].rf_value[mode]; 1655 } 1656 1657 if (channel->c_channel_flags & IEEE80211_CHAN_2GHZ) { 1658 if ((channel->c_channel_flags & IEEE80211_CHAN_G) == 1659 IEEE80211_CHAN_G) 1660 ee_mode = AR5K_EEPROM_MODE_11G; 1661 else 1662 ee_mode = AR5K_EEPROM_MODE_11B; 1663 obdb = 0; 1664 1665 if (!ar5k_rfregs_op(rf, hal->ah_offset[6], 1666 ee->ee_ob[ee_mode][obdb], 3, 287, 0, AH_TRUE)) 1667 return (AH_FALSE); 1668 1669 if (!ar5k_rfregs_op(rf, hal->ah_offset[6], 1670 ee->ee_ob[ee_mode][obdb], 3, 290, 0, AH_TRUE)) 1671 return (AH_FALSE); 1672 } else { 1673 /* For 11a, Turbo and XR */ 1674 ee_mode = AR5K_EEPROM_MODE_11A; 1675 obdb = channel->c_channel >= 5725 ? 3 : 1676 (channel->c_channel >= 5500 ? 2 : 1677 (channel->c_channel >= 5260 ? 1 : 1678 (channel->c_channel > 4000 ? 0 : -1))); 1679 1680 /* bogus channel: bad beacon? */ 1681 if (obdb < 0) 1682 return (AH_FALSE); 1683 1684 if (!ar5k_rfregs_op(rf, hal->ah_offset[6], 1685 ee->ee_ob[ee_mode][obdb], 3, 279, 0, AH_TRUE)) 1686 return (AH_FALSE); 1687 1688 if (!ar5k_rfregs_op(rf, hal->ah_offset[6], 1689 ee->ee_ob[ee_mode][obdb], 3, 282, 0, AH_TRUE)) 1690 return (AH_FALSE); 1691 } 1692 1693 #ifdef notyet 1694 ar5k_rfregs_op(rf, hal->ah_offset[6], 1695 ee->ee_x_gain[ee_mode], 2, 270, 0, AH_TRUE); 1696 ar5k_rfregs_op(rf, hal->ah_offset[6], 1697 ee->ee_x_gain[ee_mode], 2, 257, 0, AH_TRUE); 1698 #endif 1699 1700 if (!ar5k_rfregs_op(rf, hal->ah_offset[6], 1701 ee->ee_xpd[ee_mode], 1, 302, 0, AH_TRUE)) 1702 return (AH_FALSE); 1703 1704 if (!ar5k_rfregs_op(rf, hal->ah_offset[7], 1705 ee->ee_i_gain[ee_mode], 6, 14, 0, AH_TRUE)) 1706 return (AH_FALSE); 1707 1708 /* Write RF values */ 1709 for (i = 0; i < rf_size; i++) 1710 AR5K_REG_WRITE(rf_ini[i].rf_register, rf[i]); 1711 1712 return (AH_TRUE); 1713 } 1714 1715 HAL_BOOL 1716 ar5k_arxxxx_rfregs(struct ath_hal *hal, HAL_CHANNEL *channel, u_int mode) 1717 { 1718 const struct ar5k_ini_rf *rf_ini; 1719 u_int rf_size; 1720 u_int32_t *rf; 1721 int i, bank = -1; 1722 1723 AR5K_ASSERT_ENTRY(mode, AR5K_INI_VAL_MAX); 1724 1725 rf = hal->ah_rf_banks; 1726 1727 switch (hal->ah_radio) { 1728 case AR5K_AR5413: 1729 rf_ini = ar5413_rf; 1730 rf_size = nitems(ar5413_rf); 1731 break; 1732 case AR5K_AR2413: 1733 rf_ini = ar2413_rf; 1734 rf_size = nitems(ar2413_rf); 1735 break; 1736 case AR5K_AR2425: 1737 if (mode == AR5K_INI_VAL_11B) 1738 mode = AR5K_INI_VAL_11G; 1739 rf_ini = ar2425_rf; 1740 rf_size = nitems(ar2425_rf); 1741 break; 1742 default: 1743 return (AH_FALSE); 1744 } 1745 1746 /* Copy values to modify them */ 1747 for (i = 0; i < rf_size; i++) { 1748 if (rf_ini[i].rf_bank >= AR5K_MAX_RF_BANKS) { 1749 AR5K_PRINT("invalid bank\n"); 1750 return (AH_FALSE); 1751 } 1752 1753 if (bank != rf_ini[i].rf_bank) { 1754 bank = rf_ini[i].rf_bank; 1755 hal->ah_offset[bank] = i; 1756 } 1757 1758 rf[i] = rf_ini[i].rf_value[mode]; 1759 } 1760 1761 /* Write RF values */ 1762 for (i = 0; i < rf_size; i++) 1763 AR5K_REG_WRITE(rf_ini[i].rf_register, rf[i]); 1764 1765 return (AH_TRUE); 1766 } 1767 1768 HAL_BOOL 1769 ar5k_rfgain(struct ath_hal *hal, u_int freq) 1770 { 1771 const struct ar5k_ini_rfgain *rfg; 1772 size_t rfg_size; 1773 int i; 1774 1775 switch (hal->ah_radio) { 1776 case AR5K_AR5111: 1777 rfg = ar5111_rfg; 1778 rfg_size = nitems(ar5111_rfg); 1779 break; 1780 case AR5K_AR5112: 1781 rfg = ar5112_rfg; 1782 rfg_size = nitems(ar5112_rfg); 1783 break; 1784 case AR5K_AR5413: 1785 rfg = ar5413_rfg; 1786 rfg_size = nitems(ar5413_rfg); 1787 break; 1788 case AR5K_AR2413: 1789 case AR5K_AR2425: 1790 if (freq == AR5K_INI_RFGAIN_5GHZ) 1791 return (AH_FALSE); 1792 rfg = ar2413_rfg; 1793 rfg_size = nitems(ar2413_rfg); 1794 break; 1795 default: 1796 return (AH_FALSE); 1797 } 1798 1799 switch (freq) { 1800 case AR5K_INI_RFGAIN_2GHZ: 1801 case AR5K_INI_RFGAIN_5GHZ: 1802 break; 1803 default: 1804 return (AH_FALSE); 1805 } 1806 1807 for (i = 0; i < rfg_size; i++) { 1808 AR5K_REG_WAIT(i); 1809 AR5K_REG_WRITE((u_int32_t)rfg[i].rfg_register, 1810 rfg[i].rfg_value[freq]); 1811 } 1812 1813 return (AH_TRUE); 1814 } 1815 1816 /* 1817 * Common TX power setup 1818 */ 1819 void 1820 ar5k_txpower_table(struct ath_hal *hal, HAL_CHANNEL *channel, int16_t max_power) 1821 { 1822 u_int16_t txpower, *rates; 1823 int i, min, max, n; 1824 1825 rates = hal->ah_txpower.txp_rates; 1826 1827 txpower = AR5K_TUNE_DEFAULT_TXPOWER * 2; 1828 if (max_power > txpower) { 1829 txpower = max_power > AR5K_TUNE_MAX_TXPOWER ? 1830 AR5K_TUNE_MAX_TXPOWER : max_power; 1831 } 1832 1833 for (i = 0; i < AR5K_MAX_RATES; i++) 1834 rates[i] = txpower; 1835 1836 /* XXX setup target powers by rate */ 1837 1838 hal->ah_txpower.txp_min = rates[7]; 1839 hal->ah_txpower.txp_max = rates[0]; 1840 hal->ah_txpower.txp_ofdm = rates[0]; 1841 1842 /* Calculate the power table */ 1843 n = nitems(hal->ah_txpower.txp_pcdac); 1844 min = AR5K_EEPROM_PCDAC_START; 1845 max = AR5K_EEPROM_PCDAC_STOP; 1846 for (i = 0; i < n; i += AR5K_EEPROM_PCDAC_STEP) 1847 hal->ah_txpower.txp_pcdac[i] = 1848 #ifdef notyet 1849 min + ((i * (max - min)) / n); 1850 #else 1851 min; 1852 #endif 1853 } 1854 1855 void 1856 ar5k_write_ini(struct ath_hal *hal, const struct ar5k_ini *ini, 1857 size_t n, HAL_BOOL change_channel) 1858 { 1859 u_int i; 1860 1861 for (i = 0; i < n; i++) { 1862 if (change_channel == AH_TRUE && 1863 ini[i].ini_register >= AR5K_PCU_MIN && 1864 ini[i].ini_register <= AR5K_PCU_MAX) 1865 continue; 1866 switch (ini[i].ini_mode) { 1867 case AR5K_INI_READ: 1868 /* cleared on read */ 1869 AR5K_REG_READ((u_int32_t)ini[i].ini_register); 1870 break; 1871 case AR5K_INI_WRITE: 1872 AR5K_REG_WAIT(i); 1873 AR5K_REG_WRITE((u_int32_t)ini[i].ini_register, 1874 ini[i].ini_value); 1875 break; 1876 } 1877 } 1878 } 1879 1880 void 1881 ar5k_write_mode(struct ath_hal *hal, const struct ar5k_mode *ini, 1882 size_t n, u_int mode) 1883 { 1884 u_int i; 1885 1886 for (i = 0; i < n; i++) { 1887 AR5K_REG_WAIT(i); 1888 AR5K_REG_WRITE((u_int32_t)ini[i].mode_register, 1889 ini[i].mode_value[mode]); 1890 } 1891 } 1892