1 /* $OpenBSD: ar5xxx.c,v 1.56 2012/01/28 12:45:48 stsp Exp $ */ 2 3 /* 4 * Copyright (c) 2004, 2005, 2006, 2007 Reyk Floeter <reyk@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * HAL interface for Atheros Wireless LAN devices. 21 * (Please have a look at ar5xxx.h for further information) 22 */ 23 24 #include <dev/pci/pcidevs.h> 25 #include <dev/ic/ar5xxx.h> 26 27 extern ar5k_attach_t ar5k_ar5210_attach; 28 extern ar5k_attach_t ar5k_ar5211_attach; 29 extern ar5k_attach_t ar5k_ar5212_attach; 30 31 static const struct { 32 u_int16_t vendor; 33 u_int16_t device; 34 ar5k_attach_t (*attach); 35 } ar5k_known_products[] = { 36 /* 37 * From pcidevs_data.h 38 */ 39 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5210, 40 ar5k_ar5210_attach }, 41 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5210_AP, 42 ar5k_ar5210_attach }, 43 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5210_DEFAULT, 44 ar5k_ar5210_attach }, 45 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5211, 46 ar5k_ar5211_attach }, 47 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5211_DEFAULT, 48 ar5k_ar5211_attach }, 49 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5311, 50 ar5k_ar5211_attach }, 51 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5211_FPGA11B, 52 ar5k_ar5211_attach }, 53 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5211_LEGACY, 54 ar5k_ar5211_attach }, 55 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5212, 56 ar5k_ar5212_attach }, 57 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5212_DEFAULT, 58 ar5k_ar5212_attach }, 59 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5212_FPGA, 60 ar5k_ar5212_attach }, 61 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5212_IBM, 62 ar5k_ar5212_attach }, 63 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR2413, 64 ar5k_ar5212_attach }, 65 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5413, 66 ar5k_ar5212_attach }, 67 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5424, 68 ar5k_ar5212_attach }, 69 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CRDAG675, 70 ar5k_ar5212_attach }, 71 { PCI_VENDOR_3COM2, PCI_PRODUCT_3COM2_3CRPAG175, 72 ar5k_ar5212_attach } 73 }; 74 75 static const HAL_RATE_TABLE ar5k_rt_11a = AR5K_RATES_11A; 76 static const HAL_RATE_TABLE ar5k_rt_11b = AR5K_RATES_11B; 77 static const HAL_RATE_TABLE ar5k_rt_11g = AR5K_RATES_11G; 78 static const HAL_RATE_TABLE ar5k_rt_turbo = AR5K_RATES_TURBO; 79 static const HAL_RATE_TABLE ar5k_rt_xr = AR5K_RATES_XR; 80 81 int ar5k_eeprom_read_ants(struct ath_hal *, u_int32_t *, u_int); 82 int ar5k_eeprom_read_modes(struct ath_hal *, u_int32_t *, u_int); 83 u_int16_t ar5k_eeprom_bin2freq(struct ath_hal *, u_int16_t, u_int); 84 85 HAL_BOOL ar5k_ar5110_channel(struct ath_hal *, HAL_CHANNEL *); 86 u_int32_t ar5k_ar5110_chan2athchan(HAL_CHANNEL *); 87 HAL_BOOL ar5k_ar5111_channel(struct ath_hal *, HAL_CHANNEL *); 88 HAL_BOOL ar5k_ar5111_chan2athchan(u_int, struct ar5k_athchan_2ghz *); 89 HAL_BOOL ar5k_ar5112_channel(struct ath_hal *, HAL_CHANNEL *); 90 HAL_BOOL ar5k_check_channel(struct ath_hal *, u_int16_t, u_int flags); 91 92 HAL_BOOL ar5k_ar5111_rfregs(struct ath_hal *, HAL_CHANNEL *, u_int); 93 HAL_BOOL ar5k_ar5112_rfregs(struct ath_hal *, HAL_CHANNEL *, u_int); 94 HAL_BOOL ar5k_arxxxx_rfregs(struct ath_hal *, HAL_CHANNEL *, u_int); 95 u_int ar5k_rfregs_op(u_int32_t *, u_int32_t, u_int32_t, u_int32_t, 96 u_int32_t, u_int32_t, HAL_BOOL); 97 98 /* 99 * Supported channels 100 */ 101 static const struct 102 ieee80211_regchannel ar5k_5ghz_channels[] = IEEE80211_CHANNELS_5GHZ; 103 static const struct 104 ieee80211_regchannel ar5k_2ghz_channels[] = IEEE80211_CHANNELS_2GHZ; 105 106 /* 107 * Initial gain optimization values 108 */ 109 static const struct ar5k_gain_opt ar5111_gain_opt = AR5K_AR5111_GAIN_OPT; 110 static const struct ar5k_gain_opt ar5112_gain_opt = AR5K_AR5112_GAIN_OPT; 111 112 /* 113 * Initial register for the radio chipsets 114 */ 115 static const struct ar5k_ini_rf ar5111_rf[] = AR5K_AR5111_INI_RF; 116 static const struct ar5k_ini_rf ar5112_rf[] = AR5K_AR5112_INI_RF; 117 static const struct ar5k_ini_rf ar5112a_rf[] = AR5K_AR5112A_INI_RF; 118 static const struct ar5k_ini_rf ar5413_rf[] = AR5K_AR5413_INI_RF; 119 static const struct ar5k_ini_rf ar2413_rf[] = AR5K_AR2413_INI_RF; 120 static const struct ar5k_ini_rf ar2425_rf[] = AR5K_AR2425_INI_RF; 121 static const struct ar5k_ini_rfgain ar5111_rfg[] = AR5K_AR5111_INI_RFGAIN; 122 static const struct ar5k_ini_rfgain ar5112_rfg[] = AR5K_AR5112_INI_RFGAIN; 123 static const struct ar5k_ini_rfgain ar5413_rfg[] = AR5K_AR5413_INI_RFGAIN; 124 static const struct ar5k_ini_rfgain ar2413_rfg[] = AR5K_AR2413_INI_RFGAIN; 125 126 /* 127 * Enable to overwrite the country code (use "00" for debug) 128 */ 129 #if 0 130 #define COUNTRYCODE "00" 131 #endif 132 133 /* 134 * Perform a lookup if the device is supported by the HAL 135 */ 136 const char * 137 ath_hal_probe(u_int16_t vendor, u_int16_t device) 138 { 139 int i; 140 141 /* 142 * Perform a linear search on the table of supported devices 143 */ 144 for (i = 0; i < nitems(ar5k_known_products); i++) { 145 if (vendor == ar5k_known_products[i].vendor && 146 device == ar5k_known_products[i].device) 147 return (""); 148 } 149 150 return (NULL); 151 } 152 153 /* 154 * Fills in the HAL structure and initialises the device 155 */ 156 struct ath_hal * 157 ath_hal_attach(u_int16_t device, void *arg, bus_space_tag_t st, 158 bus_space_handle_t sh, u_int is_pcie, int *status) 159 { 160 struct ath_softc *sc = (struct ath_softc *)arg; 161 struct ath_hal *hal = NULL; 162 ar5k_attach_t *attach = NULL; 163 u_int8_t mac[IEEE80211_ADDR_LEN]; 164 int i; 165 166 *status = EINVAL; 167 168 /* 169 * Call the chipset-dependent attach routine by device id 170 */ 171 for (i = 0; i < nitems(ar5k_known_products); i++) { 172 if (device == ar5k_known_products[i].device && 173 ar5k_known_products[i].attach != NULL) 174 attach = ar5k_known_products[i].attach; 175 } 176 177 if (attach == NULL) { 178 *status = ENXIO; 179 AR5K_PRINTF("device not supported: 0x%04x\n", device); 180 return (NULL); 181 } 182 183 if ((hal = malloc(sizeof(struct ath_hal), 184 M_DEVBUF, M_NOWAIT | M_ZERO)) == NULL) { 185 *status = ENOMEM; 186 AR5K_PRINT("out of memory\n"); 187 return (NULL); 188 } 189 190 hal->ah_sc = sc; 191 hal->ah_st = st; 192 hal->ah_sh = sh; 193 hal->ah_device = device; 194 hal->ah_sub_vendor = 0; /* XXX unknown?! */ 195 196 /* 197 * HAL information 198 */ 199 hal->ah_abi = HAL_ABI_VERSION; 200 hal->ah_op_mode = HAL_M_STA; 201 hal->ah_radar.r_enabled = AR5K_TUNE_RADAR_ALERT; 202 hal->ah_turbo = AH_FALSE; 203 hal->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER; 204 hal->ah_imr = 0; 205 hal->ah_atim_window = 0; 206 hal->ah_aifs = AR5K_TUNE_AIFS; 207 hal->ah_cw_min = AR5K_TUNE_CWMIN; 208 hal->ah_limit_tx_retries = AR5K_INIT_TX_RETRY; 209 hal->ah_software_retry = AH_FALSE; 210 hal->ah_ant_diversity = AR5K_TUNE_ANT_DIVERSITY; 211 hal->ah_pci_express = is_pcie ? AH_TRUE : AH_FALSE; 212 213 switch (device) { 214 case PCI_PRODUCT_ATHEROS_AR2413: 215 case PCI_PRODUCT_ATHEROS_AR5413: 216 case PCI_PRODUCT_ATHEROS_AR5424: 217 /* 218 * Known single chip solutions 219 */ 220 hal->ah_single_chip = AH_TRUE; 221 break; 222 default: 223 /* 224 * Multi chip solutions 225 */ 226 hal->ah_single_chip = AH_FALSE; 227 break; 228 } 229 230 if ((attach)(device, hal, st, sh, status) == NULL) 231 goto failed; 232 233 #ifdef AR5K_DEBUG 234 hal->ah_dump_state(hal); 235 #endif 236 237 /* 238 * Get card capabilities, values, ... 239 */ 240 241 if (ar5k_eeprom_init(hal) != 0) { 242 AR5K_PRINT("unable to init EEPROM\n"); 243 goto failed; 244 } 245 246 /* Get misc capabilities */ 247 if (hal->ah_get_capabilities(hal) != AH_TRUE) { 248 AR5K_PRINTF("unable to get device capabilities: 0x%04x\n", 249 device); 250 goto failed; 251 } 252 253 /* Get MAC address */ 254 if ((*status = ar5k_eeprom_read_mac(hal, mac)) != 0) { 255 AR5K_PRINTF("unable to read address from EEPROM: 0x%04x\n", 256 device); 257 goto failed; 258 } 259 260 hal->ah_set_lladdr(hal, mac); 261 262 /* Get rate tables */ 263 if (hal->ah_capabilities.cap_mode & HAL_MODE_11A) 264 ar5k_rt_copy(&hal->ah_rt_11a, &ar5k_rt_11a); 265 if (hal->ah_capabilities.cap_mode & HAL_MODE_11B) 266 ar5k_rt_copy(&hal->ah_rt_11b, &ar5k_rt_11b); 267 if (hal->ah_capabilities.cap_mode & HAL_MODE_11G) 268 ar5k_rt_copy(&hal->ah_rt_11g, &ar5k_rt_11g); 269 if (hal->ah_capabilities.cap_mode & HAL_MODE_TURBO) 270 ar5k_rt_copy(&hal->ah_rt_turbo, &ar5k_rt_turbo); 271 if (hal->ah_capabilities.cap_mode & HAL_MODE_XR) 272 ar5k_rt_copy(&hal->ah_rt_xr, &ar5k_rt_xr); 273 274 /* Initialize the gain optimization values */ 275 if (hal->ah_radio == AR5K_AR5111) { 276 hal->ah_gain.g_step_idx = ar5111_gain_opt.go_default; 277 hal->ah_gain.g_step = 278 &ar5111_gain_opt.go_step[hal->ah_gain.g_step_idx]; 279 hal->ah_gain.g_low = 20; 280 hal->ah_gain.g_high = 35; 281 hal->ah_gain.g_active = 1; 282 } else if (hal->ah_radio == AR5K_AR5112) { 283 hal->ah_gain.g_step_idx = ar5112_gain_opt.go_default; 284 hal->ah_gain.g_step = 285 &ar5111_gain_opt.go_step[hal->ah_gain.g_step_idx]; 286 hal->ah_gain.g_low = 20; 287 hal->ah_gain.g_high = 85; 288 hal->ah_gain.g_active = 1; 289 } else { 290 /* XXX not needed for newer chipsets? */ 291 } 292 293 *status = HAL_OK; 294 295 return (hal); 296 297 failed: 298 free(hal, M_DEVBUF); 299 return (NULL); 300 } 301 302 u_int16_t 303 ath_hal_computetxtime(struct ath_hal *hal, const HAL_RATE_TABLE *rates, 304 u_int32_t frame_length, u_int16_t rate_index, HAL_BOOL short_preamble) 305 { 306 const HAL_RATE *rate; 307 u_int32_t value; 308 309 AR5K_ASSERT_ENTRY(rate_index, rates->rateCount); 310 311 /* 312 * Get rate by index 313 */ 314 rate = &rates->info[rate_index]; 315 316 /* 317 * Calculate the transmission time by operation (PHY) mode 318 */ 319 switch (rate->phy) { 320 case IEEE80211_T_CCK: 321 /* 322 * CCK / DS mode (802.11b) 323 */ 324 value = AR5K_CCK_TX_TIME(rate->rateKbps, frame_length, 325 (short_preamble && rate->shortPreamble)); 326 break; 327 328 case IEEE80211_T_OFDM: 329 /* 330 * Orthogonal Frequency Division Multiplexing 331 */ 332 if (AR5K_OFDM_NUM_BITS_PER_SYM(rate->rateKbps) == 0) 333 return (0); 334 value = AR5K_OFDM_TX_TIME(rate->rateKbps, frame_length); 335 break; 336 337 case IEEE80211_T_TURBO: 338 /* 339 * Orthogonal Frequency Division Multiplexing 340 * Atheros "Turbo Mode" (doubled rates) 341 */ 342 if (AR5K_TURBO_NUM_BITS_PER_SYM(rate->rateKbps) == 0) 343 return (0); 344 value = AR5K_TURBO_TX_TIME(rate->rateKbps, frame_length); 345 break; 346 347 case IEEE80211_T_XR: 348 /* 349 * Orthogonal Frequency Division Multiplexing 350 * Atheros "eXtended Range" (XR) 351 */ 352 if (AR5K_XR_NUM_BITS_PER_SYM(rate->rateKbps) == 0) 353 return (0); 354 value = AR5K_XR_TX_TIME(rate->rateKbps, frame_length); 355 break; 356 357 default: 358 return (0); 359 } 360 361 return (value); 362 } 363 364 HAL_BOOL 365 ar5k_check_channel(struct ath_hal *hal, u_int16_t freq, u_int flags) 366 { 367 /* Check if the channel is in our supported range */ 368 if (flags & IEEE80211_CHAN_2GHZ) { 369 if ((freq >= hal->ah_capabilities.cap_range.range_2ghz_min) && 370 (freq <= hal->ah_capabilities.cap_range.range_2ghz_max)) 371 return (AH_TRUE); 372 } else if (flags & IEEE80211_CHAN_5GHZ) { 373 if ((freq >= hal->ah_capabilities.cap_range.range_5ghz_min) && 374 (freq <= hal->ah_capabilities.cap_range.range_5ghz_max)) 375 return (AH_TRUE); 376 } 377 378 return (AH_FALSE); 379 } 380 381 HAL_BOOL 382 ath_hal_init_channels(struct ath_hal *hal, HAL_CHANNEL *channels, 383 u_int max_channels, u_int *channels_size, u_int16_t mode, 384 HAL_BOOL outdoor, HAL_BOOL extended) 385 { 386 u_int i, c; 387 u_int32_t domain_current; 388 u_int domain_5ghz, domain_2ghz; 389 HAL_CHANNEL *all_channels; 390 391 if ((all_channels = malloc(sizeof(HAL_CHANNEL) * max_channels, 392 M_TEMP, M_NOWAIT | M_ZERO)) == NULL) 393 return (AH_FALSE); 394 395 i = c = 0; 396 domain_current = hal->ah_regdomain; 397 398 /* 399 * In debugging mode, enable all channels supported by the chipset 400 */ 401 if (domain_current == DMN_DEFAULT) { 402 int min, max, freq; 403 u_int flags; 404 405 min = ieee80211_mhz2ieee(IEEE80211_CHANNELS_2GHZ_MIN, 406 IEEE80211_CHAN_2GHZ); 407 max = ieee80211_mhz2ieee(IEEE80211_CHANNELS_2GHZ_MAX, 408 IEEE80211_CHAN_2GHZ); 409 flags = CHANNEL_B | CHANNEL_TG | 410 (hal->ah_version == AR5K_AR5211 ? 411 CHANNEL_PUREG : CHANNEL_G); 412 413 debugchan: 414 for (i = min; i <= max && c < max_channels; i++) { 415 freq = ieee80211_ieee2mhz(i, flags); 416 if (ar5k_check_channel(hal, freq, flags) == AH_FALSE) 417 continue; 418 all_channels[c].c_channel = freq; 419 all_channels[c++].c_channel_flags = flags; 420 } 421 422 if (flags & IEEE80211_CHAN_2GHZ) { 423 min = ieee80211_mhz2ieee(IEEE80211_CHANNELS_5GHZ_MIN, 424 IEEE80211_CHAN_5GHZ); 425 max = ieee80211_mhz2ieee(IEEE80211_CHANNELS_5GHZ_MAX, 426 IEEE80211_CHAN_5GHZ); 427 flags = CHANNEL_A | CHANNEL_T | CHANNEL_XR; 428 goto debugchan; 429 } 430 431 goto done; 432 } 433 434 domain_5ghz = ieee80211_regdomain2flag(domain_current, 435 IEEE80211_CHANNELS_5GHZ_MIN); 436 domain_2ghz = ieee80211_regdomain2flag(domain_current, 437 IEEE80211_CHANNELS_2GHZ_MIN); 438 439 /* 440 * Create channel list based on chipset capabilities, regulation domain 441 * and mode. 5GHz... 442 */ 443 for (i = 0; (hal->ah_capabilities.cap_range.range_5ghz_max > 0) && 444 (i < nitems(ar5k_5ghz_channels)) && 445 (c < max_channels); i++) { 446 /* Check if channel is supported by the chipset */ 447 if (ar5k_check_channel(hal, 448 ar5k_5ghz_channels[i].rc_channel, 449 IEEE80211_CHAN_5GHZ) == AH_FALSE) 450 continue; 451 452 /* Match regulation domain */ 453 if ((IEEE80211_DMN(ar5k_5ghz_channels[i].rc_domain) & 454 IEEE80211_DMN(domain_5ghz)) == 0) 455 continue; 456 457 /* Match modes */ 458 if (ar5k_5ghz_channels[i].rc_mode & IEEE80211_CHAN_TURBO) { 459 all_channels[c].c_channel_flags = CHANNEL_T; 460 } else if (ar5k_5ghz_channels[i].rc_mode & 461 IEEE80211_CHAN_OFDM) { 462 all_channels[c].c_channel_flags = CHANNEL_A; 463 } else 464 continue; 465 466 /* Write channel and increment counter */ 467 all_channels[c++].channel = ar5k_5ghz_channels[i].rc_channel; 468 } 469 470 /* 471 * ...and 2GHz. 472 */ 473 for (i = 0; (hal->ah_capabilities.cap_range.range_2ghz_max > 0) && 474 (i < nitems(ar5k_2ghz_channels)) && 475 (c < max_channels); i++) { 476 /* Check if channel is supported by the chipset */ 477 if (ar5k_check_channel(hal, 478 ar5k_2ghz_channels[i].rc_channel, 479 IEEE80211_CHAN_2GHZ) == AH_FALSE) 480 continue; 481 482 /* Match regulation domain */ 483 if ((IEEE80211_DMN(ar5k_2ghz_channels[i].rc_domain) & 484 IEEE80211_DMN(domain_2ghz)) == 0) 485 continue; 486 487 /* Match modes */ 488 if ((hal->ah_capabilities.cap_mode & HAL_MODE_11B) && 489 (ar5k_2ghz_channels[i].rc_mode & IEEE80211_CHAN_CCK)) 490 all_channels[c].c_channel_flags = CHANNEL_B; 491 492 if ((hal->ah_capabilities.cap_mode & HAL_MODE_11G) && 493 (ar5k_2ghz_channels[i].rc_mode & IEEE80211_CHAN_OFDM)) { 494 all_channels[c].c_channel_flags |= 495 hal->ah_version == AR5K_AR5211 ? 496 CHANNEL_PUREG : CHANNEL_G; 497 if (ar5k_2ghz_channels[i].rc_mode & 498 IEEE80211_CHAN_TURBO) 499 all_channels[c].c_channel_flags |= CHANNEL_TG; 500 } 501 502 /* Write channel and increment counter */ 503 all_channels[c++].channel = ar5k_2ghz_channels[i].rc_channel; 504 } 505 506 done: 507 bcopy(all_channels, channels, sizeof(HAL_CHANNEL) * max_channels); 508 *channels_size = c; 509 free(all_channels, M_TEMP); 510 return (AH_TRUE); 511 } 512 513 /* 514 * Common internal functions 515 */ 516 517 const char * 518 ar5k_printver(enum ar5k_srev_type type, u_int32_t val) 519 { 520 struct ar5k_srev_name names[] = AR5K_SREV_NAME; 521 const char *name = "xxxx"; 522 int i; 523 524 for (i = 0; i < nitems(names); i++) { 525 if (type == AR5K_VERSION_DEV) { 526 if (names[i].sr_type == type && 527 names[i].sr_val == val) { 528 name = names[i].sr_name; 529 break; 530 } 531 continue; 532 } 533 if (names[i].sr_type != type || 534 names[i].sr_val == AR5K_SREV_UNKNOWN) 535 continue; 536 if ((val & 0xff) < names[i + 1].sr_val) { 537 name = names[i].sr_name; 538 break; 539 } 540 } 541 542 return (name); 543 } 544 545 void 546 ar5k_radar_alert(struct ath_hal *hal) 547 { 548 /* 549 * Limit ~1/s 550 */ 551 if (hal->ah_radar.r_last_channel.channel == 552 hal->ah_current_channel.channel && 553 tick < (hal->ah_radar.r_last_alert + hz)) 554 return; 555 556 hal->ah_radar.r_last_channel.channel = 557 hal->ah_current_channel.channel; 558 hal->ah_radar.r_last_channel.c_channel_flags = 559 hal->ah_current_channel.c_channel_flags; 560 hal->ah_radar.r_last_alert = tick; 561 562 AR5K_PRINTF("Possible radar activity detected at %u MHz (tick %u)\n", 563 hal->ah_radar.r_last_alert, hal->ah_current_channel.channel); 564 } 565 566 u_int16_t 567 ar5k_regdomain_from_ieee(ieee80211_regdomain_t ieee) 568 { 569 u_int32_t regdomain = (u_int32_t)ieee; 570 571 /* 572 * Use the default regulation domain if the value is empty 573 * or not supported by the net80211 regulation code. 574 */ 575 if (ieee80211_regdomain2flag(regdomain, 576 IEEE80211_CHANNELS_5GHZ_MIN) == DMN_DEBUG) 577 return ((u_int16_t)AR5K_TUNE_REGDOMAIN); 578 579 /* It is supported, just return the value */ 580 return (regdomain); 581 } 582 583 ieee80211_regdomain_t 584 ar5k_regdomain_to_ieee(u_int16_t regdomain) 585 { 586 ieee80211_regdomain_t ieee = (ieee80211_regdomain_t)regdomain; 587 588 return (ieee); 589 } 590 591 u_int16_t 592 ar5k_get_regdomain(struct ath_hal *hal) 593 { 594 u_int16_t regdomain; 595 ieee80211_regdomain_t ieee_regdomain; 596 #ifdef COUNTRYCODE 597 u_int16_t code; 598 #endif 599 600 ar5k_eeprom_regulation_domain(hal, AH_FALSE, &ieee_regdomain); 601 hal->ah_capabilities.cap_regdomain.reg_hw = ieee_regdomain; 602 603 #ifdef COUNTRYCODE 604 /* 605 * Get the regulation domain by country code. This will ignore 606 * the settings found in the EEPROM. 607 */ 608 code = ieee80211_name2countrycode(COUNTRYCODE); 609 ieee_regdomain = ieee80211_countrycode2regdomain(code); 610 #endif 611 612 regdomain = ar5k_regdomain_from_ieee(ieee_regdomain); 613 hal->ah_capabilities.cap_regdomain.reg_current = regdomain; 614 615 return (regdomain); 616 } 617 618 u_int32_t 619 ar5k_bitswap(u_int32_t val, u_int bits) 620 { 621 if (bits == 8) { 622 val = ((val & 0xF0) >> 4) | ((val & 0x0F) << 4); 623 val = ((val & 0xCC) >> 2) | ((val & 0x33) << 2); 624 val = ((val & 0xAA) >> 1) | ((val & 0x55) << 1); 625 626 return val; 627 } else { 628 u_int32_t retval = 0, bit, i; 629 630 for (i = 0; i < bits; i++) { 631 bit = (val >> i) & 1; 632 retval = (retval << 1) | bit; 633 } 634 635 return retval; 636 } 637 } 638 639 u_int 640 ar5k_htoclock(u_int usec, HAL_BOOL turbo) 641 { 642 return (turbo == AH_TRUE ? (usec * 80) : (usec * 40)); 643 } 644 645 u_int 646 ar5k_clocktoh(u_int clock, HAL_BOOL turbo) 647 { 648 return (turbo == AH_TRUE ? (clock / 80) : (clock / 40)); 649 } 650 651 void 652 ar5k_rt_copy(HAL_RATE_TABLE *dst, const HAL_RATE_TABLE *src) 653 { 654 bzero(dst, sizeof(HAL_RATE_TABLE)); 655 dst->rateCount = src->rateCount; 656 bcopy(src->rateCodeToIndex, dst->rateCodeToIndex, 657 sizeof(dst->rateCodeToIndex)); 658 bcopy(src->info, dst->info, sizeof(dst->info)); 659 } 660 661 HAL_BOOL 662 ar5k_register_timeout(struct ath_hal *hal, u_int32_t reg, u_int32_t flag, 663 u_int32_t val, HAL_BOOL is_set) 664 { 665 int i; 666 u_int32_t data; 667 668 for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) { 669 data = AR5K_REG_READ(reg); 670 if ((is_set == AH_TRUE) && (data & flag)) 671 break; 672 else if ((data & flag) == val) 673 break; 674 AR5K_DELAY(15); 675 } 676 677 if (i <= 0) 678 return (AH_FALSE); 679 680 return (AH_TRUE); 681 } 682 683 /* 684 * Common ar5xx EEPROM access functions 685 */ 686 687 u_int16_t 688 ar5k_eeprom_bin2freq(struct ath_hal *hal, u_int16_t bin, u_int mode) 689 { 690 u_int16_t val; 691 692 if (bin == AR5K_EEPROM_CHANNEL_DIS) 693 return (bin); 694 695 if (mode == AR5K_EEPROM_MODE_11A) { 696 if (hal->ah_ee_version > AR5K_EEPROM_VERSION_3_2) 697 val = (5 * bin) + 4800; 698 else 699 val = bin > 62 ? 700 (10 * 62) + (5 * (bin - 62)) + 5100 : 701 (bin * 10) + 5100; 702 } else { 703 if (hal->ah_ee_version > AR5K_EEPROM_VERSION_3_2) 704 val = bin + 2300; 705 else 706 val = bin + 2400; 707 } 708 709 return (val); 710 } 711 712 int 713 ar5k_eeprom_read_ants(struct ath_hal *hal, u_int32_t *offset, u_int mode) 714 { 715 struct ar5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; 716 u_int32_t o = *offset; 717 u_int16_t val; 718 int ret, i = 0; 719 720 AR5K_EEPROM_READ(o++, val); 721 ee->ee_switch_settling[mode] = (val >> 8) & 0x7f; 722 ee->ee_ant_tx_rx[mode] = (val >> 2) & 0x3f; 723 ee->ee_ant_control[mode][i] = (val << 4) & 0x3f; 724 725 AR5K_EEPROM_READ(o++, val); 726 ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf; 727 ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f; 728 ee->ee_ant_control[mode][i++] = val & 0x3f; 729 730 AR5K_EEPROM_READ(o++, val); 731 ee->ee_ant_control[mode][i++] = (val >> 10) & 0x3f; 732 ee->ee_ant_control[mode][i++] = (val >> 4) & 0x3f; 733 ee->ee_ant_control[mode][i] = (val << 2) & 0x3f; 734 735 AR5K_EEPROM_READ(o++, val); 736 ee->ee_ant_control[mode][i++] |= (val >> 14) & 0x3; 737 ee->ee_ant_control[mode][i++] = (val >> 8) & 0x3f; 738 ee->ee_ant_control[mode][i++] = (val >> 2) & 0x3f; 739 ee->ee_ant_control[mode][i] = (val << 4) & 0x3f; 740 741 AR5K_EEPROM_READ(o++, val); 742 ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf; 743 ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f; 744 ee->ee_ant_control[mode][i++] = val & 0x3f; 745 746 /* Get antenna modes */ 747 hal->ah_antenna[mode][0] = 748 (ee->ee_ant_control[mode][0] << 4) | 0x1; 749 hal->ah_antenna[mode][HAL_ANT_FIXED_A] = 750 ee->ee_ant_control[mode][1] | 751 (ee->ee_ant_control[mode][2] << 6) | 752 (ee->ee_ant_control[mode][3] << 12) | 753 (ee->ee_ant_control[mode][4] << 18) | 754 (ee->ee_ant_control[mode][5] << 24); 755 hal->ah_antenna[mode][HAL_ANT_FIXED_B] = 756 ee->ee_ant_control[mode][6] | 757 (ee->ee_ant_control[mode][7] << 6) | 758 (ee->ee_ant_control[mode][8] << 12) | 759 (ee->ee_ant_control[mode][9] << 18) | 760 (ee->ee_ant_control[mode][10] << 24); 761 762 /* return new offset */ 763 *offset = o; 764 765 return (0); 766 } 767 768 int 769 ar5k_eeprom_read_modes(struct ath_hal *hal, u_int32_t *offset, u_int mode) 770 { 771 struct ar5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; 772 u_int32_t o = *offset; 773 u_int16_t val; 774 int ret; 775 776 AR5K_EEPROM_READ(o++, val); 777 ee->ee_tx_end2xlna_enable[mode] = (val >> 8) & 0xff; 778 ee->ee_thr_62[mode] = val & 0xff; 779 780 if (hal->ah_ee_version <= AR5K_EEPROM_VERSION_3_2) 781 ee->ee_thr_62[mode] = 782 mode == AR5K_EEPROM_MODE_11A ? 15 : 28; 783 784 AR5K_EEPROM_READ(o++, val); 785 ee->ee_tx_end2xpa_disable[mode] = (val >> 8) & 0xff; 786 ee->ee_tx_frm2xpa_enable[mode] = val & 0xff; 787 788 AR5K_EEPROM_READ(o++, val); 789 ee->ee_pga_desired_size[mode] = (val >> 8) & 0xff; 790 791 if ((val & 0xff) & 0x80) 792 ee->ee_noise_floor_thr[mode] = -((((val & 0xff) ^ 0xff)) + 1); 793 else 794 ee->ee_noise_floor_thr[mode] = val & 0xff; 795 796 if (hal->ah_ee_version <= AR5K_EEPROM_VERSION_3_2) 797 ee->ee_noise_floor_thr[mode] = 798 mode == AR5K_EEPROM_MODE_11A ? -54 : -1; 799 800 AR5K_EEPROM_READ(o++, val); 801 ee->ee_xlna_gain[mode] = (val >> 5) & 0xff; 802 ee->ee_x_gain[mode] = (val >> 1) & 0xf; 803 ee->ee_xpd[mode] = val & 0x1; 804 805 if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) 806 ee->ee_fixed_bias[mode] = (val >> 13) & 0x1; 807 808 if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_3_3) { 809 AR5K_EEPROM_READ(o++, val); 810 ee->ee_false_detect[mode] = (val >> 6) & 0x7f; 811 812 if (mode == AR5K_EEPROM_MODE_11A) 813 ee->ee_xr_power[mode] = val & 0x3f; 814 else { 815 ee->ee_ob[mode][0] = val & 0x7; 816 ee->ee_db[mode][0] = (val >> 3) & 0x7; 817 } 818 } 819 820 if (hal->ah_ee_version < AR5K_EEPROM_VERSION_3_4) { 821 ee->ee_i_gain[mode] = AR5K_EEPROM_I_GAIN; 822 ee->ee_cck_ofdm_power_delta = AR5K_EEPROM_CCK_OFDM_DELTA; 823 } else { 824 ee->ee_i_gain[mode] = (val >> 13) & 0x7; 825 826 AR5K_EEPROM_READ(o++, val); 827 ee->ee_i_gain[mode] |= (val << 3) & 0x38; 828 829 if (mode == AR5K_EEPROM_MODE_11G) 830 ee->ee_cck_ofdm_power_delta = (val >> 3) & 0xff; 831 } 832 833 if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0 && 834 mode == AR5K_EEPROM_MODE_11A) { 835 ee->ee_i_cal[mode] = (val >> 8) & 0x3f; 836 ee->ee_q_cal[mode] = (val >> 3) & 0x1f; 837 } 838 839 if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_6 && 840 mode == AR5K_EEPROM_MODE_11G) 841 ee->ee_scaled_cck_delta = (val >> 11) & 0x1f; 842 843 /* return new offset */ 844 *offset = o; 845 846 return (0); 847 } 848 849 int 850 ar5k_eeprom_init(struct ath_hal *hal) 851 { 852 struct ar5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; 853 u_int32_t offset; 854 u_int16_t val; 855 int ret, i; 856 u_int mode; 857 858 /* Initial TX thermal adjustment values */ 859 ee->ee_tx_clip = 4; 860 ee->ee_pwd_84 = ee->ee_pwd_90 = 1; 861 ee->ee_gain_select = 1; 862 863 /* 864 * Read values from EEPROM and store them in the capability structure 865 */ 866 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MAGIC, ee_magic); 867 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_PROTECT, ee_protect); 868 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_REG_DOMAIN, ee_regdomain); 869 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_VERSION, ee_version); 870 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_HDR, ee_header); 871 872 /* Return if we have an old EEPROM */ 873 if (hal->ah_ee_version < AR5K_EEPROM_VERSION_3_0) 874 return (0); 875 876 #ifdef notyet 877 /* 878 * Validate the checksum of the EEPROM date. There are some 879 * devices with invalid EEPROMs. 880 */ 881 for (cksum = 0, offset = 0; offset < AR5K_EEPROM_INFO_MAX; offset++) { 882 AR5K_EEPROM_READ(AR5K_EEPROM_INFO(offset), val); 883 cksum ^= val; 884 } 885 if (cksum != AR5K_EEPROM_INFO_CKSUM) { 886 AR5K_PRINTF("Invalid EEPROM checksum 0x%04x\n", cksum); 887 return (EINVAL); 888 } 889 #endif 890 891 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_ANT_GAIN(hal->ah_ee_version), 892 ee_ant_gain); 893 894 if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) { 895 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC0, ee_misc0); 896 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC1, ee_misc1); 897 } 898 899 if (hal->ah_ee_version < AR5K_EEPROM_VERSION_3_3) { 900 AR5K_EEPROM_READ(AR5K_EEPROM_OBDB0_2GHZ, val); 901 ee->ee_ob[AR5K_EEPROM_MODE_11B][0] = val & 0x7; 902 ee->ee_db[AR5K_EEPROM_MODE_11B][0] = (val >> 3) & 0x7; 903 904 AR5K_EEPROM_READ(AR5K_EEPROM_OBDB1_2GHZ, val); 905 ee->ee_ob[AR5K_EEPROM_MODE_11G][0] = val & 0x7; 906 ee->ee_db[AR5K_EEPROM_MODE_11G][0] = (val >> 3) & 0x7; 907 } 908 909 /* 910 * Get conformance test limit values 911 */ 912 offset = AR5K_EEPROM_CTL(hal->ah_ee_version); 913 ee->ee_ctls = AR5K_EEPROM_N_CTLS(hal->ah_ee_version); 914 915 for (i = 0; i < ee->ee_ctls; i++) { 916 AR5K_EEPROM_READ(offset++, val); 917 ee->ee_ctl[i] = (val >> 8) & 0xff; 918 ee->ee_ctl[i + 1] = val & 0xff; 919 } 920 921 /* 922 * Get values for 802.11a (5GHz) 923 */ 924 mode = AR5K_EEPROM_MODE_11A; 925 926 ee->ee_turbo_max_power[mode] = 927 AR5K_EEPROM_HDR_T_5GHZ_DBM(ee->ee_header); 928 929 offset = AR5K_EEPROM_MODES_11A(hal->ah_ee_version); 930 931 if ((ret = ar5k_eeprom_read_ants(hal, &offset, mode)) != 0) 932 return (ret); 933 934 AR5K_EEPROM_READ(offset++, val); 935 ee->ee_adc_desired_size[mode] = (int8_t)((val >> 8) & 0xff); 936 ee->ee_ob[mode][3] = (val >> 5) & 0x7; 937 ee->ee_db[mode][3] = (val >> 2) & 0x7; 938 ee->ee_ob[mode][2] = (val << 1) & 0x7; 939 940 AR5K_EEPROM_READ(offset++, val); 941 ee->ee_ob[mode][2] |= (val >> 15) & 0x1; 942 ee->ee_db[mode][2] = (val >> 12) & 0x7; 943 ee->ee_ob[mode][1] = (val >> 9) & 0x7; 944 ee->ee_db[mode][1] = (val >> 6) & 0x7; 945 ee->ee_ob[mode][0] = (val >> 3) & 0x7; 946 ee->ee_db[mode][0] = val & 0x7; 947 948 if ((ret = ar5k_eeprom_read_modes(hal, &offset, mode)) != 0) 949 return (ret); 950 951 if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) { 952 AR5K_EEPROM_READ(offset++, val); 953 ee->ee_margin_tx_rx[mode] = val & 0x3f; 954 } 955 956 /* 957 * Get values for 802.11b (2.4GHz) 958 */ 959 mode = AR5K_EEPROM_MODE_11B; 960 offset = AR5K_EEPROM_MODES_11B(hal->ah_ee_version); 961 962 if ((ret = ar5k_eeprom_read_ants(hal, &offset, mode)) != 0) 963 return (ret); 964 965 AR5K_EEPROM_READ(offset++, val); 966 ee->ee_adc_desired_size[mode] = (int8_t)((val >> 8) & 0xff); 967 ee->ee_ob[mode][1] = (val >> 4) & 0x7; 968 ee->ee_db[mode][1] = val & 0x7; 969 970 if ((ret = ar5k_eeprom_read_modes(hal, &offset, mode)) != 0) 971 return (ret); 972 973 if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) { 974 AR5K_EEPROM_READ(offset++, val); 975 ee->ee_cal_pier[mode][0] = 976 ar5k_eeprom_bin2freq(hal, val & 0xff, mode); 977 ee->ee_cal_pier[mode][1] = 978 ar5k_eeprom_bin2freq(hal, (val >> 8) & 0xff, mode); 979 980 AR5K_EEPROM_READ(offset++, val); 981 ee->ee_cal_pier[mode][2] = 982 ar5k_eeprom_bin2freq(hal, val & 0xff, mode); 983 } 984 985 if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) { 986 ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f; 987 } 988 989 /* 990 * Get values for 802.11g (2.4GHz) 991 */ 992 mode = AR5K_EEPROM_MODE_11G; 993 offset = AR5K_EEPROM_MODES_11G(hal->ah_ee_version); 994 995 if ((ret = ar5k_eeprom_read_ants(hal, &offset, mode)) != 0) 996 return (ret); 997 998 AR5K_EEPROM_READ(offset++, val); 999 ee->ee_adc_desired_size[mode] = (int8_t)((val >> 8) & 0xff); 1000 ee->ee_ob[mode][1] = (val >> 4) & 0x7; 1001 ee->ee_db[mode][1] = val & 0x7; 1002 1003 if ((ret = ar5k_eeprom_read_modes(hal, &offset, mode)) != 0) 1004 return (ret); 1005 1006 if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) { 1007 AR5K_EEPROM_READ(offset++, val); 1008 ee->ee_cal_pier[mode][0] = 1009 ar5k_eeprom_bin2freq(hal, val & 0xff, mode); 1010 ee->ee_cal_pier[mode][1] = 1011 ar5k_eeprom_bin2freq(hal, (val >> 8) & 0xff, mode); 1012 1013 AR5K_EEPROM_READ(offset++, val); 1014 ee->ee_turbo_max_power[mode] = val & 0x7f; 1015 ee->ee_xr_power[mode] = (val >> 7) & 0x3f; 1016 1017 AR5K_EEPROM_READ(offset++, val); 1018 ee->ee_cal_pier[mode][2] = 1019 ar5k_eeprom_bin2freq(hal, val & 0xff, mode); 1020 1021 if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) { 1022 ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f; 1023 } 1024 1025 AR5K_EEPROM_READ(offset++, val); 1026 ee->ee_i_cal[mode] = (val >> 8) & 0x3f; 1027 ee->ee_q_cal[mode] = (val >> 3) & 0x1f; 1028 1029 if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_2) { 1030 AR5K_EEPROM_READ(offset++, val); 1031 ee->ee_cck_ofdm_gain_delta = val & 0xff; 1032 } 1033 } 1034 1035 /* 1036 * Read 5GHz EEPROM channels 1037 */ 1038 1039 return (0); 1040 } 1041 1042 int 1043 ar5k_eeprom_read_mac(struct ath_hal *hal, u_int8_t *mac) 1044 { 1045 u_int32_t total, offset; 1046 u_int16_t data; 1047 int octet; 1048 u_int8_t mac_d[IEEE80211_ADDR_LEN]; 1049 1050 bzero(mac, IEEE80211_ADDR_LEN); 1051 bzero(&mac_d, IEEE80211_ADDR_LEN); 1052 1053 if (hal->ah_eeprom_read(hal, 0x20, &data) != 0) 1054 return (EIO); 1055 1056 for (offset = 0x1f, octet = 0, total = 0; 1057 offset >= 0x1d; offset--) { 1058 if (hal->ah_eeprom_read(hal, offset, &data) != 0) 1059 return (EIO); 1060 1061 total += data; 1062 mac_d[octet + 1] = data & 0xff; 1063 mac_d[octet] = data >> 8; 1064 octet += 2; 1065 } 1066 1067 bcopy(mac_d, mac, IEEE80211_ADDR_LEN); 1068 1069 if ((!total) || total == (3 * 0xffff)) 1070 return (EINVAL); 1071 1072 return (0); 1073 } 1074 1075 HAL_BOOL 1076 ar5k_eeprom_regulation_domain(struct ath_hal *hal, HAL_BOOL write, 1077 ieee80211_regdomain_t *regdomain) 1078 { 1079 u_int16_t ee_regdomain; 1080 1081 /* Read current value */ 1082 if (write != AH_TRUE) { 1083 ee_regdomain = hal->ah_capabilities.cap_eeprom.ee_regdomain; 1084 *regdomain = ar5k_regdomain_to_ieee(ee_regdomain); 1085 return (AH_TRUE); 1086 } 1087 1088 ee_regdomain = ar5k_regdomain_from_ieee(*regdomain); 1089 1090 /* Try to write a new value */ 1091 if (hal->ah_capabilities.cap_eeprom.ee_protect & 1092 AR5K_EEPROM_PROTECT_WR_128_191) 1093 return (AH_FALSE); 1094 if (hal->ah_eeprom_write(hal, AR5K_EEPROM_REG_DOMAIN, 1095 ee_regdomain) != 0) 1096 return (AH_FALSE); 1097 1098 hal->ah_capabilities.cap_eeprom.ee_regdomain = ee_regdomain; 1099 1100 return (AH_TRUE); 1101 } 1102 1103 /* 1104 * PHY/RF access functions 1105 */ 1106 1107 HAL_BOOL 1108 ar5k_channel(struct ath_hal *hal, HAL_CHANNEL *channel) 1109 { 1110 HAL_BOOL ret; 1111 1112 /* 1113 * Check bounds supported by the PHY 1114 * (don't care about regulation restrictions at this point) 1115 */ 1116 if ((channel->channel < hal->ah_capabilities.cap_range.range_2ghz_min || 1117 channel->channel > hal->ah_capabilities.cap_range.range_2ghz_max) && 1118 (channel->channel < hal->ah_capabilities.cap_range.range_5ghz_min || 1119 channel->channel > hal->ah_capabilities.cap_range.range_5ghz_max)) { 1120 AR5K_PRINTF("channel out of supported range (%u MHz)\n", 1121 channel->channel); 1122 return (AH_FALSE); 1123 } 1124 1125 /* 1126 * Set the channel and wait 1127 */ 1128 if (hal->ah_radio == AR5K_AR5110) 1129 ret = ar5k_ar5110_channel(hal, channel); 1130 else if (hal->ah_radio == AR5K_AR5111) 1131 ret = ar5k_ar5111_channel(hal, channel); 1132 else 1133 ret = ar5k_ar5112_channel(hal, channel); 1134 1135 if (ret == AH_FALSE) 1136 return (ret); 1137 1138 hal->ah_current_channel.c_channel = channel->c_channel; 1139 hal->ah_current_channel.c_channel_flags = channel->c_channel_flags; 1140 hal->ah_turbo = channel->c_channel_flags == CHANNEL_T ? 1141 AH_TRUE : AH_FALSE; 1142 1143 return (AH_TRUE); 1144 } 1145 1146 u_int32_t 1147 ar5k_ar5110_chan2athchan(HAL_CHANNEL *channel) 1148 { 1149 u_int32_t athchan; 1150 1151 /* 1152 * Convert IEEE channel/MHz to an internal channel value used 1153 * by the AR5210 chipset. This has not been verified with 1154 * newer chipsets like the AR5212A who have a completely 1155 * different RF/PHY part. 1156 */ 1157 athchan = (ar5k_bitswap((ieee80211_mhz2ieee(channel->c_channel, 1158 channel->c_channel_flags) - 24) / 2, 5) << 1) | 1159 (1 << 6) | 0x1; 1160 1161 return (athchan); 1162 } 1163 1164 HAL_BOOL 1165 ar5k_ar5110_channel(struct ath_hal *hal, HAL_CHANNEL *channel) 1166 { 1167 u_int32_t data; 1168 1169 /* 1170 * Set the channel and wait 1171 */ 1172 data = ar5k_ar5110_chan2athchan(channel); 1173 AR5K_PHY_WRITE(0x27, data); 1174 AR5K_PHY_WRITE(0x30, 0); 1175 AR5K_DELAY(1000); 1176 1177 return (AH_TRUE); 1178 } 1179 1180 HAL_BOOL 1181 ar5k_ar5111_chan2athchan(u_int ieee, struct ar5k_athchan_2ghz *athchan) 1182 { 1183 int channel; 1184 1185 /* Cast this value to catch negative channel numbers (>= -19) */ 1186 channel = (int)ieee; 1187 1188 /* 1189 * Map 2GHz IEEE channel to 5GHz Atheros channel 1190 */ 1191 if (channel <= 13) { 1192 athchan->a2_athchan = 115 + channel; 1193 athchan->a2_flags = 0x46; 1194 } else if (channel == 14) { 1195 athchan->a2_athchan = 124; 1196 athchan->a2_flags = 0x44; 1197 } else if (channel >= 15 && channel <= 26) { 1198 athchan->a2_athchan = ((channel - 14) * 4) + 132; 1199 athchan->a2_flags = 0x46; 1200 } else 1201 return (AH_FALSE); 1202 1203 return (AH_TRUE); 1204 } 1205 1206 HAL_BOOL 1207 ar5k_ar5111_channel(struct ath_hal *hal, HAL_CHANNEL *channel) 1208 { 1209 u_int ieee_channel, ath_channel; 1210 u_int32_t data0, data1, clock; 1211 struct ar5k_athchan_2ghz ath_channel_2ghz; 1212 1213 /* 1214 * Set the channel on the AR5111 radio 1215 */ 1216 data0 = data1 = 0; 1217 ath_channel = ieee_channel = ieee80211_mhz2ieee(channel->c_channel, 1218 channel->c_channel_flags); 1219 1220 if (channel->c_channel_flags & IEEE80211_CHAN_2GHZ) { 1221 /* Map 2GHz channel to 5GHz Atheros channel ID */ 1222 if (ar5k_ar5111_chan2athchan(ieee_channel, 1223 &ath_channel_2ghz) == AH_FALSE) 1224 return (AH_FALSE); 1225 1226 ath_channel = ath_channel_2ghz.a2_athchan; 1227 data0 = ((ar5k_bitswap(ath_channel_2ghz.a2_flags, 8) & 0xff) 1228 << 5) | (1 << 4); 1229 } 1230 1231 if (ath_channel < 145 || !(ath_channel & 1)) { 1232 clock = 1; 1233 data1 = ((ar5k_bitswap(ath_channel - 24, 8) & 0xff) << 2) 1234 | (clock << 1) | (1 << 10) | 1; 1235 } else { 1236 clock = 0; 1237 data1 = ((ar5k_bitswap((ath_channel - 24) / 2, 8) & 0xff) << 2) 1238 | (clock << 1) | (1 << 10) | 1; 1239 } 1240 1241 AR5K_PHY_WRITE(0x27, (data1 & 0xff) | ((data0 & 0xff) << 8)); 1242 AR5K_PHY_WRITE(0x34, ((data1 >> 8) & 0xff) | (data0 & 0xff00)); 1243 1244 return (AH_TRUE); 1245 } 1246 1247 HAL_BOOL 1248 ar5k_ar5112_channel(struct ath_hal *hal, HAL_CHANNEL *channel) 1249 { 1250 u_int32_t data, data0, data1, data2; 1251 u_int16_t c; 1252 1253 data = data0 = data1 = data2 = 0; 1254 c = channel->c_channel + hal->ah_chanoff; 1255 1256 /* 1257 * Set the channel on the AR5112 or newer 1258 */ 1259 if (c < 4800) { 1260 if (!((c - 2224) % 5)) { 1261 data0 = ((2 * (c - 704)) - 3040) / 10; 1262 data1 = 1; 1263 } else if (!((c - 2192) % 5)) { 1264 data0 = ((2 * (c - 672)) - 3040) / 10; 1265 data1 = 0; 1266 } else 1267 return (AH_FALSE); 1268 1269 data0 = ar5k_bitswap((data0 << 2) & 0xff, 8); 1270 } else { 1271 if (!(c % 20) && c >= 5120) { 1272 data0 = ar5k_bitswap(((c - 4800) / 20 << 2), 8); 1273 data2 = ar5k_bitswap(3, 2); 1274 } else if (!(c % 10)) { 1275 data0 = ar5k_bitswap(((c - 4800) / 10 << 1), 8); 1276 data2 = ar5k_bitswap(2, 2); 1277 } else if (!(c % 5)) { 1278 data0 = ar5k_bitswap((c - 4800) / 5, 8); 1279 data2 = ar5k_bitswap(1, 2); 1280 } else 1281 return (AH_FALSE); 1282 } 1283 1284 data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001; 1285 1286 AR5K_PHY_WRITE(0x27, data & 0xff); 1287 AR5K_PHY_WRITE(0x36, (data >> 8) & 0x7f); 1288 1289 return (AH_TRUE); 1290 } 1291 1292 u_int 1293 ar5k_rfregs_op(u_int32_t *rf, u_int32_t offset, u_int32_t reg, u_int32_t bits, 1294 u_int32_t first, u_int32_t col, HAL_BOOL set) 1295 { 1296 u_int32_t mask, entry, last, data, shift, position; 1297 int32_t left; 1298 int i; 1299 1300 if (rf == NULL) { 1301 /* should not happen */ 1302 return (0); 1303 } 1304 1305 if (!(col <= 3 && bits <= 32 && first + bits <= 319)) { 1306 AR5K_PRINTF("invalid values at offset %u\n", offset); 1307 return (0); 1308 } 1309 1310 entry = ((first - 1) / 8) + offset; 1311 position = (first - 1) % 8; 1312 1313 if (set == AH_TRUE) 1314 data = ar5k_bitswap(reg, bits); 1315 1316 for (i = shift = 0, left = bits; left > 0; position = 0, entry++, i++) { 1317 last = (position + left > 8) ? 8 : position + left; 1318 mask = (((1 << last) - 1) ^ ((1 << position) - 1)) << 1319 (col * 8); 1320 1321 if (set == AH_TRUE) { 1322 rf[entry] &= ~mask; 1323 rf[entry] |= ((data << position) << (col * 8)) & mask; 1324 data >>= (8 - position); 1325 } else { 1326 data = (((rf[entry] & mask) >> (col * 8)) >> 1327 position) << shift; 1328 shift += last - position; 1329 } 1330 1331 left -= 8 - position; 1332 } 1333 1334 data = set == AH_TRUE ? 1 : ar5k_bitswap(data, bits); 1335 1336 return (data); 1337 } 1338 1339 u_int32_t 1340 ar5k_rfregs_gainf_corr(struct ath_hal *hal) 1341 { 1342 u_int32_t mix, step; 1343 u_int32_t *rf; 1344 1345 if (hal->ah_rf_banks == NULL) 1346 return (0); 1347 1348 rf = hal->ah_rf_banks; 1349 hal->ah_gain.g_f_corr = 0; 1350 1351 if (ar5k_rfregs_op(rf, hal->ah_offset[7], 0, 1, 36, 0, AH_FALSE) != 1) 1352 return (0); 1353 1354 step = ar5k_rfregs_op(rf, hal->ah_offset[7], 0, 4, 32, 0, AH_FALSE); 1355 mix = hal->ah_gain.g_step->gos_param[0]; 1356 1357 switch (mix) { 1358 case 3: 1359 hal->ah_gain.g_f_corr = step * 2; 1360 break; 1361 case 2: 1362 hal->ah_gain.g_f_corr = (step - 5) * 2; 1363 break; 1364 case 1: 1365 hal->ah_gain.g_f_corr = step; 1366 break; 1367 default: 1368 hal->ah_gain.g_f_corr = 0; 1369 break; 1370 } 1371 1372 return (hal->ah_gain.g_f_corr); 1373 } 1374 1375 HAL_BOOL 1376 ar5k_rfregs_gain_readback(struct ath_hal *hal) 1377 { 1378 u_int32_t step, mix, level[4]; 1379 u_int32_t *rf; 1380 1381 if (hal->ah_rf_banks == NULL) 1382 return (0); 1383 1384 rf = hal->ah_rf_banks; 1385 1386 if (hal->ah_radio == AR5K_AR5111) { 1387 step = ar5k_rfregs_op(rf, hal->ah_offset[7], 1388 0, 6, 37, 0, AH_FALSE); 1389 level[0] = 0; 1390 level[1] = (step == 0x3f) ? 0x32 : step + 4; 1391 level[2] = (step != 0x3f) ? 0x40 : level[0]; 1392 level[3] = level[2] + 0x32; 1393 1394 hal->ah_gain.g_high = level[3] - 1395 (step == 0x3f ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5); 1396 hal->ah_gain.g_low = level[0] + 1397 (step == 0x3f ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0); 1398 } else { 1399 mix = ar5k_rfregs_op(rf, hal->ah_offset[7], 1400 0, 1, 36, 0, AH_FALSE); 1401 level[0] = level[2] = 0; 1402 1403 if (mix == 1) { 1404 level[1] = level[3] = 83; 1405 } else { 1406 level[1] = level[3] = 107; 1407 hal->ah_gain.g_high = 55; 1408 } 1409 } 1410 1411 return ((hal->ah_gain.g_current >= level[0] && 1412 hal->ah_gain.g_current <= level[1]) || 1413 (hal->ah_gain.g_current >= level[2] && 1414 hal->ah_gain.g_current <= level[3])); 1415 } 1416 1417 int32_t 1418 ar5k_rfregs_gain_adjust(struct ath_hal *hal) 1419 { 1420 int ret = 0; 1421 const struct ar5k_gain_opt *go; 1422 1423 go = hal->ah_radio == AR5K_AR5111 ? 1424 &ar5111_gain_opt : &ar5112_gain_opt; 1425 1426 hal->ah_gain.g_step = &go->go_step[hal->ah_gain.g_step_idx]; 1427 1428 if (hal->ah_gain.g_current >= hal->ah_gain.g_high) { 1429 if (hal->ah_gain.g_step_idx == 0) 1430 return (-1); 1431 for (hal->ah_gain.g_target = hal->ah_gain.g_current; 1432 hal->ah_gain.g_target >= hal->ah_gain.g_high && 1433 hal->ah_gain.g_step_idx > 0; 1434 hal->ah_gain.g_step = 1435 &go->go_step[hal->ah_gain.g_step_idx]) { 1436 hal->ah_gain.g_target -= 2 * 1437 (go->go_step[--(hal->ah_gain.g_step_idx)].gos_gain - 1438 hal->ah_gain.g_step->gos_gain); 1439 } 1440 1441 ret = 1; 1442 goto done; 1443 } 1444 1445 if (hal->ah_gain.g_current <= hal->ah_gain.g_low) { 1446 if (hal->ah_gain.g_step_idx == (go->go_steps_count - 1)) 1447 return (-2); 1448 for (hal->ah_gain.g_target = hal->ah_gain.g_current; 1449 hal->ah_gain.g_target <= hal->ah_gain.g_low && 1450 hal->ah_gain.g_step_idx < (go->go_steps_count - 1); 1451 hal->ah_gain.g_step = 1452 &go->go_step[hal->ah_gain.g_step_idx]) { 1453 hal->ah_gain.g_target -= 2 * 1454 (go->go_step[++(hal->ah_gain.g_step_idx)].gos_gain - 1455 hal->ah_gain.g_step->gos_gain); 1456 } 1457 1458 ret = 2; 1459 goto done; 1460 } 1461 1462 done: 1463 #ifdef AR5K_DEBUG 1464 AR5K_PRINTF("ret %d, gain step %u, current gain %u, target gain %u\n", 1465 ret, 1466 hal->ah_gain.g_step_idx, 1467 hal->ah_gain.g_current, 1468 hal->ah_gain.g_target); 1469 #endif 1470 1471 return (ret); 1472 } 1473 1474 HAL_BOOL 1475 ar5k_rfregs(struct ath_hal *hal, HAL_CHANNEL *channel, u_int mode) 1476 { 1477 ar5k_rfgain_t *func = NULL; 1478 HAL_BOOL ret; 1479 1480 switch (hal->ah_radio) { 1481 case AR5K_AR5111: 1482 hal->ah_rf_banks_size = sizeof(ar5111_rf); 1483 func = ar5k_ar5111_rfregs; 1484 break; 1485 case AR5K_AR5112: 1486 if (hal->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) 1487 hal->ah_rf_banks_size = sizeof(ar5112a_rf); 1488 else 1489 hal->ah_rf_banks_size = sizeof(ar5112_rf); 1490 func = ar5k_ar5112_rfregs; 1491 break; 1492 case AR5K_AR5413: 1493 hal->ah_rf_banks_size = sizeof(ar5413_rf); 1494 func = ar5k_arxxxx_rfregs; 1495 break; 1496 case AR5K_AR2413: 1497 hal->ah_rf_banks_size = sizeof(ar2413_rf); 1498 func = ar5k_arxxxx_rfregs; 1499 break; 1500 case AR5K_AR2425: 1501 hal->ah_rf_banks_size = sizeof(ar2425_rf); 1502 func = ar5k_arxxxx_rfregs; 1503 break; 1504 default: 1505 return (AH_FALSE); 1506 } 1507 1508 if (hal->ah_rf_banks == NULL) { 1509 /* XXX do extra checks? */ 1510 if ((hal->ah_rf_banks = malloc(hal->ah_rf_banks_size, 1511 M_DEVBUF, M_NOWAIT | M_ZERO)) == NULL) { 1512 AR5K_PRINT("out of memory\n"); 1513 return (AH_FALSE); 1514 } 1515 } 1516 1517 ret = (func)(hal, channel, mode); 1518 1519 if (ret == AH_TRUE) 1520 hal->ah_rf_gain = HAL_RFGAIN_INACTIVE; 1521 1522 return (ret); 1523 } 1524 1525 HAL_BOOL 1526 ar5k_ar5111_rfregs(struct ath_hal *hal, HAL_CHANNEL *channel, u_int mode) 1527 { 1528 struct ar5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; 1529 const u_int rf_size = nitems(ar5111_rf); 1530 u_int32_t *rf; 1531 int i, obdb = -1, bank = -1; 1532 u_int32_t ee_mode; 1533 1534 AR5K_ASSERT_ENTRY(mode, AR5K_INI_VAL_MAX); 1535 1536 rf = hal->ah_rf_banks; 1537 1538 /* Copy values to modify them */ 1539 for (i = 0; i < rf_size; i++) { 1540 if (ar5111_rf[i].rf_bank >= 1541 AR5K_AR5111_INI_RF_MAX_BANKS) { 1542 AR5K_PRINT("invalid bank\n"); 1543 return (AH_FALSE); 1544 } 1545 1546 if (bank != ar5111_rf[i].rf_bank) { 1547 bank = ar5111_rf[i].rf_bank; 1548 hal->ah_offset[bank] = i; 1549 } 1550 1551 rf[i] = ar5111_rf[i].rf_value[mode]; 1552 } 1553 1554 if (channel->c_channel_flags & IEEE80211_CHAN_2GHZ) { 1555 if ((channel->c_channel_flags & IEEE80211_CHAN_G) == 1556 IEEE80211_CHAN_G) 1557 ee_mode = AR5K_EEPROM_MODE_11G; 1558 else 1559 ee_mode = AR5K_EEPROM_MODE_11B; 1560 obdb = 0; 1561 1562 if (!ar5k_rfregs_op(rf, hal->ah_offset[0], 1563 ee->ee_ob[ee_mode][obdb], 3, 119, 0, AH_TRUE)) 1564 return (AH_FALSE); 1565 1566 if (!ar5k_rfregs_op(rf, hal->ah_offset[0], 1567 ee->ee_ob[ee_mode][obdb], 3, 122, 0, AH_TRUE)) 1568 return (AH_FALSE); 1569 1570 obdb = 1; 1571 } else { 1572 /* For 11a, Turbo and XR */ 1573 ee_mode = AR5K_EEPROM_MODE_11A; 1574 obdb = channel->c_channel >= 5725 ? 3 : 1575 (channel->c_channel >= 5500 ? 2 : 1576 (channel->c_channel >= 5260 ? 1 : 1577 (channel->c_channel > 4000 ? 0 : -1))); 1578 1579 if (!ar5k_rfregs_op(rf, hal->ah_offset[6], 1580 ee->ee_pwd_84, 1, 51, 3, AH_TRUE)) 1581 return (AH_FALSE); 1582 1583 if (!ar5k_rfregs_op(rf, hal->ah_offset[6], 1584 ee->ee_pwd_90, 1, 45, 3, AH_TRUE)) 1585 return (AH_FALSE); 1586 } 1587 1588 if (!ar5k_rfregs_op(rf, hal->ah_offset[6], 1589 !ee->ee_xpd[ee_mode], 1, 95, 0, AH_TRUE)) 1590 return (AH_FALSE); 1591 1592 if (!ar5k_rfregs_op(rf, hal->ah_offset[6], 1593 ee->ee_x_gain[ee_mode], 4, 96, 0, AH_TRUE)) 1594 return (AH_FALSE); 1595 1596 if (!ar5k_rfregs_op(rf, hal->ah_offset[6], 1597 obdb >= 0 ? ee->ee_ob[ee_mode][obdb] : 0, 3, 104, 0, AH_TRUE)) 1598 return (AH_FALSE); 1599 1600 if (!ar5k_rfregs_op(rf, hal->ah_offset[6], 1601 obdb >= 0 ? ee->ee_db[ee_mode][obdb] : 0, 3, 107, 0, AH_TRUE)) 1602 return (AH_FALSE); 1603 1604 if (!ar5k_rfregs_op(rf, hal->ah_offset[7], 1605 ee->ee_i_gain[ee_mode], 6, 29, 0, AH_TRUE)) 1606 return (AH_FALSE); 1607 1608 if (!ar5k_rfregs_op(rf, hal->ah_offset[7], 1609 ee->ee_xpd[ee_mode], 1, 4, 0, AH_TRUE)) 1610 return (AH_FALSE); 1611 1612 /* Write RF values */ 1613 for (i = 0; i < rf_size; i++) { 1614 AR5K_REG_WAIT(i); 1615 AR5K_REG_WRITE(ar5111_rf[i].rf_register, rf[i]); 1616 } 1617 1618 return (AH_TRUE); 1619 } 1620 1621 HAL_BOOL 1622 ar5k_ar5112_rfregs(struct ath_hal *hal, HAL_CHANNEL *channel, u_int mode) 1623 { 1624 struct ar5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; 1625 u_int rf_size; 1626 u_int32_t *rf; 1627 int i, obdb = -1, bank = -1; 1628 u_int32_t ee_mode; 1629 const struct ar5k_ini_rf *rf_ini; 1630 1631 AR5K_ASSERT_ENTRY(mode, AR5K_INI_VAL_MAX); 1632 1633 rf = hal->ah_rf_banks; 1634 1635 if (hal->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) { 1636 rf_ini = ar5112a_rf; 1637 rf_size = nitems(ar5112a_rf); 1638 } else { 1639 rf_ini = ar5112_rf; 1640 rf_size = nitems(ar5112_rf); 1641 } 1642 1643 /* Copy values to modify them */ 1644 for (i = 0; i < rf_size; i++) { 1645 if (rf_ini[i].rf_bank >= 1646 AR5K_AR5112_INI_RF_MAX_BANKS) { 1647 AR5K_PRINT("invalid bank\n"); 1648 return (AH_FALSE); 1649 } 1650 1651 if (bank != rf_ini[i].rf_bank) { 1652 bank = rf_ini[i].rf_bank; 1653 hal->ah_offset[bank] = i; 1654 } 1655 1656 rf[i] = rf_ini[i].rf_value[mode]; 1657 } 1658 1659 if (channel->c_channel_flags & IEEE80211_CHAN_2GHZ) { 1660 if ((channel->c_channel_flags & IEEE80211_CHAN_G) == 1661 IEEE80211_CHAN_G) 1662 ee_mode = AR5K_EEPROM_MODE_11G; 1663 else 1664 ee_mode = AR5K_EEPROM_MODE_11B; 1665 obdb = 0; 1666 1667 if (!ar5k_rfregs_op(rf, hal->ah_offset[6], 1668 ee->ee_ob[ee_mode][obdb], 3, 287, 0, AH_TRUE)) 1669 return (AH_FALSE); 1670 1671 if (!ar5k_rfregs_op(rf, hal->ah_offset[6], 1672 ee->ee_ob[ee_mode][obdb], 3, 290, 0, AH_TRUE)) 1673 return (AH_FALSE); 1674 } else { 1675 /* For 11a, Turbo and XR */ 1676 ee_mode = AR5K_EEPROM_MODE_11A; 1677 obdb = channel->c_channel >= 5725 ? 3 : 1678 (channel->c_channel >= 5500 ? 2 : 1679 (channel->c_channel >= 5260 ? 1 : 1680 (channel->c_channel > 4000 ? 0 : -1))); 1681 1682 /* bogus channel: bad beacon? */ 1683 if (obdb < 0) 1684 return (AH_FALSE); 1685 1686 if (!ar5k_rfregs_op(rf, hal->ah_offset[6], 1687 ee->ee_ob[ee_mode][obdb], 3, 279, 0, AH_TRUE)) 1688 return (AH_FALSE); 1689 1690 if (!ar5k_rfregs_op(rf, hal->ah_offset[6], 1691 ee->ee_ob[ee_mode][obdb], 3, 282, 0, AH_TRUE)) 1692 return (AH_FALSE); 1693 } 1694 1695 #ifdef notyet 1696 ar5k_rfregs_op(rf, hal->ah_offset[6], 1697 ee->ee_x_gain[ee_mode], 2, 270, 0, AH_TRUE); 1698 ar5k_rfregs_op(rf, hal->ah_offset[6], 1699 ee->ee_x_gain[ee_mode], 2, 257, 0, AH_TRUE); 1700 #endif 1701 1702 if (!ar5k_rfregs_op(rf, hal->ah_offset[6], 1703 ee->ee_xpd[ee_mode], 1, 302, 0, AH_TRUE)) 1704 return (AH_FALSE); 1705 1706 if (!ar5k_rfregs_op(rf, hal->ah_offset[7], 1707 ee->ee_i_gain[ee_mode], 6, 14, 0, AH_TRUE)) 1708 return (AH_FALSE); 1709 1710 /* Write RF values */ 1711 for (i = 0; i < rf_size; i++) 1712 AR5K_REG_WRITE(rf_ini[i].rf_register, rf[i]); 1713 1714 return (AH_TRUE); 1715 } 1716 1717 HAL_BOOL 1718 ar5k_arxxxx_rfregs(struct ath_hal *hal, HAL_CHANNEL *channel, u_int mode) 1719 { 1720 const struct ar5k_ini_rf *rf_ini; 1721 u_int rf_size; 1722 u_int32_t *rf; 1723 int i, bank = -1; 1724 1725 AR5K_ASSERT_ENTRY(mode, AR5K_INI_VAL_MAX); 1726 1727 rf = hal->ah_rf_banks; 1728 1729 switch (hal->ah_radio) { 1730 case AR5K_AR5413: 1731 rf_ini = ar5413_rf; 1732 rf_size = nitems(ar5413_rf); 1733 break; 1734 case AR5K_AR2413: 1735 rf_ini = ar2413_rf; 1736 rf_size = nitems(ar2413_rf); 1737 break; 1738 case AR5K_AR2425: 1739 if (mode == AR5K_INI_VAL_11B) 1740 mode = AR5K_INI_VAL_11G; 1741 rf_ini = ar2425_rf; 1742 rf_size = nitems(ar2425_rf); 1743 break; 1744 default: 1745 return (AH_FALSE); 1746 } 1747 1748 /* Copy values to modify them */ 1749 for (i = 0; i < rf_size; i++) { 1750 if (rf_ini[i].rf_bank >= AR5K_MAX_RF_BANKS) { 1751 AR5K_PRINT("invalid bank\n"); 1752 return (AH_FALSE); 1753 } 1754 1755 if (bank != rf_ini[i].rf_bank) { 1756 bank = rf_ini[i].rf_bank; 1757 hal->ah_offset[bank] = i; 1758 } 1759 1760 rf[i] = rf_ini[i].rf_value[mode]; 1761 } 1762 1763 /* Write RF values */ 1764 for (i = 0; i < rf_size; i++) 1765 AR5K_REG_WRITE(rf_ini[i].rf_register, rf[i]); 1766 1767 return (AH_TRUE); 1768 } 1769 1770 HAL_BOOL 1771 ar5k_rfgain(struct ath_hal *hal, u_int freq) 1772 { 1773 const struct ar5k_ini_rfgain *rfg; 1774 size_t rfg_size; 1775 int i; 1776 1777 switch (hal->ah_radio) { 1778 case AR5K_AR5111: 1779 rfg = ar5111_rfg; 1780 rfg_size = nitems(ar5111_rfg); 1781 break; 1782 case AR5K_AR5112: 1783 rfg = ar5112_rfg; 1784 rfg_size = nitems(ar5112_rfg); 1785 break; 1786 case AR5K_AR5413: 1787 rfg = ar5413_rfg; 1788 rfg_size = nitems(ar5413_rfg); 1789 break; 1790 case AR5K_AR2413: 1791 case AR5K_AR2425: 1792 if (freq == AR5K_INI_RFGAIN_5GHZ) 1793 return (AH_FALSE); 1794 rfg = ar2413_rfg; 1795 rfg_size = nitems(ar2413_rfg); 1796 break; 1797 default: 1798 return (AH_FALSE); 1799 } 1800 1801 switch (freq) { 1802 case AR5K_INI_RFGAIN_2GHZ: 1803 case AR5K_INI_RFGAIN_5GHZ: 1804 break; 1805 default: 1806 return (AH_FALSE); 1807 } 1808 1809 for (i = 0; i < rfg_size; i++) { 1810 AR5K_REG_WAIT(i); 1811 AR5K_REG_WRITE((u_int32_t)rfg[i].rfg_register, 1812 rfg[i].rfg_value[freq]); 1813 } 1814 1815 return (AH_TRUE); 1816 } 1817 1818 /* 1819 * Common TX power setup 1820 */ 1821 void 1822 ar5k_txpower_table(struct ath_hal *hal, HAL_CHANNEL *channel, int16_t max_power) 1823 { 1824 u_int16_t txpower, *rates; 1825 int i, min, max, n; 1826 1827 rates = hal->ah_txpower.txp_rates; 1828 1829 txpower = AR5K_TUNE_DEFAULT_TXPOWER * 2; 1830 if (max_power > txpower) { 1831 txpower = max_power > AR5K_TUNE_MAX_TXPOWER ? 1832 AR5K_TUNE_MAX_TXPOWER : max_power; 1833 } 1834 1835 for (i = 0; i < AR5K_MAX_RATES; i++) 1836 rates[i] = txpower; 1837 1838 /* XXX setup target powers by rate */ 1839 1840 hal->ah_txpower.txp_min = rates[7]; 1841 hal->ah_txpower.txp_max = rates[0]; 1842 hal->ah_txpower.txp_ofdm = rates[0]; 1843 1844 /* Calculate the power table */ 1845 n = nitems(hal->ah_txpower.txp_pcdac); 1846 min = AR5K_EEPROM_PCDAC_START; 1847 max = AR5K_EEPROM_PCDAC_STOP; 1848 for (i = 0; i < n; i += AR5K_EEPROM_PCDAC_STEP) 1849 hal->ah_txpower.txp_pcdac[i] = 1850 #ifdef notyet 1851 min + ((i * (max - min)) / n); 1852 #else 1853 min; 1854 #endif 1855 } 1856 1857 void 1858 ar5k_write_ini(struct ath_hal *hal, const struct ar5k_ini *ini, 1859 size_t n, HAL_BOOL change_channel) 1860 { 1861 u_int i; 1862 1863 for (i = 0; i < n; i++) { 1864 if (change_channel == AH_TRUE && 1865 ini[i].ini_register >= AR5K_PCU_MIN && 1866 ini[i].ini_register <= AR5K_PCU_MAX) 1867 continue; 1868 switch (ini[i].ini_mode) { 1869 case AR5K_INI_READ: 1870 /* cleared on read */ 1871 AR5K_REG_READ((u_int32_t)ini[i].ini_register); 1872 break; 1873 case AR5K_INI_WRITE: 1874 AR5K_REG_WAIT(i); 1875 AR5K_REG_WRITE((u_int32_t)ini[i].ini_register, 1876 ini[i].ini_value); 1877 break; 1878 } 1879 } 1880 } 1881 1882 void 1883 ar5k_write_mode(struct ath_hal *hal, const struct ar5k_mode *ini, 1884 size_t n, u_int mode) 1885 { 1886 u_int i; 1887 1888 for (i = 0; i < n; i++) { 1889 AR5K_REG_WAIT(i); 1890 AR5K_REG_WRITE((u_int32_t)ini[i].mode_register, 1891 ini[i].mode_value[mode]); 1892 } 1893 } 1894