1 /* $OpenBSD: ar5xxx.c,v 1.52 2008/07/30 07:43:01 reyk Exp $ */ 2 3 /* 4 * Copyright (c) 2004, 2005, 2006, 2007 Reyk Floeter <reyk@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * HAL interface for Atheros Wireless LAN devices. 21 * (Please have a look at ar5xxx.h for further information) 22 */ 23 24 #include <dev/pci/pcidevs.h> 25 #include <dev/ic/ar5xxx.h> 26 27 extern ar5k_attach_t ar5k_ar5210_attach; 28 extern ar5k_attach_t ar5k_ar5211_attach; 29 extern ar5k_attach_t ar5k_ar5212_attach; 30 31 static const struct { 32 u_int16_t vendor; 33 u_int16_t device; 34 ar5k_attach_t (*attach); 35 } ar5k_known_products[] = { 36 /* 37 * From pcidevs_data.h 38 */ 39 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5210, 40 ar5k_ar5210_attach }, 41 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5210_AP, 42 ar5k_ar5210_attach }, 43 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5210_DEFAULT, 44 ar5k_ar5210_attach }, 45 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5211, 46 ar5k_ar5211_attach }, 47 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5211_DEFAULT, 48 ar5k_ar5211_attach }, 49 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5311, 50 ar5k_ar5211_attach }, 51 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5211_FPGA11B, 52 ar5k_ar5211_attach }, 53 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5211_LEGACY, 54 ar5k_ar5211_attach }, 55 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5212, 56 ar5k_ar5212_attach }, 57 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5212_DEFAULT, 58 ar5k_ar5212_attach }, 59 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5212_FPGA, 60 ar5k_ar5212_attach }, 61 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5212_IBM, 62 ar5k_ar5212_attach }, 63 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR2413, 64 ar5k_ar5212_attach }, 65 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5413, 66 ar5k_ar5212_attach }, 67 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5424, 68 ar5k_ar5212_attach }, 69 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5416, 70 ar5k_ar5212_attach }, 71 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5418, 72 ar5k_ar5212_attach }, 73 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CRDAG675, 74 ar5k_ar5212_attach }, 75 { PCI_VENDOR_3COM2, PCI_PRODUCT_3COM2_3CRPAG175, 76 ar5k_ar5212_attach } 77 }; 78 79 static const HAL_RATE_TABLE ar5k_rt_11a = AR5K_RATES_11A; 80 static const HAL_RATE_TABLE ar5k_rt_11b = AR5K_RATES_11B; 81 static const HAL_RATE_TABLE ar5k_rt_11g = AR5K_RATES_11G; 82 static const HAL_RATE_TABLE ar5k_rt_turbo = AR5K_RATES_TURBO; 83 static const HAL_RATE_TABLE ar5k_rt_xr = AR5K_RATES_XR; 84 85 int ar5k_eeprom_read_ants(struct ath_hal *, u_int32_t *, u_int); 86 int ar5k_eeprom_read_modes(struct ath_hal *, u_int32_t *, u_int); 87 u_int16_t ar5k_eeprom_bin2freq(struct ath_hal *, u_int16_t, u_int); 88 89 HAL_BOOL ar5k_ar5110_channel(struct ath_hal *, HAL_CHANNEL *); 90 u_int32_t ar5k_ar5110_chan2athchan(HAL_CHANNEL *); 91 HAL_BOOL ar5k_ar5111_channel(struct ath_hal *, HAL_CHANNEL *); 92 HAL_BOOL ar5k_ar5111_chan2athchan(u_int, struct ar5k_athchan_2ghz *); 93 HAL_BOOL ar5k_ar5112_channel(struct ath_hal *, HAL_CHANNEL *); 94 HAL_BOOL ar5k_check_channel(struct ath_hal *, u_int16_t, u_int flags); 95 96 HAL_BOOL ar5k_ar5111_rfregs(struct ath_hal *, HAL_CHANNEL *, u_int); 97 HAL_BOOL ar5k_ar5112_rfregs(struct ath_hal *, HAL_CHANNEL *, u_int); 98 HAL_BOOL ar5k_arxxxx_rfregs(struct ath_hal *, HAL_CHANNEL *, u_int); 99 u_int ar5k_rfregs_op(u_int32_t *, u_int32_t, u_int32_t, u_int32_t, 100 u_int32_t, u_int32_t, HAL_BOOL); 101 102 /* 103 * Supported channels 104 */ 105 static const struct 106 ieee80211_regchannel ar5k_5ghz_channels[] = IEEE80211_CHANNELS_5GHZ; 107 static const struct 108 ieee80211_regchannel ar5k_2ghz_channels[] = IEEE80211_CHANNELS_2GHZ; 109 110 /* 111 * Initial gain optimization values 112 */ 113 static const struct ar5k_gain_opt ar5111_gain_opt = AR5K_AR5111_GAIN_OPT; 114 static const struct ar5k_gain_opt ar5112_gain_opt = AR5K_AR5112_GAIN_OPT; 115 116 /* 117 * Initial register for the radio chipsets 118 */ 119 static const struct ar5k_ini_rf ar5111_rf[] = AR5K_AR5111_INI_RF; 120 static const struct ar5k_ini_rf ar5112_rf[] = AR5K_AR5112_INI_RF; 121 static const struct ar5k_ini_rf ar5112a_rf[] = AR5K_AR5112A_INI_RF; 122 static const struct ar5k_ini_rf ar5413_rf[] = AR5K_AR5413_INI_RF; 123 static const struct ar5k_ini_rf ar2413_rf[] = AR5K_AR2413_INI_RF; 124 static const struct ar5k_ini_rf ar2425_rf[] = AR5K_AR2425_INI_RF; 125 static const struct ar5k_ini_rfgain ar5111_rfg[] = AR5K_AR5111_INI_RFGAIN; 126 static const struct ar5k_ini_rfgain ar5112_rfg[] = AR5K_AR5112_INI_RFGAIN; 127 static const struct ar5k_ini_rfgain ar5413_rfg[] = AR5K_AR5413_INI_RFGAIN; 128 static const struct ar5k_ini_rfgain ar2413_rfg[] = AR5K_AR2413_INI_RFGAIN; 129 130 /* 131 * Enable to overwrite the country code (use "00" for debug) 132 */ 133 #if 0 134 #define COUNTRYCODE "00" 135 #endif 136 137 /* 138 * Perform a lookup if the device is supported by the HAL 139 */ 140 const char * 141 ath_hal_probe(u_int16_t vendor, u_int16_t device) 142 { 143 int i; 144 145 /* 146 * Perform a linear search on the table of supported devices 147 */ 148 for (i = 0; i < AR5K_ELEMENTS(ar5k_known_products); i++) { 149 if (vendor == ar5k_known_products[i].vendor && 150 device == ar5k_known_products[i].device) 151 return (""); 152 } 153 154 return (NULL); 155 } 156 157 /* 158 * Fills in the HAL structure and initialises the device 159 */ 160 struct ath_hal * 161 ath_hal_attach(u_int16_t device, void *arg, bus_space_tag_t st, 162 bus_space_handle_t sh, u_int is_pcie, int *status) 163 { 164 struct ath_softc *sc = (struct ath_softc *)arg; 165 struct ath_hal *hal = NULL; 166 ar5k_attach_t *attach = NULL; 167 u_int8_t mac[IEEE80211_ADDR_LEN]; 168 int i; 169 170 *status = EINVAL; 171 172 /* 173 * Call the chipset-dependent attach routine by device id 174 */ 175 for (i = 0; i < AR5K_ELEMENTS(ar5k_known_products); i++) { 176 if (device == ar5k_known_products[i].device && 177 ar5k_known_products[i].attach != NULL) 178 attach = ar5k_known_products[i].attach; 179 } 180 181 if (attach == NULL) { 182 *status = ENXIO; 183 AR5K_PRINTF("device not supported: 0x%04x\n", device); 184 return (NULL); 185 } 186 187 if ((hal = malloc(sizeof(struct ath_hal), 188 M_DEVBUF, M_NOWAIT | M_ZERO)) == NULL) { 189 *status = ENOMEM; 190 AR5K_PRINT("out of memory\n"); 191 return (NULL); 192 } 193 194 hal->ah_sc = sc; 195 hal->ah_st = st; 196 hal->ah_sh = sh; 197 hal->ah_device = device; 198 hal->ah_sub_vendor = 0; /* XXX unknown?! */ 199 200 /* 201 * HAL information 202 */ 203 hal->ah_abi = HAL_ABI_VERSION; 204 hal->ah_op_mode = HAL_M_STA; 205 hal->ah_radar.r_enabled = AR5K_TUNE_RADAR_ALERT; 206 hal->ah_turbo = AH_FALSE; 207 hal->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER; 208 hal->ah_imr = 0; 209 hal->ah_atim_window = 0; 210 hal->ah_aifs = AR5K_TUNE_AIFS; 211 hal->ah_cw_min = AR5K_TUNE_CWMIN; 212 hal->ah_limit_tx_retries = AR5K_INIT_TX_RETRY; 213 hal->ah_software_retry = AH_FALSE; 214 hal->ah_ant_diversity = AR5K_TUNE_ANT_DIVERSITY; 215 hal->ah_pci_express = is_pcie ? AH_TRUE : AH_FALSE; 216 217 switch (device) { 218 case PCI_PRODUCT_ATHEROS_AR2413: 219 case PCI_PRODUCT_ATHEROS_AR5413: 220 case PCI_PRODUCT_ATHEROS_AR5424: 221 /* 222 * Known single chip solutions 223 */ 224 hal->ah_single_chip = AH_TRUE; 225 break; 226 default: 227 /* 228 * Multi chip solutions 229 */ 230 hal->ah_single_chip = AH_FALSE; 231 break; 232 } 233 234 if ((attach)(device, hal, st, sh, status) == NULL) 235 goto failed; 236 237 #ifdef AR5K_DEBUG 238 hal->ah_dump_state(hal); 239 #endif 240 241 /* 242 * Get card capabilities, values, ... 243 */ 244 245 if (ar5k_eeprom_init(hal) != 0) { 246 AR5K_PRINT("unable to init EEPROM\n"); 247 goto failed; 248 } 249 250 /* Get misc capabilities */ 251 if (hal->ah_get_capabilities(hal) != AH_TRUE) { 252 AR5K_PRINTF("unable to get device capabilities: 0x%04x\n", 253 device); 254 goto failed; 255 } 256 257 /* Get MAC address */ 258 if ((*status = ar5k_eeprom_read_mac(hal, mac)) != 0) { 259 AR5K_PRINTF("unable to read address from EEPROM: 0x%04x\n", 260 device); 261 goto failed; 262 } 263 264 hal->ah_set_lladdr(hal, mac); 265 266 /* Get rate tables */ 267 if (hal->ah_capabilities.cap_mode & HAL_MODE_11A) 268 ar5k_rt_copy(&hal->ah_rt_11a, &ar5k_rt_11a); 269 if (hal->ah_capabilities.cap_mode & HAL_MODE_11B) 270 ar5k_rt_copy(&hal->ah_rt_11b, &ar5k_rt_11b); 271 if (hal->ah_capabilities.cap_mode & HAL_MODE_11G) 272 ar5k_rt_copy(&hal->ah_rt_11g, &ar5k_rt_11g); 273 if (hal->ah_capabilities.cap_mode & HAL_MODE_TURBO) 274 ar5k_rt_copy(&hal->ah_rt_turbo, &ar5k_rt_turbo); 275 if (hal->ah_capabilities.cap_mode & HAL_MODE_XR) 276 ar5k_rt_copy(&hal->ah_rt_xr, &ar5k_rt_xr); 277 278 /* Initialize the gain optimization values */ 279 if (hal->ah_radio == AR5K_AR5111) { 280 hal->ah_gain.g_step_idx = ar5111_gain_opt.go_default; 281 hal->ah_gain.g_step = 282 &ar5111_gain_opt.go_step[hal->ah_gain.g_step_idx]; 283 hal->ah_gain.g_low = 20; 284 hal->ah_gain.g_high = 35; 285 hal->ah_gain.g_active = 1; 286 } else if (hal->ah_radio == AR5K_AR5112) { 287 hal->ah_gain.g_step_idx = ar5112_gain_opt.go_default; 288 hal->ah_gain.g_step = 289 &ar5111_gain_opt.go_step[hal->ah_gain.g_step_idx]; 290 hal->ah_gain.g_low = 20; 291 hal->ah_gain.g_high = 85; 292 hal->ah_gain.g_active = 1; 293 } else { 294 /* XXX not needed for newer chipsets? */ 295 } 296 297 *status = HAL_OK; 298 299 return (hal); 300 301 failed: 302 free(hal, M_DEVBUF); 303 return (NULL); 304 } 305 306 u_int16_t 307 ath_hal_computetxtime(struct ath_hal *hal, const HAL_RATE_TABLE *rates, 308 u_int32_t frame_length, u_int16_t rate_index, HAL_BOOL short_preamble) 309 { 310 const HAL_RATE *rate; 311 u_int32_t value; 312 313 AR5K_ASSERT_ENTRY(rate_index, rates->rateCount); 314 315 /* 316 * Get rate by index 317 */ 318 rate = &rates->info[rate_index]; 319 320 /* 321 * Calculate the transmission time by operation (PHY) mode 322 */ 323 switch (rate->phy) { 324 case IEEE80211_T_CCK: 325 /* 326 * CCK / DS mode (802.11b) 327 */ 328 value = AR5K_CCK_TX_TIME(rate->rateKbps, frame_length, 329 (short_preamble && rate->shortPreamble)); 330 break; 331 332 case IEEE80211_T_OFDM: 333 /* 334 * Orthogonal Frequency Division Multiplexing 335 */ 336 if (AR5K_OFDM_NUM_BITS_PER_SYM(rate->rateKbps) == 0) 337 return (0); 338 value = AR5K_OFDM_TX_TIME(rate->rateKbps, frame_length); 339 break; 340 341 case IEEE80211_T_TURBO: 342 /* 343 * Orthogonal Frequency Division Multiplexing 344 * Atheros "Turbo Mode" (doubled rates) 345 */ 346 if (AR5K_TURBO_NUM_BITS_PER_SYM(rate->rateKbps) == 0) 347 return (0); 348 value = AR5K_TURBO_TX_TIME(rate->rateKbps, frame_length); 349 break; 350 351 case IEEE80211_T_XR: 352 /* 353 * Orthogonal Frequency Division Multiplexing 354 * Atheros "eXtended Range" (XR) 355 */ 356 if (AR5K_XR_NUM_BITS_PER_SYM(rate->rateKbps) == 0) 357 return (0); 358 value = AR5K_XR_TX_TIME(rate->rateKbps, frame_length); 359 break; 360 361 default: 362 return (0); 363 } 364 365 return (value); 366 } 367 368 HAL_BOOL 369 ar5k_check_channel(struct ath_hal *hal, u_int16_t freq, u_int flags) 370 { 371 /* Check if the channel is in our supported range */ 372 if (flags & IEEE80211_CHAN_2GHZ) { 373 if ((freq >= hal->ah_capabilities.cap_range.range_2ghz_min) && 374 (freq <= hal->ah_capabilities.cap_range.range_2ghz_max)) 375 return (AH_TRUE); 376 } else if (flags & IEEE80211_CHAN_5GHZ) { 377 if ((freq >= hal->ah_capabilities.cap_range.range_5ghz_min) && 378 (freq <= hal->ah_capabilities.cap_range.range_5ghz_max)) 379 return (AH_TRUE); 380 } 381 382 return (AH_FALSE); 383 } 384 385 HAL_BOOL 386 ath_hal_init_channels(struct ath_hal *hal, HAL_CHANNEL *channels, 387 u_int max_channels, u_int *channels_size, u_int16_t mode, 388 HAL_BOOL outdoor, HAL_BOOL extended) 389 { 390 u_int i, c; 391 u_int32_t domain_current; 392 u_int domain_5ghz, domain_2ghz; 393 HAL_CHANNEL *all_channels; 394 395 if ((all_channels = malloc(sizeof(HAL_CHANNEL) * max_channels, 396 M_TEMP, M_NOWAIT | M_ZERO)) == NULL) 397 return (AH_FALSE); 398 399 i = c = 0; 400 domain_current = hal->ah_regdomain; 401 402 /* 403 * In debugging mode, enable all channels supported by the chipset 404 */ 405 if (domain_current == DMN_DEFAULT) { 406 int min, max, freq; 407 u_int flags; 408 409 min = ieee80211_mhz2ieee(IEEE80211_CHANNELS_2GHZ_MIN, 410 IEEE80211_CHAN_2GHZ); 411 max = ieee80211_mhz2ieee(IEEE80211_CHANNELS_2GHZ_MAX, 412 IEEE80211_CHAN_2GHZ); 413 flags = CHANNEL_B | CHANNEL_TG | 414 (hal->ah_version == AR5K_AR5211 ? 415 CHANNEL_PUREG : CHANNEL_G); 416 417 debugchan: 418 for (i = min; i <= max && c < max_channels; i++) { 419 freq = ieee80211_ieee2mhz(i, flags); 420 if (ar5k_check_channel(hal, freq, flags) == AH_FALSE) 421 continue; 422 all_channels[c].c_channel = freq; 423 all_channels[c++].c_channel_flags = flags; 424 } 425 426 if (flags & IEEE80211_CHAN_2GHZ) { 427 min = ieee80211_mhz2ieee(IEEE80211_CHANNELS_5GHZ_MIN, 428 IEEE80211_CHAN_5GHZ); 429 max = ieee80211_mhz2ieee(IEEE80211_CHANNELS_5GHZ_MAX, 430 IEEE80211_CHAN_5GHZ); 431 flags = CHANNEL_A | CHANNEL_T | CHANNEL_XR; 432 goto debugchan; 433 } 434 435 goto done; 436 } 437 438 domain_5ghz = ieee80211_regdomain2flag(domain_current, 439 IEEE80211_CHANNELS_5GHZ_MIN); 440 domain_2ghz = ieee80211_regdomain2flag(domain_current, 441 IEEE80211_CHANNELS_2GHZ_MIN); 442 443 /* 444 * Create channel list based on chipset capabilities, regulation domain 445 * and mode. 5GHz... 446 */ 447 for (i = 0; (hal->ah_capabilities.cap_range.range_5ghz_max > 0) && 448 (i < AR5K_ELEMENTS(ar5k_5ghz_channels)) && 449 (c < max_channels); i++) { 450 /* Check if channel is supported by the chipset */ 451 if (ar5k_check_channel(hal, 452 ar5k_5ghz_channels[i].rc_channel, 453 IEEE80211_CHAN_5GHZ) == AH_FALSE) 454 continue; 455 456 /* Match regulation domain */ 457 if ((IEEE80211_DMN(ar5k_5ghz_channels[i].rc_domain) & 458 IEEE80211_DMN(domain_5ghz)) == 0) 459 continue; 460 461 /* Match modes */ 462 if (ar5k_5ghz_channels[i].rc_mode & IEEE80211_CHAN_TURBO) { 463 all_channels[c].c_channel_flags = CHANNEL_T; 464 } else if (ar5k_5ghz_channels[i].rc_mode & 465 IEEE80211_CHAN_OFDM) { 466 all_channels[c].c_channel_flags = CHANNEL_A; 467 } else 468 continue; 469 470 /* Write channel and increment counter */ 471 all_channels[c++].channel = ar5k_5ghz_channels[i].rc_channel; 472 } 473 474 /* 475 * ...and 2GHz. 476 */ 477 for (i = 0; (hal->ah_capabilities.cap_range.range_2ghz_max > 0) && 478 (i < AR5K_ELEMENTS(ar5k_2ghz_channels)) && 479 (c < max_channels); i++) { 480 /* Check if channel is supported by the chipset */ 481 if (ar5k_check_channel(hal, 482 ar5k_2ghz_channels[i].rc_channel, 483 IEEE80211_CHAN_2GHZ) == AH_FALSE) 484 continue; 485 486 /* Match regulation domain */ 487 if ((IEEE80211_DMN(ar5k_2ghz_channels[i].rc_domain) & 488 IEEE80211_DMN(domain_2ghz)) == 0) 489 continue; 490 491 /* Match modes */ 492 if ((hal->ah_capabilities.cap_mode & HAL_MODE_11B) && 493 (ar5k_2ghz_channels[i].rc_mode & IEEE80211_CHAN_CCK)) 494 all_channels[c].c_channel_flags = CHANNEL_B; 495 496 if ((hal->ah_capabilities.cap_mode & HAL_MODE_11G) && 497 (ar5k_2ghz_channels[i].rc_mode & IEEE80211_CHAN_OFDM)) { 498 all_channels[c].c_channel_flags |= 499 hal->ah_version == AR5K_AR5211 ? 500 CHANNEL_PUREG : CHANNEL_G; 501 if (ar5k_2ghz_channels[i].rc_mode & 502 IEEE80211_CHAN_TURBO) 503 all_channels[c].c_channel_flags |= CHANNEL_TG; 504 } 505 506 /* Write channel and increment counter */ 507 all_channels[c++].channel = ar5k_2ghz_channels[i].rc_channel; 508 } 509 510 done: 511 bcopy(all_channels, channels, sizeof(HAL_CHANNEL) * max_channels); 512 *channels_size = c; 513 free(all_channels, M_TEMP); 514 return (AH_TRUE); 515 } 516 517 /* 518 * Common internal functions 519 */ 520 521 const char * 522 ar5k_printver(enum ar5k_srev_type type, u_int32_t val) 523 { 524 struct ar5k_srev_name names[] = AR5K_SREV_NAME; 525 const char *name = "xxxx"; 526 int i; 527 528 for (i = 0; i < AR5K_ELEMENTS(names); i++) { 529 if (type == AR5K_VERSION_DEV) { 530 if (names[i].sr_type == type && 531 names[i].sr_val == val) { 532 name = names[i].sr_name; 533 break; 534 } 535 continue; 536 } 537 if (names[i].sr_type != type || 538 names[i].sr_val == AR5K_SREV_UNKNOWN) 539 continue; 540 if ((val & 0xff) < names[i + 1].sr_val) { 541 name = names[i].sr_name; 542 break; 543 } 544 } 545 546 return (name); 547 } 548 549 void 550 ar5k_radar_alert(struct ath_hal *hal) 551 { 552 /* 553 * Limit ~1/s 554 */ 555 if (hal->ah_radar.r_last_channel.channel == 556 hal->ah_current_channel.channel && 557 tick < (hal->ah_radar.r_last_alert + hz)) 558 return; 559 560 hal->ah_radar.r_last_channel.channel = 561 hal->ah_current_channel.channel; 562 hal->ah_radar.r_last_channel.c_channel_flags = 563 hal->ah_current_channel.c_channel_flags; 564 hal->ah_radar.r_last_alert = tick; 565 566 AR5K_PRINTF("Possible radar activity detected at %u MHz (tick %u)\n", 567 hal->ah_radar.r_last_alert, hal->ah_current_channel.channel); 568 } 569 570 u_int16_t 571 ar5k_regdomain_from_ieee(ieee80211_regdomain_t ieee) 572 { 573 u_int32_t regdomain = (u_int32_t)ieee; 574 575 /* 576 * Use the default regulation domain if the value is empty 577 * or not supported by the net80211 regulation code. 578 */ 579 if (ieee80211_regdomain2flag(regdomain, 580 IEEE80211_CHANNELS_5GHZ_MIN) == DMN_DEBUG) 581 return ((u_int16_t)AR5K_TUNE_REGDOMAIN); 582 583 /* It is supported, just return the value */ 584 return (regdomain); 585 } 586 587 ieee80211_regdomain_t 588 ar5k_regdomain_to_ieee(u_int16_t regdomain) 589 { 590 ieee80211_regdomain_t ieee = (ieee80211_regdomain_t)regdomain; 591 592 return (ieee); 593 } 594 595 u_int16_t 596 ar5k_get_regdomain(struct ath_hal *hal) 597 { 598 u_int16_t regdomain; 599 ieee80211_regdomain_t ieee_regdomain; 600 #ifdef COUNTRYCODE 601 u_int16_t code; 602 #endif 603 604 ar5k_eeprom_regulation_domain(hal, AH_FALSE, &ieee_regdomain); 605 hal->ah_capabilities.cap_regdomain.reg_hw = ieee_regdomain; 606 607 #ifdef COUNTRYCODE 608 /* 609 * Get the regulation domain by country code. This will ignore 610 * the settings found in the EEPROM. 611 */ 612 code = ieee80211_name2countrycode(COUNTRYCODE); 613 ieee_regdomain = ieee80211_countrycode2regdomain(code); 614 #endif 615 616 regdomain = ar5k_regdomain_from_ieee(ieee_regdomain); 617 hal->ah_capabilities.cap_regdomain.reg_current = regdomain; 618 619 return (regdomain); 620 } 621 622 u_int32_t 623 ar5k_bitswap(u_int32_t val, u_int bits) 624 { 625 if (bits == 8) { 626 val = ((val & 0xF0) >> 4) | ((val & 0x0F) << 4); 627 val = ((val & 0xCC) >> 2) | ((val & 0x33) << 2); 628 val = ((val & 0xAA) >> 1) | ((val & 0x55) << 1); 629 630 return val; 631 } else { 632 u_int32_t retval = 0, bit, i; 633 634 for (i = 0; i < bits; i++) { 635 bit = (val >> i) & 1; 636 retval = (retval << 1) | bit; 637 } 638 639 return retval; 640 } 641 } 642 643 u_int 644 ar5k_htoclock(u_int usec, HAL_BOOL turbo) 645 { 646 return (turbo == AH_TRUE ? (usec * 80) : (usec * 40)); 647 } 648 649 u_int 650 ar5k_clocktoh(u_int clock, HAL_BOOL turbo) 651 { 652 return (turbo == AH_TRUE ? (clock / 80) : (clock / 40)); 653 } 654 655 void 656 ar5k_rt_copy(HAL_RATE_TABLE *dst, const HAL_RATE_TABLE *src) 657 { 658 bzero(dst, sizeof(HAL_RATE_TABLE)); 659 dst->rateCount = src->rateCount; 660 bcopy(src->info, dst->info, sizeof(dst->info)); 661 } 662 663 HAL_BOOL 664 ar5k_register_timeout(struct ath_hal *hal, u_int32_t reg, u_int32_t flag, 665 u_int32_t val, HAL_BOOL is_set) 666 { 667 int i; 668 u_int32_t data; 669 670 for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) { 671 data = AR5K_REG_READ(reg); 672 if ((is_set == AH_TRUE) && (data & flag)) 673 break; 674 else if ((data & flag) == val) 675 break; 676 AR5K_DELAY(15); 677 } 678 679 if (i <= 0) 680 return (AH_FALSE); 681 682 return (AH_TRUE); 683 } 684 685 /* 686 * Common ar5xx EEPROM access functions 687 */ 688 689 u_int16_t 690 ar5k_eeprom_bin2freq(struct ath_hal *hal, u_int16_t bin, u_int mode) 691 { 692 u_int16_t val; 693 694 if (bin == AR5K_EEPROM_CHANNEL_DIS) 695 return (bin); 696 697 if (mode == AR5K_EEPROM_MODE_11A) { 698 if (hal->ah_ee_version > AR5K_EEPROM_VERSION_3_2) 699 val = (5 * bin) + 4800; 700 else 701 val = bin > 62 ? 702 (10 * 62) + (5 * (bin - 62)) + 5100 : 703 (bin * 10) + 5100; 704 } else { 705 if (hal->ah_ee_version > AR5K_EEPROM_VERSION_3_2) 706 val = bin + 2300; 707 else 708 val = bin + 2400; 709 } 710 711 return (val); 712 } 713 714 int 715 ar5k_eeprom_read_ants(struct ath_hal *hal, u_int32_t *offset, u_int mode) 716 { 717 struct ar5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; 718 u_int32_t o = *offset; 719 u_int16_t val; 720 int ret, i = 0; 721 722 AR5K_EEPROM_READ(o++, val); 723 ee->ee_switch_settling[mode] = (val >> 8) & 0x7f; 724 ee->ee_ant_tx_rx[mode] = (val >> 2) & 0x3f; 725 ee->ee_ant_control[mode][i] = (val << 4) & 0x3f; 726 727 AR5K_EEPROM_READ(o++, val); 728 ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf; 729 ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f; 730 ee->ee_ant_control[mode][i++] = val & 0x3f; 731 732 AR5K_EEPROM_READ(o++, val); 733 ee->ee_ant_control[mode][i++] = (val >> 10) & 0x3f; 734 ee->ee_ant_control[mode][i++] = (val >> 4) & 0x3f; 735 ee->ee_ant_control[mode][i] = (val << 2) & 0x3f; 736 737 AR5K_EEPROM_READ(o++, val); 738 ee->ee_ant_control[mode][i++] |= (val >> 14) & 0x3; 739 ee->ee_ant_control[mode][i++] = (val >> 8) & 0x3f; 740 ee->ee_ant_control[mode][i++] = (val >> 2) & 0x3f; 741 ee->ee_ant_control[mode][i] = (val << 4) & 0x3f; 742 743 AR5K_EEPROM_READ(o++, val); 744 ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf; 745 ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f; 746 ee->ee_ant_control[mode][i++] = val & 0x3f; 747 748 /* Get antenna modes */ 749 hal->ah_antenna[mode][0] = 750 (ee->ee_ant_control[mode][0] << 4) | 0x1; 751 hal->ah_antenna[mode][HAL_ANT_FIXED_A] = 752 ee->ee_ant_control[mode][1] | 753 (ee->ee_ant_control[mode][2] << 6) | 754 (ee->ee_ant_control[mode][3] << 12) | 755 (ee->ee_ant_control[mode][4] << 18) | 756 (ee->ee_ant_control[mode][5] << 24); 757 hal->ah_antenna[mode][HAL_ANT_FIXED_B] = 758 ee->ee_ant_control[mode][6] | 759 (ee->ee_ant_control[mode][7] << 6) | 760 (ee->ee_ant_control[mode][8] << 12) | 761 (ee->ee_ant_control[mode][9] << 18) | 762 (ee->ee_ant_control[mode][10] << 24); 763 764 /* return new offset */ 765 *offset = o; 766 767 return (0); 768 } 769 770 int 771 ar5k_eeprom_read_modes(struct ath_hal *hal, u_int32_t *offset, u_int mode) 772 { 773 struct ar5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; 774 u_int32_t o = *offset; 775 u_int16_t val; 776 int ret; 777 778 AR5K_EEPROM_READ(o++, val); 779 ee->ee_tx_end2xlna_enable[mode] = (val >> 8) & 0xff; 780 ee->ee_thr_62[mode] = val & 0xff; 781 782 if (hal->ah_ee_version <= AR5K_EEPROM_VERSION_3_2) 783 ee->ee_thr_62[mode] = 784 mode == AR5K_EEPROM_MODE_11A ? 15 : 28; 785 786 AR5K_EEPROM_READ(o++, val); 787 ee->ee_tx_end2xpa_disable[mode] = (val >> 8) & 0xff; 788 ee->ee_tx_frm2xpa_enable[mode] = val & 0xff; 789 790 AR5K_EEPROM_READ(o++, val); 791 ee->ee_pga_desired_size[mode] = (val >> 8) & 0xff; 792 793 if ((val & 0xff) & 0x80) 794 ee->ee_noise_floor_thr[mode] = -((((val & 0xff) ^ 0xff)) + 1); 795 else 796 ee->ee_noise_floor_thr[mode] = val & 0xff; 797 798 if (hal->ah_ee_version <= AR5K_EEPROM_VERSION_3_2) 799 ee->ee_noise_floor_thr[mode] = 800 mode == AR5K_EEPROM_MODE_11A ? -54 : -1; 801 802 AR5K_EEPROM_READ(o++, val); 803 ee->ee_xlna_gain[mode] = (val >> 5) & 0xff; 804 ee->ee_x_gain[mode] = (val >> 1) & 0xf; 805 ee->ee_xpd[mode] = val & 0x1; 806 807 if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) 808 ee->ee_fixed_bias[mode] = (val >> 13) & 0x1; 809 810 if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_3_3) { 811 AR5K_EEPROM_READ(o++, val); 812 ee->ee_false_detect[mode] = (val >> 6) & 0x7f; 813 814 if (mode == AR5K_EEPROM_MODE_11A) 815 ee->ee_xr_power[mode] = val & 0x3f; 816 else { 817 ee->ee_ob[mode][0] = val & 0x7; 818 ee->ee_db[mode][0] = (val >> 3) & 0x7; 819 } 820 } 821 822 if (hal->ah_ee_version < AR5K_EEPROM_VERSION_3_4) { 823 ee->ee_i_gain[mode] = AR5K_EEPROM_I_GAIN; 824 ee->ee_cck_ofdm_power_delta = AR5K_EEPROM_CCK_OFDM_DELTA; 825 } else { 826 ee->ee_i_gain[mode] = (val >> 13) & 0x7; 827 828 AR5K_EEPROM_READ(o++, val); 829 ee->ee_i_gain[mode] |= (val << 3) & 0x38; 830 831 if (mode == AR5K_EEPROM_MODE_11G) 832 ee->ee_cck_ofdm_power_delta = (val >> 3) & 0xff; 833 } 834 835 if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0 && 836 mode == AR5K_EEPROM_MODE_11A) { 837 ee->ee_i_cal[mode] = (val >> 8) & 0x3f; 838 ee->ee_q_cal[mode] = (val >> 3) & 0x1f; 839 } 840 841 if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_6 && 842 mode == AR5K_EEPROM_MODE_11G) 843 ee->ee_scaled_cck_delta = (val >> 11) & 0x1f; 844 845 /* return new offset */ 846 *offset = o; 847 848 return (0); 849 } 850 851 int 852 ar5k_eeprom_init(struct ath_hal *hal) 853 { 854 struct ar5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; 855 u_int32_t offset; 856 u_int16_t val; 857 int ret, i; 858 u_int mode; 859 860 /* Initial TX thermal adjustment values */ 861 ee->ee_tx_clip = 4; 862 ee->ee_pwd_84 = ee->ee_pwd_90 = 1; 863 ee->ee_gain_select = 1; 864 865 /* 866 * Read values from EEPROM and store them in the capability structure 867 */ 868 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MAGIC, ee_magic); 869 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_PROTECT, ee_protect); 870 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_REG_DOMAIN, ee_regdomain); 871 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_VERSION, ee_version); 872 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_HDR, ee_header); 873 874 /* Return if we have an old EEPROM */ 875 if (hal->ah_ee_version < AR5K_EEPROM_VERSION_3_0) 876 return (0); 877 878 #ifdef notyet 879 /* 880 * Validate the checksum of the EEPROM date. There are some 881 * devices with invalid EEPROMs. 882 */ 883 for (cksum = 0, offset = 0; offset < AR5K_EEPROM_INFO_MAX; offset++) { 884 AR5K_EEPROM_READ(AR5K_EEPROM_INFO(offset), val); 885 cksum ^= val; 886 } 887 if (cksum != AR5K_EEPROM_INFO_CKSUM) { 888 AR5K_PRINTF("Invalid EEPROM checksum 0x%04x\n", cksum); 889 return (EINVAL); 890 } 891 #endif 892 893 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_ANT_GAIN(hal->ah_ee_version), 894 ee_ant_gain); 895 896 if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) { 897 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC0, ee_misc0); 898 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC1, ee_misc1); 899 } 900 901 if (hal->ah_ee_version < AR5K_EEPROM_VERSION_3_3) { 902 AR5K_EEPROM_READ(AR5K_EEPROM_OBDB0_2GHZ, val); 903 ee->ee_ob[AR5K_EEPROM_MODE_11B][0] = val & 0x7; 904 ee->ee_db[AR5K_EEPROM_MODE_11B][0] = (val >> 3) & 0x7; 905 906 AR5K_EEPROM_READ(AR5K_EEPROM_OBDB1_2GHZ, val); 907 ee->ee_ob[AR5K_EEPROM_MODE_11G][0] = val & 0x7; 908 ee->ee_db[AR5K_EEPROM_MODE_11G][0] = (val >> 3) & 0x7; 909 } 910 911 /* 912 * Get conformance test limit values 913 */ 914 offset = AR5K_EEPROM_CTL(hal->ah_ee_version); 915 ee->ee_ctls = AR5K_EEPROM_N_CTLS(hal->ah_ee_version); 916 917 for (i = 0; i < ee->ee_ctls; i++) { 918 AR5K_EEPROM_READ(offset++, val); 919 ee->ee_ctl[i] = (val >> 8) & 0xff; 920 ee->ee_ctl[i + 1] = val & 0xff; 921 } 922 923 /* 924 * Get values for 802.11a (5GHz) 925 */ 926 mode = AR5K_EEPROM_MODE_11A; 927 928 ee->ee_turbo_max_power[mode] = 929 AR5K_EEPROM_HDR_T_5GHZ_DBM(ee->ee_header); 930 931 offset = AR5K_EEPROM_MODES_11A(hal->ah_ee_version); 932 933 if ((ret = ar5k_eeprom_read_ants(hal, &offset, mode)) != 0) 934 return (ret); 935 936 AR5K_EEPROM_READ(offset++, val); 937 ee->ee_adc_desired_size[mode] = (int8_t)((val >> 8) & 0xff); 938 ee->ee_ob[mode][3] = (val >> 5) & 0x7; 939 ee->ee_db[mode][3] = (val >> 2) & 0x7; 940 ee->ee_ob[mode][2] = (val << 1) & 0x7; 941 942 AR5K_EEPROM_READ(offset++, val); 943 ee->ee_ob[mode][2] |= (val >> 15) & 0x1; 944 ee->ee_db[mode][2] = (val >> 12) & 0x7; 945 ee->ee_ob[mode][1] = (val >> 9) & 0x7; 946 ee->ee_db[mode][1] = (val >> 6) & 0x7; 947 ee->ee_ob[mode][0] = (val >> 3) & 0x7; 948 ee->ee_db[mode][0] = val & 0x7; 949 950 if ((ret = ar5k_eeprom_read_modes(hal, &offset, mode)) != 0) 951 return (ret); 952 953 if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) { 954 AR5K_EEPROM_READ(offset++, val); 955 ee->ee_margin_tx_rx[mode] = val & 0x3f; 956 } 957 958 /* 959 * Get values for 802.11b (2.4GHz) 960 */ 961 mode = AR5K_EEPROM_MODE_11B; 962 offset = AR5K_EEPROM_MODES_11B(hal->ah_ee_version); 963 964 if ((ret = ar5k_eeprom_read_ants(hal, &offset, mode)) != 0) 965 return (ret); 966 967 AR5K_EEPROM_READ(offset++, val); 968 ee->ee_adc_desired_size[mode] = (int8_t)((val >> 8) & 0xff); 969 ee->ee_ob[mode][1] = (val >> 4) & 0x7; 970 ee->ee_db[mode][1] = val & 0x7; 971 972 if ((ret = ar5k_eeprom_read_modes(hal, &offset, mode)) != 0) 973 return (ret); 974 975 if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) { 976 AR5K_EEPROM_READ(offset++, val); 977 ee->ee_cal_pier[mode][0] = 978 ar5k_eeprom_bin2freq(hal, val & 0xff, mode); 979 ee->ee_cal_pier[mode][1] = 980 ar5k_eeprom_bin2freq(hal, (val >> 8) & 0xff, mode); 981 982 AR5K_EEPROM_READ(offset++, val); 983 ee->ee_cal_pier[mode][2] = 984 ar5k_eeprom_bin2freq(hal, val & 0xff, mode); 985 } 986 987 if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) { 988 ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f; 989 } 990 991 /* 992 * Get values for 802.11g (2.4GHz) 993 */ 994 mode = AR5K_EEPROM_MODE_11G; 995 offset = AR5K_EEPROM_MODES_11G(hal->ah_ee_version); 996 997 if ((ret = ar5k_eeprom_read_ants(hal, &offset, mode)) != 0) 998 return (ret); 999 1000 AR5K_EEPROM_READ(offset++, val); 1001 ee->ee_adc_desired_size[mode] = (int8_t)((val >> 8) & 0xff); 1002 ee->ee_ob[mode][1] = (val >> 4) & 0x7; 1003 ee->ee_db[mode][1] = val & 0x7; 1004 1005 if ((ret = ar5k_eeprom_read_modes(hal, &offset, mode)) != 0) 1006 return (ret); 1007 1008 if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) { 1009 AR5K_EEPROM_READ(offset++, val); 1010 ee->ee_cal_pier[mode][0] = 1011 ar5k_eeprom_bin2freq(hal, val & 0xff, mode); 1012 ee->ee_cal_pier[mode][1] = 1013 ar5k_eeprom_bin2freq(hal, (val >> 8) & 0xff, mode); 1014 1015 AR5K_EEPROM_READ(offset++, val); 1016 ee->ee_turbo_max_power[mode] = val & 0x7f; 1017 ee->ee_xr_power[mode] = (val >> 7) & 0x3f; 1018 1019 AR5K_EEPROM_READ(offset++, val); 1020 ee->ee_cal_pier[mode][2] = 1021 ar5k_eeprom_bin2freq(hal, val & 0xff, mode); 1022 1023 if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) { 1024 ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f; 1025 } 1026 1027 AR5K_EEPROM_READ(offset++, val); 1028 ee->ee_i_cal[mode] = (val >> 8) & 0x3f; 1029 ee->ee_q_cal[mode] = (val >> 3) & 0x1f; 1030 1031 if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_2) { 1032 AR5K_EEPROM_READ(offset++, val); 1033 ee->ee_cck_ofdm_gain_delta = val & 0xff; 1034 } 1035 } 1036 1037 /* 1038 * Read 5GHz EEPROM channels 1039 */ 1040 1041 return (0); 1042 } 1043 1044 int 1045 ar5k_eeprom_read_mac(struct ath_hal *hal, u_int8_t *mac) 1046 { 1047 u_int32_t total, offset; 1048 u_int16_t data; 1049 int octet; 1050 u_int8_t mac_d[IEEE80211_ADDR_LEN]; 1051 1052 bzero(mac, IEEE80211_ADDR_LEN); 1053 bzero(&mac_d, IEEE80211_ADDR_LEN); 1054 1055 if (hal->ah_eeprom_read(hal, 0x20, &data) != 0) 1056 return (EIO); 1057 1058 for (offset = 0x1f, octet = 0, total = 0; 1059 offset >= 0x1d; offset--) { 1060 if (hal->ah_eeprom_read(hal, offset, &data) != 0) 1061 return (EIO); 1062 1063 total += data; 1064 mac_d[octet + 1] = data & 0xff; 1065 mac_d[octet] = data >> 8; 1066 octet += 2; 1067 } 1068 1069 bcopy(mac_d, mac, IEEE80211_ADDR_LEN); 1070 1071 if ((!total) || total == (3 * 0xffff)) 1072 return (EINVAL); 1073 1074 return (0); 1075 } 1076 1077 HAL_BOOL 1078 ar5k_eeprom_regulation_domain(struct ath_hal *hal, HAL_BOOL write, 1079 ieee80211_regdomain_t *regdomain) 1080 { 1081 u_int16_t ee_regdomain; 1082 1083 /* Read current value */ 1084 if (write != AH_TRUE) { 1085 ee_regdomain = hal->ah_capabilities.cap_eeprom.ee_regdomain; 1086 *regdomain = ar5k_regdomain_to_ieee(ee_regdomain); 1087 return (AH_TRUE); 1088 } 1089 1090 ee_regdomain = ar5k_regdomain_from_ieee(*regdomain); 1091 1092 /* Try to write a new value */ 1093 if (hal->ah_capabilities.cap_eeprom.ee_protect & 1094 AR5K_EEPROM_PROTECT_WR_128_191) 1095 return (AH_FALSE); 1096 if (hal->ah_eeprom_write(hal, AR5K_EEPROM_REG_DOMAIN, 1097 ee_regdomain) != 0) 1098 return (AH_FALSE); 1099 1100 hal->ah_capabilities.cap_eeprom.ee_regdomain = ee_regdomain; 1101 1102 return (AH_TRUE); 1103 } 1104 1105 /* 1106 * PHY/RF access functions 1107 */ 1108 1109 HAL_BOOL 1110 ar5k_channel(struct ath_hal *hal, HAL_CHANNEL *channel) 1111 { 1112 HAL_BOOL ret; 1113 1114 /* 1115 * Check bounds supported by the PHY 1116 * (don't care about regulation restrictions at this point) 1117 */ 1118 if ((channel->channel < hal->ah_capabilities.cap_range.range_2ghz_min || 1119 channel->channel > hal->ah_capabilities.cap_range.range_2ghz_max) && 1120 (channel->channel < hal->ah_capabilities.cap_range.range_5ghz_min || 1121 channel->channel > hal->ah_capabilities.cap_range.range_5ghz_max)) { 1122 AR5K_PRINTF("channel out of supported range (%u MHz)\n", 1123 channel->channel); 1124 return (AH_FALSE); 1125 } 1126 1127 /* 1128 * Set the channel and wait 1129 */ 1130 if (hal->ah_radio == AR5K_AR5110) 1131 ret = ar5k_ar5110_channel(hal, channel); 1132 else if (hal->ah_radio == AR5K_AR5111) 1133 ret = ar5k_ar5111_channel(hal, channel); 1134 else 1135 ret = ar5k_ar5112_channel(hal, channel); 1136 1137 if (ret == AH_FALSE) 1138 return (ret); 1139 1140 hal->ah_current_channel.c_channel = channel->c_channel; 1141 hal->ah_current_channel.c_channel_flags = channel->c_channel_flags; 1142 hal->ah_turbo = channel->c_channel_flags == CHANNEL_T ? 1143 AH_TRUE : AH_FALSE; 1144 1145 return (AH_TRUE); 1146 } 1147 1148 u_int32_t 1149 ar5k_ar5110_chan2athchan(HAL_CHANNEL *channel) 1150 { 1151 u_int32_t athchan; 1152 1153 /* 1154 * Convert IEEE channel/MHz to an internal channel value used 1155 * by the AR5210 chipset. This has not been verified with 1156 * newer chipsets like the AR5212A who have a completely 1157 * different RF/PHY part. 1158 */ 1159 athchan = (ar5k_bitswap((ieee80211_mhz2ieee(channel->c_channel, 1160 channel->c_channel_flags) - 24) / 2, 5) << 1) | 1161 (1 << 6) | 0x1; 1162 1163 return (athchan); 1164 } 1165 1166 HAL_BOOL 1167 ar5k_ar5110_channel(struct ath_hal *hal, HAL_CHANNEL *channel) 1168 { 1169 u_int32_t data; 1170 1171 /* 1172 * Set the channel and wait 1173 */ 1174 data = ar5k_ar5110_chan2athchan(channel); 1175 AR5K_PHY_WRITE(0x27, data); 1176 AR5K_PHY_WRITE(0x30, 0); 1177 AR5K_DELAY(1000); 1178 1179 return (AH_TRUE); 1180 } 1181 1182 HAL_BOOL 1183 ar5k_ar5111_chan2athchan(u_int ieee, struct ar5k_athchan_2ghz *athchan) 1184 { 1185 int channel; 1186 1187 /* Cast this value to catch negative channel numbers (>= -19) */ 1188 channel = (int)ieee; 1189 1190 /* 1191 * Map 2GHz IEEE channel to 5GHz Atheros channel 1192 */ 1193 if (channel <= 13) { 1194 athchan->a2_athchan = 115 + channel; 1195 athchan->a2_flags = 0x46; 1196 } else if (channel == 14) { 1197 athchan->a2_athchan = 124; 1198 athchan->a2_flags = 0x44; 1199 } else if (channel >= 15 && channel <= 26) { 1200 athchan->a2_athchan = ((channel - 14) * 4) + 132; 1201 athchan->a2_flags = 0x46; 1202 } else 1203 return (AH_FALSE); 1204 1205 return (AH_TRUE); 1206 } 1207 1208 HAL_BOOL 1209 ar5k_ar5111_channel(struct ath_hal *hal, HAL_CHANNEL *channel) 1210 { 1211 u_int ieee_channel, ath_channel; 1212 u_int32_t data0, data1, clock; 1213 struct ar5k_athchan_2ghz ath_channel_2ghz; 1214 1215 /* 1216 * Set the channel on the AR5111 radio 1217 */ 1218 data0 = data1 = 0; 1219 ath_channel = ieee_channel = ieee80211_mhz2ieee(channel->c_channel, 1220 channel->c_channel_flags); 1221 1222 if (channel->c_channel_flags & IEEE80211_CHAN_2GHZ) { 1223 /* Map 2GHz channel to 5GHz Atheros channel ID */ 1224 if (ar5k_ar5111_chan2athchan(ieee_channel, 1225 &ath_channel_2ghz) == AH_FALSE) 1226 return (AH_FALSE); 1227 1228 ath_channel = ath_channel_2ghz.a2_athchan; 1229 data0 = ((ar5k_bitswap(ath_channel_2ghz.a2_flags, 8) & 0xff) 1230 << 5) | (1 << 4); 1231 } 1232 1233 if (ath_channel < 145 || !(ath_channel & 1)) { 1234 clock = 1; 1235 data1 = ((ar5k_bitswap(ath_channel - 24, 8) & 0xff) << 2) 1236 | (clock << 1) | (1 << 10) | 1; 1237 } else { 1238 clock = 0; 1239 data1 = ((ar5k_bitswap((ath_channel - 24) / 2, 8) & 0xff) << 2) 1240 | (clock << 1) | (1 << 10) | 1; 1241 } 1242 1243 AR5K_PHY_WRITE(0x27, (data1 & 0xff) | ((data0 & 0xff) << 8)); 1244 AR5K_PHY_WRITE(0x34, ((data1 >> 8) & 0xff) | (data0 & 0xff00)); 1245 1246 return (AH_TRUE); 1247 } 1248 1249 HAL_BOOL 1250 ar5k_ar5112_channel(struct ath_hal *hal, HAL_CHANNEL *channel) 1251 { 1252 u_int32_t data, data0, data1, data2; 1253 u_int16_t c; 1254 1255 data = data0 = data1 = data2 = 0; 1256 c = channel->c_channel + hal->ah_chanoff; 1257 1258 /* 1259 * Set the channel on the AR5112 or newer 1260 */ 1261 if (c < 4800) { 1262 if (!((c - 2224) % 5)) { 1263 data0 = ((2 * (c - 704)) - 3040) / 10; 1264 data1 = 1; 1265 } else if (!((c - 2192) % 5)) { 1266 data0 = ((2 * (c - 672)) - 3040) / 10; 1267 data1 = 0; 1268 } else 1269 return (AH_FALSE); 1270 1271 data0 = ar5k_bitswap((data0 << 2) & 0xff, 8); 1272 } else { 1273 if (!(c % 20) && c >= 5120) { 1274 data0 = ar5k_bitswap(((c - 4800) / 20 << 2), 8); 1275 data2 = ar5k_bitswap(3, 2); 1276 } else if (!(c % 10)) { 1277 data0 = ar5k_bitswap(((c - 4800) / 10 << 1), 8); 1278 data2 = ar5k_bitswap(2, 2); 1279 } else if (!(c % 5)) { 1280 data0 = ar5k_bitswap((c - 4800) / 5, 8); 1281 data2 = ar5k_bitswap(1, 2); 1282 } else 1283 return (AH_FALSE); 1284 } 1285 1286 data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001; 1287 1288 AR5K_PHY_WRITE(0x27, data & 0xff); 1289 AR5K_PHY_WRITE(0x36, (data >> 8) & 0x7f); 1290 1291 return (AH_TRUE); 1292 } 1293 1294 u_int 1295 ar5k_rfregs_op(u_int32_t *rf, u_int32_t offset, u_int32_t reg, u_int32_t bits, 1296 u_int32_t first, u_int32_t col, HAL_BOOL set) 1297 { 1298 u_int32_t mask, entry, last, data, shift, position; 1299 int32_t left; 1300 int i; 1301 1302 if (rf == NULL) { 1303 /* should not happen */ 1304 return (0); 1305 } 1306 1307 if (!(col <= 3 && bits <= 32 && first + bits <= 319)) { 1308 AR5K_PRINTF("invalid values at offset %u\n", offset); 1309 return (0); 1310 } 1311 1312 entry = ((first - 1) / 8) + offset; 1313 position = (first - 1) % 8; 1314 1315 if (set == AH_TRUE) 1316 data = ar5k_bitswap(reg, bits); 1317 1318 for (i = shift = 0, left = bits; left > 0; position = 0, entry++, i++) { 1319 last = (position + left > 8) ? 8 : position + left; 1320 mask = (((1 << last) - 1) ^ ((1 << position) - 1)) << 1321 (col * 8); 1322 1323 if (set == AH_TRUE) { 1324 rf[entry] &= ~mask; 1325 rf[entry] |= ((data << position) << (col * 8)) & mask; 1326 data >>= (8 - position); 1327 } else { 1328 data = (((rf[entry] & mask) >> (col * 8)) >> 1329 position) << shift; 1330 shift += last - position; 1331 } 1332 1333 left -= 8 - position; 1334 } 1335 1336 data = set == AH_TRUE ? 1 : ar5k_bitswap(data, bits); 1337 1338 return (data); 1339 } 1340 1341 u_int32_t 1342 ar5k_rfregs_gainf_corr(struct ath_hal *hal) 1343 { 1344 u_int32_t mix, step; 1345 u_int32_t *rf; 1346 1347 if (hal->ah_rf_banks == NULL) 1348 return (0); 1349 1350 rf = hal->ah_rf_banks; 1351 hal->ah_gain.g_f_corr = 0; 1352 1353 if (ar5k_rfregs_op(rf, hal->ah_offset[7], 0, 1, 36, 0, AH_FALSE) != 1) 1354 return (0); 1355 1356 step = ar5k_rfregs_op(rf, hal->ah_offset[7], 0, 4, 32, 0, AH_FALSE); 1357 mix = hal->ah_gain.g_step->gos_param[0]; 1358 1359 switch (mix) { 1360 case 3: 1361 hal->ah_gain.g_f_corr = step * 2; 1362 break; 1363 case 2: 1364 hal->ah_gain.g_f_corr = (step - 5) * 2; 1365 break; 1366 case 1: 1367 hal->ah_gain.g_f_corr = step; 1368 break; 1369 default: 1370 hal->ah_gain.g_f_corr = 0; 1371 break; 1372 } 1373 1374 return (hal->ah_gain.g_f_corr); 1375 } 1376 1377 HAL_BOOL 1378 ar5k_rfregs_gain_readback(struct ath_hal *hal) 1379 { 1380 u_int32_t step, mix, level[4]; 1381 u_int32_t *rf; 1382 1383 if (hal->ah_rf_banks == NULL) 1384 return (0); 1385 1386 rf = hal->ah_rf_banks; 1387 1388 if (hal->ah_radio == AR5K_AR5111) { 1389 step = ar5k_rfregs_op(rf, hal->ah_offset[7], 1390 0, 6, 37, 0, AH_FALSE); 1391 level[0] = 0; 1392 level[1] = (step == 0x3f) ? 0x32 : step + 4; 1393 level[2] = (step != 0x3f) ? 0x40 : level[0]; 1394 level[3] = level[2] + 0x32; 1395 1396 hal->ah_gain.g_high = level[3] - 1397 (step == 0x3f ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5); 1398 hal->ah_gain.g_low = level[0] + 1399 (step == 0x3f ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0); 1400 } else { 1401 mix = ar5k_rfregs_op(rf, hal->ah_offset[7], 1402 0, 1, 36, 0, AH_FALSE); 1403 level[0] = level[2] = 0; 1404 1405 if (mix == 1) { 1406 level[1] = level[3] = 83; 1407 } else { 1408 level[1] = level[3] = 107; 1409 hal->ah_gain.g_high = 55; 1410 } 1411 } 1412 1413 return ((hal->ah_gain.g_current >= level[0] && 1414 hal->ah_gain.g_current <= level[1]) || 1415 (hal->ah_gain.g_current >= level[2] && 1416 hal->ah_gain.g_current <= level[3])); 1417 } 1418 1419 int32_t 1420 ar5k_rfregs_gain_adjust(struct ath_hal *hal) 1421 { 1422 int ret = 0; 1423 const struct ar5k_gain_opt *go; 1424 1425 go = hal->ah_radio == AR5K_AR5111 ? 1426 &ar5111_gain_opt : &ar5112_gain_opt; 1427 1428 hal->ah_gain.g_step = &go->go_step[hal->ah_gain.g_step_idx]; 1429 1430 if (hal->ah_gain.g_current >= hal->ah_gain.g_high) { 1431 if (hal->ah_gain.g_step_idx == 0) 1432 return (-1); 1433 for (hal->ah_gain.g_target = hal->ah_gain.g_current; 1434 hal->ah_gain.g_target >= hal->ah_gain.g_high && 1435 hal->ah_gain.g_step_idx > 0; 1436 hal->ah_gain.g_step = 1437 &go->go_step[hal->ah_gain.g_step_idx]) { 1438 hal->ah_gain.g_target -= 2 * 1439 (go->go_step[--(hal->ah_gain.g_step_idx)].gos_gain - 1440 hal->ah_gain.g_step->gos_gain); 1441 } 1442 1443 ret = 1; 1444 goto done; 1445 } 1446 1447 if (hal->ah_gain.g_current <= hal->ah_gain.g_low) { 1448 if (hal->ah_gain.g_step_idx == (go->go_steps_count - 1)) 1449 return (-2); 1450 for (hal->ah_gain.g_target = hal->ah_gain.g_current; 1451 hal->ah_gain.g_target <= hal->ah_gain.g_low && 1452 hal->ah_gain.g_step_idx < (go->go_steps_count - 1); 1453 hal->ah_gain.g_step = 1454 &go->go_step[hal->ah_gain.g_step_idx]) { 1455 hal->ah_gain.g_target -= 2 * 1456 (go->go_step[++(hal->ah_gain.g_step_idx)].gos_gain - 1457 hal->ah_gain.g_step->gos_gain); 1458 } 1459 1460 ret = 2; 1461 goto done; 1462 } 1463 1464 done: 1465 #ifdef AR5K_DEBUG 1466 AR5K_PRINTF("ret %d, gain step %u, current gain %u, target gain %u\n", 1467 ret, 1468 hal->ah_gain.g_step_idx, 1469 hal->ah_gain.g_current, 1470 hal->ah_gain.g_target); 1471 #endif 1472 1473 return (ret); 1474 } 1475 1476 HAL_BOOL 1477 ar5k_rfregs(struct ath_hal *hal, HAL_CHANNEL *channel, u_int mode) 1478 { 1479 ar5k_rfgain_t *func = NULL; 1480 HAL_BOOL ret; 1481 1482 switch (hal->ah_radio) { 1483 case AR5K_AR5111: 1484 hal->ah_rf_banks_size = sizeof(ar5111_rf); 1485 func = ar5k_ar5111_rfregs; 1486 break; 1487 case AR5K_AR5112: 1488 if (hal->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) 1489 hal->ah_rf_banks_size = sizeof(ar5112a_rf); 1490 else 1491 hal->ah_rf_banks_size = sizeof(ar5112_rf); 1492 func = ar5k_ar5112_rfregs; 1493 break; 1494 case AR5K_AR5413: 1495 hal->ah_rf_banks_size = sizeof(ar5413_rf); 1496 func = ar5k_arxxxx_rfregs; 1497 break; 1498 case AR5K_AR2413: 1499 hal->ah_rf_banks_size = sizeof(ar2413_rf); 1500 func = ar5k_arxxxx_rfregs; 1501 break; 1502 case AR5K_AR2425: 1503 hal->ah_rf_banks_size = sizeof(ar2425_rf); 1504 func = ar5k_arxxxx_rfregs; 1505 break; 1506 default: 1507 return (AH_FALSE); 1508 } 1509 1510 if (hal->ah_rf_banks == NULL) { 1511 /* XXX do extra checks? */ 1512 if ((hal->ah_rf_banks = malloc(hal->ah_rf_banks_size, 1513 M_DEVBUF, M_NOWAIT | M_ZERO)) == NULL) { 1514 AR5K_PRINT("out of memory\n"); 1515 return (AH_FALSE); 1516 } 1517 } 1518 1519 ret = (func)(hal, channel, mode); 1520 1521 if (ret == AH_TRUE) 1522 hal->ah_rf_gain = HAL_RFGAIN_INACTIVE; 1523 1524 return (ret); 1525 } 1526 1527 HAL_BOOL 1528 ar5k_ar5111_rfregs(struct ath_hal *hal, HAL_CHANNEL *channel, u_int mode) 1529 { 1530 struct ar5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; 1531 const u_int rf_size = AR5K_ELEMENTS(ar5111_rf); 1532 u_int32_t *rf; 1533 int i, obdb = -1, bank = -1; 1534 u_int32_t ee_mode; 1535 1536 AR5K_ASSERT_ENTRY(mode, AR5K_INI_VAL_MAX); 1537 1538 rf = hal->ah_rf_banks; 1539 1540 /* Copy values to modify them */ 1541 for (i = 0; i < rf_size; i++) { 1542 if (ar5111_rf[i].rf_bank >= 1543 AR5K_AR5111_INI_RF_MAX_BANKS) { 1544 AR5K_PRINT("invalid bank\n"); 1545 return (AH_FALSE); 1546 } 1547 1548 if (bank != ar5111_rf[i].rf_bank) { 1549 bank = ar5111_rf[i].rf_bank; 1550 hal->ah_offset[bank] = i; 1551 } 1552 1553 rf[i] = ar5111_rf[i].rf_value[mode]; 1554 } 1555 1556 if (channel->c_channel_flags & IEEE80211_CHAN_2GHZ) { 1557 if ((channel->c_channel_flags & IEEE80211_CHAN_G) == 1558 IEEE80211_CHAN_G) 1559 ee_mode = AR5K_EEPROM_MODE_11G; 1560 else 1561 ee_mode = AR5K_EEPROM_MODE_11B; 1562 obdb = 0; 1563 1564 if (!ar5k_rfregs_op(rf, hal->ah_offset[0], 1565 ee->ee_ob[ee_mode][obdb], 3, 119, 0, AH_TRUE)) 1566 return (AH_FALSE); 1567 1568 if (!ar5k_rfregs_op(rf, hal->ah_offset[0], 1569 ee->ee_ob[ee_mode][obdb], 3, 122, 0, AH_TRUE)) 1570 return (AH_FALSE); 1571 1572 obdb = 1; 1573 } else { 1574 /* For 11a, Turbo and XR */ 1575 ee_mode = AR5K_EEPROM_MODE_11A; 1576 obdb = channel->c_channel >= 5725 ? 3 : 1577 (channel->c_channel >= 5500 ? 2 : 1578 (channel->c_channel >= 5260 ? 1 : 1579 (channel->c_channel > 4000 ? 0 : -1))); 1580 1581 if (!ar5k_rfregs_op(rf, hal->ah_offset[6], 1582 ee->ee_pwd_84, 1, 51, 3, AH_TRUE)) 1583 return (AH_FALSE); 1584 1585 if (!ar5k_rfregs_op(rf, hal->ah_offset[6], 1586 ee->ee_pwd_90, 1, 45, 3, AH_TRUE)) 1587 return (AH_FALSE); 1588 } 1589 1590 if (!ar5k_rfregs_op(rf, hal->ah_offset[6], 1591 !ee->ee_xpd[ee_mode], 1, 95, 0, AH_TRUE)) 1592 return (AH_FALSE); 1593 1594 if (!ar5k_rfregs_op(rf, hal->ah_offset[6], 1595 ee->ee_x_gain[ee_mode], 4, 96, 0, AH_TRUE)) 1596 return (AH_FALSE); 1597 1598 if (!ar5k_rfregs_op(rf, hal->ah_offset[6], 1599 obdb >= 0 ? ee->ee_ob[ee_mode][obdb] : 0, 3, 104, 0, AH_TRUE)) 1600 return (AH_FALSE); 1601 1602 if (!ar5k_rfregs_op(rf, hal->ah_offset[6], 1603 obdb >= 0 ? ee->ee_db[ee_mode][obdb] : 0, 3, 107, 0, AH_TRUE)) 1604 return (AH_FALSE); 1605 1606 if (!ar5k_rfregs_op(rf, hal->ah_offset[7], 1607 ee->ee_i_gain[ee_mode], 6, 29, 0, AH_TRUE)) 1608 return (AH_FALSE); 1609 1610 if (!ar5k_rfregs_op(rf, hal->ah_offset[7], 1611 ee->ee_xpd[ee_mode], 1, 4, 0, AH_TRUE)) 1612 return (AH_FALSE); 1613 1614 /* Write RF values */ 1615 for (i = 0; i < rf_size; i++) { 1616 AR5K_REG_WAIT(i); 1617 AR5K_REG_WRITE(ar5111_rf[i].rf_register, rf[i]); 1618 } 1619 1620 return (AH_TRUE); 1621 } 1622 1623 HAL_BOOL 1624 ar5k_ar5112_rfregs(struct ath_hal *hal, HAL_CHANNEL *channel, u_int mode) 1625 { 1626 struct ar5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; 1627 u_int rf_size; 1628 u_int32_t *rf; 1629 int i, obdb = -1, bank = -1; 1630 u_int32_t ee_mode; 1631 const struct ar5k_ini_rf *rf_ini; 1632 1633 AR5K_ASSERT_ENTRY(mode, AR5K_INI_VAL_MAX); 1634 1635 rf = hal->ah_rf_banks; 1636 1637 if (hal->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) { 1638 rf_ini = ar5112a_rf; 1639 rf_size = AR5K_ELEMENTS(ar5112a_rf); 1640 } else { 1641 rf_ini = ar5112_rf; 1642 rf_size = AR5K_ELEMENTS(ar5112_rf); 1643 } 1644 1645 /* Copy values to modify them */ 1646 for (i = 0; i < rf_size; i++) { 1647 if (rf_ini[i].rf_bank >= 1648 AR5K_AR5112_INI_RF_MAX_BANKS) { 1649 AR5K_PRINT("invalid bank\n"); 1650 return (AH_FALSE); 1651 } 1652 1653 if (bank != rf_ini[i].rf_bank) { 1654 bank = rf_ini[i].rf_bank; 1655 hal->ah_offset[bank] = i; 1656 } 1657 1658 rf[i] = rf_ini[i].rf_value[mode]; 1659 } 1660 1661 if (channel->c_channel_flags & IEEE80211_CHAN_2GHZ) { 1662 if ((channel->c_channel_flags & IEEE80211_CHAN_G) == 1663 IEEE80211_CHAN_G) 1664 ee_mode = AR5K_EEPROM_MODE_11G; 1665 else 1666 ee_mode = AR5K_EEPROM_MODE_11B; 1667 obdb = 0; 1668 1669 if (!ar5k_rfregs_op(rf, hal->ah_offset[6], 1670 ee->ee_ob[ee_mode][obdb], 3, 287, 0, AH_TRUE)) 1671 return (AH_FALSE); 1672 1673 if (!ar5k_rfregs_op(rf, hal->ah_offset[6], 1674 ee->ee_ob[ee_mode][obdb], 3, 290, 0, AH_TRUE)) 1675 return (AH_FALSE); 1676 } else { 1677 /* For 11a, Turbo and XR */ 1678 ee_mode = AR5K_EEPROM_MODE_11A; 1679 obdb = channel->c_channel >= 5725 ? 3 : 1680 (channel->c_channel >= 5500 ? 2 : 1681 (channel->c_channel >= 5260 ? 1 : 1682 (channel->c_channel > 4000 ? 0 : -1))); 1683 1684 if (!ar5k_rfregs_op(rf, hal->ah_offset[6], 1685 ee->ee_ob[ee_mode][obdb], 3, 279, 0, AH_TRUE)) 1686 return (AH_FALSE); 1687 1688 if (!ar5k_rfregs_op(rf, hal->ah_offset[6], 1689 ee->ee_ob[ee_mode][obdb], 3, 282, 0, AH_TRUE)) 1690 return (AH_FALSE); 1691 } 1692 1693 #ifdef notyet 1694 ar5k_rfregs_op(rf, hal->ah_offset[6], 1695 ee->ee_x_gain[ee_mode], 2, 270, 0, AH_TRUE); 1696 ar5k_rfregs_op(rf, hal->ah_offset[6], 1697 ee->ee_x_gain[ee_mode], 2, 257, 0, AH_TRUE); 1698 #endif 1699 1700 if (!ar5k_rfregs_op(rf, hal->ah_offset[6], 1701 ee->ee_xpd[ee_mode], 1, 302, 0, AH_TRUE)) 1702 return (AH_FALSE); 1703 1704 if (!ar5k_rfregs_op(rf, hal->ah_offset[7], 1705 ee->ee_i_gain[ee_mode], 6, 14, 0, AH_TRUE)) 1706 return (AH_FALSE); 1707 1708 /* Write RF values */ 1709 for (i = 0; i < rf_size; i++) 1710 AR5K_REG_WRITE(rf_ini[i].rf_register, rf[i]); 1711 1712 return (AH_TRUE); 1713 } 1714 1715 HAL_BOOL 1716 ar5k_arxxxx_rfregs(struct ath_hal *hal, HAL_CHANNEL *channel, u_int mode) 1717 { 1718 const struct ar5k_ini_rf *rf_ini; 1719 u_int rf_size; 1720 u_int32_t *rf; 1721 int i, bank = -1; 1722 1723 AR5K_ASSERT_ENTRY(mode, AR5K_INI_VAL_MAX); 1724 1725 rf = hal->ah_rf_banks; 1726 1727 switch (hal->ah_radio) { 1728 case AR5K_AR5413: 1729 rf_ini = ar5413_rf; 1730 rf_size = AR5K_ELEMENTS(ar5413_rf); 1731 break; 1732 case AR5K_AR2413: 1733 rf_ini = ar2413_rf; 1734 rf_size = AR5K_ELEMENTS(ar2413_rf); 1735 break; 1736 case AR5K_AR2425: 1737 if (mode == AR5K_INI_VAL_11B) 1738 mode = AR5K_INI_VAL_11G; 1739 rf_ini = ar2425_rf; 1740 rf_size = AR5K_ELEMENTS(ar2425_rf); 1741 break; 1742 default: 1743 return (AH_FALSE); 1744 } 1745 1746 /* Copy values to modify them */ 1747 for (i = 0; i < rf_size; i++) { 1748 if (rf_ini[i].rf_bank >= AR5K_MAX_RF_BANKS) { 1749 AR5K_PRINT("invalid bank\n"); 1750 return (AH_FALSE); 1751 } 1752 1753 if (bank != rf_ini[i].rf_bank) { 1754 bank = rf_ini[i].rf_bank; 1755 hal->ah_offset[bank] = i; 1756 } 1757 1758 rf[i] = rf_ini[i].rf_value[mode]; 1759 } 1760 1761 /* Write RF values */ 1762 for (i = 0; i < rf_size; i++) 1763 AR5K_REG_WRITE(rf_ini[i].rf_register, rf[i]); 1764 1765 return (AH_TRUE); 1766 } 1767 1768 HAL_BOOL 1769 ar5k_rfgain(struct ath_hal *hal, u_int freq) 1770 { 1771 const struct ar5k_ini_rfgain *rfg; 1772 size_t rfg_size; 1773 int i; 1774 1775 switch (hal->ah_radio) { 1776 case AR5K_AR5111: 1777 rfg = ar5111_rfg; 1778 rfg_size = AR5K_ELEMENTS(ar5111_rfg); 1779 break; 1780 case AR5K_AR5112: 1781 rfg = ar5112_rfg; 1782 rfg_size = AR5K_ELEMENTS(ar5112_rfg); 1783 break; 1784 case AR5K_AR5413: 1785 rfg = ar5413_rfg; 1786 rfg_size = AR5K_ELEMENTS(ar5413_rfg); 1787 break; 1788 case AR5K_AR2413: 1789 case AR5K_AR2425: 1790 if (freq == AR5K_INI_RFGAIN_5GHZ) 1791 return (AH_FALSE); 1792 rfg = ar2413_rfg; 1793 rfg_size = AR5K_ELEMENTS(ar2413_rfg); 1794 break; 1795 default: 1796 return (AH_FALSE); 1797 } 1798 1799 switch (freq) { 1800 case AR5K_INI_RFGAIN_2GHZ: 1801 case AR5K_INI_RFGAIN_5GHZ: 1802 break; 1803 default: 1804 return (AH_FALSE); 1805 } 1806 1807 for (i = 0; i < rfg_size; i++) { 1808 AR5K_REG_WAIT(i); 1809 AR5K_REG_WRITE((u_int32_t)rfg[i].rfg_register, 1810 rfg[i].rfg_value[freq]); 1811 } 1812 1813 return (AH_TRUE); 1814 } 1815 1816 /* 1817 * Common TX power setup 1818 */ 1819 void 1820 ar5k_txpower_table(struct ath_hal *hal, HAL_CHANNEL *channel, int16_t max_power) 1821 { 1822 u_int16_t txpower, *rates; 1823 int i, min, max, n; 1824 1825 rates = hal->ah_txpower.txp_rates; 1826 1827 txpower = AR5K_TUNE_DEFAULT_TXPOWER * 2; 1828 if (max_power > txpower) { 1829 txpower = max_power > AR5K_TUNE_MAX_TXPOWER ? 1830 AR5K_TUNE_MAX_TXPOWER : max_power; 1831 } 1832 1833 for (i = 0; i < AR5K_MAX_RATES; i++) 1834 rates[i] = txpower; 1835 1836 /* XXX setup target powers by rate */ 1837 1838 hal->ah_txpower.txp_min = rates[7]; 1839 hal->ah_txpower.txp_max = rates[0]; 1840 hal->ah_txpower.txp_ofdm = rates[0]; 1841 1842 /* Calculate the power table */ 1843 n = AR5K_ELEMENTS(hal->ah_txpower.txp_pcdac); 1844 min = AR5K_EEPROM_PCDAC_START; 1845 max = AR5K_EEPROM_PCDAC_STOP; 1846 for (i = 0; i < n; i += AR5K_EEPROM_PCDAC_STEP) 1847 hal->ah_txpower.txp_pcdac[i] = 1848 #ifdef notyet 1849 min + ((i * (max - min)) / n); 1850 #else 1851 min; 1852 #endif 1853 } 1854 1855 void 1856 ar5k_write_ini(struct ath_hal *hal, const struct ar5k_ini *ini, 1857 size_t n, HAL_BOOL change_channel) 1858 { 1859 u_int i; 1860 1861 for (i = 0; i < n; i++) { 1862 if (change_channel == AH_TRUE && 1863 ini[i].ini_register >= AR5K_PCU_MIN && 1864 ini[i].ini_register <= AR5K_PCU_MAX) 1865 continue; 1866 switch (ini[i].ini_mode) { 1867 case AR5K_INI_READ: 1868 /* cleared on read */ 1869 AR5K_REG_READ((u_int32_t)ini[i].ini_register); 1870 break; 1871 case AR5K_INI_WRITE: 1872 AR5K_REG_WAIT(i); 1873 AR5K_REG_WRITE((u_int32_t)ini[i].ini_register, 1874 ini[i].ini_value); 1875 break; 1876 } 1877 } 1878 } 1879 1880 void 1881 ar5k_write_mode(struct ath_hal *hal, const struct ar5k_mode *ini, 1882 size_t n, u_int mode) 1883 { 1884 u_int i; 1885 1886 for (i = 0; i < n; i++) { 1887 AR5K_REG_WAIT(i); 1888 AR5K_REG_WRITE((u_int32_t)ini[i].mode_register, 1889 ini[i].mode_value[mode]); 1890 } 1891 } 1892