1 /* $OpenBSD: ar5211.c,v 1.44 2009/06/02 12:39:02 reyk Exp $ */ 2 3 /* 4 * Copyright (c) 2004, 2005, 2006, 2007 Reyk Floeter <reyk@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * HAL interface for the Atheros AR5001 Wireless LAN chipset 21 * (AR5211 + AR5111). 22 */ 23 24 #include <dev/ic/ar5xxx.h> 25 #include <dev/ic/ar5211reg.h> 26 #include <dev/ic/ar5211var.h> 27 28 HAL_BOOL ar5k_ar5211_nic_reset(struct ath_hal *, u_int32_t); 29 HAL_BOOL ar5k_ar5211_nic_wakeup(struct ath_hal *, u_int16_t); 30 u_int16_t ar5k_ar5211_radio_revision(struct ath_hal *, HAL_CHIP); 31 void ar5k_ar5211_fill(struct ath_hal *); 32 HAL_BOOL ar5k_ar5211_rfregs(struct ath_hal *, HAL_CHANNEL *, u_int, 33 u_int); 34 35 /* 36 * Initial register setting for the AR5211 37 */ 38 static const struct ar5k_ini ar5211_ini[] = 39 AR5K_AR5211_INI; 40 static const struct ar5k_ar5211_ini_mode ar5211_mode[] = 41 AR5K_AR5211_INI_MODE; 42 static const struct ar5k_ar5211_ini_rf ar5211_rf[] = 43 AR5K_AR5211_INI_RF; 44 45 AR5K_HAL_FUNCTIONS(extern, ar5k_ar5211,); 46 47 void 48 ar5k_ar5211_fill(struct ath_hal *hal) 49 { 50 hal->ah_magic = AR5K_AR5211_MAGIC; 51 52 /* 53 * Init/Exit functions 54 */ 55 AR5K_HAL_FUNCTION(hal, ar5211, get_rate_table); 56 AR5K_HAL_FUNCTION(hal, ar5211, detach); 57 58 /* 59 * Reset functions 60 */ 61 AR5K_HAL_FUNCTION(hal, ar5211, reset); 62 AR5K_HAL_FUNCTION(hal, ar5211, set_opmode); 63 AR5K_HAL_FUNCTION(hal, ar5211, calibrate); 64 65 /* 66 * TX functions 67 */ 68 AR5K_HAL_FUNCTION(hal, ar5211, update_tx_triglevel); 69 AR5K_HAL_FUNCTION(hal, ar5211, setup_tx_queue); 70 AR5K_HAL_FUNCTION(hal, ar5211, setup_tx_queueprops); 71 AR5K_HAL_FUNCTION(hal, ar5211, release_tx_queue); 72 AR5K_HAL_FUNCTION(hal, ar5211, reset_tx_queue); 73 AR5K_HAL_FUNCTION(hal, ar5211, get_tx_buf); 74 AR5K_HAL_FUNCTION(hal, ar5211, put_tx_buf); 75 AR5K_HAL_FUNCTION(hal, ar5211, tx_start); 76 AR5K_HAL_FUNCTION(hal, ar5211, stop_tx_dma); 77 AR5K_HAL_FUNCTION(hal, ar5211, setup_tx_desc); 78 AR5K_HAL_FUNCTION(hal, ar5211, setup_xtx_desc); 79 AR5K_HAL_FUNCTION(hal, ar5211, fill_tx_desc); 80 AR5K_HAL_FUNCTION(hal, ar5211, proc_tx_desc); 81 AR5K_HAL_FUNCTION(hal, ar5211, has_veol); 82 83 /* 84 * RX functions 85 */ 86 AR5K_HAL_FUNCTION(hal, ar5211, get_rx_buf); 87 AR5K_HAL_FUNCTION(hal, ar5211, put_rx_buf); 88 AR5K_HAL_FUNCTION(hal, ar5211, start_rx); 89 AR5K_HAL_FUNCTION(hal, ar5211, stop_rx_dma); 90 AR5K_HAL_FUNCTION(hal, ar5211, start_rx_pcu); 91 AR5K_HAL_FUNCTION(hal, ar5211, stop_pcu_recv); 92 AR5K_HAL_FUNCTION(hal, ar5211, set_mcast_filter); 93 AR5K_HAL_FUNCTION(hal, ar5211, set_mcast_filterindex); 94 AR5K_HAL_FUNCTION(hal, ar5211, clear_mcast_filter_idx); 95 AR5K_HAL_FUNCTION(hal, ar5211, get_rx_filter); 96 AR5K_HAL_FUNCTION(hal, ar5211, set_rx_filter); 97 AR5K_HAL_FUNCTION(hal, ar5211, setup_rx_desc); 98 AR5K_HAL_FUNCTION(hal, ar5211, proc_rx_desc); 99 AR5K_HAL_FUNCTION(hal, ar5211, set_rx_signal); 100 101 /* 102 * Misc functions 103 */ 104 AR5K_HAL_FUNCTION(hal, ar5211, dump_state); 105 AR5K_HAL_FUNCTION(hal, ar5211, get_diag_state); 106 AR5K_HAL_FUNCTION(hal, ar5211, get_lladdr); 107 AR5K_HAL_FUNCTION(hal, ar5211, set_lladdr); 108 AR5K_HAL_FUNCTION(hal, ar5211, set_regdomain); 109 AR5K_HAL_FUNCTION(hal, ar5211, set_ledstate); 110 AR5K_HAL_FUNCTION(hal, ar5211, set_associd); 111 AR5K_HAL_FUNCTION(hal, ar5211, set_gpio_input); 112 AR5K_HAL_FUNCTION(hal, ar5211, set_gpio_output); 113 AR5K_HAL_FUNCTION(hal, ar5211, get_gpio); 114 AR5K_HAL_FUNCTION(hal, ar5211, set_gpio); 115 AR5K_HAL_FUNCTION(hal, ar5211, set_gpio_intr); 116 AR5K_HAL_FUNCTION(hal, ar5211, get_tsf32); 117 AR5K_HAL_FUNCTION(hal, ar5211, get_tsf64); 118 AR5K_HAL_FUNCTION(hal, ar5211, reset_tsf); 119 AR5K_HAL_FUNCTION(hal, ar5211, get_regdomain); 120 AR5K_HAL_FUNCTION(hal, ar5211, detect_card_present); 121 AR5K_HAL_FUNCTION(hal, ar5211, update_mib_counters); 122 AR5K_HAL_FUNCTION(hal, ar5211, get_rf_gain); 123 AR5K_HAL_FUNCTION(hal, ar5211, set_slot_time); 124 AR5K_HAL_FUNCTION(hal, ar5211, get_slot_time); 125 AR5K_HAL_FUNCTION(hal, ar5211, set_ack_timeout); 126 AR5K_HAL_FUNCTION(hal, ar5211, get_ack_timeout); 127 AR5K_HAL_FUNCTION(hal, ar5211, set_cts_timeout); 128 AR5K_HAL_FUNCTION(hal, ar5211, get_cts_timeout); 129 130 /* 131 * Key table (WEP) functions 132 */ 133 AR5K_HAL_FUNCTION(hal, ar5211, is_cipher_supported); 134 AR5K_HAL_FUNCTION(hal, ar5211, get_keycache_size); 135 AR5K_HAL_FUNCTION(hal, ar5211, reset_key); 136 AR5K_HAL_FUNCTION(hal, ar5211, is_key_valid); 137 AR5K_HAL_FUNCTION(hal, ar5211, set_key); 138 AR5K_HAL_FUNCTION(hal, ar5211, set_key_lladdr); 139 AR5K_HAL_FUNCTION(hal, ar5211, softcrypto); 140 141 /* 142 * Power management functions 143 */ 144 AR5K_HAL_FUNCTION(hal, ar5211, set_power); 145 AR5K_HAL_FUNCTION(hal, ar5211, get_power_mode); 146 AR5K_HAL_FUNCTION(hal, ar5211, query_pspoll_support); 147 AR5K_HAL_FUNCTION(hal, ar5211, init_pspoll); 148 AR5K_HAL_FUNCTION(hal, ar5211, enable_pspoll); 149 AR5K_HAL_FUNCTION(hal, ar5211, disable_pspoll); 150 151 /* 152 * Beacon functions 153 */ 154 AR5K_HAL_FUNCTION(hal, ar5211, init_beacon); 155 AR5K_HAL_FUNCTION(hal, ar5211, set_beacon_timers); 156 AR5K_HAL_FUNCTION(hal, ar5211, reset_beacon); 157 AR5K_HAL_FUNCTION(hal, ar5211, wait_for_beacon); 158 159 /* 160 * Interrupt functions 161 */ 162 AR5K_HAL_FUNCTION(hal, ar5211, is_intr_pending); 163 AR5K_HAL_FUNCTION(hal, ar5211, get_isr); 164 AR5K_HAL_FUNCTION(hal, ar5211, get_intr); 165 AR5K_HAL_FUNCTION(hal, ar5211, set_intr); 166 167 /* 168 * Chipset functions (ar5k-specific, non-HAL) 169 */ 170 AR5K_HAL_FUNCTION(hal, ar5211, get_capabilities); 171 AR5K_HAL_FUNCTION(hal, ar5211, radar_alert); 172 173 /* 174 * EEPROM access 175 */ 176 AR5K_HAL_FUNCTION(hal, ar5211, eeprom_is_busy); 177 AR5K_HAL_FUNCTION(hal, ar5211, eeprom_read); 178 AR5K_HAL_FUNCTION(hal, ar5211, eeprom_write); 179 180 /* 181 * Unused functions or functions not implemented 182 */ 183 AR5K_HAL_FUNCTION(hal, ar5211, get_tx_queueprops); 184 AR5K_HAL_FUNCTION(hal, ar5211, num_tx_pending); 185 AR5K_HAL_FUNCTION(hal, ar5211, phy_disable); 186 AR5K_HAL_FUNCTION(hal, ar5211, set_txpower_limit); 187 AR5K_HAL_FUNCTION(hal, ar5211, set_def_antenna); 188 AR5K_HAL_FUNCTION(hal, ar5211, get_def_antenna); 189 AR5K_HAL_FUNCTION(hal, ar5211, set_bssid_mask); 190 #ifdef notyet 191 AR5K_HAL_FUNCTION(hal, ar5211, set_capability); 192 AR5K_HAL_FUNCTION(hal, ar5211, proc_mib_event); 193 AR5K_HAL_FUNCTION(hal, ar5211, get_tx_inter_queue); 194 #endif 195 } 196 197 struct ath_hal * 198 ar5k_ar5211_attach(u_int16_t device, void *sc, bus_space_tag_t st, 199 bus_space_handle_t sh, int *status) 200 { 201 struct ath_hal *hal = (struct ath_hal*) sc; 202 u_int8_t mac[IEEE80211_ADDR_LEN]; 203 u_int32_t srev; 204 205 ar5k_ar5211_fill(hal); 206 207 /* Bring device out of sleep and reset its units */ 208 if (ar5k_ar5211_nic_wakeup(hal, AR5K_INIT_MODE) != AH_TRUE) 209 return (NULL); 210 211 /* Get MAC, PHY and RADIO revisions */ 212 srev = AR5K_REG_READ(AR5K_AR5211_SREV); 213 hal->ah_mac_srev = srev; 214 hal->ah_mac_version = AR5K_REG_MS(srev, AR5K_AR5211_SREV_VER); 215 hal->ah_mac_revision = AR5K_REG_MS(srev, AR5K_AR5211_SREV_REV); 216 hal->ah_phy_revision = AR5K_REG_READ(AR5K_AR5211_PHY_CHIP_ID) & 217 0x00ffffffff; 218 hal->ah_radio_5ghz_revision = 219 ar5k_ar5211_radio_revision(hal, HAL_CHIP_5GHZ); 220 hal->ah_radio_2ghz_revision = 0; 221 222 /* Identify the chipset (this has to be done in an early step) */ 223 hal->ah_version = AR5K_AR5211; 224 hal->ah_radio = AR5K_AR5111; 225 hal->ah_phy = AR5K_AR5211_PHY(0); 226 227 bcopy(etherbroadcastaddr, mac, IEEE80211_ADDR_LEN); 228 ar5k_ar5211_set_associd(hal, mac, 0, 0); 229 ar5k_ar5211_get_lladdr(hal, mac); 230 ar5k_ar5211_set_opmode(hal); 231 232 return (hal); 233 } 234 235 HAL_BOOL 236 ar5k_ar5211_nic_reset(struct ath_hal *hal, u_int32_t val) 237 { 238 HAL_BOOL ret = AH_FALSE; 239 u_int32_t mask = val ? val : ~0; 240 241 /* Read-and-clear */ 242 AR5K_REG_READ(AR5K_AR5211_RXDP); 243 244 /* 245 * Reset the device and wait until success 246 */ 247 AR5K_REG_WRITE(AR5K_AR5211_RC, val); 248 249 /* Wait at least 128 PCI clocks */ 250 AR5K_DELAY(15); 251 252 val &= 253 AR5K_AR5211_RC_PCU | AR5K_AR5211_RC_BB; 254 255 mask &= 256 AR5K_AR5211_RC_PCU | AR5K_AR5211_RC_BB; 257 258 ret = ar5k_register_timeout(hal, AR5K_AR5211_RC, mask, val, AH_FALSE); 259 260 /* 261 * Reset configuration register 262 */ 263 if ((val & AR5K_AR5211_RC_PCU) == 0) 264 AR5K_REG_WRITE(AR5K_AR5211_CFG, AR5K_AR5211_INIT_CFG); 265 266 return (ret); 267 } 268 269 HAL_BOOL 270 ar5k_ar5211_nic_wakeup(struct ath_hal *hal, u_int16_t flags) 271 { 272 u_int32_t turbo, mode, clock; 273 274 turbo = 0; 275 mode = 0; 276 clock = 0; 277 278 /* 279 * Get channel mode flags 280 */ 281 282 if (flags & IEEE80211_CHAN_2GHZ) { 283 mode |= AR5K_AR5211_PHY_MODE_FREQ_2GHZ; 284 clock |= AR5K_AR5211_PHY_PLL_44MHZ; 285 } else if (flags & IEEE80211_CHAN_5GHZ) { 286 mode |= AR5K_AR5211_PHY_MODE_FREQ_5GHZ; 287 clock |= AR5K_AR5211_PHY_PLL_40MHZ; 288 } else { 289 AR5K_PRINT("invalid radio frequency mode\n"); 290 return (AH_FALSE); 291 } 292 293 if ((flags & IEEE80211_CHAN_CCK) || 294 (flags & IEEE80211_CHAN_DYN)) { 295 /* Dynamic OFDM/CCK is not supported by the AR5211 */ 296 mode |= AR5K_AR5211_PHY_MODE_MOD_CCK; 297 } else if (flags & IEEE80211_CHAN_OFDM) { 298 mode |= AR5K_AR5211_PHY_MODE_MOD_OFDM; 299 } else { 300 AR5K_PRINT("invalid radio frequency mode\n"); 301 return (AH_FALSE); 302 } 303 304 if (flags & IEEE80211_CHAN_TURBO) { 305 turbo = AR5K_AR5211_PHY_TURBO_MODE | 306 AR5K_AR5211_PHY_TURBO_SHORT; 307 } 308 309 /* 310 * Reset and wakeup the device 311 */ 312 313 /* ...reset chipset and PCI device */ 314 if (ar5k_ar5211_nic_reset(hal, 315 AR5K_AR5211_RC_CHIP | AR5K_AR5211_RC_PCI) == AH_FALSE) { 316 AR5K_PRINT("failed to reset the AR5211 + PCI chipset\n"); 317 return (AH_FALSE); 318 } 319 320 /* ...wakeup */ 321 if (ar5k_ar5211_set_power(hal, 322 HAL_PM_AWAKE, AH_TRUE, 0) == AH_FALSE) { 323 AR5K_PRINT("failed to resume the AR5211 (again)\n"); 324 return (AH_FALSE); 325 } 326 327 /* ...final warm reset */ 328 if (ar5k_ar5211_nic_reset(hal, 0) == AH_FALSE) { 329 AR5K_PRINT("failed to warm reset the AR5211\n"); 330 return (AH_FALSE); 331 } 332 333 /* ...set the PHY operating mode */ 334 AR5K_REG_WRITE(AR5K_AR5211_PHY_PLL, clock); 335 AR5K_DELAY(300); 336 337 AR5K_REG_WRITE(AR5K_AR5211_PHY_MODE, mode); 338 AR5K_REG_WRITE(AR5K_AR5211_PHY_TURBO, turbo); 339 340 return (AH_TRUE); 341 } 342 343 u_int16_t 344 ar5k_ar5211_radio_revision(struct ath_hal *hal, HAL_CHIP chip) 345 { 346 int i; 347 u_int32_t srev; 348 u_int16_t ret; 349 350 /* 351 * Set the radio chip access register 352 */ 353 switch (chip) { 354 case HAL_CHIP_2GHZ: 355 AR5K_REG_WRITE(AR5K_AR5211_PHY(0), AR5K_AR5211_PHY_SHIFT_2GHZ); 356 break; 357 case HAL_CHIP_5GHZ: 358 AR5K_REG_WRITE(AR5K_AR5211_PHY(0), AR5K_AR5211_PHY_SHIFT_5GHZ); 359 break; 360 default: 361 return (0); 362 } 363 364 AR5K_DELAY(2000); 365 366 /* ...wait until PHY is ready and read the selected radio revision */ 367 AR5K_REG_WRITE(AR5K_AR5211_PHY(0x34), 0x00001c16); 368 369 for (i = 0; i < 8; i++) 370 AR5K_REG_WRITE(AR5K_AR5211_PHY(0x20), 0x00010000); 371 srev = (AR5K_REG_READ(AR5K_AR5211_PHY(0x100)) >> 24) & 0xff; 372 373 ret = ar5k_bitswap(((srev & 0xf0) >> 4) | ((srev & 0x0f) << 4), 8); 374 375 /* Reset to the 5GHz mode */ 376 AR5K_REG_WRITE(AR5K_AR5211_PHY(0), AR5K_AR5211_PHY_SHIFT_5GHZ); 377 378 return (ret); 379 } 380 381 const HAL_RATE_TABLE * 382 ar5k_ar5211_get_rate_table(struct ath_hal *hal, u_int mode) 383 { 384 switch (mode) { 385 case HAL_MODE_11A: 386 return (&hal->ah_rt_11a); 387 case HAL_MODE_TURBO: 388 return (&hal->ah_rt_turbo); 389 case HAL_MODE_11B: 390 return (&hal->ah_rt_11b); 391 case HAL_MODE_11G: 392 case HAL_MODE_PUREG: 393 return (&hal->ah_rt_11g); 394 default: 395 return (NULL); 396 } 397 398 return (NULL); 399 } 400 401 void 402 ar5k_ar5211_detach(struct ath_hal *hal) 403 { 404 /* 405 * Free HAL structure, assume interrupts are down 406 */ 407 free(hal, M_DEVBUF); 408 } 409 410 HAL_BOOL 411 ar5k_ar5211_phy_disable(struct ath_hal *hal) 412 { 413 AR5K_REG_WRITE(AR5K_AR5211_PHY_ACTIVE, AR5K_AR5211_PHY_DISABLE); 414 return (AH_TRUE); 415 } 416 417 HAL_BOOL 418 ar5k_ar5211_reset(struct ath_hal *hal, HAL_OPMODE op_mode, HAL_CHANNEL *channel, 419 HAL_BOOL change_channel, HAL_STATUS *status) 420 { 421 struct ar5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; 422 u_int8_t mac[IEEE80211_ADDR_LEN]; 423 u_int32_t data, s_seq, s_ant, s_led[3]; 424 u_int i, mode, freq, ee_mode, ant[2]; 425 426 /* 427 * Save some registers before a reset 428 */ 429 if (change_channel == AH_TRUE) { 430 s_seq = AR5K_REG_READ(AR5K_AR5211_DCU_SEQNUM(0)); 431 s_ant = AR5K_REG_READ(AR5K_AR5211_DEFAULT_ANTENNA); 432 } else { 433 s_seq = 0; 434 s_ant = 1; 435 } 436 437 s_led[0] = AR5K_REG_READ(AR5K_AR5211_PCICFG) & 438 AR5K_AR5211_PCICFG_LEDSTATE; 439 s_led[1] = AR5K_REG_READ(AR5K_AR5211_GPIOCR); 440 s_led[2] = AR5K_REG_READ(AR5K_AR5211_GPIODO); 441 442 if (ar5k_ar5211_nic_wakeup(hal, channel->c_channel_flags) == AH_FALSE) 443 return (AH_FALSE); 444 445 /* 446 * Initialize operating mode 447 */ 448 hal->ah_op_mode = op_mode; 449 450 switch (channel->c_channel_flags & CHANNEL_MODES) { 451 case CHANNEL_A: 452 mode = AR5K_INI_VAL_11A; 453 freq = AR5K_INI_RFGAIN_5GHZ; 454 ee_mode = AR5K_EEPROM_MODE_11A; 455 break; 456 case CHANNEL_T: 457 mode = AR5K_INI_VAL_11A_TURBO; 458 freq = AR5K_INI_RFGAIN_5GHZ; 459 ee_mode = AR5K_EEPROM_MODE_11A; 460 break; 461 case CHANNEL_B: 462 mode = AR5K_INI_VAL_11B; 463 freq = AR5K_INI_RFGAIN_2GHZ; 464 ee_mode = AR5K_EEPROM_MODE_11B; 465 break; 466 case CHANNEL_G: 467 case CHANNEL_PUREG: 468 mode = AR5K_INI_VAL_11G; 469 freq = AR5K_INI_RFGAIN_2GHZ; 470 ee_mode = AR5K_EEPROM_MODE_11G; 471 break; 472 default: 473 AR5K_PRINTF("invalid channel: %d\n", channel->c_channel); 474 return (AH_FALSE); 475 } 476 477 /* PHY access enable */ 478 AR5K_REG_WRITE(AR5K_AR5211_PHY(0), AR5K_AR5211_PHY_SHIFT_5GHZ); 479 480 /* 481 * Write initial RF registers 482 */ 483 if (ar5k_ar5211_rfregs(hal, channel, freq, ee_mode) == AH_FALSE) 484 return (AH_FALSE); 485 486 /* 487 * Write initial mode settings 488 */ 489 for (i = 0; i < nitems(ar5211_mode); i++) { 490 AR5K_REG_WAIT(i); 491 AR5K_REG_WRITE((u_int32_t)ar5211_mode[i].mode_register, 492 ar5211_mode[i].mode_value[mode]); 493 } 494 495 /* 496 * Write initial register settings 497 */ 498 for (i = 0; i < nitems(ar5211_ini); i++) { 499 if (change_channel == AH_TRUE && 500 ar5211_ini[i].ini_register >= AR5K_AR5211_PCU_MIN && 501 ar5211_ini[i].ini_register <= AR5K_AR5211_PCU_MAX) 502 continue; 503 504 AR5K_REG_WAIT(i); 505 AR5K_REG_WRITE((u_int32_t)ar5211_ini[i].ini_register, 506 ar5211_ini[i].ini_value); 507 } 508 509 /* 510 * Write initial RF gain settings 511 */ 512 if (ar5k_rfgain(hal, freq) == AH_FALSE) 513 return (AH_FALSE); 514 515 AR5K_DELAY(1000); 516 517 /* 518 * Configure additional registers 519 */ 520 521 if (hal->ah_radio == AR5K_AR5111) { 522 if (channel->c_channel_flags & IEEE80211_CHAN_B) 523 AR5K_REG_ENABLE_BITS(AR5K_AR5211_TXCFG, 524 AR5K_AR5211_TXCFG_B_MODE); 525 else 526 AR5K_REG_DISABLE_BITS(AR5K_AR5211_TXCFG, 527 AR5K_AR5211_TXCFG_B_MODE); 528 } 529 530 /* Set antenna mode */ 531 AR5K_REG_MASKED_BITS(AR5K_AR5211_PHY(0x44), 532 hal->ah_antenna[ee_mode][0], 0xfffffc06); 533 534 if (freq == AR5K_INI_RFGAIN_2GHZ) 535 ant[0] = ant[1] = HAL_ANT_FIXED_B; 536 else 537 ant[0] = ant[1] = HAL_ANT_FIXED_A; 538 539 AR5K_REG_WRITE(AR5K_AR5211_PHY_ANT_SWITCH_TABLE_0, 540 hal->ah_antenna[ee_mode][ant[0]]); 541 AR5K_REG_WRITE(AR5K_AR5211_PHY_ANT_SWITCH_TABLE_1, 542 hal->ah_antenna[ee_mode][ant[1]]); 543 544 /* Commit values from EEPROM */ 545 AR5K_REG_WRITE_BITS(AR5K_AR5211_PHY_FC, 546 AR5K_AR5211_PHY_FC_TX_CLIP, ee->ee_tx_clip); 547 548 AR5K_REG_WRITE(AR5K_AR5211_PHY(0x5a), 549 AR5K_AR5211_PHY_NF_SVAL(ee->ee_noise_floor_thr[ee_mode])); 550 551 AR5K_REG_MASKED_BITS(AR5K_AR5211_PHY(0x11), 552 (ee->ee_switch_settling[ee_mode] << 7) & 0x3f80, 0xffffc07f); 553 AR5K_REG_MASKED_BITS(AR5K_AR5211_PHY(0x12), 554 (ee->ee_ant_tx_rx[ee_mode] << 12) & 0x3f000, 0xfffc0fff); 555 AR5K_REG_MASKED_BITS(AR5K_AR5211_PHY(0x14), 556 (ee->ee_adc_desired_size[ee_mode] & 0x00ff) | 557 ((ee->ee_pga_desired_size[ee_mode] << 8) & 0xff00), 0xffff0000); 558 559 AR5K_REG_WRITE(AR5K_AR5211_PHY(0x0d), 560 (ee->ee_tx_end2xpa_disable[ee_mode] << 24) | 561 (ee->ee_tx_end2xpa_disable[ee_mode] << 16) | 562 (ee->ee_tx_frm2xpa_enable[ee_mode] << 8) | 563 (ee->ee_tx_frm2xpa_enable[ee_mode])); 564 565 AR5K_REG_MASKED_BITS(AR5K_AR5211_PHY(0x0a), 566 ee->ee_tx_end2xlna_enable[ee_mode] << 8, 0xffff00ff); 567 AR5K_REG_MASKED_BITS(AR5K_AR5211_PHY(0x19), 568 (ee->ee_thr_62[ee_mode] << 12) & 0x7f000, 0xfff80fff); 569 AR5K_REG_MASKED_BITS(AR5K_AR5211_PHY(0x49), 4, 0xffffff01); 570 571 AR5K_REG_ENABLE_BITS(AR5K_AR5211_PHY_IQ, 572 AR5K_AR5211_PHY_IQ_CORR_ENABLE | 573 (ee->ee_i_cal[ee_mode] << AR5K_AR5211_PHY_IQ_CORR_Q_I_COFF_S) | 574 ee->ee_q_cal[ee_mode]); 575 576 /* 577 * Restore saved values 578 */ 579 AR5K_REG_WRITE(AR5K_AR5211_DCU_SEQNUM(0), s_seq); 580 AR5K_REG_WRITE(AR5K_AR5211_DEFAULT_ANTENNA, s_ant); 581 AR5K_REG_ENABLE_BITS(AR5K_AR5211_PCICFG, s_led[0]); 582 AR5K_REG_WRITE(AR5K_AR5211_GPIOCR, s_led[1]); 583 AR5K_REG_WRITE(AR5K_AR5211_GPIODO, s_led[2]); 584 585 /* 586 * Misc 587 */ 588 bcopy(etherbroadcastaddr, mac, IEEE80211_ADDR_LEN); 589 ar5k_ar5211_set_associd(hal, mac, 0, 0); 590 ar5k_ar5211_set_opmode(hal); 591 AR5K_REG_WRITE(AR5K_AR5211_PISR, 0xffffffff); 592 AR5K_REG_WRITE(AR5K_AR5211_RSSI_THR, AR5K_TUNE_RSSI_THRES); 593 594 /* 595 * Set Rx/Tx DMA Configuration 596 */ 597 AR5K_REG_WRITE_BITS(AR5K_AR5211_TXCFG, AR5K_AR5211_TXCFG_SDMAMR, 598 AR5K_AR5211_DMASIZE_512B | AR5K_AR5211_TXCFG_DMASIZE); 599 AR5K_REG_WRITE_BITS(AR5K_AR5211_RXCFG, AR5K_AR5211_RXCFG_SDMAMW, 600 AR5K_AR5211_DMASIZE_512B); 601 602 /* 603 * Set channel and calibrate the PHY 604 */ 605 if (ar5k_channel(hal, channel) == AH_FALSE) 606 return (AH_FALSE); 607 608 /* 609 * Enable the PHY and wait until completion 610 */ 611 AR5K_REG_WRITE(AR5K_AR5211_PHY_ACTIVE, AR5K_AR5211_PHY_ENABLE); 612 613 data = AR5K_REG_READ(AR5K_AR5211_PHY_RX_DELAY) & 614 AR5K_AR5211_PHY_RX_DELAY_M; 615 data = (channel->c_channel_flags & IEEE80211_CHAN_CCK) ? 616 ((data << 2) / 22) : (data / 10); 617 618 AR5K_DELAY(100 + data); 619 620 /* 621 * Start calibration 622 */ 623 AR5K_REG_ENABLE_BITS(AR5K_AR5211_PHY_AGCCTL, 624 AR5K_AR5211_PHY_AGCCTL_NF | 625 AR5K_AR5211_PHY_AGCCTL_CAL); 626 627 if (channel->c_channel_flags & IEEE80211_CHAN_B) { 628 hal->ah_calibration = AH_FALSE; 629 } else { 630 hal->ah_calibration = AH_TRUE; 631 AR5K_REG_WRITE_BITS(AR5K_AR5211_PHY_IQ, 632 AR5K_AR5211_PHY_IQ_CAL_NUM_LOG_MAX, 15); 633 AR5K_REG_ENABLE_BITS(AR5K_AR5211_PHY_IQ, 634 AR5K_AR5211_PHY_IQ_RUN); 635 } 636 637 /* 638 * Reset queues and start beacon timers at the end of the reset routine 639 */ 640 for (i = 0; i < hal->ah_capabilities.cap_queues.q_tx_num; i++) { 641 AR5K_REG_WRITE_Q(AR5K_AR5211_DCU_QCUMASK(i), i); 642 if (ar5k_ar5211_reset_tx_queue(hal, i) == AH_FALSE) { 643 AR5K_PRINTF("failed to reset TX queue #%d\n", i); 644 return (AH_FALSE); 645 } 646 } 647 648 /* Pre-enable interrupts */ 649 ar5k_ar5211_set_intr(hal, HAL_INT_RX | HAL_INT_TX | HAL_INT_FATAL); 650 651 /* 652 * Set RF kill flags if supported by the device (read from the EEPROM) 653 */ 654 if (AR5K_EEPROM_HDR_RFKILL(hal->ah_capabilities.cap_eeprom.ee_header)) { 655 ar5k_ar5211_set_gpio_input(hal, 0); 656 if ((hal->ah_gpio[0] = ar5k_ar5211_get_gpio(hal, 0)) == 0) 657 ar5k_ar5211_set_gpio_intr(hal, 0, 1); 658 else 659 ar5k_ar5211_set_gpio_intr(hal, 0, 0); 660 } 661 662 /* 663 * Disable beacons and reset the register 664 */ 665 AR5K_REG_DISABLE_BITS(AR5K_AR5211_BEACON, 666 AR5K_AR5211_BEACON_ENABLE | AR5K_AR5211_BEACON_RESET_TSF); 667 668 return (AH_TRUE); 669 } 670 671 void 672 ar5k_ar5211_set_def_antenna(struct ath_hal *hal, u_int ant) 673 { 674 AR5K_REG_WRITE(AR5K_AR5211_DEFAULT_ANTENNA, ant); 675 } 676 677 u_int 678 ar5k_ar5211_get_def_antenna(struct ath_hal *hal) 679 { 680 return AR5K_REG_READ(AR5K_AR5211_DEFAULT_ANTENNA); 681 } 682 683 void 684 ar5k_ar5211_set_opmode(struct ath_hal *hal) 685 { 686 u_int32_t pcu_reg, low_id, high_id; 687 688 pcu_reg = 0; 689 690 switch (hal->ah_op_mode) { 691 #ifndef IEEE80211_STA_ONLY 692 case IEEE80211_M_IBSS: 693 pcu_reg |= AR5K_AR5211_STA_ID1_ADHOC | 694 AR5K_AR5211_STA_ID1_DESC_ANTENNA; 695 break; 696 697 case IEEE80211_M_HOSTAP: 698 pcu_reg |= AR5K_AR5211_STA_ID1_AP | 699 AR5K_AR5211_STA_ID1_RTS_DEFAULT_ANTENNA; 700 break; 701 #endif 702 703 case IEEE80211_M_STA: 704 case IEEE80211_M_MONITOR: 705 pcu_reg |= AR5K_AR5211_STA_ID1_DEFAULT_ANTENNA; 706 break; 707 708 default: 709 return; 710 } 711 712 /* 713 * Set PCU registers 714 */ 715 low_id = AR5K_LOW_ID(hal->ah_sta_id); 716 high_id = AR5K_HIGH_ID(hal->ah_sta_id); 717 AR5K_REG_WRITE(AR5K_AR5211_STA_ID0, low_id); 718 AR5K_REG_WRITE(AR5K_AR5211_STA_ID1, pcu_reg | high_id); 719 720 return; 721 } 722 723 HAL_BOOL 724 ar5k_ar5211_calibrate(struct ath_hal *hal, HAL_CHANNEL *channel) 725 { 726 u_int32_t i_pwr, q_pwr; 727 int32_t iq_corr, i_coff, i_coffd, q_coff, q_coffd; 728 729 if (hal->ah_calibration == AH_FALSE || 730 AR5K_REG_READ(AR5K_AR5211_PHY_IQ) & AR5K_AR5211_PHY_IQ_RUN) 731 goto done; 732 733 hal->ah_calibration = AH_FALSE; 734 735 iq_corr = AR5K_REG_READ(AR5K_AR5211_PHY_IQRES_CAL_CORR); 736 i_pwr = AR5K_REG_READ(AR5K_AR5211_PHY_IQRES_CAL_PWR_I); 737 q_pwr = AR5K_REG_READ(AR5K_AR5211_PHY_IQRES_CAL_PWR_Q); 738 i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7; 739 q_coffd = q_pwr >> 6; 740 741 if (i_coffd == 0 || q_coffd == 0) 742 goto done; 743 744 i_coff = ((-iq_corr) / i_coffd) & 0x3f; 745 q_coff = (((int32_t)i_pwr / q_coffd) - 64) & 0x1f; 746 747 /* Commit new IQ value */ 748 AR5K_REG_ENABLE_BITS(AR5K_AR5211_PHY_IQ, 749 AR5K_AR5211_PHY_IQ_CORR_ENABLE | 750 ((u_int32_t)q_coff) | 751 ((u_int32_t)i_coff << AR5K_AR5211_PHY_IQ_CORR_Q_I_COFF_S)); 752 753 done: 754 /* Start noise floor calibration */ 755 AR5K_REG_ENABLE_BITS(AR5K_AR5211_PHY_AGCCTL, 756 AR5K_AR5211_PHY_AGCCTL_NF); 757 758 return (AH_TRUE); 759 } 760 761 /* 762 * Transmit functions 763 */ 764 765 HAL_BOOL 766 ar5k_ar5211_update_tx_triglevel(struct ath_hal *hal, HAL_BOOL increase) 767 { 768 u_int32_t trigger_level, imr; 769 HAL_BOOL status = AH_FALSE; 770 771 /* 772 * Disable interrupts by setting the mask 773 */ 774 imr = ar5k_ar5211_set_intr(hal, hal->ah_imr & ~HAL_INT_GLOBAL); 775 776 trigger_level = AR5K_REG_MS(AR5K_REG_READ(AR5K_AR5211_TXCFG), 777 AR5K_AR5211_TXCFG_TXFULL); 778 779 if (increase == AH_FALSE) { 780 if (--trigger_level < AR5K_TUNE_MIN_TX_FIFO_THRES) 781 goto done; 782 } else 783 trigger_level += 784 ((AR5K_TUNE_MAX_TX_FIFO_THRES - trigger_level) / 2); 785 786 /* 787 * Update trigger level on success 788 */ 789 AR5K_REG_WRITE_BITS(AR5K_AR5211_TXCFG, 790 AR5K_AR5211_TXCFG_TXFULL, trigger_level); 791 status = AH_TRUE; 792 793 done: 794 /* 795 * Restore interrupt mask 796 */ 797 ar5k_ar5211_set_intr(hal, imr); 798 799 return (status); 800 } 801 802 int 803 ar5k_ar5211_setup_tx_queue(struct ath_hal *hal, HAL_TX_QUEUE queue_type, 804 const HAL_TXQ_INFO *queue_info) 805 { 806 u_int queue; 807 808 /* 809 * Get queue by type 810 */ 811 if (queue_type == HAL_TX_QUEUE_DATA) { 812 for (queue = HAL_TX_QUEUE_ID_DATA_MIN; 813 hal->ah_txq[queue].tqi_type != HAL_TX_QUEUE_INACTIVE; 814 queue++) 815 if (queue > HAL_TX_QUEUE_ID_DATA_MAX) 816 return (-1); 817 } else if (queue_type == HAL_TX_QUEUE_PSPOLL) { 818 queue = HAL_TX_QUEUE_ID_PSPOLL; 819 } else if (queue_type == HAL_TX_QUEUE_BEACON) { 820 queue = HAL_TX_QUEUE_ID_BEACON; 821 } else if (queue_type == HAL_TX_QUEUE_CAB) { 822 queue = HAL_TX_QUEUE_ID_CAB; 823 } else 824 return (-1); 825 826 /* 827 * Setup internal queue structure 828 */ 829 bzero(&hal->ah_txq[queue], sizeof(HAL_TXQ_INFO)); 830 hal->ah_txq[queue].tqi_type = queue_type; 831 832 if (queue_info != NULL) { 833 if (ar5k_ar5211_setup_tx_queueprops(hal, queue, queue_info) 834 != AH_TRUE) 835 return (-1); 836 } 837 838 AR5K_Q_ENABLE_BITS(hal->ah_txq_interrupts, queue); 839 840 return (queue); 841 } 842 843 HAL_BOOL 844 ar5k_ar5211_setup_tx_queueprops(struct ath_hal *hal, int queue, 845 const HAL_TXQ_INFO *queue_info) 846 { 847 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); 848 849 if (hal->ah_txq[queue].tqi_type == HAL_TX_QUEUE_INACTIVE) 850 return (AH_FALSE); 851 852 bcopy(queue_info, &hal->ah_txq[queue], sizeof(HAL_TXQ_INFO)); 853 854 if (queue_info->tqi_type == HAL_TX_QUEUE_DATA && 855 (queue_info->tqi_subtype >= HAL_WME_AC_VI) && 856 (queue_info->tqi_subtype <= HAL_WME_UPSD)) 857 hal->ah_txq[queue].tqi_flags |= 858 AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS; 859 860 return (AH_TRUE); 861 } 862 863 HAL_BOOL 864 ar5k_ar5211_get_tx_queueprops(struct ath_hal *hal, int queue, 865 HAL_TXQ_INFO *queue_info) 866 { 867 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); 868 bcopy(&hal->ah_txq[queue], queue_info, sizeof(HAL_TXQ_INFO)); 869 return (AH_TRUE); 870 } 871 872 HAL_BOOL 873 ar5k_ar5211_release_tx_queue(struct ath_hal *hal, u_int queue) 874 { 875 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); 876 877 /* This queue will be skipped in further operations */ 878 hal->ah_txq[queue].tqi_type = HAL_TX_QUEUE_INACTIVE; 879 AR5K_Q_DISABLE_BITS(hal->ah_txq_interrupts, queue); 880 881 return (AH_FALSE); 882 } 883 884 HAL_BOOL 885 ar5k_ar5211_reset_tx_queue(struct ath_hal *hal, u_int queue) 886 { 887 u_int32_t cw_min, cw_max, retry_lg, retry_sh; 888 struct ieee80211_channel *channel = (struct ieee80211_channel*) 889 &hal->ah_current_channel; 890 HAL_TXQ_INFO *tq; 891 892 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); 893 894 tq = &hal->ah_txq[queue]; 895 896 if (tq->tqi_type == HAL_TX_QUEUE_INACTIVE) 897 return (AH_TRUE); 898 899 /* 900 * Set registers by channel mode 901 */ 902 if (IEEE80211_IS_CHAN_B(channel)) { 903 hal->ah_cw_min = AR5K_TUNE_CWMIN_11B; 904 cw_max = hal->ah_cw_max = AR5K_TUNE_CWMAX_11B; 905 hal->ah_aifs = AR5K_TUNE_AIFS_11B; 906 } else { 907 hal->ah_cw_min = AR5K_TUNE_CWMIN; 908 cw_max = hal->ah_cw_max = AR5K_TUNE_CWMAX; 909 hal->ah_aifs = AR5K_TUNE_AIFS; 910 } 911 912 /* 913 * Set retry limits 914 */ 915 if (hal->ah_software_retry == AH_TRUE) { 916 /* XXX Need to test this */ 917 retry_lg = hal->ah_limit_tx_retries; 918 retry_sh = retry_lg = 919 retry_lg > AR5K_AR5211_DCU_RETRY_LMT_SH_RETRY ? 920 AR5K_AR5211_DCU_RETRY_LMT_SH_RETRY : retry_lg; 921 } else { 922 retry_lg = AR5K_INIT_LG_RETRY; 923 retry_sh = AR5K_INIT_SH_RETRY; 924 } 925 926 AR5K_REG_WRITE(AR5K_AR5211_DCU_RETRY_LMT(queue), 927 AR5K_REG_SM(AR5K_INIT_SLG_RETRY, 928 AR5K_AR5211_DCU_RETRY_LMT_SLG_RETRY) | 929 AR5K_REG_SM(AR5K_INIT_SSH_RETRY, 930 AR5K_AR5211_DCU_RETRY_LMT_SSH_RETRY) | 931 AR5K_REG_SM(retry_lg, AR5K_AR5211_DCU_RETRY_LMT_LG_RETRY) | 932 AR5K_REG_SM(retry_sh, AR5K_AR5211_DCU_RETRY_LMT_SH_RETRY)); 933 934 /* 935 * Set initial content window (cw_min/cw_max) 936 */ 937 cw_min = 1; 938 while (cw_min < hal->ah_cw_min) 939 cw_min = (cw_min << 1) | 1; 940 941 cw_min = tq->tqi_cw_min < 0 ? 942 (cw_min >> (-tq->tqi_cw_min)) : 943 ((cw_min << tq->tqi_cw_min) + (1 << tq->tqi_cw_min) - 1); 944 cw_max = tq->tqi_cw_max < 0 ? 945 (cw_max >> (-tq->tqi_cw_max)) : 946 ((cw_max << tq->tqi_cw_max) + (1 << tq->tqi_cw_max) - 1); 947 948 AR5K_REG_WRITE(AR5K_AR5211_DCU_LCL_IFS(queue), 949 AR5K_REG_SM(cw_min, AR5K_AR5211_DCU_LCL_IFS_CW_MIN) | 950 AR5K_REG_SM(cw_max, AR5K_AR5211_DCU_LCL_IFS_CW_MAX) | 951 AR5K_REG_SM(hal->ah_aifs + tq->tqi_aifs, 952 AR5K_AR5211_DCU_LCL_IFS_AIFS)); 953 954 /* 955 * Set misc registers 956 */ 957 AR5K_REG_WRITE(AR5K_AR5211_QCU_MISC(queue), 958 AR5K_AR5211_QCU_MISC_DCU_EARLY); 959 960 if (tq->tqi_cbr_period) { 961 AR5K_REG_WRITE(AR5K_AR5211_QCU_CBRCFG(queue), 962 AR5K_REG_SM(tq->tqi_cbr_period, 963 AR5K_AR5211_QCU_CBRCFG_INTVAL) | 964 AR5K_REG_SM(tq->tqi_cbr_overflow_limit, 965 AR5K_AR5211_QCU_CBRCFG_ORN_THRES)); 966 AR5K_REG_ENABLE_BITS(AR5K_AR5211_QCU_MISC(queue), 967 AR5K_AR5211_QCU_MISC_FRSHED_CBR); 968 if (tq->tqi_cbr_overflow_limit) 969 AR5K_REG_ENABLE_BITS(AR5K_AR5211_QCU_MISC(queue), 970 AR5K_AR5211_QCU_MISC_CBR_THRES_ENABLE); 971 } 972 973 if (tq->tqi_ready_time) { 974 AR5K_REG_WRITE(AR5K_AR5211_QCU_RDYTIMECFG(queue), 975 AR5K_REG_SM(tq->tqi_ready_time, 976 AR5K_AR5211_QCU_RDYTIMECFG_INTVAL) | 977 AR5K_AR5211_QCU_RDYTIMECFG_ENABLE); 978 } 979 980 if (tq->tqi_burst_time) { 981 AR5K_REG_WRITE(AR5K_AR5211_DCU_CHAN_TIME(queue), 982 AR5K_REG_SM(tq->tqi_burst_time, 983 AR5K_AR5211_DCU_CHAN_TIME_DUR) | 984 AR5K_AR5211_DCU_CHAN_TIME_ENABLE); 985 986 if (tq->tqi_flags & AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE) { 987 AR5K_REG_ENABLE_BITS(AR5K_AR5211_QCU_MISC(queue), 988 AR5K_AR5211_QCU_MISC_TXE); 989 } 990 } 991 992 if (tq->tqi_flags & AR5K_TXQ_FLAG_BACKOFF_DISABLE) { 993 AR5K_REG_WRITE(AR5K_AR5211_DCU_MISC(queue), 994 AR5K_AR5211_DCU_MISC_POST_FR_BKOFF_DIS); 995 } 996 997 if (tq->tqi_flags & AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE) { 998 AR5K_REG_WRITE(AR5K_AR5211_DCU_MISC(queue), 999 AR5K_AR5211_DCU_MISC_BACKOFF_FRAG); 1000 } 1001 1002 /* 1003 * Set registers by queue type 1004 */ 1005 switch (tq->tqi_type) { 1006 case HAL_TX_QUEUE_BEACON: 1007 AR5K_REG_ENABLE_BITS(AR5K_AR5211_QCU_MISC(queue), 1008 AR5K_AR5211_QCU_MISC_FRSHED_DBA_GT | 1009 AR5K_AR5211_QCU_MISC_CBREXP_BCN | 1010 AR5K_AR5211_QCU_MISC_BCN_ENABLE); 1011 1012 AR5K_REG_ENABLE_BITS(AR5K_AR5211_DCU_MISC(queue), 1013 (AR5K_AR5211_DCU_MISC_ARBLOCK_CTL_GLOBAL << 1014 AR5K_AR5211_DCU_MISC_ARBLOCK_CTL_GLOBAL) | 1015 AR5K_AR5211_DCU_MISC_POST_FR_BKOFF_DIS | 1016 AR5K_AR5211_DCU_MISC_BCN_ENABLE); 1017 1018 AR5K_REG_WRITE(AR5K_AR5211_QCU_RDYTIMECFG(queue), 1019 ((AR5K_TUNE_BEACON_INTERVAL - 1020 (AR5K_TUNE_SW_BEACON_RESP - AR5K_TUNE_DMA_BEACON_RESP) - 1021 AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF) * 1024) | 1022 AR5K_AR5211_QCU_RDYTIMECFG_ENABLE); 1023 break; 1024 1025 case HAL_TX_QUEUE_CAB: 1026 AR5K_REG_ENABLE_BITS(AR5K_AR5211_QCU_MISC(queue), 1027 AR5K_AR5211_QCU_MISC_FRSHED_DBA_GT | 1028 AR5K_AR5211_QCU_MISC_CBREXP | 1029 AR5K_AR5211_QCU_MISC_CBREXP_BCN); 1030 1031 AR5K_REG_ENABLE_BITS(AR5K_AR5211_DCU_MISC(queue), 1032 (AR5K_AR5211_DCU_MISC_ARBLOCK_CTL_GLOBAL << 1033 AR5K_AR5211_DCU_MISC_ARBLOCK_CTL_GLOBAL)); 1034 break; 1035 1036 case HAL_TX_QUEUE_PSPOLL: 1037 AR5K_REG_ENABLE_BITS(AR5K_AR5211_QCU_MISC(queue), 1038 AR5K_AR5211_QCU_MISC_CBREXP); 1039 break; 1040 1041 case HAL_TX_QUEUE_DATA: 1042 default: 1043 break; 1044 } 1045 1046 /* 1047 * Enable tx queue in the secondary interrupt mask registers 1048 */ 1049 AR5K_REG_WRITE(AR5K_AR5211_SIMR0, 1050 AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_AR5211_SIMR0_QCU_TXOK) | 1051 AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_AR5211_SIMR0_QCU_TXDESC)); 1052 AR5K_REG_WRITE(AR5K_AR5211_SIMR1, 1053 AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_AR5211_SIMR1_QCU_TXERR)); 1054 AR5K_REG_WRITE(AR5K_AR5211_SIMR2, 1055 AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_AR5211_SIMR2_QCU_TXURN)); 1056 1057 return (AH_TRUE); 1058 } 1059 1060 u_int32_t 1061 ar5k_ar5211_get_tx_buf(struct ath_hal *hal, u_int queue) 1062 { 1063 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); 1064 1065 /* 1066 * Get the transmit queue descriptor pointer from the selected queue 1067 */ 1068 return (AR5K_REG_READ(AR5K_AR5211_QCU_TXDP(queue))); 1069 } 1070 1071 HAL_BOOL 1072 ar5k_ar5211_put_tx_buf(struct ath_hal *hal, u_int queue, u_int32_t phys_addr) 1073 { 1074 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); 1075 1076 /* 1077 * Set the transmit queue descriptor pointer for the selected queue 1078 * (this won't work if the queue is still active) 1079 */ 1080 if (AR5K_REG_READ_Q(AR5K_AR5211_QCU_TXE, queue)) 1081 return (AH_FALSE); 1082 1083 AR5K_REG_WRITE(AR5K_AR5211_QCU_TXDP(queue), phys_addr); 1084 1085 return (AH_TRUE); 1086 } 1087 1088 u_int32_t 1089 ar5k_ar5211_num_tx_pending(struct ath_hal *hal, u_int queue) 1090 { 1091 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); 1092 return (AR5K_AR5211_QCU_STS(queue) & AR5K_AR5211_QCU_STS_FRMPENDCNT); 1093 } 1094 1095 HAL_BOOL 1096 ar5k_ar5211_tx_start(struct ath_hal *hal, u_int queue) 1097 { 1098 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); 1099 1100 /* Return if queue is disabled */ 1101 if (AR5K_REG_READ_Q(AR5K_AR5211_QCU_TXD, queue)) 1102 return (AH_FALSE); 1103 1104 /* Start queue */ 1105 AR5K_REG_WRITE_Q(AR5K_AR5211_QCU_TXE, queue); 1106 1107 return (AH_TRUE); 1108 } 1109 1110 HAL_BOOL 1111 ar5k_ar5211_stop_tx_dma(struct ath_hal *hal, u_int queue) 1112 { 1113 int i = 100, pending; 1114 1115 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); 1116 1117 /* 1118 * Schedule TX disable and wait until queue is empty 1119 */ 1120 AR5K_REG_WRITE_Q(AR5K_AR5211_QCU_TXD, queue); 1121 1122 do { 1123 pending = AR5K_REG_READ(AR5K_AR5211_QCU_STS(queue)) & 1124 AR5K_AR5211_QCU_STS_FRMPENDCNT; 1125 delay(100); 1126 } while (--i && pending); 1127 1128 /* Clear register */ 1129 AR5K_REG_WRITE(AR5K_AR5211_QCU_TXD, 0); 1130 1131 return (AH_TRUE); 1132 } 1133 1134 HAL_BOOL 1135 ar5k_ar5211_setup_tx_desc(struct ath_hal *hal, struct ath_desc *desc, 1136 u_int packet_length, u_int header_length, HAL_PKT_TYPE type, u_int tx_power, 1137 u_int tx_rate0, u_int tx_tries0, u_int key_index, u_int antenna_mode, 1138 u_int flags, u_int rtscts_rate, u_int rtscts_duration) 1139 { 1140 struct ar5k_ar5211_tx_desc *tx_desc; 1141 1142 tx_desc = (struct ar5k_ar5211_tx_desc*)&desc->ds_ctl0; 1143 1144 /* 1145 * Validate input 1146 */ 1147 if (tx_tries0 == 0) 1148 return (AH_FALSE); 1149 1150 if ((tx_desc->tx_control_0 = (packet_length & 1151 AR5K_AR5211_DESC_TX_CTL0_FRAME_LEN)) != packet_length) 1152 return (AH_FALSE); 1153 1154 tx_desc->tx_control_0 |= 1155 AR5K_REG_SM(tx_rate0, AR5K_AR5211_DESC_TX_CTL0_XMIT_RATE) | 1156 AR5K_REG_SM(antenna_mode, AR5K_AR5211_DESC_TX_CTL0_ANT_MODE_XMIT); 1157 tx_desc->tx_control_1 = 1158 AR5K_REG_SM(type, AR5K_AR5211_DESC_TX_CTL1_FRAME_TYPE); 1159 1160 #define _TX_FLAGS(_c, _flag) \ 1161 if (flags & HAL_TXDESC_##_flag) \ 1162 tx_desc->tx_control_##_c |= \ 1163 AR5K_AR5211_DESC_TX_CTL##_c##_##_flag 1164 1165 _TX_FLAGS(0, CLRDMASK); 1166 _TX_FLAGS(0, VEOL); 1167 _TX_FLAGS(0, INTREQ); 1168 _TX_FLAGS(0, RTSENA); 1169 _TX_FLAGS(1, NOACK); 1170 1171 #undef _TX_FLAGS 1172 1173 /* 1174 * WEP crap 1175 */ 1176 if (key_index != HAL_TXKEYIX_INVALID) { 1177 tx_desc->tx_control_0 |= 1178 AR5K_AR5211_DESC_TX_CTL0_ENCRYPT_KEY_VALID; 1179 tx_desc->tx_control_1 |= 1180 AR5K_REG_SM(key_index, 1181 AR5K_AR5211_DESC_TX_CTL1_ENCRYPT_KEY_INDEX); 1182 } 1183 1184 return (AH_TRUE); 1185 } 1186 1187 HAL_BOOL 1188 ar5k_ar5211_fill_tx_desc(struct ath_hal *hal, struct ath_desc *desc, 1189 u_int segment_length, HAL_BOOL first_segment, HAL_BOOL last_segment) 1190 { 1191 struct ar5k_ar5211_tx_desc *tx_desc; 1192 1193 tx_desc = (struct ar5k_ar5211_tx_desc*)&desc->ds_ctl0; 1194 1195 /* Clear status descriptor */ 1196 bzero(desc->ds_hw, sizeof(desc->ds_hw)); 1197 1198 /* Validate segment length and initialize the descriptor */ 1199 if (segment_length & ~AR5K_AR5211_DESC_TX_CTL1_BUF_LEN) 1200 return (AH_FALSE); 1201 tx_desc->tx_control_1 = 1202 #if 0 1203 (tx_desc->tx_control_1 & ~AR5K_AR5211_DESC_TX_CTL1_BUF_LEN) | 1204 #endif 1205 segment_length; 1206 1207 if (first_segment != AH_TRUE) 1208 tx_desc->tx_control_0 &= ~AR5K_AR5211_DESC_TX_CTL0_FRAME_LEN; 1209 1210 if (last_segment != AH_TRUE) 1211 tx_desc->tx_control_1 |= AR5K_AR5211_DESC_TX_CTL1_MORE; 1212 1213 return (AH_TRUE); 1214 } 1215 1216 HAL_BOOL 1217 ar5k_ar5211_setup_xtx_desc(struct ath_hal *hal, struct ath_desc *desc, 1218 u_int tx_rate1, u_int tx_tries1, u_int tx_rate2, u_int tx_tries2, 1219 u_int tx_rate3, u_int tx_tries3) 1220 { 1221 return (AH_FALSE); 1222 } 1223 1224 HAL_STATUS 1225 ar5k_ar5211_proc_tx_desc(struct ath_hal *hal, struct ath_desc *desc) 1226 { 1227 struct ar5k_ar5211_tx_status *tx_status; 1228 struct ar5k_ar5211_tx_desc *tx_desc; 1229 1230 tx_desc = (struct ar5k_ar5211_tx_desc*)&desc->ds_ctl0; 1231 tx_status = (struct ar5k_ar5211_tx_status*)&desc->ds_hw[0]; 1232 1233 /* No frame has been send or error */ 1234 if ((tx_status->tx_status_1 & AR5K_AR5211_DESC_TX_STATUS1_DONE) == 0) 1235 return (HAL_EINPROGRESS); 1236 1237 /* 1238 * Get descriptor status 1239 */ 1240 desc->ds_us.tx.ts_tstamp = 1241 AR5K_REG_MS(tx_status->tx_status_0, 1242 AR5K_AR5211_DESC_TX_STATUS0_SEND_TIMESTAMP); 1243 desc->ds_us.tx.ts_shortretry = 1244 AR5K_REG_MS(tx_status->tx_status_0, 1245 AR5K_AR5211_DESC_TX_STATUS0_RTS_FAIL_COUNT); 1246 desc->ds_us.tx.ts_longretry = 1247 AR5K_REG_MS(tx_status->tx_status_0, 1248 AR5K_AR5211_DESC_TX_STATUS0_DATA_FAIL_COUNT); 1249 desc->ds_us.tx.ts_seqnum = 1250 AR5K_REG_MS(tx_status->tx_status_1, 1251 AR5K_AR5211_DESC_TX_STATUS1_SEQ_NUM); 1252 desc->ds_us.tx.ts_rssi = 1253 AR5K_REG_MS(tx_status->tx_status_1, 1254 AR5K_AR5211_DESC_TX_STATUS1_ACK_SIG_STRENGTH); 1255 desc->ds_us.tx.ts_antenna = 1; 1256 desc->ds_us.tx.ts_status = 0; 1257 desc->ds_us.tx.ts_rate = 1258 AR5K_REG_MS(tx_desc->tx_control_0, 1259 AR5K_AR5211_DESC_TX_CTL0_XMIT_RATE); 1260 1261 if ((tx_status->tx_status_0 & 1262 AR5K_AR5211_DESC_TX_STATUS0_FRAME_XMIT_OK) == 0) { 1263 if (tx_status->tx_status_0 & 1264 AR5K_AR5211_DESC_TX_STATUS0_EXCESSIVE_RETRIES) 1265 desc->ds_us.tx.ts_status |= HAL_TXERR_XRETRY; 1266 1267 if (tx_status->tx_status_0 & 1268 AR5K_AR5211_DESC_TX_STATUS0_FIFO_UNDERRUN) 1269 desc->ds_us.tx.ts_status |= HAL_TXERR_FIFO; 1270 1271 if (tx_status->tx_status_0 & 1272 AR5K_AR5211_DESC_TX_STATUS0_FILTERED) 1273 desc->ds_us.tx.ts_status |= HAL_TXERR_FILT; 1274 } 1275 1276 return (HAL_OK); 1277 } 1278 1279 HAL_BOOL 1280 ar5k_ar5211_has_veol(struct ath_hal *hal) 1281 { 1282 return (AH_TRUE); 1283 } 1284 1285 /* 1286 * Receive functions 1287 */ 1288 1289 u_int32_t 1290 ar5k_ar5211_get_rx_buf(struct ath_hal *hal) 1291 { 1292 return (AR5K_REG_READ(AR5K_AR5211_RXDP)); 1293 } 1294 1295 void 1296 ar5k_ar5211_put_rx_buf(struct ath_hal *hal, u_int32_t phys_addr) 1297 { 1298 AR5K_REG_WRITE(AR5K_AR5211_RXDP, phys_addr); 1299 } 1300 1301 void 1302 ar5k_ar5211_start_rx(struct ath_hal *hal) 1303 { 1304 AR5K_REG_WRITE(AR5K_AR5211_CR, AR5K_AR5211_CR_RXE); 1305 } 1306 1307 HAL_BOOL 1308 ar5k_ar5211_stop_rx_dma(struct ath_hal *hal) 1309 { 1310 int i; 1311 1312 AR5K_REG_WRITE(AR5K_AR5211_CR, AR5K_AR5211_CR_RXD); 1313 1314 /* 1315 * It may take some time to disable the DMA receive unit 1316 */ 1317 for (i = 2000; 1318 i > 0 && (AR5K_REG_READ(AR5K_AR5211_CR) & AR5K_AR5211_CR_RXE) != 0; 1319 i--) 1320 AR5K_DELAY(10); 1321 1322 return (i > 0 ? AH_TRUE : AH_FALSE); 1323 } 1324 1325 void 1326 ar5k_ar5211_start_rx_pcu(struct ath_hal *hal) 1327 { 1328 AR5K_REG_DISABLE_BITS(AR5K_AR5211_DIAG_SW, AR5K_AR5211_DIAG_SW_DIS_RX); 1329 } 1330 1331 void 1332 ar5k_ar5211_stop_pcu_recv(struct ath_hal *hal) 1333 { 1334 AR5K_REG_ENABLE_BITS(AR5K_AR5211_DIAG_SW, AR5K_AR5211_DIAG_SW_DIS_RX); 1335 } 1336 1337 void 1338 ar5k_ar5211_set_mcast_filter(struct ath_hal *hal, u_int32_t filter0, 1339 u_int32_t filter1) 1340 { 1341 /* Set the multicat filter */ 1342 AR5K_REG_WRITE(AR5K_AR5211_MCAST_FIL0, filter0); 1343 AR5K_REG_WRITE(AR5K_AR5211_MCAST_FIL1, filter1); 1344 } 1345 1346 HAL_BOOL 1347 ar5k_ar5211_set_mcast_filterindex(struct ath_hal *hal, u_int32_t index) 1348 { 1349 if (index >= 64) { 1350 return (AH_FALSE); 1351 } else if (index >= 32) { 1352 AR5K_REG_ENABLE_BITS(AR5K_AR5211_MCAST_FIL1, 1353 (1 << (index - 32))); 1354 } else { 1355 AR5K_REG_ENABLE_BITS(AR5K_AR5211_MCAST_FIL0, 1356 (1 << index)); 1357 } 1358 1359 return (AH_TRUE); 1360 } 1361 1362 HAL_BOOL 1363 ar5k_ar5211_clear_mcast_filter_idx(struct ath_hal *hal, u_int32_t index) 1364 { 1365 1366 if (index >= 64) { 1367 return (AH_FALSE); 1368 } else if (index >= 32) { 1369 AR5K_REG_DISABLE_BITS(AR5K_AR5211_MCAST_FIL1, 1370 (1 << (index - 32))); 1371 } else { 1372 AR5K_REG_DISABLE_BITS(AR5K_AR5211_MCAST_FIL0, 1373 (1 << index)); 1374 } 1375 1376 return (AH_TRUE); 1377 } 1378 1379 u_int32_t 1380 ar5k_ar5211_get_rx_filter(struct ath_hal *hal) 1381 { 1382 return (AR5K_REG_READ(AR5K_AR5211_RX_FILTER)); 1383 } 1384 1385 void 1386 ar5k_ar5211_set_rx_filter(struct ath_hal *hal, u_int32_t filter) 1387 { 1388 AR5K_REG_WRITE(AR5K_AR5211_RX_FILTER, filter); 1389 } 1390 1391 HAL_BOOL 1392 ar5k_ar5211_setup_rx_desc(struct ath_hal *hal, struct ath_desc *desc, 1393 u_int32_t size, u_int flags) 1394 { 1395 struct ar5k_ar5211_rx_desc *rx_desc; 1396 1397 rx_desc = (struct ar5k_ar5211_rx_desc*)&desc->ds_ctl0; 1398 1399 if ((rx_desc->rx_control_1 = (size & 1400 AR5K_AR5211_DESC_RX_CTL1_BUF_LEN)) != size) 1401 return (AH_FALSE); 1402 1403 if (flags & HAL_RXDESC_INTREQ) 1404 rx_desc->rx_control_1 |= AR5K_AR5211_DESC_RX_CTL1_INTREQ; 1405 1406 return (AH_TRUE); 1407 } 1408 1409 HAL_STATUS 1410 ar5k_ar5211_proc_rx_desc(struct ath_hal *hal, struct ath_desc *desc, 1411 u_int32_t phys_addr, struct ath_desc *next) 1412 { 1413 struct ar5k_ar5211_rx_status *rx_status; 1414 1415 rx_status = (struct ar5k_ar5211_rx_status*)&desc->ds_hw[0]; 1416 1417 /* No frame received / not ready */ 1418 if ((rx_status->rx_status_1 & AR5K_AR5211_DESC_RX_STATUS1_DONE) == 0) 1419 return (HAL_EINPROGRESS); 1420 1421 /* 1422 * Frame receive status 1423 */ 1424 desc->ds_us.rx.rs_datalen = rx_status->rx_status_0 & 1425 AR5K_AR5211_DESC_RX_STATUS0_DATA_LEN; 1426 desc->ds_us.rx.rs_rssi = 1427 AR5K_REG_MS(rx_status->rx_status_0, 1428 AR5K_AR5211_DESC_RX_STATUS0_RECEIVE_SIGNAL); 1429 desc->ds_us.rx.rs_rate = 1430 AR5K_REG_MS(rx_status->rx_status_0, 1431 AR5K_AR5211_DESC_RX_STATUS0_RECEIVE_RATE); 1432 desc->ds_us.rx.rs_antenna = rx_status->rx_status_0 & 1433 AR5K_AR5211_DESC_RX_STATUS0_RECEIVE_ANTENNA; 1434 desc->ds_us.rx.rs_more = rx_status->rx_status_0 & 1435 AR5K_AR5211_DESC_RX_STATUS0_MORE; 1436 desc->ds_us.rx.rs_tstamp = 1437 AR5K_REG_MS(rx_status->rx_status_1, 1438 AR5K_AR5211_DESC_RX_STATUS1_RECEIVE_TIMESTAMP); 1439 desc->ds_us.rx.rs_status = 0; 1440 1441 /* 1442 * Key table status 1443 */ 1444 if (rx_status->rx_status_1 & 1445 AR5K_AR5211_DESC_RX_STATUS1_KEY_INDEX_VALID) { 1446 desc->ds_us.rx.rs_keyix = 1447 AR5K_REG_MS(rx_status->rx_status_1, 1448 AR5K_AR5211_DESC_RX_STATUS1_KEY_INDEX); 1449 } else { 1450 desc->ds_us.rx.rs_keyix = HAL_RXKEYIX_INVALID; 1451 } 1452 1453 /* 1454 * Receive/descriptor errors 1455 */ 1456 if ((rx_status->rx_status_1 & 1457 AR5K_AR5211_DESC_RX_STATUS1_FRAME_RECEIVE_OK) == 0) { 1458 if (rx_status->rx_status_1 & 1459 AR5K_AR5211_DESC_RX_STATUS1_CRC_ERROR) 1460 desc->ds_us.rx.rs_status |= HAL_RXERR_CRC; 1461 1462 if (rx_status->rx_status_1 & 1463 AR5K_AR5211_DESC_RX_STATUS1_PHY_ERROR) { 1464 desc->ds_us.rx.rs_status |= HAL_RXERR_PHY; 1465 desc->ds_us.rx.rs_phyerr = 1466 AR5K_REG_MS(rx_status->rx_status_1, 1467 AR5K_AR5211_DESC_RX_STATUS1_PHY_ERROR); 1468 } 1469 1470 if (rx_status->rx_status_1 & 1471 AR5K_AR5211_DESC_RX_STATUS1_DECRYPT_CRC_ERROR) 1472 desc->ds_us.rx.rs_status |= HAL_RXERR_DECRYPT; 1473 } 1474 1475 return (HAL_OK); 1476 } 1477 1478 void 1479 ar5k_ar5211_set_rx_signal(struct ath_hal *hal) 1480 { 1481 /* Signal state monitoring is not yet supported */ 1482 } 1483 1484 /* 1485 * Misc functions 1486 */ 1487 1488 void 1489 ar5k_ar5211_dump_state(struct ath_hal *hal) 1490 { 1491 #ifdef AR5K_DEBUG 1492 #define AR5K_PRINT_REGISTER(_x) \ 1493 printf("(%s: %08x) ", #_x, AR5K_REG_READ(AR5K_AR5211_##_x)); 1494 1495 printf("MAC registers:\n"); 1496 AR5K_PRINT_REGISTER(CR); 1497 AR5K_PRINT_REGISTER(CFG); 1498 AR5K_PRINT_REGISTER(IER); 1499 AR5K_PRINT_REGISTER(RTSD0); 1500 AR5K_PRINT_REGISTER(TXCFG); 1501 AR5K_PRINT_REGISTER(RXCFG); 1502 AR5K_PRINT_REGISTER(RXJLA); 1503 AR5K_PRINT_REGISTER(MIBC); 1504 AR5K_PRINT_REGISTER(TOPS); 1505 AR5K_PRINT_REGISTER(RXNOFRM); 1506 AR5K_PRINT_REGISTER(RPGTO); 1507 AR5K_PRINT_REGISTER(RFCNT); 1508 AR5K_PRINT_REGISTER(MISC); 1509 AR5K_PRINT_REGISTER(PISR); 1510 AR5K_PRINT_REGISTER(SISR0); 1511 AR5K_PRINT_REGISTER(SISR1); 1512 AR5K_PRINT_REGISTER(SISR3); 1513 AR5K_PRINT_REGISTER(SISR4); 1514 AR5K_PRINT_REGISTER(QCU_TXE); 1515 AR5K_PRINT_REGISTER(QCU_TXD); 1516 AR5K_PRINT_REGISTER(DCU_GBL_IFS_SIFS); 1517 AR5K_PRINT_REGISTER(DCU_GBL_IFS_SLOT); 1518 AR5K_PRINT_REGISTER(DCU_FP); 1519 AR5K_PRINT_REGISTER(DCU_TXP); 1520 AR5K_PRINT_REGISTER(DCU_TX_FILTER); 1521 AR5K_PRINT_REGISTER(RC); 1522 AR5K_PRINT_REGISTER(SCR); 1523 AR5K_PRINT_REGISTER(INTPEND); 1524 AR5K_PRINT_REGISTER(PCICFG); 1525 AR5K_PRINT_REGISTER(GPIOCR); 1526 AR5K_PRINT_REGISTER(GPIODO); 1527 AR5K_PRINT_REGISTER(SREV); 1528 AR5K_PRINT_REGISTER(EEPROM_BASE); 1529 AR5K_PRINT_REGISTER(EEPROM_DATA); 1530 AR5K_PRINT_REGISTER(EEPROM_CMD); 1531 AR5K_PRINT_REGISTER(EEPROM_CFG); 1532 AR5K_PRINT_REGISTER(PCU_MIN); 1533 AR5K_PRINT_REGISTER(STA_ID0); 1534 AR5K_PRINT_REGISTER(STA_ID1); 1535 AR5K_PRINT_REGISTER(BSS_ID0); 1536 AR5K_PRINT_REGISTER(SLOT_TIME); 1537 AR5K_PRINT_REGISTER(TIME_OUT); 1538 AR5K_PRINT_REGISTER(RSSI_THR); 1539 AR5K_PRINT_REGISTER(BEACON); 1540 AR5K_PRINT_REGISTER(CFP_PERIOD); 1541 AR5K_PRINT_REGISTER(TIMER0); 1542 AR5K_PRINT_REGISTER(TIMER2); 1543 AR5K_PRINT_REGISTER(TIMER3); 1544 AR5K_PRINT_REGISTER(CFP_DUR); 1545 AR5K_PRINT_REGISTER(MCAST_FIL0); 1546 AR5K_PRINT_REGISTER(MCAST_FIL1); 1547 AR5K_PRINT_REGISTER(DIAG_SW); 1548 AR5K_PRINT_REGISTER(TSF_U32); 1549 AR5K_PRINT_REGISTER(ADDAC_TEST); 1550 AR5K_PRINT_REGISTER(DEFAULT_ANTENNA); 1551 AR5K_PRINT_REGISTER(LAST_TSTP); 1552 AR5K_PRINT_REGISTER(NAV); 1553 AR5K_PRINT_REGISTER(RTS_OK); 1554 AR5K_PRINT_REGISTER(ACK_FAIL); 1555 AR5K_PRINT_REGISTER(FCS_FAIL); 1556 AR5K_PRINT_REGISTER(BEACON_CNT); 1557 AR5K_PRINT_REGISTER(KEYTABLE_0); 1558 printf("\n"); 1559 1560 printf("PHY registers:\n"); 1561 AR5K_PRINT_REGISTER(PHY_TURBO); 1562 AR5K_PRINT_REGISTER(PHY_AGC); 1563 AR5K_PRINT_REGISTER(PHY_CHIP_ID); 1564 AR5K_PRINT_REGISTER(PHY_AGCCTL); 1565 AR5K_PRINT_REGISTER(PHY_NF); 1566 AR5K_PRINT_REGISTER(PHY_RX_DELAY); 1567 AR5K_PRINT_REGISTER(PHY_IQ); 1568 AR5K_PRINT_REGISTER(PHY_PAPD_PROBE); 1569 AR5K_PRINT_REGISTER(PHY_FC); 1570 AR5K_PRINT_REGISTER(PHY_RADAR); 1571 AR5K_PRINT_REGISTER(PHY_ANT_SWITCH_TABLE_0); 1572 AR5K_PRINT_REGISTER(PHY_ANT_SWITCH_TABLE_1); 1573 printf("\n"); 1574 #endif 1575 } 1576 1577 HAL_BOOL 1578 ar5k_ar5211_get_diag_state(struct ath_hal *hal, int id, void **device, 1579 u_int *size) 1580 { 1581 /* 1582 * We'll ignore this right now. This seems to be some kind of an obscure 1583 * debugging interface for the binary-only HAL. 1584 */ 1585 return (AH_FALSE); 1586 } 1587 1588 void 1589 ar5k_ar5211_get_lladdr(struct ath_hal *hal, u_int8_t *mac) 1590 { 1591 bcopy(hal->ah_sta_id, mac, IEEE80211_ADDR_LEN); 1592 } 1593 1594 HAL_BOOL 1595 ar5k_ar5211_set_lladdr(struct ath_hal *hal, const u_int8_t *mac) 1596 { 1597 u_int32_t low_id, high_id; 1598 1599 /* Set new station ID */ 1600 bcopy(mac, hal->ah_sta_id, IEEE80211_ADDR_LEN); 1601 1602 low_id = AR5K_LOW_ID(mac); 1603 high_id = 0x0000ffff & AR5K_HIGH_ID(mac); 1604 1605 AR5K_REG_WRITE(AR5K_AR5211_STA_ID0, low_id); 1606 AR5K_REG_WRITE(AR5K_AR5211_STA_ID1, high_id); 1607 1608 return (AH_TRUE); 1609 } 1610 1611 HAL_BOOL 1612 ar5k_ar5211_set_regdomain(struct ath_hal *hal, u_int16_t regdomain, 1613 HAL_STATUS *status) 1614 { 1615 ieee80211_regdomain_t ieee_regdomain; 1616 1617 ieee_regdomain = ar5k_regdomain_to_ieee(regdomain); 1618 1619 if (ar5k_eeprom_regulation_domain(hal, AH_TRUE, 1620 &ieee_regdomain) == AH_TRUE) { 1621 *status = HAL_OK; 1622 return (AH_TRUE); 1623 } 1624 1625 *status = EIO; 1626 1627 return (AH_FALSE); 1628 } 1629 1630 void 1631 ar5k_ar5211_set_ledstate(struct ath_hal *hal, HAL_LED_STATE state) 1632 { 1633 u_int32_t led; 1634 1635 AR5K_REG_DISABLE_BITS(AR5K_AR5211_PCICFG, 1636 AR5K_AR5211_PCICFG_LEDMODE | AR5K_AR5211_PCICFG_LED); 1637 1638 /* 1639 * Some blinking values, define at your wish 1640 */ 1641 switch (state) { 1642 case IEEE80211_S_SCAN: 1643 case IEEE80211_S_AUTH: 1644 led = AR5K_AR5211_PCICFG_LEDMODE_PROP | 1645 AR5K_AR5211_PCICFG_LED_PEND; 1646 break; 1647 1648 case IEEE80211_S_INIT: 1649 led = AR5K_AR5211_PCICFG_LEDMODE_PROP | 1650 AR5K_AR5211_PCICFG_LED_NONE; 1651 break; 1652 1653 case IEEE80211_S_ASSOC: 1654 case IEEE80211_S_RUN: 1655 led = AR5K_AR5211_PCICFG_LEDMODE_PROP | 1656 AR5K_AR5211_PCICFG_LED_ASSOC; 1657 break; 1658 1659 default: 1660 led = AR5K_AR5211_PCICFG_LEDMODE_PROM | 1661 AR5K_AR5211_PCICFG_LED_NONE; 1662 break; 1663 } 1664 1665 AR5K_REG_ENABLE_BITS(AR5K_AR5211_PCICFG, led); 1666 } 1667 1668 void 1669 ar5k_ar5211_set_associd(struct ath_hal *hal, const u_int8_t *bssid, 1670 u_int16_t assoc_id, u_int16_t tim_offset) 1671 { 1672 u_int32_t low_id, high_id; 1673 1674 /* 1675 * Set BSSID which triggers the "SME Join" operation 1676 */ 1677 low_id = AR5K_LOW_ID(bssid); 1678 high_id = AR5K_HIGH_ID(bssid); 1679 AR5K_REG_WRITE(AR5K_AR5211_BSS_ID0, low_id); 1680 AR5K_REG_WRITE(AR5K_AR5211_BSS_ID1, high_id | 1681 ((assoc_id & 0x3fff) << AR5K_AR5211_BSS_ID1_AID_S)); 1682 bcopy(bssid, hal->ah_bssid, IEEE80211_ADDR_LEN); 1683 1684 if (assoc_id == 0) { 1685 ar5k_ar5211_disable_pspoll(hal); 1686 return; 1687 } 1688 1689 AR5K_REG_WRITE(AR5K_AR5211_BEACON, 1690 (AR5K_REG_READ(AR5K_AR5211_BEACON) & 1691 ~AR5K_AR5211_BEACON_TIM) | 1692 (((tim_offset ? tim_offset + 4 : 0) << 1693 AR5K_AR5211_BEACON_TIM_S) & 1694 AR5K_AR5211_BEACON_TIM)); 1695 1696 ar5k_ar5211_enable_pspoll(hal, NULL, 0); 1697 } 1698 1699 HAL_BOOL 1700 ar5k_ar5211_set_bssid_mask(struct ath_hal *hal, const u_int8_t* mask) 1701 { 1702 /* Not supported in 5211 */ 1703 return (AH_FALSE); 1704 } 1705 1706 HAL_BOOL 1707 ar5k_ar5211_set_gpio_output(struct ath_hal *hal, u_int32_t gpio) 1708 { 1709 if (gpio > AR5K_AR5211_NUM_GPIO) 1710 return (AH_FALSE); 1711 1712 AR5K_REG_WRITE(AR5K_AR5211_GPIOCR, 1713 (AR5K_REG_READ(AR5K_AR5211_GPIOCR) &~ AR5K_AR5211_GPIOCR_ALL(gpio)) 1714 | AR5K_AR5211_GPIOCR_ALL(gpio)); 1715 1716 return (AH_TRUE); 1717 } 1718 1719 HAL_BOOL 1720 ar5k_ar5211_set_gpio_input(struct ath_hal *hal, u_int32_t gpio) 1721 { 1722 if (gpio > AR5K_AR5211_NUM_GPIO) 1723 return (AH_FALSE); 1724 1725 AR5K_REG_WRITE(AR5K_AR5211_GPIOCR, 1726 (AR5K_REG_READ(AR5K_AR5211_GPIOCR) &~ AR5K_AR5211_GPIOCR_ALL(gpio)) 1727 | AR5K_AR5211_GPIOCR_NONE(gpio)); 1728 1729 return (AH_TRUE); 1730 } 1731 1732 u_int32_t 1733 ar5k_ar5211_get_gpio(struct ath_hal *hal, u_int32_t gpio) 1734 { 1735 if (gpio > AR5K_AR5211_NUM_GPIO) 1736 return (0xffffffff); 1737 1738 /* GPIO input magic */ 1739 return (((AR5K_REG_READ(AR5K_AR5211_GPIODI) & 1740 AR5K_AR5211_GPIODI_M) >> gpio) & 0x1); 1741 } 1742 1743 HAL_BOOL 1744 ar5k_ar5211_set_gpio(struct ath_hal *hal, u_int32_t gpio, u_int32_t val) 1745 { 1746 u_int32_t data; 1747 1748 if (gpio > AR5K_AR5211_NUM_GPIO) 1749 return (0xffffffff); 1750 1751 /* GPIO output magic */ 1752 data = AR5K_REG_READ(AR5K_AR5211_GPIODO); 1753 1754 data &= ~(1 << gpio); 1755 data |= (val&1) << gpio; 1756 1757 AR5K_REG_WRITE(AR5K_AR5211_GPIODO, data); 1758 1759 return (AH_TRUE); 1760 } 1761 1762 void 1763 ar5k_ar5211_set_gpio_intr(struct ath_hal *hal, u_int gpio, 1764 u_int32_t interrupt_level) 1765 { 1766 u_int32_t data; 1767 1768 if (gpio > AR5K_AR5211_NUM_GPIO) 1769 return; 1770 1771 /* 1772 * Set the GPIO interrupt 1773 */ 1774 data = (AR5K_REG_READ(AR5K_AR5211_GPIOCR) & 1775 ~(AR5K_AR5211_GPIOCR_INT_SEL(gpio) | AR5K_AR5211_GPIOCR_INT_SELH | 1776 AR5K_AR5211_GPIOCR_INT_ENA | AR5K_AR5211_GPIOCR_ALL(gpio))) | 1777 (AR5K_AR5211_GPIOCR_INT_SEL(gpio) | AR5K_AR5211_GPIOCR_INT_ENA); 1778 1779 AR5K_REG_WRITE(AR5K_AR5211_GPIOCR, 1780 interrupt_level ? data : (data | AR5K_AR5211_GPIOCR_INT_SELH)); 1781 1782 hal->ah_imr |= AR5K_AR5211_PIMR_GPIO; 1783 1784 /* Enable GPIO interrupts */ 1785 AR5K_REG_ENABLE_BITS(AR5K_AR5211_PIMR, AR5K_AR5211_PIMR_GPIO); 1786 } 1787 1788 u_int32_t 1789 ar5k_ar5211_get_tsf32(struct ath_hal *hal) 1790 { 1791 return (AR5K_REG_READ(AR5K_AR5211_TSF_L32)); 1792 } 1793 1794 u_int64_t 1795 ar5k_ar5211_get_tsf64(struct ath_hal *hal) 1796 { 1797 u_int64_t tsf = AR5K_REG_READ(AR5K_AR5211_TSF_U32); 1798 1799 return (AR5K_REG_READ(AR5K_AR5211_TSF_L32) | (tsf << 32)); 1800 } 1801 1802 void 1803 ar5k_ar5211_reset_tsf(struct ath_hal *hal) 1804 { 1805 AR5K_REG_ENABLE_BITS(AR5K_AR5211_BEACON, 1806 AR5K_AR5211_BEACON_RESET_TSF); 1807 } 1808 1809 u_int16_t 1810 ar5k_ar5211_get_regdomain(struct ath_hal *hal) 1811 { 1812 return (ar5k_get_regdomain(hal)); 1813 } 1814 1815 HAL_BOOL 1816 ar5k_ar5211_detect_card_present(struct ath_hal *hal) 1817 { 1818 u_int16_t magic; 1819 1820 /* 1821 * Checking the EEPROM's magic value could be an indication 1822 * if the card is still present. I didn't find another suitable 1823 * way to do this. 1824 */ 1825 if (ar5k_ar5211_eeprom_read(hal, AR5K_EEPROM_MAGIC, &magic) != 0) 1826 return (AH_FALSE); 1827 1828 return (magic == AR5K_EEPROM_MAGIC_VALUE ? AH_TRUE : AH_FALSE); 1829 } 1830 1831 void 1832 ar5k_ar5211_update_mib_counters(struct ath_hal *hal, HAL_MIB_STATS *statistics) 1833 { 1834 statistics->ackrcv_bad += AR5K_REG_READ(AR5K_AR5211_ACK_FAIL); 1835 statistics->rts_bad += AR5K_REG_READ(AR5K_AR5211_RTS_FAIL); 1836 statistics->rts_good += AR5K_REG_READ(AR5K_AR5211_RTS_OK); 1837 statistics->fcs_bad += AR5K_REG_READ(AR5K_AR5211_FCS_FAIL); 1838 statistics->beacons += AR5K_REG_READ(AR5K_AR5211_BEACON_CNT); 1839 } 1840 1841 HAL_RFGAIN 1842 ar5k_ar5211_get_rf_gain(struct ath_hal *hal) 1843 { 1844 return (HAL_RFGAIN_INACTIVE); 1845 } 1846 1847 HAL_BOOL 1848 ar5k_ar5211_set_slot_time(struct ath_hal *hal, u_int slot_time) 1849 { 1850 if (slot_time < HAL_SLOT_TIME_9 || slot_time > HAL_SLOT_TIME_MAX) 1851 return (AH_FALSE); 1852 1853 AR5K_REG_WRITE(AR5K_AR5211_DCU_GBL_IFS_SLOT, slot_time); 1854 1855 return (AH_TRUE); 1856 } 1857 1858 u_int 1859 ar5k_ar5211_get_slot_time(struct ath_hal *hal) 1860 { 1861 return (AR5K_REG_READ(AR5K_AR5211_DCU_GBL_IFS_SLOT) & 0xffff); 1862 } 1863 1864 HAL_BOOL 1865 ar5k_ar5211_set_ack_timeout(struct ath_hal *hal, u_int timeout) 1866 { 1867 if (ar5k_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_AR5211_TIME_OUT_ACK), 1868 hal->ah_turbo) <= timeout) 1869 return (AH_FALSE); 1870 1871 AR5K_REG_WRITE_BITS(AR5K_AR5211_TIME_OUT, AR5K_AR5211_TIME_OUT_ACK, 1872 ar5k_htoclock(timeout, hal->ah_turbo)); 1873 1874 return (AH_TRUE); 1875 } 1876 1877 u_int 1878 ar5k_ar5211_get_ack_timeout(struct ath_hal *hal) 1879 { 1880 return (ar5k_clocktoh(AR5K_REG_MS(AR5K_REG_READ(AR5K_AR5211_TIME_OUT), 1881 AR5K_AR5211_TIME_OUT_ACK), hal->ah_turbo)); 1882 } 1883 1884 HAL_BOOL 1885 ar5k_ar5211_set_cts_timeout(struct ath_hal *hal, u_int timeout) 1886 { 1887 if (ar5k_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_AR5211_TIME_OUT_CTS), 1888 hal->ah_turbo) <= timeout) 1889 return (AH_FALSE); 1890 1891 AR5K_REG_WRITE_BITS(AR5K_AR5211_TIME_OUT, AR5K_AR5211_TIME_OUT_CTS, 1892 ar5k_htoclock(timeout, hal->ah_turbo)); 1893 1894 return (AH_TRUE); 1895 } 1896 1897 u_int 1898 ar5k_ar5211_get_cts_timeout(struct ath_hal *hal) 1899 { 1900 return (ar5k_clocktoh(AR5K_REG_MS(AR5K_REG_READ(AR5K_AR5211_TIME_OUT), 1901 AR5K_AR5211_TIME_OUT_CTS), hal->ah_turbo)); 1902 } 1903 1904 /* 1905 * Key table (WEP) functions 1906 */ 1907 1908 HAL_BOOL 1909 ar5k_ar5211_is_cipher_supported(struct ath_hal *hal, HAL_CIPHER cipher) 1910 { 1911 /* 1912 * The AR5211 only supports WEP 1913 */ 1914 if (cipher == HAL_CIPHER_WEP) 1915 return (AH_TRUE); 1916 1917 return (AH_FALSE); 1918 } 1919 1920 u_int32_t 1921 ar5k_ar5211_get_keycache_size(struct ath_hal *hal) 1922 { 1923 return (AR5K_AR5211_KEYCACHE_SIZE); 1924 } 1925 1926 HAL_BOOL 1927 ar5k_ar5211_reset_key(struct ath_hal *hal, u_int16_t entry) 1928 { 1929 int i; 1930 1931 AR5K_ASSERT_ENTRY(entry, AR5K_AR5211_KEYTABLE_SIZE); 1932 1933 for (i = 0; i < AR5K_AR5211_KEYCACHE_SIZE; i++) 1934 AR5K_REG_WRITE(AR5K_AR5211_KEYTABLE_OFF(entry, i), 0); 1935 1936 return (AH_FALSE); 1937 } 1938 1939 HAL_BOOL 1940 ar5k_ar5211_is_key_valid(struct ath_hal *hal, u_int16_t entry) 1941 { 1942 AR5K_ASSERT_ENTRY(entry, AR5K_AR5211_KEYTABLE_SIZE); 1943 1944 /* 1945 * Check the validation flag at the end of the entry 1946 */ 1947 if (AR5K_REG_READ(AR5K_AR5211_KEYTABLE_MAC1(entry)) & 1948 AR5K_AR5211_KEYTABLE_VALID) 1949 return (AH_TRUE); 1950 1951 return (AH_FALSE); 1952 } 1953 1954 HAL_BOOL 1955 ar5k_ar5211_set_key(struct ath_hal *hal, u_int16_t entry, 1956 const HAL_KEYVAL *keyval, const u_int8_t *mac, int xor_notused) 1957 { 1958 int i; 1959 u_int32_t key_v[AR5K_AR5211_KEYCACHE_SIZE - 2]; 1960 1961 AR5K_ASSERT_ENTRY(entry, AR5K_AR5211_KEYTABLE_SIZE); 1962 1963 bzero(&key_v, sizeof(key_v)); 1964 1965 switch (keyval->wk_len) { 1966 case AR5K_KEYVAL_LENGTH_40: 1967 bcopy(keyval->wk_key, &key_v[0], 4); 1968 bcopy(keyval->wk_key + 4, &key_v[1], 1); 1969 key_v[5] = AR5K_AR5211_KEYTABLE_TYPE_40; 1970 break; 1971 1972 case AR5K_KEYVAL_LENGTH_104: 1973 bcopy(keyval->wk_key, &key_v[0], 4); 1974 bcopy(keyval->wk_key + 4, &key_v[1], 2); 1975 bcopy(keyval->wk_key + 6, &key_v[2], 4); 1976 bcopy(keyval->wk_key + 10, &key_v[3], 2); 1977 bcopy(keyval->wk_key + 12, &key_v[4], 1); 1978 key_v[5] = AR5K_AR5211_KEYTABLE_TYPE_104; 1979 break; 1980 1981 case AR5K_KEYVAL_LENGTH_128: 1982 bcopy(keyval->wk_key, &key_v[0], 4); 1983 bcopy(keyval->wk_key + 4, &key_v[1], 2); 1984 bcopy(keyval->wk_key + 6, &key_v[2], 4); 1985 bcopy(keyval->wk_key + 10, &key_v[3], 2); 1986 bcopy(keyval->wk_key + 12, &key_v[4], 4); 1987 key_v[5] = AR5K_AR5211_KEYTABLE_TYPE_128; 1988 break; 1989 1990 default: 1991 /* Unsupported key length (not WEP40/104/128) */ 1992 return (AH_FALSE); 1993 } 1994 1995 for (i = 0; i < nitems(key_v); i++) 1996 AR5K_REG_WRITE(AR5K_AR5211_KEYTABLE_OFF(entry, i), key_v[i]); 1997 1998 return (ar5k_ar5211_set_key_lladdr(hal, entry, mac)); 1999 } 2000 2001 HAL_BOOL 2002 ar5k_ar5211_set_key_lladdr(struct ath_hal *hal, u_int16_t entry, 2003 const u_int8_t *mac) 2004 { 2005 u_int32_t low_id, high_id; 2006 const u_int8_t *mac_v; 2007 2008 /* 2009 * Invalid entry (key table overflow) 2010 */ 2011 AR5K_ASSERT_ENTRY(entry, AR5K_AR5211_KEYTABLE_SIZE); 2012 2013 /* MAC may be NULL if it's a broadcast key */ 2014 mac_v = mac == NULL ? etherbroadcastaddr : mac; 2015 2016 low_id = AR5K_LOW_ID(mac_v); 2017 high_id = AR5K_HIGH_ID(mac_v) | AR5K_AR5211_KEYTABLE_VALID; 2018 2019 AR5K_REG_WRITE(AR5K_AR5211_KEYTABLE_MAC0(entry), low_id); 2020 AR5K_REG_WRITE(AR5K_AR5211_KEYTABLE_MAC1(entry), high_id); 2021 2022 return (AH_TRUE); 2023 } 2024 2025 HAL_BOOL 2026 ar5k_ar5211_softcrypto(struct ath_hal *hal, HAL_BOOL enable) 2027 { 2028 u_int32_t bits; 2029 int i; 2030 2031 bits = AR5K_AR5211_DIAG_SW_DIS_ENC | AR5K_AR5211_DIAG_SW_DIS_DEC; 2032 if (enable == AH_TRUE) { 2033 /* Disable the hardware crypto engine */ 2034 AR5K_REG_ENABLE_BITS(AR5K_AR5211_DIAG_SW, bits); 2035 } else { 2036 /* Enable the hardware crypto engine */ 2037 AR5K_REG_DISABLE_BITS(AR5K_AR5211_DIAG_SW, bits); 2038 } 2039 2040 /* Reset the key cache */ 2041 for (i = 0; i < AR5K_AR5211_KEYTABLE_SIZE; i++) 2042 ar5k_ar5211_reset_key(hal, i); 2043 2044 return (AH_TRUE); 2045 } 2046 2047 /* 2048 * Power management functions 2049 */ 2050 2051 HAL_BOOL 2052 ar5k_ar5211_set_power(struct ath_hal *hal, HAL_POWER_MODE mode, 2053 HAL_BOOL set_chip, u_int16_t sleep_duration) 2054 { 2055 u_int32_t staid; 2056 int i; 2057 2058 staid = AR5K_REG_READ(AR5K_AR5211_STA_ID1); 2059 2060 switch (mode) { 2061 case HAL_PM_AUTO: 2062 staid &= ~AR5K_AR5211_STA_ID1_DEFAULT_ANTENNA; 2063 /* FALLTHROUGH */ 2064 case HAL_PM_NETWORK_SLEEP: 2065 if (set_chip == AH_TRUE) { 2066 AR5K_REG_WRITE(AR5K_AR5211_SCR, 2067 AR5K_AR5211_SCR_SLE | sleep_duration); 2068 } 2069 staid |= AR5K_AR5211_STA_ID1_PWR_SV; 2070 break; 2071 2072 case HAL_PM_FULL_SLEEP: 2073 if (set_chip == AH_TRUE) { 2074 AR5K_REG_WRITE(AR5K_AR5211_SCR, 2075 AR5K_AR5211_SCR_SLE_SLP); 2076 } 2077 staid |= AR5K_AR5211_STA_ID1_PWR_SV; 2078 break; 2079 2080 case HAL_PM_AWAKE: 2081 if (set_chip == AH_FALSE) 2082 goto commit; 2083 2084 AR5K_REG_WRITE(AR5K_AR5211_SCR, AR5K_AR5211_SCR_SLE_WAKE); 2085 2086 for (i = 5000; i > 0; i--) { 2087 /* Check if the AR5211 did wake up */ 2088 if ((AR5K_REG_READ(AR5K_AR5211_PCICFG) & 2089 AR5K_AR5211_PCICFG_SPWR_DN) == 0) 2090 break; 2091 2092 /* Wait a bit and retry */ 2093 AR5K_DELAY(200); 2094 AR5K_REG_WRITE(AR5K_AR5211_SCR, 2095 AR5K_AR5211_SCR_SLE_WAKE); 2096 } 2097 2098 /* Fail if the AR5211 didn't wake up */ 2099 if (i <= 0) 2100 return (AH_FALSE); 2101 2102 staid &= ~AR5K_AR5211_STA_ID1_PWR_SV; 2103 break; 2104 2105 default: 2106 return (AH_FALSE); 2107 } 2108 2109 commit: 2110 hal->ah_power_mode = mode; 2111 2112 AR5K_REG_WRITE(AR5K_AR5211_STA_ID1, staid); 2113 2114 return (AH_TRUE); 2115 } 2116 2117 HAL_POWER_MODE 2118 ar5k_ar5211_get_power_mode(struct ath_hal *hal) 2119 { 2120 return (hal->ah_power_mode); 2121 } 2122 2123 HAL_BOOL 2124 ar5k_ar5211_query_pspoll_support(struct ath_hal *hal) 2125 { 2126 /* nope */ 2127 return (AH_FALSE); 2128 } 2129 2130 HAL_BOOL 2131 ar5k_ar5211_init_pspoll(struct ath_hal *hal) 2132 { 2133 /* 2134 * Not used on the AR5211 2135 */ 2136 return (AH_FALSE); 2137 } 2138 2139 HAL_BOOL 2140 ar5k_ar5211_enable_pspoll(struct ath_hal *hal, u_int8_t *bssid, 2141 u_int16_t assoc_id) 2142 { 2143 return (AH_FALSE); 2144 } 2145 2146 HAL_BOOL 2147 ar5k_ar5211_disable_pspoll(struct ath_hal *hal) 2148 { 2149 return (AH_FALSE); 2150 } 2151 2152 /* 2153 * Beacon functions 2154 */ 2155 2156 void 2157 ar5k_ar5211_init_beacon(struct ath_hal *hal, u_int32_t next_beacon, 2158 u_int32_t interval) 2159 { 2160 u_int32_t timer1, timer2, timer3; 2161 2162 /* 2163 * Set the additional timers by mode 2164 */ 2165 switch (hal->ah_op_mode) { 2166 case HAL_M_STA: 2167 timer1 = 0x0000ffff; 2168 timer2 = 0x0007ffff; 2169 break; 2170 2171 default: 2172 timer1 = (next_beacon - AR5K_TUNE_DMA_BEACON_RESP) << 2173 0x00000003; 2174 timer2 = (next_beacon - AR5K_TUNE_SW_BEACON_RESP) << 2175 0x00000003; 2176 } 2177 2178 timer3 = next_beacon + 2179 (hal->ah_atim_window ? hal->ah_atim_window : 1); 2180 2181 /* 2182 * Enable all timers and set the beacon register 2183 * (next beacon, DMA beacon, software beacon, ATIM window time) 2184 */ 2185 AR5K_REG_WRITE(AR5K_AR5211_TIMER0, next_beacon); 2186 AR5K_REG_WRITE(AR5K_AR5211_TIMER1, timer1); 2187 AR5K_REG_WRITE(AR5K_AR5211_TIMER2, timer2); 2188 AR5K_REG_WRITE(AR5K_AR5211_TIMER3, timer3); 2189 2190 AR5K_REG_WRITE(AR5K_AR5211_BEACON, interval & 2191 (AR5K_AR5211_BEACON_PERIOD | AR5K_AR5211_BEACON_RESET_TSF | 2192 AR5K_AR5211_BEACON_ENABLE)); 2193 } 2194 2195 void 2196 ar5k_ar5211_set_beacon_timers(struct ath_hal *hal, 2197 const HAL_BEACON_STATE *state, u_int32_t tsf, u_int32_t dtim_count, 2198 u_int32_t cfp_count) 2199 { 2200 u_int32_t cfp_period, next_cfp; 2201 2202 /* Return on an invalid beacon state */ 2203 if (state->bs_interval < 1) 2204 return; 2205 2206 /* 2207 * PCF support? 2208 */ 2209 if (state->bs_cfp_period > 0) { 2210 /* Enable CFP mode and set the CFP and timer registers */ 2211 cfp_period = state->bs_cfp_period * state->bs_dtim_period * 2212 state->bs_interval; 2213 next_cfp = (cfp_count * state->bs_dtim_period + dtim_count) * 2214 state->bs_interval; 2215 2216 AR5K_REG_DISABLE_BITS(AR5K_AR5211_STA_ID1, 2217 AR5K_AR5211_STA_ID1_DEFAULT_ANTENNA | 2218 AR5K_AR5211_STA_ID1_PCF); 2219 AR5K_REG_WRITE(AR5K_AR5211_CFP_PERIOD, cfp_period); 2220 AR5K_REG_WRITE(AR5K_AR5211_CFP_DUR, state->bs_cfp_max_duration); 2221 AR5K_REG_WRITE(AR5K_AR5211_TIMER2, 2222 (tsf + (next_cfp == 0 ? cfp_period : next_cfp)) << 3); 2223 } else { 2224 /* Disable PCF mode */ 2225 AR5K_REG_DISABLE_BITS(AR5K_AR5211_STA_ID1, 2226 AR5K_AR5211_STA_ID1_DEFAULT_ANTENNA | 2227 AR5K_AR5211_STA_ID1_PCF); 2228 } 2229 2230 /* 2231 * Enable the beacon timer register 2232 */ 2233 AR5K_REG_WRITE(AR5K_AR5211_TIMER0, state->bs_next_beacon); 2234 2235 /* 2236 * Start the beacon timers 2237 */ 2238 AR5K_REG_WRITE(AR5K_AR5211_BEACON, 2239 (AR5K_REG_READ(AR5K_AR5211_BEACON) &~ 2240 (AR5K_AR5211_BEACON_PERIOD | AR5K_AR5211_BEACON_TIM)) | 2241 AR5K_REG_SM(state->bs_tim_offset ? state->bs_tim_offset + 4 : 0, 2242 AR5K_AR5211_BEACON_TIM) | AR5K_REG_SM(state->bs_interval, 2243 AR5K_AR5211_BEACON_PERIOD)); 2244 2245 /* 2246 * Write new beacon miss threshold, if it appears to be valid 2247 */ 2248 if ((AR5K_AR5211_RSSI_THR_BMISS >> AR5K_AR5211_RSSI_THR_BMISS_S) < 2249 state->bs_bmiss_threshold) 2250 return; 2251 2252 AR5K_REG_WRITE_BITS(AR5K_AR5211_RSSI_THR_M, 2253 AR5K_AR5211_RSSI_THR_BMISS, state->bs_bmiss_threshold); 2254 AR5K_REG_WRITE_BITS(AR5K_AR5211_SCR, AR5K_AR5211_SCR_SLDUR, 2255 (state->bs_sleepduration - 3) << 3); 2256 } 2257 2258 void 2259 ar5k_ar5211_reset_beacon(struct ath_hal *hal) 2260 { 2261 /* 2262 * Disable beacon timer 2263 */ 2264 AR5K_REG_WRITE(AR5K_AR5211_TIMER0, 0); 2265 2266 /* 2267 * Disable some beacon register values 2268 */ 2269 AR5K_REG_DISABLE_BITS(AR5K_AR5211_STA_ID1, 2270 AR5K_AR5211_STA_ID1_DEFAULT_ANTENNA | AR5K_AR5211_STA_ID1_PCF); 2271 AR5K_REG_WRITE(AR5K_AR5211_BEACON, AR5K_AR5211_BEACON_PERIOD); 2272 } 2273 2274 HAL_BOOL 2275 ar5k_ar5211_wait_for_beacon(struct ath_hal *hal, bus_addr_t phys_addr) 2276 { 2277 HAL_BOOL ret; 2278 2279 /* 2280 * Wait for beaconn queue to be done 2281 */ 2282 ret = ar5k_register_timeout(hal, 2283 AR5K_AR5211_QCU_STS(HAL_TX_QUEUE_ID_BEACON), 2284 AR5K_AR5211_QCU_STS_FRMPENDCNT, 0, AH_FALSE); 2285 2286 if (AR5K_REG_READ_Q(AR5K_AR5211_QCU_TXE, HAL_TX_QUEUE_ID_BEACON)) 2287 return (AH_FALSE); 2288 2289 return (ret); 2290 } 2291 2292 /* 2293 * Interrupt handling 2294 */ 2295 2296 HAL_BOOL 2297 ar5k_ar5211_is_intr_pending(struct ath_hal *hal) 2298 { 2299 return (AR5K_REG_READ(AR5K_AR5211_INTPEND) == 0 ? AH_FALSE : AH_TRUE); 2300 } 2301 2302 HAL_BOOL 2303 ar5k_ar5211_get_isr(struct ath_hal *hal, u_int32_t *interrupt_mask) 2304 { 2305 u_int32_t data; 2306 2307 /* 2308 * Read interrupt status from the Read-And-Clear shadow register 2309 */ 2310 data = AR5K_REG_READ(AR5K_AR5211_RAC_PISR); 2311 2312 /* 2313 * Get abstract interrupt mask (HAL-compatible) 2314 */ 2315 *interrupt_mask = (data & HAL_INT_COMMON) & hal->ah_imr; 2316 2317 if (data == HAL_INT_NOCARD) 2318 return (AH_FALSE); 2319 2320 if (data & (AR5K_AR5211_PISR_RXOK | AR5K_AR5211_PISR_RXERR)) 2321 *interrupt_mask |= HAL_INT_RX; 2322 2323 if (data & (AR5K_AR5211_PISR_TXOK | AR5K_AR5211_PISR_TXERR)) 2324 *interrupt_mask |= HAL_INT_TX; 2325 2326 if (data & (AR5K_AR5211_PISR_HIUERR)) 2327 *interrupt_mask |= HAL_INT_FATAL; 2328 2329 /* 2330 * Special interrupt handling (not caught by the driver) 2331 */ 2332 if (((*interrupt_mask) & AR5K_AR5211_PISR_RXPHY) && 2333 hal->ah_radar.r_enabled == AH_TRUE) 2334 ar5k_radar_alert(hal); 2335 2336 return (AH_TRUE); 2337 } 2338 2339 u_int32_t 2340 ar5k_ar5211_get_intr(struct ath_hal *hal) 2341 { 2342 /* Return the interrupt mask stored previously */ 2343 return (hal->ah_imr); 2344 } 2345 2346 HAL_INT 2347 ar5k_ar5211_set_intr(struct ath_hal *hal, HAL_INT new_mask) 2348 { 2349 HAL_INT old_mask, int_mask; 2350 2351 /* 2352 * Disable card interrupts to prevent any race conditions 2353 * (they will be re-enabled afterwards). 2354 */ 2355 AR5K_REG_WRITE(AR5K_AR5211_IER, AR5K_AR5211_IER_DISABLE); 2356 2357 old_mask = hal->ah_imr; 2358 2359 /* 2360 * Add additional, chipset-dependent interrupt mask flags 2361 * and write them to the IMR (interrupt mask register). 2362 */ 2363 int_mask = new_mask & HAL_INT_COMMON; 2364 2365 if (new_mask & HAL_INT_RX) 2366 int_mask |= 2367 AR5K_AR5211_PIMR_RXOK | 2368 AR5K_AR5211_PIMR_RXERR | 2369 AR5K_AR5211_PIMR_RXORN | 2370 AR5K_AR5211_PIMR_RXDESC; 2371 2372 if (new_mask & HAL_INT_TX) 2373 int_mask |= 2374 AR5K_AR5211_PIMR_TXOK | 2375 AR5K_AR5211_PIMR_TXERR | 2376 AR5K_AR5211_PIMR_TXDESC | 2377 AR5K_AR5211_PIMR_TXURN; 2378 2379 if (new_mask & HAL_INT_FATAL) { 2380 int_mask |= AR5K_AR5211_PIMR_HIUERR; 2381 AR5K_REG_ENABLE_BITS(AR5K_AR5211_SIMR2, 2382 AR5K_AR5211_SIMR2_MCABT | 2383 AR5K_AR5211_SIMR2_SSERR | 2384 AR5K_AR5211_SIMR2_DPERR); 2385 } 2386 2387 AR5K_REG_WRITE(AR5K_AR5211_PIMR, int_mask); 2388 2389 /* Store new interrupt mask */ 2390 hal->ah_imr = new_mask; 2391 2392 /* ..re-enable interrupts */ 2393 AR5K_REG_WRITE(AR5K_AR5211_IER, AR5K_AR5211_IER_ENABLE); 2394 2395 return (old_mask); 2396 } 2397 2398 /* 2399 * Misc internal functions 2400 */ 2401 2402 HAL_BOOL 2403 ar5k_ar5211_get_capabilities(struct ath_hal *hal) 2404 { 2405 u_int16_t ee_header; 2406 u_int a, b, g; 2407 2408 /* Capabilities stored in the EEPROM */ 2409 ee_header = hal->ah_capabilities.cap_eeprom.ee_header; 2410 2411 a = AR5K_EEPROM_HDR_11A(ee_header); 2412 b = AR5K_EEPROM_HDR_11B(ee_header); 2413 g = AR5K_EEPROM_HDR_11G(ee_header); 2414 2415 /* 2416 * If the EEPROM is not reporting any mode, we try 11b. 2417 * This might fix a few broken devices with invalid EEPROM. 2418 */ 2419 if (!a && !b && !g) 2420 b = 1; 2421 2422 /* 2423 * XXX The AR5211 tranceiver supports frequencies from 4920 to 6100GHz 2424 * XXX and from 2312 to 2732GHz. There are problems with the current 2425 * XXX ieee80211 implementation because the IEEE channel mapping 2426 * XXX does not support negative channel numbers (2312MHz is channel 2427 * XXX -19). Of course, this doesn't matter because these channels 2428 * XXX are out of range but some regulation domains like MKK (Japan) 2429 * XXX will support frequencies somewhere around 4.8GHz. 2430 */ 2431 2432 /* 2433 * Set radio capabilities 2434 */ 2435 2436 if (a) { 2437 hal->ah_capabilities.cap_range.range_5ghz_min = 5005; /* 4920 */ 2438 hal->ah_capabilities.cap_range.range_5ghz_max = 6100; 2439 2440 /* Set supported modes */ 2441 hal->ah_capabilities.cap_mode = HAL_MODE_11A | HAL_MODE_TURBO; 2442 } 2443 2444 /* This chip will support 802.11b if the 2GHz radio is connected */ 2445 if (b || g) { 2446 hal->ah_capabilities.cap_range.range_2ghz_min = 2412; /* 2312 */ 2447 hal->ah_capabilities.cap_range.range_2ghz_max = 2732; 2448 2449 if (b) 2450 hal->ah_capabilities.cap_mode |= HAL_MODE_11B; 2451 #if 0 2452 if (g) 2453 hal->ah_capabilities.cap_mode |= HAL_MODE_11G; 2454 #endif 2455 } 2456 2457 /* GPIO */ 2458 hal->ah_gpio_npins = AR5K_AR5211_NUM_GPIO; 2459 2460 /* Set number of supported TX queues */ 2461 hal->ah_capabilities.cap_queues.q_tx_num = AR5K_AR5211_TX_NUM_QUEUES; 2462 2463 return (AH_TRUE); 2464 } 2465 2466 void 2467 ar5k_ar5211_radar_alert(struct ath_hal *hal, HAL_BOOL enable) 2468 { 2469 /* 2470 * Enable radar detection 2471 */ 2472 AR5K_REG_WRITE(AR5K_AR5211_IER, AR5K_AR5211_IER_DISABLE); 2473 2474 if (enable == AH_TRUE) { 2475 AR5K_REG_WRITE(AR5K_AR5211_PHY_RADAR, 2476 AR5K_AR5211_PHY_RADAR_ENABLE); 2477 AR5K_REG_ENABLE_BITS(AR5K_AR5211_PIMR, 2478 AR5K_AR5211_PIMR_RXPHY); 2479 } else { 2480 AR5K_REG_WRITE(AR5K_AR5211_PHY_RADAR, 2481 AR5K_AR5211_PHY_RADAR_DISABLE); 2482 AR5K_REG_DISABLE_BITS(AR5K_AR5211_PIMR, 2483 AR5K_AR5211_PIMR_RXPHY); 2484 } 2485 2486 AR5K_REG_WRITE(AR5K_AR5211_IER, AR5K_AR5211_IER_ENABLE); 2487 } 2488 2489 /* 2490 * EEPROM access functions 2491 */ 2492 2493 HAL_BOOL 2494 ar5k_ar5211_eeprom_is_busy(struct ath_hal *hal) 2495 { 2496 return (AR5K_REG_READ(AR5K_AR5211_CFG) & AR5K_AR5211_CFG_EEBS ? 2497 AH_TRUE : AH_FALSE); 2498 } 2499 2500 int 2501 ar5k_ar5211_eeprom_read(struct ath_hal *hal, u_int32_t offset, u_int16_t *data) 2502 { 2503 u_int32_t status, i; 2504 2505 /* 2506 * Initialize EEPROM access 2507 */ 2508 AR5K_REG_WRITE(AR5K_AR5211_EEPROM_BASE, (u_int8_t)offset); 2509 AR5K_REG_ENABLE_BITS(AR5K_AR5211_EEPROM_CMD, 2510 AR5K_AR5211_EEPROM_CMD_READ); 2511 2512 for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) { 2513 status = AR5K_REG_READ(AR5K_AR5211_EEPROM_STATUS); 2514 if (status & AR5K_AR5211_EEPROM_STAT_RDDONE) { 2515 if (status & AR5K_AR5211_EEPROM_STAT_RDERR) 2516 return (EIO); 2517 *data = (u_int16_t) 2518 (AR5K_REG_READ(AR5K_AR5211_EEPROM_DATA) & 0xffff); 2519 return (0); 2520 } 2521 AR5K_DELAY(15); 2522 } 2523 2524 return (ETIMEDOUT); 2525 } 2526 2527 int 2528 ar5k_ar5211_eeprom_write(struct ath_hal *hal, u_int32_t offset, u_int16_t data) 2529 { 2530 u_int32_t status, timeout; 2531 2532 /* Enable eeprom access */ 2533 AR5K_REG_ENABLE_BITS(AR5K_AR5211_EEPROM_CMD, 2534 AR5K_AR5211_EEPROM_CMD_RESET); 2535 AR5K_REG_ENABLE_BITS(AR5K_AR5211_EEPROM_CMD, 2536 AR5K_AR5211_EEPROM_CMD_WRITE); 2537 2538 /* 2539 * Prime write pump 2540 */ 2541 AR5K_REG_WRITE(AR5K_AR5211_EEPROM_BASE, (u_int8_t)offset - 1); 2542 2543 for (timeout = 10000; timeout > 0; timeout--) { 2544 AR5K_DELAY(1); 2545 status = AR5K_REG_READ(AR5K_AR5211_EEPROM_STATUS); 2546 if (status & AR5K_AR5211_EEPROM_STAT_WRDONE) { 2547 if (status & AR5K_AR5211_EEPROM_STAT_WRERR) 2548 return (EIO); 2549 return (0); 2550 } 2551 } 2552 2553 return (ETIMEDOUT); 2554 } 2555 2556 /* 2557 * RF register settings 2558 */ 2559 2560 HAL_BOOL 2561 ar5k_ar5211_rfregs(struct ath_hal *hal, HAL_CHANNEL *channel, u_int freq, 2562 u_int ee_mode) 2563 { 2564 struct ar5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; 2565 struct ar5k_ar5211_ini_rf rf[nitems(ar5211_rf)]; 2566 u_int32_t ob, db, obdb, xpds, xpdp, x_gain; 2567 u_int i; 2568 2569 bcopy(ar5211_rf, rf, sizeof(rf)); 2570 obdb = 0; 2571 2572 if (freq == AR5K_INI_RFGAIN_2GHZ && 2573 hal->ah_ee_version >= AR5K_EEPROM_VERSION_3_1) { 2574 ob = ar5k_bitswap(ee->ee_ob[ee_mode][0], 3); 2575 db = ar5k_bitswap(ee->ee_db[ee_mode][0], 3); 2576 rf[25].rf_value[freq] = 2577 ((ob << 6) & 0xc0) | (rf[25].rf_value[freq] & ~0xc0); 2578 rf[26].rf_value[freq] = 2579 (((ob >> 2) & 0x1) | ((db << 1) & 0xe)) | 2580 (rf[26].rf_value[freq] & ~0xf); 2581 } 2582 2583 if (freq == AR5K_INI_RFGAIN_5GHZ) { 2584 /* For 11a and Turbo */ 2585 obdb = channel->c_channel >= 5725 ? 3 : 2586 (channel->c_channel >= 5500 ? 2 : 2587 (channel->c_channel >= 5260 ? 1 : 2588 (channel->c_channel > 4000 ? 0 : -1))); 2589 } 2590 2591 /* bogus channel: bad beacon? */ 2592 if (obdb < 0) 2593 return (AH_FALSE); 2594 2595 ob = ee->ee_ob[ee_mode][obdb]; 2596 db = ee->ee_db[ee_mode][obdb]; 2597 x_gain = ee->ee_x_gain[ee_mode]; 2598 xpds = ee->ee_xpd[ee_mode]; 2599 xpdp = !xpds; 2600 2601 rf[11].rf_value[freq] = (rf[11].rf_value[freq] & ~0xc0) | 2602 (((ar5k_bitswap(x_gain, 4) << 7) | (xpdp << 6)) & 0xc0); 2603 rf[12].rf_value[freq] = (rf[12].rf_value[freq] & ~0x7) | 2604 ((ar5k_bitswap(x_gain, 4) >> 1) & 0x7); 2605 rf[12].rf_value[freq] = (rf[12].rf_value[freq] & ~0x80) | 2606 ((ar5k_bitswap(ob, 3) << 7) & 0x80); 2607 rf[13].rf_value[freq] = (rf[13].rf_value[freq] & ~0x3) | 2608 ((ar5k_bitswap(ob, 3) >> 1) & 0x3); 2609 rf[13].rf_value[freq] = (rf[13].rf_value[freq] & ~0x1c) | 2610 ((ar5k_bitswap(db, 3) << 2) & 0x1c); 2611 rf[17].rf_value[freq] = (rf[17].rf_value[freq] & ~0x8) | 2612 ((xpds << 3) & 0x8); 2613 2614 for (i = 0; i < nitems(rf); i++) { 2615 AR5K_REG_WAIT(i); 2616 AR5K_REG_WRITE((u_int32_t)rf[i].rf_register, 2617 rf[i].rf_value[freq]); 2618 } 2619 2620 hal->ah_rf_gain = HAL_RFGAIN_INACTIVE; 2621 2622 return (AH_TRUE); 2623 } 2624 2625 HAL_BOOL 2626 ar5k_ar5211_set_txpower_limit(struct ath_hal *hal, u_int power) 2627 { 2628 /* Not implemented */ 2629 return (AH_FALSE); 2630 } 2631