1 /* $OpenBSD: ar5211.c,v 1.42 2009/02/06 17:06:45 grange Exp $ */ 2 3 /* 4 * Copyright (c) 2004, 2005, 2006, 2007 Reyk Floeter <reyk@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * HAL interface for the Atheros AR5001 Wireless LAN chipset 21 * (AR5211 + AR5111). 22 */ 23 24 #include <dev/ic/ar5xxx.h> 25 #include <dev/ic/ar5211reg.h> 26 #include <dev/ic/ar5211var.h> 27 28 HAL_BOOL ar5k_ar5211_nic_reset(struct ath_hal *, u_int32_t); 29 HAL_BOOL ar5k_ar5211_nic_wakeup(struct ath_hal *, u_int16_t); 30 u_int16_t ar5k_ar5211_radio_revision(struct ath_hal *, HAL_CHIP); 31 void ar5k_ar5211_fill(struct ath_hal *); 32 void ar5k_ar5211_rfregs(struct ath_hal *, HAL_CHANNEL *, u_int, 33 u_int); 34 35 /* 36 * Initial register setting for the AR5211 37 */ 38 static const struct ar5k_ini ar5211_ini[] = 39 AR5K_AR5211_INI; 40 static const struct ar5k_ar5211_ini_mode ar5211_mode[] = 41 AR5K_AR5211_INI_MODE; 42 static const struct ar5k_ar5211_ini_rf ar5211_rf[] = 43 AR5K_AR5211_INI_RF; 44 45 AR5K_HAL_FUNCTIONS(extern, ar5k_ar5211,); 46 47 void 48 ar5k_ar5211_fill(struct ath_hal *hal) 49 { 50 hal->ah_magic = AR5K_AR5211_MAGIC; 51 52 /* 53 * Init/Exit functions 54 */ 55 AR5K_HAL_FUNCTION(hal, ar5211, get_rate_table); 56 AR5K_HAL_FUNCTION(hal, ar5211, detach); 57 58 /* 59 * Reset functions 60 */ 61 AR5K_HAL_FUNCTION(hal, ar5211, reset); 62 AR5K_HAL_FUNCTION(hal, ar5211, set_opmode); 63 AR5K_HAL_FUNCTION(hal, ar5211, calibrate); 64 65 /* 66 * TX functions 67 */ 68 AR5K_HAL_FUNCTION(hal, ar5211, update_tx_triglevel); 69 AR5K_HAL_FUNCTION(hal, ar5211, setup_tx_queue); 70 AR5K_HAL_FUNCTION(hal, ar5211, setup_tx_queueprops); 71 AR5K_HAL_FUNCTION(hal, ar5211, release_tx_queue); 72 AR5K_HAL_FUNCTION(hal, ar5211, reset_tx_queue); 73 AR5K_HAL_FUNCTION(hal, ar5211, get_tx_buf); 74 AR5K_HAL_FUNCTION(hal, ar5211, put_tx_buf); 75 AR5K_HAL_FUNCTION(hal, ar5211, tx_start); 76 AR5K_HAL_FUNCTION(hal, ar5211, stop_tx_dma); 77 AR5K_HAL_FUNCTION(hal, ar5211, setup_tx_desc); 78 AR5K_HAL_FUNCTION(hal, ar5211, setup_xtx_desc); 79 AR5K_HAL_FUNCTION(hal, ar5211, fill_tx_desc); 80 AR5K_HAL_FUNCTION(hal, ar5211, proc_tx_desc); 81 AR5K_HAL_FUNCTION(hal, ar5211, has_veol); 82 83 /* 84 * RX functions 85 */ 86 AR5K_HAL_FUNCTION(hal, ar5211, get_rx_buf); 87 AR5K_HAL_FUNCTION(hal, ar5211, put_rx_buf); 88 AR5K_HAL_FUNCTION(hal, ar5211, start_rx); 89 AR5K_HAL_FUNCTION(hal, ar5211, stop_rx_dma); 90 AR5K_HAL_FUNCTION(hal, ar5211, start_rx_pcu); 91 AR5K_HAL_FUNCTION(hal, ar5211, stop_pcu_recv); 92 AR5K_HAL_FUNCTION(hal, ar5211, set_mcast_filter); 93 AR5K_HAL_FUNCTION(hal, ar5211, set_mcast_filterindex); 94 AR5K_HAL_FUNCTION(hal, ar5211, clear_mcast_filter_idx); 95 AR5K_HAL_FUNCTION(hal, ar5211, get_rx_filter); 96 AR5K_HAL_FUNCTION(hal, ar5211, set_rx_filter); 97 AR5K_HAL_FUNCTION(hal, ar5211, setup_rx_desc); 98 AR5K_HAL_FUNCTION(hal, ar5211, proc_rx_desc); 99 AR5K_HAL_FUNCTION(hal, ar5211, set_rx_signal); 100 101 /* 102 * Misc functions 103 */ 104 AR5K_HAL_FUNCTION(hal, ar5211, dump_state); 105 AR5K_HAL_FUNCTION(hal, ar5211, get_diag_state); 106 AR5K_HAL_FUNCTION(hal, ar5211, get_lladdr); 107 AR5K_HAL_FUNCTION(hal, ar5211, set_lladdr); 108 AR5K_HAL_FUNCTION(hal, ar5211, set_regdomain); 109 AR5K_HAL_FUNCTION(hal, ar5211, set_ledstate); 110 AR5K_HAL_FUNCTION(hal, ar5211, set_associd); 111 AR5K_HAL_FUNCTION(hal, ar5211, set_gpio_input); 112 AR5K_HAL_FUNCTION(hal, ar5211, set_gpio_output); 113 AR5K_HAL_FUNCTION(hal, ar5211, get_gpio); 114 AR5K_HAL_FUNCTION(hal, ar5211, set_gpio); 115 AR5K_HAL_FUNCTION(hal, ar5211, set_gpio_intr); 116 AR5K_HAL_FUNCTION(hal, ar5211, get_tsf32); 117 AR5K_HAL_FUNCTION(hal, ar5211, get_tsf64); 118 AR5K_HAL_FUNCTION(hal, ar5211, reset_tsf); 119 AR5K_HAL_FUNCTION(hal, ar5211, get_regdomain); 120 AR5K_HAL_FUNCTION(hal, ar5211, detect_card_present); 121 AR5K_HAL_FUNCTION(hal, ar5211, update_mib_counters); 122 AR5K_HAL_FUNCTION(hal, ar5211, get_rf_gain); 123 AR5K_HAL_FUNCTION(hal, ar5211, set_slot_time); 124 AR5K_HAL_FUNCTION(hal, ar5211, get_slot_time); 125 AR5K_HAL_FUNCTION(hal, ar5211, set_ack_timeout); 126 AR5K_HAL_FUNCTION(hal, ar5211, get_ack_timeout); 127 AR5K_HAL_FUNCTION(hal, ar5211, set_cts_timeout); 128 AR5K_HAL_FUNCTION(hal, ar5211, get_cts_timeout); 129 130 /* 131 * Key table (WEP) functions 132 */ 133 AR5K_HAL_FUNCTION(hal, ar5211, is_cipher_supported); 134 AR5K_HAL_FUNCTION(hal, ar5211, get_keycache_size); 135 AR5K_HAL_FUNCTION(hal, ar5211, reset_key); 136 AR5K_HAL_FUNCTION(hal, ar5211, is_key_valid); 137 AR5K_HAL_FUNCTION(hal, ar5211, set_key); 138 AR5K_HAL_FUNCTION(hal, ar5211, set_key_lladdr); 139 AR5K_HAL_FUNCTION(hal, ar5211, softcrypto); 140 141 /* 142 * Power management functions 143 */ 144 AR5K_HAL_FUNCTION(hal, ar5211, set_power); 145 AR5K_HAL_FUNCTION(hal, ar5211, get_power_mode); 146 AR5K_HAL_FUNCTION(hal, ar5211, query_pspoll_support); 147 AR5K_HAL_FUNCTION(hal, ar5211, init_pspoll); 148 AR5K_HAL_FUNCTION(hal, ar5211, enable_pspoll); 149 AR5K_HAL_FUNCTION(hal, ar5211, disable_pspoll); 150 151 /* 152 * Beacon functions 153 */ 154 AR5K_HAL_FUNCTION(hal, ar5211, init_beacon); 155 AR5K_HAL_FUNCTION(hal, ar5211, set_beacon_timers); 156 AR5K_HAL_FUNCTION(hal, ar5211, reset_beacon); 157 AR5K_HAL_FUNCTION(hal, ar5211, wait_for_beacon); 158 159 /* 160 * Interrupt functions 161 */ 162 AR5K_HAL_FUNCTION(hal, ar5211, is_intr_pending); 163 AR5K_HAL_FUNCTION(hal, ar5211, get_isr); 164 AR5K_HAL_FUNCTION(hal, ar5211, get_intr); 165 AR5K_HAL_FUNCTION(hal, ar5211, set_intr); 166 167 /* 168 * Chipset functions (ar5k-specific, non-HAL) 169 */ 170 AR5K_HAL_FUNCTION(hal, ar5211, get_capabilities); 171 AR5K_HAL_FUNCTION(hal, ar5211, radar_alert); 172 173 /* 174 * EEPROM access 175 */ 176 AR5K_HAL_FUNCTION(hal, ar5211, eeprom_is_busy); 177 AR5K_HAL_FUNCTION(hal, ar5211, eeprom_read); 178 AR5K_HAL_FUNCTION(hal, ar5211, eeprom_write); 179 180 /* 181 * Unused functions or functions not implemented 182 */ 183 AR5K_HAL_FUNCTION(hal, ar5211, get_tx_queueprops); 184 AR5K_HAL_FUNCTION(hal, ar5211, num_tx_pending); 185 AR5K_HAL_FUNCTION(hal, ar5211, phy_disable); 186 AR5K_HAL_FUNCTION(hal, ar5211, set_txpower_limit); 187 AR5K_HAL_FUNCTION(hal, ar5211, set_def_antenna); 188 AR5K_HAL_FUNCTION(hal, ar5211, get_def_antenna); 189 AR5K_HAL_FUNCTION(hal, ar5211, set_bssid_mask); 190 #ifdef notyet 191 AR5K_HAL_FUNCTION(hal, ar5211, set_capability); 192 AR5K_HAL_FUNCTION(hal, ar5211, proc_mib_event); 193 AR5K_HAL_FUNCTION(hal, ar5211, get_tx_inter_queue); 194 #endif 195 } 196 197 struct ath_hal * 198 ar5k_ar5211_attach(u_int16_t device, void *sc, bus_space_tag_t st, 199 bus_space_handle_t sh, int *status) 200 { 201 struct ath_hal *hal = (struct ath_hal*) sc; 202 u_int8_t mac[IEEE80211_ADDR_LEN]; 203 u_int32_t srev; 204 205 ar5k_ar5211_fill(hal); 206 207 /* Bring device out of sleep and reset its units */ 208 if (ar5k_ar5211_nic_wakeup(hal, AR5K_INIT_MODE) != AH_TRUE) 209 return (NULL); 210 211 /* Get MAC, PHY and RADIO revisions */ 212 srev = AR5K_REG_READ(AR5K_AR5211_SREV); 213 hal->ah_mac_srev = srev; 214 hal->ah_mac_version = AR5K_REG_MS(srev, AR5K_AR5211_SREV_VER); 215 hal->ah_mac_revision = AR5K_REG_MS(srev, AR5K_AR5211_SREV_REV); 216 hal->ah_phy_revision = AR5K_REG_READ(AR5K_AR5211_PHY_CHIP_ID) & 217 0x00ffffffff; 218 hal->ah_radio_5ghz_revision = 219 ar5k_ar5211_radio_revision(hal, HAL_CHIP_5GHZ); 220 hal->ah_radio_2ghz_revision = 0; 221 222 /* Identify the chipset (this has to be done in an early step) */ 223 hal->ah_version = AR5K_AR5211; 224 hal->ah_radio = AR5K_AR5111; 225 hal->ah_phy = AR5K_AR5211_PHY(0); 226 227 bcopy(etherbroadcastaddr, mac, IEEE80211_ADDR_LEN); 228 ar5k_ar5211_set_associd(hal, mac, 0, 0); 229 ar5k_ar5211_get_lladdr(hal, mac); 230 ar5k_ar5211_set_opmode(hal); 231 232 return (hal); 233 } 234 235 HAL_BOOL 236 ar5k_ar5211_nic_reset(struct ath_hal *hal, u_int32_t val) 237 { 238 HAL_BOOL ret = AH_FALSE; 239 u_int32_t mask = val ? val : ~0; 240 241 /* Read-and-clear */ 242 AR5K_REG_READ(AR5K_AR5211_RXDP); 243 244 /* 245 * Reset the device and wait until success 246 */ 247 AR5K_REG_WRITE(AR5K_AR5211_RC, val); 248 249 /* Wait at least 128 PCI clocks */ 250 AR5K_DELAY(15); 251 252 val &= 253 AR5K_AR5211_RC_PCU | AR5K_AR5211_RC_BB; 254 255 mask &= 256 AR5K_AR5211_RC_PCU | AR5K_AR5211_RC_BB; 257 258 ret = ar5k_register_timeout(hal, AR5K_AR5211_RC, mask, val, AH_FALSE); 259 260 /* 261 * Reset configuration register 262 */ 263 if ((val & AR5K_AR5211_RC_PCU) == 0) 264 AR5K_REG_WRITE(AR5K_AR5211_CFG, AR5K_AR5211_INIT_CFG); 265 266 return (ret); 267 } 268 269 HAL_BOOL 270 ar5k_ar5211_nic_wakeup(struct ath_hal *hal, u_int16_t flags) 271 { 272 u_int32_t turbo, mode, clock; 273 274 turbo = 0; 275 mode = 0; 276 clock = 0; 277 278 /* 279 * Get channel mode flags 280 */ 281 282 if (flags & IEEE80211_CHAN_2GHZ) { 283 mode |= AR5K_AR5211_PHY_MODE_FREQ_2GHZ; 284 clock |= AR5K_AR5211_PHY_PLL_44MHZ; 285 } else if (flags & IEEE80211_CHAN_5GHZ) { 286 mode |= AR5K_AR5211_PHY_MODE_FREQ_5GHZ; 287 clock |= AR5K_AR5211_PHY_PLL_40MHZ; 288 } else { 289 AR5K_PRINT("invalid radio frequency mode\n"); 290 return (AH_FALSE); 291 } 292 293 if ((flags & IEEE80211_CHAN_CCK) || 294 (flags & IEEE80211_CHAN_DYN)) { 295 /* Dynamic OFDM/CCK is not supported by the AR5211 */ 296 mode |= AR5K_AR5211_PHY_MODE_MOD_CCK; 297 } else if (flags & IEEE80211_CHAN_OFDM) { 298 mode |= AR5K_AR5211_PHY_MODE_MOD_OFDM; 299 } else { 300 AR5K_PRINT("invalid radio frequency mode\n"); 301 return (AH_FALSE); 302 } 303 304 if (flags & IEEE80211_CHAN_TURBO) { 305 turbo = AR5K_AR5211_PHY_TURBO_MODE | 306 AR5K_AR5211_PHY_TURBO_SHORT; 307 } 308 309 /* 310 * Reset and wakeup the device 311 */ 312 313 /* ...reset chipset and PCI device */ 314 if (ar5k_ar5211_nic_reset(hal, 315 AR5K_AR5211_RC_CHIP | AR5K_AR5211_RC_PCI) == AH_FALSE) { 316 AR5K_PRINT("failed to reset the AR5211 + PCI chipset\n"); 317 return (AH_FALSE); 318 } 319 320 /* ...wakeup */ 321 if (ar5k_ar5211_set_power(hal, 322 HAL_PM_AWAKE, AH_TRUE, 0) == AH_FALSE) { 323 AR5K_PRINT("failed to resume the AR5211 (again)\n"); 324 return (AH_FALSE); 325 } 326 327 /* ...final warm reset */ 328 if (ar5k_ar5211_nic_reset(hal, 0) == AH_FALSE) { 329 AR5K_PRINT("failed to warm reset the AR5211\n"); 330 return (AH_FALSE); 331 } 332 333 /* ...set the PHY operating mode */ 334 AR5K_REG_WRITE(AR5K_AR5211_PHY_PLL, clock); 335 AR5K_DELAY(300); 336 337 AR5K_REG_WRITE(AR5K_AR5211_PHY_MODE, mode); 338 AR5K_REG_WRITE(AR5K_AR5211_PHY_TURBO, turbo); 339 340 return (AH_TRUE); 341 } 342 343 u_int16_t 344 ar5k_ar5211_radio_revision(struct ath_hal *hal, HAL_CHIP chip) 345 { 346 int i; 347 u_int32_t srev; 348 u_int16_t ret; 349 350 /* 351 * Set the radio chip access register 352 */ 353 switch (chip) { 354 case HAL_CHIP_2GHZ: 355 AR5K_REG_WRITE(AR5K_AR5211_PHY(0), AR5K_AR5211_PHY_SHIFT_2GHZ); 356 break; 357 case HAL_CHIP_5GHZ: 358 AR5K_REG_WRITE(AR5K_AR5211_PHY(0), AR5K_AR5211_PHY_SHIFT_5GHZ); 359 break; 360 default: 361 return (0); 362 } 363 364 AR5K_DELAY(2000); 365 366 /* ...wait until PHY is ready and read the selected radio revision */ 367 AR5K_REG_WRITE(AR5K_AR5211_PHY(0x34), 0x00001c16); 368 369 for (i = 0; i < 8; i++) 370 AR5K_REG_WRITE(AR5K_AR5211_PHY(0x20), 0x00010000); 371 srev = (AR5K_REG_READ(AR5K_AR5211_PHY(0x100)) >> 24) & 0xff; 372 373 ret = ar5k_bitswap(((srev & 0xf0) >> 4) | ((srev & 0x0f) << 4), 8); 374 375 /* Reset to the 5GHz mode */ 376 AR5K_REG_WRITE(AR5K_AR5211_PHY(0), AR5K_AR5211_PHY_SHIFT_5GHZ); 377 378 return (ret); 379 } 380 381 const HAL_RATE_TABLE * 382 ar5k_ar5211_get_rate_table(struct ath_hal *hal, u_int mode) 383 { 384 switch (mode) { 385 case HAL_MODE_11A: 386 return (&hal->ah_rt_11a); 387 case HAL_MODE_TURBO: 388 return (&hal->ah_rt_turbo); 389 case HAL_MODE_11B: 390 return (&hal->ah_rt_11b); 391 case HAL_MODE_11G: 392 case HAL_MODE_PUREG: 393 return (&hal->ah_rt_11g); 394 default: 395 return (NULL); 396 } 397 398 return (NULL); 399 } 400 401 void 402 ar5k_ar5211_detach(struct ath_hal *hal) 403 { 404 /* 405 * Free HAL structure, assume interrupts are down 406 */ 407 free(hal, M_DEVBUF); 408 } 409 410 HAL_BOOL 411 ar5k_ar5211_phy_disable(struct ath_hal *hal) 412 { 413 AR5K_REG_WRITE(AR5K_AR5211_PHY_ACTIVE, AR5K_AR5211_PHY_DISABLE); 414 return (AH_TRUE); 415 } 416 417 HAL_BOOL 418 ar5k_ar5211_reset(struct ath_hal *hal, HAL_OPMODE op_mode, HAL_CHANNEL *channel, 419 HAL_BOOL change_channel, HAL_STATUS *status) 420 { 421 struct ar5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; 422 u_int8_t mac[IEEE80211_ADDR_LEN]; 423 u_int32_t data, s_seq, s_ant, s_led[3]; 424 u_int i, mode, freq, ee_mode, ant[2]; 425 426 /* 427 * Save some registers before a reset 428 */ 429 if (change_channel == AH_TRUE) { 430 s_seq = AR5K_REG_READ(AR5K_AR5211_DCU_SEQNUM(0)); 431 s_ant = AR5K_REG_READ(AR5K_AR5211_DEFAULT_ANTENNA); 432 } else { 433 s_seq = 0; 434 s_ant = 1; 435 } 436 437 s_led[0] = AR5K_REG_READ(AR5K_AR5211_PCICFG) & 438 AR5K_AR5211_PCICFG_LEDSTATE; 439 s_led[1] = AR5K_REG_READ(AR5K_AR5211_GPIOCR); 440 s_led[2] = AR5K_REG_READ(AR5K_AR5211_GPIODO); 441 442 if (ar5k_ar5211_nic_wakeup(hal, channel->c_channel_flags) == AH_FALSE) 443 return (AH_FALSE); 444 445 /* 446 * Initialize operating mode 447 */ 448 hal->ah_op_mode = op_mode; 449 450 switch (channel->c_channel_flags & CHANNEL_MODES) { 451 case CHANNEL_A: 452 mode = AR5K_INI_VAL_11A; 453 freq = AR5K_INI_RFGAIN_5GHZ; 454 ee_mode = AR5K_EEPROM_MODE_11A; 455 break; 456 case CHANNEL_T: 457 mode = AR5K_INI_VAL_11A_TURBO; 458 freq = AR5K_INI_RFGAIN_5GHZ; 459 ee_mode = AR5K_EEPROM_MODE_11A; 460 break; 461 case CHANNEL_B: 462 mode = AR5K_INI_VAL_11B; 463 freq = AR5K_INI_RFGAIN_2GHZ; 464 ee_mode = AR5K_EEPROM_MODE_11B; 465 break; 466 case CHANNEL_G: 467 case CHANNEL_PUREG: 468 mode = AR5K_INI_VAL_11G; 469 freq = AR5K_INI_RFGAIN_2GHZ; 470 ee_mode = AR5K_EEPROM_MODE_11G; 471 break; 472 default: 473 AR5K_PRINTF("invalid channel: %d\n", channel->c_channel); 474 return (AH_FALSE); 475 } 476 477 /* PHY access enable */ 478 AR5K_REG_WRITE(AR5K_AR5211_PHY(0), AR5K_AR5211_PHY_SHIFT_5GHZ); 479 480 /* 481 * Write initial RF registers 482 */ 483 ar5k_ar5211_rfregs(hal, channel, freq, ee_mode); 484 485 /* 486 * Write initial mode settings 487 */ 488 for (i = 0; i < AR5K_ELEMENTS(ar5211_mode); i++) { 489 AR5K_REG_WAIT(i); 490 AR5K_REG_WRITE((u_int32_t)ar5211_mode[i].mode_register, 491 ar5211_mode[i].mode_value[mode]); 492 } 493 494 /* 495 * Write initial register settings 496 */ 497 for (i = 0; i < AR5K_ELEMENTS(ar5211_ini); i++) { 498 if (change_channel == AH_TRUE && 499 ar5211_ini[i].ini_register >= AR5K_AR5211_PCU_MIN && 500 ar5211_ini[i].ini_register <= AR5K_AR5211_PCU_MAX) 501 continue; 502 503 AR5K_REG_WAIT(i); 504 AR5K_REG_WRITE((u_int32_t)ar5211_ini[i].ini_register, 505 ar5211_ini[i].ini_value); 506 } 507 508 /* 509 * Write initial RF gain settings 510 */ 511 if (ar5k_rfgain(hal, freq) == AH_FALSE) 512 return (AH_FALSE); 513 514 AR5K_DELAY(1000); 515 516 /* 517 * Configure additional registers 518 */ 519 520 if (hal->ah_radio == AR5K_AR5111) { 521 if (channel->c_channel_flags & IEEE80211_CHAN_B) 522 AR5K_REG_ENABLE_BITS(AR5K_AR5211_TXCFG, 523 AR5K_AR5211_TXCFG_B_MODE); 524 else 525 AR5K_REG_DISABLE_BITS(AR5K_AR5211_TXCFG, 526 AR5K_AR5211_TXCFG_B_MODE); 527 } 528 529 /* Set antenna mode */ 530 AR5K_REG_MASKED_BITS(AR5K_AR5211_PHY(0x44), 531 hal->ah_antenna[ee_mode][0], 0xfffffc06); 532 533 if (freq == AR5K_INI_RFGAIN_2GHZ) 534 ant[0] = ant[1] = HAL_ANT_FIXED_B; 535 else 536 ant[0] = ant[1] = HAL_ANT_FIXED_A; 537 538 AR5K_REG_WRITE(AR5K_AR5211_PHY_ANT_SWITCH_TABLE_0, 539 hal->ah_antenna[ee_mode][ant[0]]); 540 AR5K_REG_WRITE(AR5K_AR5211_PHY_ANT_SWITCH_TABLE_1, 541 hal->ah_antenna[ee_mode][ant[1]]); 542 543 /* Commit values from EEPROM */ 544 AR5K_REG_WRITE_BITS(AR5K_AR5211_PHY_FC, 545 AR5K_AR5211_PHY_FC_TX_CLIP, ee->ee_tx_clip); 546 547 AR5K_REG_WRITE(AR5K_AR5211_PHY(0x5a), 548 AR5K_AR5211_PHY_NF_SVAL(ee->ee_noise_floor_thr[ee_mode])); 549 550 AR5K_REG_MASKED_BITS(AR5K_AR5211_PHY(0x11), 551 (ee->ee_switch_settling[ee_mode] << 7) & 0x3f80, 0xffffc07f); 552 AR5K_REG_MASKED_BITS(AR5K_AR5211_PHY(0x12), 553 (ee->ee_ant_tx_rx[ee_mode] << 12) & 0x3f000, 0xfffc0fff); 554 AR5K_REG_MASKED_BITS(AR5K_AR5211_PHY(0x14), 555 (ee->ee_adc_desired_size[ee_mode] & 0x00ff) | 556 ((ee->ee_pga_desired_size[ee_mode] << 8) & 0xff00), 0xffff0000); 557 558 AR5K_REG_WRITE(AR5K_AR5211_PHY(0x0d), 559 (ee->ee_tx_end2xpa_disable[ee_mode] << 24) | 560 (ee->ee_tx_end2xpa_disable[ee_mode] << 16) | 561 (ee->ee_tx_frm2xpa_enable[ee_mode] << 8) | 562 (ee->ee_tx_frm2xpa_enable[ee_mode])); 563 564 AR5K_REG_MASKED_BITS(AR5K_AR5211_PHY(0x0a), 565 ee->ee_tx_end2xlna_enable[ee_mode] << 8, 0xffff00ff); 566 AR5K_REG_MASKED_BITS(AR5K_AR5211_PHY(0x19), 567 (ee->ee_thr_62[ee_mode] << 12) & 0x7f000, 0xfff80fff); 568 AR5K_REG_MASKED_BITS(AR5K_AR5211_PHY(0x49), 4, 0xffffff01); 569 570 AR5K_REG_ENABLE_BITS(AR5K_AR5211_PHY_IQ, 571 AR5K_AR5211_PHY_IQ_CORR_ENABLE | 572 (ee->ee_i_cal[ee_mode] << AR5K_AR5211_PHY_IQ_CORR_Q_I_COFF_S) | 573 ee->ee_q_cal[ee_mode]); 574 575 /* 576 * Restore saved values 577 */ 578 AR5K_REG_WRITE(AR5K_AR5211_DCU_SEQNUM(0), s_seq); 579 AR5K_REG_WRITE(AR5K_AR5211_DEFAULT_ANTENNA, s_ant); 580 AR5K_REG_ENABLE_BITS(AR5K_AR5211_PCICFG, s_led[0]); 581 AR5K_REG_WRITE(AR5K_AR5211_GPIOCR, s_led[1]); 582 AR5K_REG_WRITE(AR5K_AR5211_GPIODO, s_led[2]); 583 584 /* 585 * Misc 586 */ 587 bcopy(etherbroadcastaddr, mac, IEEE80211_ADDR_LEN); 588 ar5k_ar5211_set_associd(hal, mac, 0, 0); 589 ar5k_ar5211_set_opmode(hal); 590 AR5K_REG_WRITE(AR5K_AR5211_PISR, 0xffffffff); 591 AR5K_REG_WRITE(AR5K_AR5211_RSSI_THR, AR5K_TUNE_RSSI_THRES); 592 593 /* 594 * Set Rx/Tx DMA Configuration 595 */ 596 AR5K_REG_WRITE_BITS(AR5K_AR5211_TXCFG, AR5K_AR5211_TXCFG_SDMAMR, 597 AR5K_AR5211_DMASIZE_512B | AR5K_AR5211_TXCFG_DMASIZE); 598 AR5K_REG_WRITE_BITS(AR5K_AR5211_RXCFG, AR5K_AR5211_RXCFG_SDMAMW, 599 AR5K_AR5211_DMASIZE_512B); 600 601 /* 602 * Set channel and calibrate the PHY 603 */ 604 if (ar5k_channel(hal, channel) == AH_FALSE) 605 return (AH_FALSE); 606 607 /* 608 * Enable the PHY and wait until completion 609 */ 610 AR5K_REG_WRITE(AR5K_AR5211_PHY_ACTIVE, AR5K_AR5211_PHY_ENABLE); 611 612 data = AR5K_REG_READ(AR5K_AR5211_PHY_RX_DELAY) & 613 AR5K_AR5211_PHY_RX_DELAY_M; 614 data = (channel->c_channel_flags & IEEE80211_CHAN_CCK) ? 615 ((data << 2) / 22) : (data / 10); 616 617 AR5K_DELAY(100 + data); 618 619 /* 620 * Start calibration 621 */ 622 AR5K_REG_ENABLE_BITS(AR5K_AR5211_PHY_AGCCTL, 623 AR5K_AR5211_PHY_AGCCTL_NF | 624 AR5K_AR5211_PHY_AGCCTL_CAL); 625 626 if (channel->c_channel_flags & IEEE80211_CHAN_B) { 627 hal->ah_calibration = AH_FALSE; 628 } else { 629 hal->ah_calibration = AH_TRUE; 630 AR5K_REG_WRITE_BITS(AR5K_AR5211_PHY_IQ, 631 AR5K_AR5211_PHY_IQ_CAL_NUM_LOG_MAX, 15); 632 AR5K_REG_ENABLE_BITS(AR5K_AR5211_PHY_IQ, 633 AR5K_AR5211_PHY_IQ_RUN); 634 } 635 636 /* 637 * Reset queues and start beacon timers at the end of the reset routine 638 */ 639 for (i = 0; i < hal->ah_capabilities.cap_queues.q_tx_num; i++) { 640 AR5K_REG_WRITE_Q(AR5K_AR5211_DCU_QCUMASK(i), i); 641 if (ar5k_ar5211_reset_tx_queue(hal, i) == AH_FALSE) { 642 AR5K_PRINTF("failed to reset TX queue #%d\n", i); 643 return (AH_FALSE); 644 } 645 } 646 647 /* Pre-enable interrupts */ 648 ar5k_ar5211_set_intr(hal, HAL_INT_RX | HAL_INT_TX | HAL_INT_FATAL); 649 650 /* 651 * Set RF kill flags if supported by the device (read from the EEPROM) 652 */ 653 if (AR5K_EEPROM_HDR_RFKILL(hal->ah_capabilities.cap_eeprom.ee_header)) { 654 ar5k_ar5211_set_gpio_input(hal, 0); 655 if ((hal->ah_gpio[0] = ar5k_ar5211_get_gpio(hal, 0)) == 0) 656 ar5k_ar5211_set_gpio_intr(hal, 0, 1); 657 else 658 ar5k_ar5211_set_gpio_intr(hal, 0, 0); 659 } 660 661 /* 662 * Disable beacons and reset the register 663 */ 664 AR5K_REG_DISABLE_BITS(AR5K_AR5211_BEACON, 665 AR5K_AR5211_BEACON_ENABLE | AR5K_AR5211_BEACON_RESET_TSF); 666 667 return (AH_TRUE); 668 } 669 670 void 671 ar5k_ar5211_set_def_antenna(struct ath_hal *hal, u_int ant) 672 { 673 AR5K_REG_WRITE(AR5K_AR5211_DEFAULT_ANTENNA, ant); 674 } 675 676 u_int 677 ar5k_ar5211_get_def_antenna(struct ath_hal *hal) 678 { 679 return AR5K_REG_READ(AR5K_AR5211_DEFAULT_ANTENNA); 680 } 681 682 void 683 ar5k_ar5211_set_opmode(struct ath_hal *hal) 684 { 685 u_int32_t pcu_reg, low_id, high_id; 686 687 pcu_reg = 0; 688 689 switch (hal->ah_op_mode) { 690 #ifndef IEEE80211_STA_ONLY 691 case IEEE80211_M_IBSS: 692 pcu_reg |= AR5K_AR5211_STA_ID1_ADHOC | 693 AR5K_AR5211_STA_ID1_DESC_ANTENNA; 694 break; 695 696 case IEEE80211_M_HOSTAP: 697 pcu_reg |= AR5K_AR5211_STA_ID1_AP | 698 AR5K_AR5211_STA_ID1_RTS_DEFAULT_ANTENNA; 699 break; 700 #endif 701 702 case IEEE80211_M_STA: 703 case IEEE80211_M_MONITOR: 704 pcu_reg |= AR5K_AR5211_STA_ID1_DEFAULT_ANTENNA; 705 break; 706 707 default: 708 return; 709 } 710 711 /* 712 * Set PCU registers 713 */ 714 low_id = AR5K_LOW_ID(hal->ah_sta_id); 715 high_id = AR5K_HIGH_ID(hal->ah_sta_id); 716 AR5K_REG_WRITE(AR5K_AR5211_STA_ID0, low_id); 717 AR5K_REG_WRITE(AR5K_AR5211_STA_ID1, pcu_reg | high_id); 718 719 return; 720 } 721 722 HAL_BOOL 723 ar5k_ar5211_calibrate(struct ath_hal *hal, HAL_CHANNEL *channel) 724 { 725 u_int32_t i_pwr, q_pwr; 726 int32_t iq_corr, i_coff, i_coffd, q_coff, q_coffd; 727 728 if (hal->ah_calibration == AH_FALSE || 729 AR5K_REG_READ(AR5K_AR5211_PHY_IQ) & AR5K_AR5211_PHY_IQ_RUN) 730 goto done; 731 732 hal->ah_calibration = AH_FALSE; 733 734 iq_corr = AR5K_REG_READ(AR5K_AR5211_PHY_IQRES_CAL_CORR); 735 i_pwr = AR5K_REG_READ(AR5K_AR5211_PHY_IQRES_CAL_PWR_I); 736 q_pwr = AR5K_REG_READ(AR5K_AR5211_PHY_IQRES_CAL_PWR_Q); 737 i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7; 738 q_coffd = q_pwr >> 6; 739 740 if (i_coffd == 0 || q_coffd == 0) 741 goto done; 742 743 i_coff = ((-iq_corr) / i_coffd) & 0x3f; 744 q_coff = (((int32_t)i_pwr / q_coffd) - 64) & 0x1f; 745 746 /* Commit new IQ value */ 747 AR5K_REG_ENABLE_BITS(AR5K_AR5211_PHY_IQ, 748 AR5K_AR5211_PHY_IQ_CORR_ENABLE | 749 ((u_int32_t)q_coff) | 750 ((u_int32_t)i_coff << AR5K_AR5211_PHY_IQ_CORR_Q_I_COFF_S)); 751 752 done: 753 /* Start noise floor calibration */ 754 AR5K_REG_ENABLE_BITS(AR5K_AR5211_PHY_AGCCTL, 755 AR5K_AR5211_PHY_AGCCTL_NF); 756 757 return (AH_TRUE); 758 } 759 760 /* 761 * Transmit functions 762 */ 763 764 HAL_BOOL 765 ar5k_ar5211_update_tx_triglevel(struct ath_hal *hal, HAL_BOOL increase) 766 { 767 u_int32_t trigger_level, imr; 768 HAL_BOOL status = AH_FALSE; 769 770 /* 771 * Disable interrupts by setting the mask 772 */ 773 imr = ar5k_ar5211_set_intr(hal, hal->ah_imr & ~HAL_INT_GLOBAL); 774 775 trigger_level = AR5K_REG_MS(AR5K_REG_READ(AR5K_AR5211_TXCFG), 776 AR5K_AR5211_TXCFG_TXFULL); 777 778 if (increase == AH_FALSE) { 779 if (--trigger_level < AR5K_TUNE_MIN_TX_FIFO_THRES) 780 goto done; 781 } else 782 trigger_level += 783 ((AR5K_TUNE_MAX_TX_FIFO_THRES - trigger_level) / 2); 784 785 /* 786 * Update trigger level on success 787 */ 788 AR5K_REG_WRITE_BITS(AR5K_AR5211_TXCFG, 789 AR5K_AR5211_TXCFG_TXFULL, trigger_level); 790 status = AH_TRUE; 791 792 done: 793 /* 794 * Restore interrupt mask 795 */ 796 ar5k_ar5211_set_intr(hal, imr); 797 798 return (status); 799 } 800 801 int 802 ar5k_ar5211_setup_tx_queue(struct ath_hal *hal, HAL_TX_QUEUE queue_type, 803 const HAL_TXQ_INFO *queue_info) 804 { 805 u_int queue; 806 807 /* 808 * Get queue by type 809 */ 810 if (queue_type == HAL_TX_QUEUE_DATA) { 811 for (queue = HAL_TX_QUEUE_ID_DATA_MIN; 812 hal->ah_txq[queue].tqi_type != HAL_TX_QUEUE_INACTIVE; 813 queue++) 814 if (queue > HAL_TX_QUEUE_ID_DATA_MAX) 815 return (-1); 816 } else if (queue_type == HAL_TX_QUEUE_PSPOLL) { 817 queue = HAL_TX_QUEUE_ID_PSPOLL; 818 } else if (queue_type == HAL_TX_QUEUE_BEACON) { 819 queue = HAL_TX_QUEUE_ID_BEACON; 820 } else if (queue_type == HAL_TX_QUEUE_CAB) { 821 queue = HAL_TX_QUEUE_ID_CAB; 822 } else 823 return (-1); 824 825 /* 826 * Setup internal queue structure 827 */ 828 bzero(&hal->ah_txq[queue], sizeof(HAL_TXQ_INFO)); 829 hal->ah_txq[queue].tqi_type = queue_type; 830 831 if (queue_info != NULL) { 832 if (ar5k_ar5211_setup_tx_queueprops(hal, queue, queue_info) 833 != AH_TRUE) 834 return (-1); 835 } 836 837 AR5K_Q_ENABLE_BITS(hal->ah_txq_interrupts, queue); 838 839 return (queue); 840 } 841 842 HAL_BOOL 843 ar5k_ar5211_setup_tx_queueprops(struct ath_hal *hal, int queue, 844 const HAL_TXQ_INFO *queue_info) 845 { 846 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); 847 848 if (hal->ah_txq[queue].tqi_type == HAL_TX_QUEUE_INACTIVE) 849 return (AH_FALSE); 850 851 bcopy(queue_info, &hal->ah_txq[queue], sizeof(HAL_TXQ_INFO)); 852 853 if (queue_info->tqi_type == HAL_TX_QUEUE_DATA && 854 (queue_info->tqi_subtype >= HAL_WME_AC_VI) && 855 (queue_info->tqi_subtype <= HAL_WME_UPSD)) 856 hal->ah_txq[queue].tqi_flags |= 857 AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS; 858 859 return (AH_TRUE); 860 } 861 862 HAL_BOOL 863 ar5k_ar5211_get_tx_queueprops(struct ath_hal *hal, int queue, 864 HAL_TXQ_INFO *queue_info) 865 { 866 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); 867 bcopy(&hal->ah_txq[queue], queue_info, sizeof(HAL_TXQ_INFO)); 868 return (AH_TRUE); 869 } 870 871 HAL_BOOL 872 ar5k_ar5211_release_tx_queue(struct ath_hal *hal, u_int queue) 873 { 874 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); 875 876 /* This queue will be skipped in further operations */ 877 hal->ah_txq[queue].tqi_type = HAL_TX_QUEUE_INACTIVE; 878 AR5K_Q_DISABLE_BITS(hal->ah_txq_interrupts, queue); 879 880 return (AH_FALSE); 881 } 882 883 HAL_BOOL 884 ar5k_ar5211_reset_tx_queue(struct ath_hal *hal, u_int queue) 885 { 886 u_int32_t cw_min, cw_max, retry_lg, retry_sh; 887 struct ieee80211_channel *channel = (struct ieee80211_channel*) 888 &hal->ah_current_channel; 889 HAL_TXQ_INFO *tq; 890 891 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); 892 893 tq = &hal->ah_txq[queue]; 894 895 if (tq->tqi_type == HAL_TX_QUEUE_INACTIVE) 896 return (AH_TRUE); 897 898 /* 899 * Set registers by channel mode 900 */ 901 if (IEEE80211_IS_CHAN_B(channel)) { 902 hal->ah_cw_min = AR5K_TUNE_CWMIN_11B; 903 cw_max = hal->ah_cw_max = AR5K_TUNE_CWMAX_11B; 904 hal->ah_aifs = AR5K_TUNE_AIFS_11B; 905 } else { 906 hal->ah_cw_min = AR5K_TUNE_CWMIN; 907 cw_max = hal->ah_cw_max = AR5K_TUNE_CWMAX; 908 hal->ah_aifs = AR5K_TUNE_AIFS; 909 } 910 911 /* 912 * Set retry limits 913 */ 914 if (hal->ah_software_retry == AH_TRUE) { 915 /* XXX Need to test this */ 916 retry_lg = hal->ah_limit_tx_retries; 917 retry_sh = retry_lg = 918 retry_lg > AR5K_AR5211_DCU_RETRY_LMT_SH_RETRY ? 919 AR5K_AR5211_DCU_RETRY_LMT_SH_RETRY : retry_lg; 920 } else { 921 retry_lg = AR5K_INIT_LG_RETRY; 922 retry_sh = AR5K_INIT_SH_RETRY; 923 } 924 925 AR5K_REG_WRITE(AR5K_AR5211_DCU_RETRY_LMT(queue), 926 AR5K_REG_SM(AR5K_INIT_SLG_RETRY, 927 AR5K_AR5211_DCU_RETRY_LMT_SLG_RETRY) | 928 AR5K_REG_SM(AR5K_INIT_SSH_RETRY, 929 AR5K_AR5211_DCU_RETRY_LMT_SSH_RETRY) | 930 AR5K_REG_SM(retry_lg, AR5K_AR5211_DCU_RETRY_LMT_LG_RETRY) | 931 AR5K_REG_SM(retry_sh, AR5K_AR5211_DCU_RETRY_LMT_SH_RETRY)); 932 933 /* 934 * Set initial content window (cw_min/cw_max) 935 */ 936 cw_min = 1; 937 while (cw_min < hal->ah_cw_min) 938 cw_min = (cw_min << 1) | 1; 939 940 cw_min = tq->tqi_cw_min < 0 ? 941 (cw_min >> (-tq->tqi_cw_min)) : 942 ((cw_min << tq->tqi_cw_min) + (1 << tq->tqi_cw_min) - 1); 943 cw_max = tq->tqi_cw_max < 0 ? 944 (cw_max >> (-tq->tqi_cw_max)) : 945 ((cw_max << tq->tqi_cw_max) + (1 << tq->tqi_cw_max) - 1); 946 947 AR5K_REG_WRITE(AR5K_AR5211_DCU_LCL_IFS(queue), 948 AR5K_REG_SM(cw_min, AR5K_AR5211_DCU_LCL_IFS_CW_MIN) | 949 AR5K_REG_SM(cw_max, AR5K_AR5211_DCU_LCL_IFS_CW_MAX) | 950 AR5K_REG_SM(hal->ah_aifs + tq->tqi_aifs, 951 AR5K_AR5211_DCU_LCL_IFS_AIFS)); 952 953 /* 954 * Set misc registers 955 */ 956 AR5K_REG_WRITE(AR5K_AR5211_QCU_MISC(queue), 957 AR5K_AR5211_QCU_MISC_DCU_EARLY); 958 959 if (tq->tqi_cbr_period) { 960 AR5K_REG_WRITE(AR5K_AR5211_QCU_CBRCFG(queue), 961 AR5K_REG_SM(tq->tqi_cbr_period, 962 AR5K_AR5211_QCU_CBRCFG_INTVAL) | 963 AR5K_REG_SM(tq->tqi_cbr_overflow_limit, 964 AR5K_AR5211_QCU_CBRCFG_ORN_THRES)); 965 AR5K_REG_ENABLE_BITS(AR5K_AR5211_QCU_MISC(queue), 966 AR5K_AR5211_QCU_MISC_FRSHED_CBR); 967 if (tq->tqi_cbr_overflow_limit) 968 AR5K_REG_ENABLE_BITS(AR5K_AR5211_QCU_MISC(queue), 969 AR5K_AR5211_QCU_MISC_CBR_THRES_ENABLE); 970 } 971 972 if (tq->tqi_ready_time) { 973 AR5K_REG_WRITE(AR5K_AR5211_QCU_RDYTIMECFG(queue), 974 AR5K_REG_SM(tq->tqi_ready_time, 975 AR5K_AR5211_QCU_RDYTIMECFG_INTVAL) | 976 AR5K_AR5211_QCU_RDYTIMECFG_ENABLE); 977 } 978 979 if (tq->tqi_burst_time) { 980 AR5K_REG_WRITE(AR5K_AR5211_DCU_CHAN_TIME(queue), 981 AR5K_REG_SM(tq->tqi_burst_time, 982 AR5K_AR5211_DCU_CHAN_TIME_DUR) | 983 AR5K_AR5211_DCU_CHAN_TIME_ENABLE); 984 985 if (tq->tqi_flags & AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE) { 986 AR5K_REG_ENABLE_BITS(AR5K_AR5211_QCU_MISC(queue), 987 AR5K_AR5211_QCU_MISC_TXE); 988 } 989 } 990 991 if (tq->tqi_flags & AR5K_TXQ_FLAG_BACKOFF_DISABLE) { 992 AR5K_REG_WRITE(AR5K_AR5211_DCU_MISC(queue), 993 AR5K_AR5211_DCU_MISC_POST_FR_BKOFF_DIS); 994 } 995 996 if (tq->tqi_flags & AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE) { 997 AR5K_REG_WRITE(AR5K_AR5211_DCU_MISC(queue), 998 AR5K_AR5211_DCU_MISC_BACKOFF_FRAG); 999 } 1000 1001 /* 1002 * Set registers by queue type 1003 */ 1004 switch (tq->tqi_type) { 1005 case HAL_TX_QUEUE_BEACON: 1006 AR5K_REG_ENABLE_BITS(AR5K_AR5211_QCU_MISC(queue), 1007 AR5K_AR5211_QCU_MISC_FRSHED_DBA_GT | 1008 AR5K_AR5211_QCU_MISC_CBREXP_BCN | 1009 AR5K_AR5211_QCU_MISC_BCN_ENABLE); 1010 1011 AR5K_REG_ENABLE_BITS(AR5K_AR5211_DCU_MISC(queue), 1012 (AR5K_AR5211_DCU_MISC_ARBLOCK_CTL_GLOBAL << 1013 AR5K_AR5211_DCU_MISC_ARBLOCK_CTL_GLOBAL) | 1014 AR5K_AR5211_DCU_MISC_POST_FR_BKOFF_DIS | 1015 AR5K_AR5211_DCU_MISC_BCN_ENABLE); 1016 1017 AR5K_REG_WRITE(AR5K_AR5211_QCU_RDYTIMECFG(queue), 1018 ((AR5K_TUNE_BEACON_INTERVAL - 1019 (AR5K_TUNE_SW_BEACON_RESP - AR5K_TUNE_DMA_BEACON_RESP) - 1020 AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF) * 1024) | 1021 AR5K_AR5211_QCU_RDYTIMECFG_ENABLE); 1022 break; 1023 1024 case HAL_TX_QUEUE_CAB: 1025 AR5K_REG_ENABLE_BITS(AR5K_AR5211_QCU_MISC(queue), 1026 AR5K_AR5211_QCU_MISC_FRSHED_DBA_GT | 1027 AR5K_AR5211_QCU_MISC_CBREXP | 1028 AR5K_AR5211_QCU_MISC_CBREXP_BCN); 1029 1030 AR5K_REG_ENABLE_BITS(AR5K_AR5211_DCU_MISC(queue), 1031 (AR5K_AR5211_DCU_MISC_ARBLOCK_CTL_GLOBAL << 1032 AR5K_AR5211_DCU_MISC_ARBLOCK_CTL_GLOBAL)); 1033 break; 1034 1035 case HAL_TX_QUEUE_PSPOLL: 1036 AR5K_REG_ENABLE_BITS(AR5K_AR5211_QCU_MISC(queue), 1037 AR5K_AR5211_QCU_MISC_CBREXP); 1038 break; 1039 1040 case HAL_TX_QUEUE_DATA: 1041 default: 1042 break; 1043 } 1044 1045 /* 1046 * Enable tx queue in the secondary interrupt mask registers 1047 */ 1048 AR5K_REG_WRITE(AR5K_AR5211_SIMR0, 1049 AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_AR5211_SIMR0_QCU_TXOK) | 1050 AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_AR5211_SIMR0_QCU_TXDESC)); 1051 AR5K_REG_WRITE(AR5K_AR5211_SIMR1, 1052 AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_AR5211_SIMR1_QCU_TXERR)); 1053 AR5K_REG_WRITE(AR5K_AR5211_SIMR2, 1054 AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_AR5211_SIMR2_QCU_TXURN)); 1055 1056 return (AH_TRUE); 1057 } 1058 1059 u_int32_t 1060 ar5k_ar5211_get_tx_buf(struct ath_hal *hal, u_int queue) 1061 { 1062 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); 1063 1064 /* 1065 * Get the transmit queue descriptor pointer from the selected queue 1066 */ 1067 return (AR5K_REG_READ(AR5K_AR5211_QCU_TXDP(queue))); 1068 } 1069 1070 HAL_BOOL 1071 ar5k_ar5211_put_tx_buf(struct ath_hal *hal, u_int queue, u_int32_t phys_addr) 1072 { 1073 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); 1074 1075 /* 1076 * Set the transmit queue descriptor pointer for the selected queue 1077 * (this won't work if the queue is still active) 1078 */ 1079 if (AR5K_REG_READ_Q(AR5K_AR5211_QCU_TXE, queue)) 1080 return (AH_FALSE); 1081 1082 AR5K_REG_WRITE(AR5K_AR5211_QCU_TXDP(queue), phys_addr); 1083 1084 return (AH_TRUE); 1085 } 1086 1087 u_int32_t 1088 ar5k_ar5211_num_tx_pending(struct ath_hal *hal, u_int queue) 1089 { 1090 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); 1091 return (AR5K_AR5211_QCU_STS(queue) & AR5K_AR5211_QCU_STS_FRMPENDCNT); 1092 } 1093 1094 HAL_BOOL 1095 ar5k_ar5211_tx_start(struct ath_hal *hal, u_int queue) 1096 { 1097 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); 1098 1099 /* Return if queue is disabled */ 1100 if (AR5K_REG_READ_Q(AR5K_AR5211_QCU_TXD, queue)) 1101 return (AH_FALSE); 1102 1103 /* Start queue */ 1104 AR5K_REG_WRITE_Q(AR5K_AR5211_QCU_TXE, queue); 1105 1106 return (AH_TRUE); 1107 } 1108 1109 HAL_BOOL 1110 ar5k_ar5211_stop_tx_dma(struct ath_hal *hal, u_int queue) 1111 { 1112 int i = 100, pending; 1113 1114 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); 1115 1116 /* 1117 * Schedule TX disable and wait until queue is empty 1118 */ 1119 AR5K_REG_WRITE_Q(AR5K_AR5211_QCU_TXD, queue); 1120 1121 do { 1122 pending = AR5K_REG_READ(AR5K_AR5211_QCU_STS(queue)) & 1123 AR5K_AR5211_QCU_STS_FRMPENDCNT; 1124 delay(100); 1125 } while (--i && pending); 1126 1127 /* Clear register */ 1128 AR5K_REG_WRITE(AR5K_AR5211_QCU_TXD, 0); 1129 1130 return (AH_TRUE); 1131 } 1132 1133 HAL_BOOL 1134 ar5k_ar5211_setup_tx_desc(struct ath_hal *hal, struct ath_desc *desc, 1135 u_int packet_length, u_int header_length, HAL_PKT_TYPE type, u_int tx_power, 1136 u_int tx_rate0, u_int tx_tries0, u_int key_index, u_int antenna_mode, 1137 u_int flags, u_int rtscts_rate, u_int rtscts_duration) 1138 { 1139 struct ar5k_ar5211_tx_desc *tx_desc; 1140 1141 tx_desc = (struct ar5k_ar5211_tx_desc*)&desc->ds_ctl0; 1142 1143 /* 1144 * Validate input 1145 */ 1146 if (tx_tries0 == 0) 1147 return (AH_FALSE); 1148 1149 if ((tx_desc->tx_control_0 = (packet_length & 1150 AR5K_AR5211_DESC_TX_CTL0_FRAME_LEN)) != packet_length) 1151 return (AH_FALSE); 1152 1153 tx_desc->tx_control_0 |= 1154 AR5K_REG_SM(tx_rate0, AR5K_AR5211_DESC_TX_CTL0_XMIT_RATE) | 1155 AR5K_REG_SM(antenna_mode, AR5K_AR5211_DESC_TX_CTL0_ANT_MODE_XMIT); 1156 tx_desc->tx_control_1 = 1157 AR5K_REG_SM(type, AR5K_AR5211_DESC_TX_CTL1_FRAME_TYPE); 1158 1159 #define _TX_FLAGS(_c, _flag) \ 1160 if (flags & HAL_TXDESC_##_flag) \ 1161 tx_desc->tx_control_##_c |= \ 1162 AR5K_AR5211_DESC_TX_CTL##_c##_##_flag 1163 1164 _TX_FLAGS(0, CLRDMASK); 1165 _TX_FLAGS(0, VEOL); 1166 _TX_FLAGS(0, INTREQ); 1167 _TX_FLAGS(0, RTSENA); 1168 _TX_FLAGS(1, NOACK); 1169 1170 #undef _TX_FLAGS 1171 1172 /* 1173 * WEP crap 1174 */ 1175 if (key_index != HAL_TXKEYIX_INVALID) { 1176 tx_desc->tx_control_0 |= 1177 AR5K_AR5211_DESC_TX_CTL0_ENCRYPT_KEY_VALID; 1178 tx_desc->tx_control_1 |= 1179 AR5K_REG_SM(key_index, 1180 AR5K_AR5211_DESC_TX_CTL1_ENCRYPT_KEY_INDEX); 1181 } 1182 1183 return (AH_TRUE); 1184 } 1185 1186 HAL_BOOL 1187 ar5k_ar5211_fill_tx_desc(struct ath_hal *hal, struct ath_desc *desc, 1188 u_int segment_length, HAL_BOOL first_segment, HAL_BOOL last_segment) 1189 { 1190 struct ar5k_ar5211_tx_desc *tx_desc; 1191 1192 tx_desc = (struct ar5k_ar5211_tx_desc*)&desc->ds_ctl0; 1193 1194 /* Clear status descriptor */ 1195 bzero(desc->ds_hw, sizeof(desc->ds_hw)); 1196 1197 /* Validate segment length and initialize the descriptor */ 1198 if (segment_length & ~AR5K_AR5211_DESC_TX_CTL1_BUF_LEN) 1199 return (AH_FALSE); 1200 tx_desc->tx_control_1 = 1201 #if 0 1202 (tx_desc->tx_control_1 & ~AR5K_AR5211_DESC_TX_CTL1_BUF_LEN) | 1203 #endif 1204 segment_length; 1205 1206 if (first_segment != AH_TRUE) 1207 tx_desc->tx_control_0 &= ~AR5K_AR5211_DESC_TX_CTL0_FRAME_LEN; 1208 1209 if (last_segment != AH_TRUE) 1210 tx_desc->tx_control_1 |= AR5K_AR5211_DESC_TX_CTL1_MORE; 1211 1212 return (AH_TRUE); 1213 } 1214 1215 HAL_BOOL 1216 ar5k_ar5211_setup_xtx_desc(struct ath_hal *hal, struct ath_desc *desc, 1217 u_int tx_rate1, u_int tx_tries1, u_int tx_rate2, u_int tx_tries2, 1218 u_int tx_rate3, u_int tx_tries3) 1219 { 1220 return (AH_FALSE); 1221 } 1222 1223 HAL_STATUS 1224 ar5k_ar5211_proc_tx_desc(struct ath_hal *hal, struct ath_desc *desc) 1225 { 1226 struct ar5k_ar5211_tx_status *tx_status; 1227 struct ar5k_ar5211_tx_desc *tx_desc; 1228 1229 tx_desc = (struct ar5k_ar5211_tx_desc*)&desc->ds_ctl0; 1230 tx_status = (struct ar5k_ar5211_tx_status*)&desc->ds_hw[0]; 1231 1232 /* No frame has been send or error */ 1233 if ((tx_status->tx_status_1 & AR5K_AR5211_DESC_TX_STATUS1_DONE) == 0) 1234 return (HAL_EINPROGRESS); 1235 1236 /* 1237 * Get descriptor status 1238 */ 1239 desc->ds_us.tx.ts_tstamp = 1240 AR5K_REG_MS(tx_status->tx_status_0, 1241 AR5K_AR5211_DESC_TX_STATUS0_SEND_TIMESTAMP); 1242 desc->ds_us.tx.ts_shortretry = 1243 AR5K_REG_MS(tx_status->tx_status_0, 1244 AR5K_AR5211_DESC_TX_STATUS0_RTS_FAIL_COUNT); 1245 desc->ds_us.tx.ts_longretry = 1246 AR5K_REG_MS(tx_status->tx_status_0, 1247 AR5K_AR5211_DESC_TX_STATUS0_DATA_FAIL_COUNT); 1248 desc->ds_us.tx.ts_seqnum = 1249 AR5K_REG_MS(tx_status->tx_status_1, 1250 AR5K_AR5211_DESC_TX_STATUS1_SEQ_NUM); 1251 desc->ds_us.tx.ts_rssi = 1252 AR5K_REG_MS(tx_status->tx_status_1, 1253 AR5K_AR5211_DESC_TX_STATUS1_ACK_SIG_STRENGTH); 1254 desc->ds_us.tx.ts_antenna = 1; 1255 desc->ds_us.tx.ts_status = 0; 1256 desc->ds_us.tx.ts_rate = 1257 AR5K_REG_MS(tx_desc->tx_control_0, 1258 AR5K_AR5211_DESC_TX_CTL0_XMIT_RATE); 1259 1260 if ((tx_status->tx_status_0 & 1261 AR5K_AR5211_DESC_TX_STATUS0_FRAME_XMIT_OK) == 0) { 1262 if (tx_status->tx_status_0 & 1263 AR5K_AR5211_DESC_TX_STATUS0_EXCESSIVE_RETRIES) 1264 desc->ds_us.tx.ts_status |= HAL_TXERR_XRETRY; 1265 1266 if (tx_status->tx_status_0 & 1267 AR5K_AR5211_DESC_TX_STATUS0_FIFO_UNDERRUN) 1268 desc->ds_us.tx.ts_status |= HAL_TXERR_FIFO; 1269 1270 if (tx_status->tx_status_0 & 1271 AR5K_AR5211_DESC_TX_STATUS0_FILTERED) 1272 desc->ds_us.tx.ts_status |= HAL_TXERR_FILT; 1273 } 1274 1275 return (HAL_OK); 1276 } 1277 1278 HAL_BOOL 1279 ar5k_ar5211_has_veol(struct ath_hal *hal) 1280 { 1281 return (AH_TRUE); 1282 } 1283 1284 /* 1285 * Receive functions 1286 */ 1287 1288 u_int32_t 1289 ar5k_ar5211_get_rx_buf(struct ath_hal *hal) 1290 { 1291 return (AR5K_REG_READ(AR5K_AR5211_RXDP)); 1292 } 1293 1294 void 1295 ar5k_ar5211_put_rx_buf(struct ath_hal *hal, u_int32_t phys_addr) 1296 { 1297 AR5K_REG_WRITE(AR5K_AR5211_RXDP, phys_addr); 1298 } 1299 1300 void 1301 ar5k_ar5211_start_rx(struct ath_hal *hal) 1302 { 1303 AR5K_REG_WRITE(AR5K_AR5211_CR, AR5K_AR5211_CR_RXE); 1304 } 1305 1306 HAL_BOOL 1307 ar5k_ar5211_stop_rx_dma(struct ath_hal *hal) 1308 { 1309 int i; 1310 1311 AR5K_REG_WRITE(AR5K_AR5211_CR, AR5K_AR5211_CR_RXD); 1312 1313 /* 1314 * It may take some time to disable the DMA receive unit 1315 */ 1316 for (i = 2000; 1317 i > 0 && (AR5K_REG_READ(AR5K_AR5211_CR) & AR5K_AR5211_CR_RXE) != 0; 1318 i--) 1319 AR5K_DELAY(10); 1320 1321 return (i > 0 ? AH_TRUE : AH_FALSE); 1322 } 1323 1324 void 1325 ar5k_ar5211_start_rx_pcu(struct ath_hal *hal) 1326 { 1327 AR5K_REG_DISABLE_BITS(AR5K_AR5211_DIAG_SW, AR5K_AR5211_DIAG_SW_DIS_RX); 1328 } 1329 1330 void 1331 ar5k_ar5211_stop_pcu_recv(struct ath_hal *hal) 1332 { 1333 AR5K_REG_ENABLE_BITS(AR5K_AR5211_DIAG_SW, AR5K_AR5211_DIAG_SW_DIS_RX); 1334 } 1335 1336 void 1337 ar5k_ar5211_set_mcast_filter(struct ath_hal *hal, u_int32_t filter0, 1338 u_int32_t filter1) 1339 { 1340 /* Set the multicat filter */ 1341 AR5K_REG_WRITE(AR5K_AR5211_MCAST_FIL0, filter0); 1342 AR5K_REG_WRITE(AR5K_AR5211_MCAST_FIL1, filter1); 1343 } 1344 1345 HAL_BOOL 1346 ar5k_ar5211_set_mcast_filterindex(struct ath_hal *hal, u_int32_t index) 1347 { 1348 if (index >= 64) { 1349 return (AH_FALSE); 1350 } else if (index >= 32) { 1351 AR5K_REG_ENABLE_BITS(AR5K_AR5211_MCAST_FIL1, 1352 (1 << (index - 32))); 1353 } else { 1354 AR5K_REG_ENABLE_BITS(AR5K_AR5211_MCAST_FIL0, 1355 (1 << index)); 1356 } 1357 1358 return (AH_TRUE); 1359 } 1360 1361 HAL_BOOL 1362 ar5k_ar5211_clear_mcast_filter_idx(struct ath_hal *hal, u_int32_t index) 1363 { 1364 1365 if (index >= 64) { 1366 return (AH_FALSE); 1367 } else if (index >= 32) { 1368 AR5K_REG_DISABLE_BITS(AR5K_AR5211_MCAST_FIL1, 1369 (1 << (index - 32))); 1370 } else { 1371 AR5K_REG_DISABLE_BITS(AR5K_AR5211_MCAST_FIL0, 1372 (1 << index)); 1373 } 1374 1375 return (AH_TRUE); 1376 } 1377 1378 u_int32_t 1379 ar5k_ar5211_get_rx_filter(struct ath_hal *hal) 1380 { 1381 return (AR5K_REG_READ(AR5K_AR5211_RX_FILTER)); 1382 } 1383 1384 void 1385 ar5k_ar5211_set_rx_filter(struct ath_hal *hal, u_int32_t filter) 1386 { 1387 AR5K_REG_WRITE(AR5K_AR5211_RX_FILTER, filter); 1388 } 1389 1390 HAL_BOOL 1391 ar5k_ar5211_setup_rx_desc(struct ath_hal *hal, struct ath_desc *desc, 1392 u_int32_t size, u_int flags) 1393 { 1394 struct ar5k_ar5211_rx_desc *rx_desc; 1395 1396 rx_desc = (struct ar5k_ar5211_rx_desc*)&desc->ds_ctl0; 1397 1398 if ((rx_desc->rx_control_1 = (size & 1399 AR5K_AR5211_DESC_RX_CTL1_BUF_LEN)) != size) 1400 return (AH_FALSE); 1401 1402 if (flags & HAL_RXDESC_INTREQ) 1403 rx_desc->rx_control_1 |= AR5K_AR5211_DESC_RX_CTL1_INTREQ; 1404 1405 return (AH_TRUE); 1406 } 1407 1408 HAL_STATUS 1409 ar5k_ar5211_proc_rx_desc(struct ath_hal *hal, struct ath_desc *desc, 1410 u_int32_t phys_addr, struct ath_desc *next) 1411 { 1412 struct ar5k_ar5211_rx_status *rx_status; 1413 1414 rx_status = (struct ar5k_ar5211_rx_status*)&desc->ds_hw[0]; 1415 1416 /* No frame received / not ready */ 1417 if ((rx_status->rx_status_1 & AR5K_AR5211_DESC_RX_STATUS1_DONE) == 0) 1418 return (HAL_EINPROGRESS); 1419 1420 /* 1421 * Frame receive status 1422 */ 1423 desc->ds_us.rx.rs_datalen = rx_status->rx_status_0 & 1424 AR5K_AR5211_DESC_RX_STATUS0_DATA_LEN; 1425 desc->ds_us.rx.rs_rssi = 1426 AR5K_REG_MS(rx_status->rx_status_0, 1427 AR5K_AR5211_DESC_RX_STATUS0_RECEIVE_SIGNAL); 1428 desc->ds_us.rx.rs_rate = 1429 AR5K_REG_MS(rx_status->rx_status_0, 1430 AR5K_AR5211_DESC_RX_STATUS0_RECEIVE_RATE); 1431 desc->ds_us.rx.rs_antenna = rx_status->rx_status_0 & 1432 AR5K_AR5211_DESC_RX_STATUS0_RECEIVE_ANTENNA; 1433 desc->ds_us.rx.rs_more = rx_status->rx_status_0 & 1434 AR5K_AR5211_DESC_RX_STATUS0_MORE; 1435 desc->ds_us.rx.rs_tstamp = 1436 AR5K_REG_MS(rx_status->rx_status_1, 1437 AR5K_AR5211_DESC_RX_STATUS1_RECEIVE_TIMESTAMP); 1438 desc->ds_us.rx.rs_status = 0; 1439 1440 /* 1441 * Key table status 1442 */ 1443 if (rx_status->rx_status_1 & 1444 AR5K_AR5211_DESC_RX_STATUS1_KEY_INDEX_VALID) { 1445 desc->ds_us.rx.rs_keyix = 1446 AR5K_REG_MS(rx_status->rx_status_1, 1447 AR5K_AR5211_DESC_RX_STATUS1_KEY_INDEX); 1448 } else { 1449 desc->ds_us.rx.rs_keyix = HAL_RXKEYIX_INVALID; 1450 } 1451 1452 /* 1453 * Receive/descriptor errors 1454 */ 1455 if ((rx_status->rx_status_1 & 1456 AR5K_AR5211_DESC_RX_STATUS1_FRAME_RECEIVE_OK) == 0) { 1457 if (rx_status->rx_status_1 & 1458 AR5K_AR5211_DESC_RX_STATUS1_CRC_ERROR) 1459 desc->ds_us.rx.rs_status |= HAL_RXERR_CRC; 1460 1461 if (rx_status->rx_status_1 & 1462 AR5K_AR5211_DESC_RX_STATUS1_PHY_ERROR) { 1463 desc->ds_us.rx.rs_status |= HAL_RXERR_PHY; 1464 desc->ds_us.rx.rs_phyerr = 1465 AR5K_REG_MS(rx_status->rx_status_1, 1466 AR5K_AR5211_DESC_RX_STATUS1_PHY_ERROR); 1467 } 1468 1469 if (rx_status->rx_status_1 & 1470 AR5K_AR5211_DESC_RX_STATUS1_DECRYPT_CRC_ERROR) 1471 desc->ds_us.rx.rs_status |= HAL_RXERR_DECRYPT; 1472 } 1473 1474 return (HAL_OK); 1475 } 1476 1477 void 1478 ar5k_ar5211_set_rx_signal(struct ath_hal *hal) 1479 { 1480 /* Signal state monitoring is not yet supported */ 1481 } 1482 1483 /* 1484 * Misc functions 1485 */ 1486 1487 void 1488 ar5k_ar5211_dump_state(struct ath_hal *hal) 1489 { 1490 #ifdef AR5K_DEBUG 1491 #define AR5K_PRINT_REGISTER(_x) \ 1492 printf("(%s: %08x) ", #_x, AR5K_REG_READ(AR5K_AR5211_##_x)); 1493 1494 printf("MAC registers:\n"); 1495 AR5K_PRINT_REGISTER(CR); 1496 AR5K_PRINT_REGISTER(CFG); 1497 AR5K_PRINT_REGISTER(IER); 1498 AR5K_PRINT_REGISTER(RTSD0); 1499 AR5K_PRINT_REGISTER(TXCFG); 1500 AR5K_PRINT_REGISTER(RXCFG); 1501 AR5K_PRINT_REGISTER(RXJLA); 1502 AR5K_PRINT_REGISTER(MIBC); 1503 AR5K_PRINT_REGISTER(TOPS); 1504 AR5K_PRINT_REGISTER(RXNOFRM); 1505 AR5K_PRINT_REGISTER(RPGTO); 1506 AR5K_PRINT_REGISTER(RFCNT); 1507 AR5K_PRINT_REGISTER(MISC); 1508 AR5K_PRINT_REGISTER(PISR); 1509 AR5K_PRINT_REGISTER(SISR0); 1510 AR5K_PRINT_REGISTER(SISR1); 1511 AR5K_PRINT_REGISTER(SISR3); 1512 AR5K_PRINT_REGISTER(SISR4); 1513 AR5K_PRINT_REGISTER(QCU_TXE); 1514 AR5K_PRINT_REGISTER(QCU_TXD); 1515 AR5K_PRINT_REGISTER(DCU_GBL_IFS_SIFS); 1516 AR5K_PRINT_REGISTER(DCU_GBL_IFS_SLOT); 1517 AR5K_PRINT_REGISTER(DCU_FP); 1518 AR5K_PRINT_REGISTER(DCU_TXP); 1519 AR5K_PRINT_REGISTER(DCU_TX_FILTER); 1520 AR5K_PRINT_REGISTER(RC); 1521 AR5K_PRINT_REGISTER(SCR); 1522 AR5K_PRINT_REGISTER(INTPEND); 1523 AR5K_PRINT_REGISTER(PCICFG); 1524 AR5K_PRINT_REGISTER(GPIOCR); 1525 AR5K_PRINT_REGISTER(GPIODO); 1526 AR5K_PRINT_REGISTER(SREV); 1527 AR5K_PRINT_REGISTER(EEPROM_BASE); 1528 AR5K_PRINT_REGISTER(EEPROM_DATA); 1529 AR5K_PRINT_REGISTER(EEPROM_CMD); 1530 AR5K_PRINT_REGISTER(EEPROM_CFG); 1531 AR5K_PRINT_REGISTER(PCU_MIN); 1532 AR5K_PRINT_REGISTER(STA_ID0); 1533 AR5K_PRINT_REGISTER(STA_ID1); 1534 AR5K_PRINT_REGISTER(BSS_ID0); 1535 AR5K_PRINT_REGISTER(SLOT_TIME); 1536 AR5K_PRINT_REGISTER(TIME_OUT); 1537 AR5K_PRINT_REGISTER(RSSI_THR); 1538 AR5K_PRINT_REGISTER(BEACON); 1539 AR5K_PRINT_REGISTER(CFP_PERIOD); 1540 AR5K_PRINT_REGISTER(TIMER0); 1541 AR5K_PRINT_REGISTER(TIMER2); 1542 AR5K_PRINT_REGISTER(TIMER3); 1543 AR5K_PRINT_REGISTER(CFP_DUR); 1544 AR5K_PRINT_REGISTER(MCAST_FIL0); 1545 AR5K_PRINT_REGISTER(MCAST_FIL1); 1546 AR5K_PRINT_REGISTER(DIAG_SW); 1547 AR5K_PRINT_REGISTER(TSF_U32); 1548 AR5K_PRINT_REGISTER(ADDAC_TEST); 1549 AR5K_PRINT_REGISTER(DEFAULT_ANTENNA); 1550 AR5K_PRINT_REGISTER(LAST_TSTP); 1551 AR5K_PRINT_REGISTER(NAV); 1552 AR5K_PRINT_REGISTER(RTS_OK); 1553 AR5K_PRINT_REGISTER(ACK_FAIL); 1554 AR5K_PRINT_REGISTER(FCS_FAIL); 1555 AR5K_PRINT_REGISTER(BEACON_CNT); 1556 AR5K_PRINT_REGISTER(KEYTABLE_0); 1557 printf("\n"); 1558 1559 printf("PHY registers:\n"); 1560 AR5K_PRINT_REGISTER(PHY_TURBO); 1561 AR5K_PRINT_REGISTER(PHY_AGC); 1562 AR5K_PRINT_REGISTER(PHY_CHIP_ID); 1563 AR5K_PRINT_REGISTER(PHY_AGCCTL); 1564 AR5K_PRINT_REGISTER(PHY_NF); 1565 AR5K_PRINT_REGISTER(PHY_RX_DELAY); 1566 AR5K_PRINT_REGISTER(PHY_IQ); 1567 AR5K_PRINT_REGISTER(PHY_PAPD_PROBE); 1568 AR5K_PRINT_REGISTER(PHY_FC); 1569 AR5K_PRINT_REGISTER(PHY_RADAR); 1570 AR5K_PRINT_REGISTER(PHY_ANT_SWITCH_TABLE_0); 1571 AR5K_PRINT_REGISTER(PHY_ANT_SWITCH_TABLE_1); 1572 printf("\n"); 1573 #endif 1574 } 1575 1576 HAL_BOOL 1577 ar5k_ar5211_get_diag_state(struct ath_hal *hal, int id, void **device, 1578 u_int *size) 1579 { 1580 /* 1581 * We'll ignore this right now. This seems to be some kind of an obscure 1582 * debugging interface for the binary-only HAL. 1583 */ 1584 return (AH_FALSE); 1585 } 1586 1587 void 1588 ar5k_ar5211_get_lladdr(struct ath_hal *hal, u_int8_t *mac) 1589 { 1590 bcopy(hal->ah_sta_id, mac, IEEE80211_ADDR_LEN); 1591 } 1592 1593 HAL_BOOL 1594 ar5k_ar5211_set_lladdr(struct ath_hal *hal, const u_int8_t *mac) 1595 { 1596 u_int32_t low_id, high_id; 1597 1598 /* Set new station ID */ 1599 bcopy(mac, hal->ah_sta_id, IEEE80211_ADDR_LEN); 1600 1601 low_id = AR5K_LOW_ID(mac); 1602 high_id = 0x0000ffff & AR5K_HIGH_ID(mac); 1603 1604 AR5K_REG_WRITE(AR5K_AR5211_STA_ID0, low_id); 1605 AR5K_REG_WRITE(AR5K_AR5211_STA_ID1, high_id); 1606 1607 return (AH_TRUE); 1608 } 1609 1610 HAL_BOOL 1611 ar5k_ar5211_set_regdomain(struct ath_hal *hal, u_int16_t regdomain, 1612 HAL_STATUS *status) 1613 { 1614 ieee80211_regdomain_t ieee_regdomain; 1615 1616 ieee_regdomain = ar5k_regdomain_to_ieee(regdomain); 1617 1618 if (ar5k_eeprom_regulation_domain(hal, AH_TRUE, 1619 &ieee_regdomain) == AH_TRUE) { 1620 *status = HAL_OK; 1621 return (AH_TRUE); 1622 } 1623 1624 *status = EIO; 1625 1626 return (AH_FALSE); 1627 } 1628 1629 void 1630 ar5k_ar5211_set_ledstate(struct ath_hal *hal, HAL_LED_STATE state) 1631 { 1632 u_int32_t led; 1633 1634 AR5K_REG_DISABLE_BITS(AR5K_AR5211_PCICFG, 1635 AR5K_AR5211_PCICFG_LEDMODE | AR5K_AR5211_PCICFG_LED); 1636 1637 /* 1638 * Some blinking values, define at your wish 1639 */ 1640 switch (state) { 1641 case IEEE80211_S_SCAN: 1642 case IEEE80211_S_AUTH: 1643 led = AR5K_AR5211_PCICFG_LEDMODE_PROP | 1644 AR5K_AR5211_PCICFG_LED_PEND; 1645 break; 1646 1647 case IEEE80211_S_INIT: 1648 led = AR5K_AR5211_PCICFG_LEDMODE_PROP | 1649 AR5K_AR5211_PCICFG_LED_NONE; 1650 break; 1651 1652 case IEEE80211_S_ASSOC: 1653 case IEEE80211_S_RUN: 1654 led = AR5K_AR5211_PCICFG_LEDMODE_PROP | 1655 AR5K_AR5211_PCICFG_LED_ASSOC; 1656 break; 1657 1658 default: 1659 led = AR5K_AR5211_PCICFG_LEDMODE_PROM | 1660 AR5K_AR5211_PCICFG_LED_NONE; 1661 break; 1662 } 1663 1664 AR5K_REG_ENABLE_BITS(AR5K_AR5211_PCICFG, led); 1665 } 1666 1667 void 1668 ar5k_ar5211_set_associd(struct ath_hal *hal, const u_int8_t *bssid, 1669 u_int16_t assoc_id, u_int16_t tim_offset) 1670 { 1671 u_int32_t low_id, high_id; 1672 1673 /* 1674 * Set BSSID which triggers the "SME Join" operation 1675 */ 1676 low_id = AR5K_LOW_ID(bssid); 1677 high_id = AR5K_HIGH_ID(bssid); 1678 AR5K_REG_WRITE(AR5K_AR5211_BSS_ID0, low_id); 1679 AR5K_REG_WRITE(AR5K_AR5211_BSS_ID1, high_id | 1680 ((assoc_id & 0x3fff) << AR5K_AR5211_BSS_ID1_AID_S)); 1681 bcopy(bssid, hal->ah_bssid, IEEE80211_ADDR_LEN); 1682 1683 if (assoc_id == 0) { 1684 ar5k_ar5211_disable_pspoll(hal); 1685 return; 1686 } 1687 1688 AR5K_REG_WRITE(AR5K_AR5211_BEACON, 1689 (AR5K_REG_READ(AR5K_AR5211_BEACON) & 1690 ~AR5K_AR5211_BEACON_TIM) | 1691 (((tim_offset ? tim_offset + 4 : 0) << 1692 AR5K_AR5211_BEACON_TIM_S) & 1693 AR5K_AR5211_BEACON_TIM)); 1694 1695 ar5k_ar5211_enable_pspoll(hal, NULL, 0); 1696 } 1697 1698 HAL_BOOL 1699 ar5k_ar5211_set_bssid_mask(struct ath_hal *hal, const u_int8_t* mask) 1700 { 1701 /* Not supported in 5211 */ 1702 return (AH_FALSE); 1703 } 1704 1705 HAL_BOOL 1706 ar5k_ar5211_set_gpio_output(struct ath_hal *hal, u_int32_t gpio) 1707 { 1708 if (gpio > AR5K_AR5211_NUM_GPIO) 1709 return (AH_FALSE); 1710 1711 AR5K_REG_WRITE(AR5K_AR5211_GPIOCR, 1712 (AR5K_REG_READ(AR5K_AR5211_GPIOCR) &~ AR5K_AR5211_GPIOCR_ALL(gpio)) 1713 | AR5K_AR5211_GPIOCR_ALL(gpio)); 1714 1715 return (AH_TRUE); 1716 } 1717 1718 HAL_BOOL 1719 ar5k_ar5211_set_gpio_input(struct ath_hal *hal, u_int32_t gpio) 1720 { 1721 if (gpio > AR5K_AR5211_NUM_GPIO) 1722 return (AH_FALSE); 1723 1724 AR5K_REG_WRITE(AR5K_AR5211_GPIOCR, 1725 (AR5K_REG_READ(AR5K_AR5211_GPIOCR) &~ AR5K_AR5211_GPIOCR_ALL(gpio)) 1726 | AR5K_AR5211_GPIOCR_NONE(gpio)); 1727 1728 return (AH_TRUE); 1729 } 1730 1731 u_int32_t 1732 ar5k_ar5211_get_gpio(struct ath_hal *hal, u_int32_t gpio) 1733 { 1734 if (gpio > AR5K_AR5211_NUM_GPIO) 1735 return (0xffffffff); 1736 1737 /* GPIO input magic */ 1738 return (((AR5K_REG_READ(AR5K_AR5211_GPIODI) & 1739 AR5K_AR5211_GPIODI_M) >> gpio) & 0x1); 1740 } 1741 1742 HAL_BOOL 1743 ar5k_ar5211_set_gpio(struct ath_hal *hal, u_int32_t gpio, u_int32_t val) 1744 { 1745 u_int32_t data; 1746 1747 if (gpio > AR5K_AR5211_NUM_GPIO) 1748 return (0xffffffff); 1749 1750 /* GPIO output magic */ 1751 data = AR5K_REG_READ(AR5K_AR5211_GPIODO); 1752 1753 data &= ~(1 << gpio); 1754 data |= (val&1) << gpio; 1755 1756 AR5K_REG_WRITE(AR5K_AR5211_GPIODO, data); 1757 1758 return (AH_TRUE); 1759 } 1760 1761 void 1762 ar5k_ar5211_set_gpio_intr(struct ath_hal *hal, u_int gpio, 1763 u_int32_t interrupt_level) 1764 { 1765 u_int32_t data; 1766 1767 if (gpio > AR5K_AR5211_NUM_GPIO) 1768 return; 1769 1770 /* 1771 * Set the GPIO interrupt 1772 */ 1773 data = (AR5K_REG_READ(AR5K_AR5211_GPIOCR) & 1774 ~(AR5K_AR5211_GPIOCR_INT_SEL(gpio) | AR5K_AR5211_GPIOCR_INT_SELH | 1775 AR5K_AR5211_GPIOCR_INT_ENA | AR5K_AR5211_GPIOCR_ALL(gpio))) | 1776 (AR5K_AR5211_GPIOCR_INT_SEL(gpio) | AR5K_AR5211_GPIOCR_INT_ENA); 1777 1778 AR5K_REG_WRITE(AR5K_AR5211_GPIOCR, 1779 interrupt_level ? data : (data | AR5K_AR5211_GPIOCR_INT_SELH)); 1780 1781 hal->ah_imr |= AR5K_AR5211_PIMR_GPIO; 1782 1783 /* Enable GPIO interrupts */ 1784 AR5K_REG_ENABLE_BITS(AR5K_AR5211_PIMR, AR5K_AR5211_PIMR_GPIO); 1785 } 1786 1787 u_int32_t 1788 ar5k_ar5211_get_tsf32(struct ath_hal *hal) 1789 { 1790 return (AR5K_REG_READ(AR5K_AR5211_TSF_L32)); 1791 } 1792 1793 u_int64_t 1794 ar5k_ar5211_get_tsf64(struct ath_hal *hal) 1795 { 1796 u_int64_t tsf = AR5K_REG_READ(AR5K_AR5211_TSF_U32); 1797 1798 return (AR5K_REG_READ(AR5K_AR5211_TSF_L32) | (tsf << 32)); 1799 } 1800 1801 void 1802 ar5k_ar5211_reset_tsf(struct ath_hal *hal) 1803 { 1804 AR5K_REG_ENABLE_BITS(AR5K_AR5211_BEACON, 1805 AR5K_AR5211_BEACON_RESET_TSF); 1806 } 1807 1808 u_int16_t 1809 ar5k_ar5211_get_regdomain(struct ath_hal *hal) 1810 { 1811 return (ar5k_get_regdomain(hal)); 1812 } 1813 1814 HAL_BOOL 1815 ar5k_ar5211_detect_card_present(struct ath_hal *hal) 1816 { 1817 u_int16_t magic; 1818 1819 /* 1820 * Checking the EEPROM's magic value could be an indication 1821 * if the card is still present. I didn't find another suitable 1822 * way to do this. 1823 */ 1824 if (ar5k_ar5211_eeprom_read(hal, AR5K_EEPROM_MAGIC, &magic) != 0) 1825 return (AH_FALSE); 1826 1827 return (magic == AR5K_EEPROM_MAGIC_VALUE ? AH_TRUE : AH_FALSE); 1828 } 1829 1830 void 1831 ar5k_ar5211_update_mib_counters(struct ath_hal *hal, HAL_MIB_STATS *statistics) 1832 { 1833 statistics->ackrcv_bad += AR5K_REG_READ(AR5K_AR5211_ACK_FAIL); 1834 statistics->rts_bad += AR5K_REG_READ(AR5K_AR5211_RTS_FAIL); 1835 statistics->rts_good += AR5K_REG_READ(AR5K_AR5211_RTS_OK); 1836 statistics->fcs_bad += AR5K_REG_READ(AR5K_AR5211_FCS_FAIL); 1837 statistics->beacons += AR5K_REG_READ(AR5K_AR5211_BEACON_CNT); 1838 } 1839 1840 HAL_RFGAIN 1841 ar5k_ar5211_get_rf_gain(struct ath_hal *hal) 1842 { 1843 return (HAL_RFGAIN_INACTIVE); 1844 } 1845 1846 HAL_BOOL 1847 ar5k_ar5211_set_slot_time(struct ath_hal *hal, u_int slot_time) 1848 { 1849 if (slot_time < HAL_SLOT_TIME_9 || slot_time > HAL_SLOT_TIME_MAX) 1850 return (AH_FALSE); 1851 1852 AR5K_REG_WRITE(AR5K_AR5211_DCU_GBL_IFS_SLOT, slot_time); 1853 1854 return (AH_TRUE); 1855 } 1856 1857 u_int 1858 ar5k_ar5211_get_slot_time(struct ath_hal *hal) 1859 { 1860 return (AR5K_REG_READ(AR5K_AR5211_DCU_GBL_IFS_SLOT) & 0xffff); 1861 } 1862 1863 HAL_BOOL 1864 ar5k_ar5211_set_ack_timeout(struct ath_hal *hal, u_int timeout) 1865 { 1866 if (ar5k_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_AR5211_TIME_OUT_ACK), 1867 hal->ah_turbo) <= timeout) 1868 return (AH_FALSE); 1869 1870 AR5K_REG_WRITE_BITS(AR5K_AR5211_TIME_OUT, AR5K_AR5211_TIME_OUT_ACK, 1871 ar5k_htoclock(timeout, hal->ah_turbo)); 1872 1873 return (AH_TRUE); 1874 } 1875 1876 u_int 1877 ar5k_ar5211_get_ack_timeout(struct ath_hal *hal) 1878 { 1879 return (ar5k_clocktoh(AR5K_REG_MS(AR5K_REG_READ(AR5K_AR5211_TIME_OUT), 1880 AR5K_AR5211_TIME_OUT_ACK), hal->ah_turbo)); 1881 } 1882 1883 HAL_BOOL 1884 ar5k_ar5211_set_cts_timeout(struct ath_hal *hal, u_int timeout) 1885 { 1886 if (ar5k_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_AR5211_TIME_OUT_CTS), 1887 hal->ah_turbo) <= timeout) 1888 return (AH_FALSE); 1889 1890 AR5K_REG_WRITE_BITS(AR5K_AR5211_TIME_OUT, AR5K_AR5211_TIME_OUT_CTS, 1891 ar5k_htoclock(timeout, hal->ah_turbo)); 1892 1893 return (AH_TRUE); 1894 } 1895 1896 u_int 1897 ar5k_ar5211_get_cts_timeout(struct ath_hal *hal) 1898 { 1899 return (ar5k_clocktoh(AR5K_REG_MS(AR5K_REG_READ(AR5K_AR5211_TIME_OUT), 1900 AR5K_AR5211_TIME_OUT_CTS), hal->ah_turbo)); 1901 } 1902 1903 /* 1904 * Key table (WEP) functions 1905 */ 1906 1907 HAL_BOOL 1908 ar5k_ar5211_is_cipher_supported(struct ath_hal *hal, HAL_CIPHER cipher) 1909 { 1910 /* 1911 * The AR5211 only supports WEP 1912 */ 1913 if (cipher == HAL_CIPHER_WEP) 1914 return (AH_TRUE); 1915 1916 return (AH_FALSE); 1917 } 1918 1919 u_int32_t 1920 ar5k_ar5211_get_keycache_size(struct ath_hal *hal) 1921 { 1922 return (AR5K_AR5211_KEYCACHE_SIZE); 1923 } 1924 1925 HAL_BOOL 1926 ar5k_ar5211_reset_key(struct ath_hal *hal, u_int16_t entry) 1927 { 1928 int i; 1929 1930 AR5K_ASSERT_ENTRY(entry, AR5K_AR5211_KEYTABLE_SIZE); 1931 1932 for (i = 0; i < AR5K_AR5211_KEYCACHE_SIZE; i++) 1933 AR5K_REG_WRITE(AR5K_AR5211_KEYTABLE_OFF(entry, i), 0); 1934 1935 return (AH_FALSE); 1936 } 1937 1938 HAL_BOOL 1939 ar5k_ar5211_is_key_valid(struct ath_hal *hal, u_int16_t entry) 1940 { 1941 AR5K_ASSERT_ENTRY(entry, AR5K_AR5211_KEYTABLE_SIZE); 1942 1943 /* 1944 * Check the validation flag at the end of the entry 1945 */ 1946 if (AR5K_REG_READ(AR5K_AR5211_KEYTABLE_MAC1(entry)) & 1947 AR5K_AR5211_KEYTABLE_VALID) 1948 return (AH_TRUE); 1949 1950 return (AH_FALSE); 1951 } 1952 1953 HAL_BOOL 1954 ar5k_ar5211_set_key(struct ath_hal *hal, u_int16_t entry, 1955 const HAL_KEYVAL *keyval, const u_int8_t *mac, int xor_notused) 1956 { 1957 int i; 1958 u_int32_t key_v[AR5K_AR5211_KEYCACHE_SIZE - 2]; 1959 1960 AR5K_ASSERT_ENTRY(entry, AR5K_AR5211_KEYTABLE_SIZE); 1961 1962 bzero(&key_v, sizeof(key_v)); 1963 1964 switch (keyval->wk_len) { 1965 case AR5K_KEYVAL_LENGTH_40: 1966 bcopy(keyval->wk_key, &key_v[0], 4); 1967 bcopy(keyval->wk_key + 4, &key_v[1], 1); 1968 key_v[5] = AR5K_AR5211_KEYTABLE_TYPE_40; 1969 break; 1970 1971 case AR5K_KEYVAL_LENGTH_104: 1972 bcopy(keyval->wk_key, &key_v[0], 4); 1973 bcopy(keyval->wk_key + 4, &key_v[1], 2); 1974 bcopy(keyval->wk_key + 6, &key_v[2], 4); 1975 bcopy(keyval->wk_key + 10, &key_v[3], 2); 1976 bcopy(keyval->wk_key + 12, &key_v[4], 1); 1977 key_v[5] = AR5K_AR5211_KEYTABLE_TYPE_104; 1978 break; 1979 1980 case AR5K_KEYVAL_LENGTH_128: 1981 bcopy(keyval->wk_key, &key_v[0], 4); 1982 bcopy(keyval->wk_key + 4, &key_v[1], 2); 1983 bcopy(keyval->wk_key + 6, &key_v[2], 4); 1984 bcopy(keyval->wk_key + 10, &key_v[3], 2); 1985 bcopy(keyval->wk_key + 12, &key_v[4], 4); 1986 key_v[5] = AR5K_AR5211_KEYTABLE_TYPE_128; 1987 break; 1988 1989 default: 1990 /* Unsupported key length (not WEP40/104/128) */ 1991 return (AH_FALSE); 1992 } 1993 1994 for (i = 0; i < AR5K_ELEMENTS(key_v); i++) 1995 AR5K_REG_WRITE(AR5K_AR5211_KEYTABLE_OFF(entry, i), key_v[i]); 1996 1997 return (ar5k_ar5211_set_key_lladdr(hal, entry, mac)); 1998 } 1999 2000 HAL_BOOL 2001 ar5k_ar5211_set_key_lladdr(struct ath_hal *hal, u_int16_t entry, 2002 const u_int8_t *mac) 2003 { 2004 u_int32_t low_id, high_id; 2005 const u_int8_t *mac_v; 2006 2007 /* 2008 * Invalid entry (key table overflow) 2009 */ 2010 AR5K_ASSERT_ENTRY(entry, AR5K_AR5211_KEYTABLE_SIZE); 2011 2012 /* MAC may be NULL if it's a broadcast key */ 2013 mac_v = mac == NULL ? etherbroadcastaddr : mac; 2014 2015 low_id = AR5K_LOW_ID(mac_v); 2016 high_id = AR5K_HIGH_ID(mac_v) | AR5K_AR5211_KEYTABLE_VALID; 2017 2018 AR5K_REG_WRITE(AR5K_AR5211_KEYTABLE_MAC0(entry), low_id); 2019 AR5K_REG_WRITE(AR5K_AR5211_KEYTABLE_MAC1(entry), high_id); 2020 2021 return (AH_TRUE); 2022 } 2023 2024 HAL_BOOL 2025 ar5k_ar5211_softcrypto(struct ath_hal *hal, HAL_BOOL enable) 2026 { 2027 u_int32_t bits; 2028 int i; 2029 2030 bits = AR5K_AR5211_DIAG_SW_DIS_ENC | AR5K_AR5211_DIAG_SW_DIS_DEC; 2031 if (enable == AH_TRUE) { 2032 /* Disable the hardware crypto engine */ 2033 AR5K_REG_ENABLE_BITS(AR5K_AR5211_DIAG_SW, bits); 2034 } else { 2035 /* Enable the hardware crypto engine */ 2036 AR5K_REG_DISABLE_BITS(AR5K_AR5211_DIAG_SW, bits); 2037 } 2038 2039 /* Reset the key cache */ 2040 for (i = 0; i < AR5K_AR5211_KEYTABLE_SIZE; i++) 2041 ar5k_ar5211_reset_key(hal, i); 2042 2043 return (AH_TRUE); 2044 } 2045 2046 /* 2047 * Power management functions 2048 */ 2049 2050 HAL_BOOL 2051 ar5k_ar5211_set_power(struct ath_hal *hal, HAL_POWER_MODE mode, 2052 HAL_BOOL set_chip, u_int16_t sleep_duration) 2053 { 2054 u_int32_t staid; 2055 int i; 2056 2057 staid = AR5K_REG_READ(AR5K_AR5211_STA_ID1); 2058 2059 switch (mode) { 2060 case HAL_PM_AUTO: 2061 staid &= ~AR5K_AR5211_STA_ID1_DEFAULT_ANTENNA; 2062 /* FALLTHROUGH */ 2063 case HAL_PM_NETWORK_SLEEP: 2064 if (set_chip == AH_TRUE) { 2065 AR5K_REG_WRITE(AR5K_AR5211_SCR, 2066 AR5K_AR5211_SCR_SLE | sleep_duration); 2067 } 2068 staid |= AR5K_AR5211_STA_ID1_PWR_SV; 2069 break; 2070 2071 case HAL_PM_FULL_SLEEP: 2072 if (set_chip == AH_TRUE) { 2073 AR5K_REG_WRITE(AR5K_AR5211_SCR, 2074 AR5K_AR5211_SCR_SLE_SLP); 2075 } 2076 staid |= AR5K_AR5211_STA_ID1_PWR_SV; 2077 break; 2078 2079 case HAL_PM_AWAKE: 2080 if (set_chip == AH_FALSE) 2081 goto commit; 2082 2083 AR5K_REG_WRITE(AR5K_AR5211_SCR, AR5K_AR5211_SCR_SLE_WAKE); 2084 2085 for (i = 5000; i > 0; i--) { 2086 /* Check if the AR5211 did wake up */ 2087 if ((AR5K_REG_READ(AR5K_AR5211_PCICFG) & 2088 AR5K_AR5211_PCICFG_SPWR_DN) == 0) 2089 break; 2090 2091 /* Wait a bit and retry */ 2092 AR5K_DELAY(200); 2093 AR5K_REG_WRITE(AR5K_AR5211_SCR, 2094 AR5K_AR5211_SCR_SLE_WAKE); 2095 } 2096 2097 /* Fail if the AR5211 didn't wake up */ 2098 if (i <= 0) 2099 return (AH_FALSE); 2100 2101 staid &= ~AR5K_AR5211_STA_ID1_PWR_SV; 2102 break; 2103 2104 default: 2105 return (AH_FALSE); 2106 } 2107 2108 commit: 2109 hal->ah_power_mode = mode; 2110 2111 AR5K_REG_WRITE(AR5K_AR5211_STA_ID1, staid); 2112 2113 return (AH_TRUE); 2114 } 2115 2116 HAL_POWER_MODE 2117 ar5k_ar5211_get_power_mode(struct ath_hal *hal) 2118 { 2119 return (hal->ah_power_mode); 2120 } 2121 2122 HAL_BOOL 2123 ar5k_ar5211_query_pspoll_support(struct ath_hal *hal) 2124 { 2125 /* nope */ 2126 return (AH_FALSE); 2127 } 2128 2129 HAL_BOOL 2130 ar5k_ar5211_init_pspoll(struct ath_hal *hal) 2131 { 2132 /* 2133 * Not used on the AR5211 2134 */ 2135 return (AH_FALSE); 2136 } 2137 2138 HAL_BOOL 2139 ar5k_ar5211_enable_pspoll(struct ath_hal *hal, u_int8_t *bssid, 2140 u_int16_t assoc_id) 2141 { 2142 return (AH_FALSE); 2143 } 2144 2145 HAL_BOOL 2146 ar5k_ar5211_disable_pspoll(struct ath_hal *hal) 2147 { 2148 return (AH_FALSE); 2149 } 2150 2151 /* 2152 * Beacon functions 2153 */ 2154 2155 void 2156 ar5k_ar5211_init_beacon(struct ath_hal *hal, u_int32_t next_beacon, 2157 u_int32_t interval) 2158 { 2159 u_int32_t timer1, timer2, timer3; 2160 2161 /* 2162 * Set the additional timers by mode 2163 */ 2164 switch (hal->ah_op_mode) { 2165 case HAL_M_STA: 2166 timer1 = 0x0000ffff; 2167 timer2 = 0x0007ffff; 2168 break; 2169 2170 default: 2171 timer1 = (next_beacon - AR5K_TUNE_DMA_BEACON_RESP) << 2172 0x00000003; 2173 timer2 = (next_beacon - AR5K_TUNE_SW_BEACON_RESP) << 2174 0x00000003; 2175 } 2176 2177 timer3 = next_beacon + 2178 (hal->ah_atim_window ? hal->ah_atim_window : 1); 2179 2180 /* 2181 * Enable all timers and set the beacon register 2182 * (next beacon, DMA beacon, software beacon, ATIM window time) 2183 */ 2184 AR5K_REG_WRITE(AR5K_AR5211_TIMER0, next_beacon); 2185 AR5K_REG_WRITE(AR5K_AR5211_TIMER1, timer1); 2186 AR5K_REG_WRITE(AR5K_AR5211_TIMER2, timer2); 2187 AR5K_REG_WRITE(AR5K_AR5211_TIMER3, timer3); 2188 2189 AR5K_REG_WRITE(AR5K_AR5211_BEACON, interval & 2190 (AR5K_AR5211_BEACON_PERIOD | AR5K_AR5211_BEACON_RESET_TSF | 2191 AR5K_AR5211_BEACON_ENABLE)); 2192 } 2193 2194 void 2195 ar5k_ar5211_set_beacon_timers(struct ath_hal *hal, 2196 const HAL_BEACON_STATE *state, u_int32_t tsf, u_int32_t dtim_count, 2197 u_int32_t cfp_count) 2198 { 2199 u_int32_t cfp_period, next_cfp; 2200 2201 /* Return on an invalid beacon state */ 2202 if (state->bs_interval < 1) 2203 return; 2204 2205 /* 2206 * PCF support? 2207 */ 2208 if (state->bs_cfp_period > 0) { 2209 /* Enable CFP mode and set the CFP and timer registers */ 2210 cfp_period = state->bs_cfp_period * state->bs_dtim_period * 2211 state->bs_interval; 2212 next_cfp = (cfp_count * state->bs_dtim_period + dtim_count) * 2213 state->bs_interval; 2214 2215 AR5K_REG_DISABLE_BITS(AR5K_AR5211_STA_ID1, 2216 AR5K_AR5211_STA_ID1_DEFAULT_ANTENNA | 2217 AR5K_AR5211_STA_ID1_PCF); 2218 AR5K_REG_WRITE(AR5K_AR5211_CFP_PERIOD, cfp_period); 2219 AR5K_REG_WRITE(AR5K_AR5211_CFP_DUR, state->bs_cfp_max_duration); 2220 AR5K_REG_WRITE(AR5K_AR5211_TIMER2, 2221 (tsf + (next_cfp == 0 ? cfp_period : next_cfp)) << 3); 2222 } else { 2223 /* Disable PCF mode */ 2224 AR5K_REG_DISABLE_BITS(AR5K_AR5211_STA_ID1, 2225 AR5K_AR5211_STA_ID1_DEFAULT_ANTENNA | 2226 AR5K_AR5211_STA_ID1_PCF); 2227 } 2228 2229 /* 2230 * Enable the beacon timer register 2231 */ 2232 AR5K_REG_WRITE(AR5K_AR5211_TIMER0, state->bs_next_beacon); 2233 2234 /* 2235 * Start the beacon timers 2236 */ 2237 AR5K_REG_WRITE(AR5K_AR5211_BEACON, 2238 (AR5K_REG_READ(AR5K_AR5211_BEACON) &~ 2239 (AR5K_AR5211_BEACON_PERIOD | AR5K_AR5211_BEACON_TIM)) | 2240 AR5K_REG_SM(state->bs_tim_offset ? state->bs_tim_offset + 4 : 0, 2241 AR5K_AR5211_BEACON_TIM) | AR5K_REG_SM(state->bs_interval, 2242 AR5K_AR5211_BEACON_PERIOD)); 2243 2244 /* 2245 * Write new beacon miss threshold, if it appears to be valid 2246 */ 2247 if ((AR5K_AR5211_RSSI_THR_BMISS >> AR5K_AR5211_RSSI_THR_BMISS_S) < 2248 state->bs_bmiss_threshold) 2249 return; 2250 2251 AR5K_REG_WRITE_BITS(AR5K_AR5211_RSSI_THR_M, 2252 AR5K_AR5211_RSSI_THR_BMISS, state->bs_bmiss_threshold); 2253 AR5K_REG_WRITE_BITS(AR5K_AR5211_SCR, AR5K_AR5211_SCR_SLDUR, 2254 (state->bs_sleepduration - 3) << 3); 2255 } 2256 2257 void 2258 ar5k_ar5211_reset_beacon(struct ath_hal *hal) 2259 { 2260 /* 2261 * Disable beacon timer 2262 */ 2263 AR5K_REG_WRITE(AR5K_AR5211_TIMER0, 0); 2264 2265 /* 2266 * Disable some beacon register values 2267 */ 2268 AR5K_REG_DISABLE_BITS(AR5K_AR5211_STA_ID1, 2269 AR5K_AR5211_STA_ID1_DEFAULT_ANTENNA | AR5K_AR5211_STA_ID1_PCF); 2270 AR5K_REG_WRITE(AR5K_AR5211_BEACON, AR5K_AR5211_BEACON_PERIOD); 2271 } 2272 2273 HAL_BOOL 2274 ar5k_ar5211_wait_for_beacon(struct ath_hal *hal, bus_addr_t phys_addr) 2275 { 2276 HAL_BOOL ret; 2277 2278 /* 2279 * Wait for beaconn queue to be done 2280 */ 2281 ret = ar5k_register_timeout(hal, 2282 AR5K_AR5211_QCU_STS(HAL_TX_QUEUE_ID_BEACON), 2283 AR5K_AR5211_QCU_STS_FRMPENDCNT, 0, AH_FALSE); 2284 2285 if (AR5K_REG_READ_Q(AR5K_AR5211_QCU_TXE, HAL_TX_QUEUE_ID_BEACON)) 2286 return (AH_FALSE); 2287 2288 return (ret); 2289 } 2290 2291 /* 2292 * Interrupt handling 2293 */ 2294 2295 HAL_BOOL 2296 ar5k_ar5211_is_intr_pending(struct ath_hal *hal) 2297 { 2298 return (AR5K_REG_READ(AR5K_AR5211_INTPEND) == 0 ? AH_FALSE : AH_TRUE); 2299 } 2300 2301 HAL_BOOL 2302 ar5k_ar5211_get_isr(struct ath_hal *hal, u_int32_t *interrupt_mask) 2303 { 2304 u_int32_t data; 2305 2306 /* 2307 * Read interrupt status from the Read-And-Clear shadow register 2308 */ 2309 data = AR5K_REG_READ(AR5K_AR5211_RAC_PISR); 2310 2311 /* 2312 * Get abstract interrupt mask (HAL-compatible) 2313 */ 2314 *interrupt_mask = (data & HAL_INT_COMMON) & hal->ah_imr; 2315 2316 if (data == HAL_INT_NOCARD) 2317 return (AH_FALSE); 2318 2319 if (data & (AR5K_AR5211_PISR_RXOK | AR5K_AR5211_PISR_RXERR)) 2320 *interrupt_mask |= HAL_INT_RX; 2321 2322 if (data & (AR5K_AR5211_PISR_TXOK | AR5K_AR5211_PISR_TXERR)) 2323 *interrupt_mask |= HAL_INT_TX; 2324 2325 if (data & (AR5K_AR5211_PISR_HIUERR)) 2326 *interrupt_mask |= HAL_INT_FATAL; 2327 2328 /* 2329 * Special interrupt handling (not caught by the driver) 2330 */ 2331 if (((*interrupt_mask) & AR5K_AR5211_PISR_RXPHY) && 2332 hal->ah_radar.r_enabled == AH_TRUE) 2333 ar5k_radar_alert(hal); 2334 2335 return (AH_TRUE); 2336 } 2337 2338 u_int32_t 2339 ar5k_ar5211_get_intr(struct ath_hal *hal) 2340 { 2341 /* Return the interrupt mask stored previously */ 2342 return (hal->ah_imr); 2343 } 2344 2345 HAL_INT 2346 ar5k_ar5211_set_intr(struct ath_hal *hal, HAL_INT new_mask) 2347 { 2348 HAL_INT old_mask, int_mask; 2349 2350 /* 2351 * Disable card interrupts to prevent any race conditions 2352 * (they will be re-enabled afterwards). 2353 */ 2354 AR5K_REG_WRITE(AR5K_AR5211_IER, AR5K_AR5211_IER_DISABLE); 2355 2356 old_mask = hal->ah_imr; 2357 2358 /* 2359 * Add additional, chipset-dependent interrupt mask flags 2360 * and write them to the IMR (interrupt mask register). 2361 */ 2362 int_mask = new_mask & HAL_INT_COMMON; 2363 2364 if (new_mask & HAL_INT_RX) 2365 int_mask |= 2366 AR5K_AR5211_PIMR_RXOK | 2367 AR5K_AR5211_PIMR_RXERR | 2368 AR5K_AR5211_PIMR_RXORN | 2369 AR5K_AR5211_PIMR_RXDESC; 2370 2371 if (new_mask & HAL_INT_TX) 2372 int_mask |= 2373 AR5K_AR5211_PIMR_TXOK | 2374 AR5K_AR5211_PIMR_TXERR | 2375 AR5K_AR5211_PIMR_TXDESC | 2376 AR5K_AR5211_PIMR_TXURN; 2377 2378 if (new_mask & HAL_INT_FATAL) { 2379 int_mask |= AR5K_AR5211_PIMR_HIUERR; 2380 AR5K_REG_ENABLE_BITS(AR5K_AR5211_SIMR2, 2381 AR5K_AR5211_SIMR2_MCABT | 2382 AR5K_AR5211_SIMR2_SSERR | 2383 AR5K_AR5211_SIMR2_DPERR); 2384 } 2385 2386 AR5K_REG_WRITE(AR5K_AR5211_PIMR, int_mask); 2387 2388 /* Store new interrupt mask */ 2389 hal->ah_imr = new_mask; 2390 2391 /* ..re-enable interrupts */ 2392 AR5K_REG_WRITE(AR5K_AR5211_IER, AR5K_AR5211_IER_ENABLE); 2393 2394 return (old_mask); 2395 } 2396 2397 /* 2398 * Misc internal functions 2399 */ 2400 2401 HAL_BOOL 2402 ar5k_ar5211_get_capabilities(struct ath_hal *hal) 2403 { 2404 u_int16_t ee_header; 2405 u_int a, b, g; 2406 2407 /* Capabilities stored in the EEPROM */ 2408 ee_header = hal->ah_capabilities.cap_eeprom.ee_header; 2409 2410 a = AR5K_EEPROM_HDR_11A(ee_header); 2411 b = AR5K_EEPROM_HDR_11B(ee_header); 2412 g = AR5K_EEPROM_HDR_11G(ee_header); 2413 2414 /* 2415 * If the EEPROM is not reporting any mode, we try 11b. 2416 * This might fix a few broken devices with invalid EEPROM. 2417 */ 2418 if (!a && !b && !g) 2419 b = 1; 2420 2421 /* 2422 * XXX The AR5211 tranceiver supports frequencies from 4920 to 6100GHz 2423 * XXX and from 2312 to 2732GHz. There are problems with the current 2424 * XXX ieee80211 implementation because the IEEE channel mapping 2425 * XXX does not support negative channel numbers (2312MHz is channel 2426 * XXX -19). Of course, this doesn't matter because these channels 2427 * XXX are out of range but some regulation domains like MKK (Japan) 2428 * XXX will support frequencies somewhere around 4.8GHz. 2429 */ 2430 2431 /* 2432 * Set radio capabilities 2433 */ 2434 2435 if (a) { 2436 hal->ah_capabilities.cap_range.range_5ghz_min = 5005; /* 4920 */ 2437 hal->ah_capabilities.cap_range.range_5ghz_max = 6100; 2438 2439 /* Set supported modes */ 2440 hal->ah_capabilities.cap_mode = HAL_MODE_11A | HAL_MODE_TURBO; 2441 } 2442 2443 /* This chip will support 802.11b if the 2GHz radio is connected */ 2444 if (b || g) { 2445 hal->ah_capabilities.cap_range.range_2ghz_min = 2412; /* 2312 */ 2446 hal->ah_capabilities.cap_range.range_2ghz_max = 2732; 2447 2448 if (b) 2449 hal->ah_capabilities.cap_mode |= HAL_MODE_11B; 2450 #if 0 2451 if (g) 2452 hal->ah_capabilities.cap_mode |= HAL_MODE_11G; 2453 #endif 2454 } 2455 2456 /* GPIO */ 2457 hal->ah_gpio_npins = AR5K_AR5211_NUM_GPIO; 2458 2459 /* Set number of supported TX queues */ 2460 hal->ah_capabilities.cap_queues.q_tx_num = AR5K_AR5211_TX_NUM_QUEUES; 2461 2462 return (AH_TRUE); 2463 } 2464 2465 void 2466 ar5k_ar5211_radar_alert(struct ath_hal *hal, HAL_BOOL enable) 2467 { 2468 /* 2469 * Enable radar detection 2470 */ 2471 AR5K_REG_WRITE(AR5K_AR5211_IER, AR5K_AR5211_IER_DISABLE); 2472 2473 if (enable == AH_TRUE) { 2474 AR5K_REG_WRITE(AR5K_AR5211_PHY_RADAR, 2475 AR5K_AR5211_PHY_RADAR_ENABLE); 2476 AR5K_REG_ENABLE_BITS(AR5K_AR5211_PIMR, 2477 AR5K_AR5211_PIMR_RXPHY); 2478 } else { 2479 AR5K_REG_WRITE(AR5K_AR5211_PHY_RADAR, 2480 AR5K_AR5211_PHY_RADAR_DISABLE); 2481 AR5K_REG_DISABLE_BITS(AR5K_AR5211_PIMR, 2482 AR5K_AR5211_PIMR_RXPHY); 2483 } 2484 2485 AR5K_REG_WRITE(AR5K_AR5211_IER, AR5K_AR5211_IER_ENABLE); 2486 } 2487 2488 /* 2489 * EEPROM access functions 2490 */ 2491 2492 HAL_BOOL 2493 ar5k_ar5211_eeprom_is_busy(struct ath_hal *hal) 2494 { 2495 return (AR5K_REG_READ(AR5K_AR5211_CFG) & AR5K_AR5211_CFG_EEBS ? 2496 AH_TRUE : AH_FALSE); 2497 } 2498 2499 int 2500 ar5k_ar5211_eeprom_read(struct ath_hal *hal, u_int32_t offset, u_int16_t *data) 2501 { 2502 u_int32_t status, i; 2503 2504 /* 2505 * Initialize EEPROM access 2506 */ 2507 AR5K_REG_WRITE(AR5K_AR5211_EEPROM_BASE, (u_int8_t)offset); 2508 AR5K_REG_ENABLE_BITS(AR5K_AR5211_EEPROM_CMD, 2509 AR5K_AR5211_EEPROM_CMD_READ); 2510 2511 for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) { 2512 status = AR5K_REG_READ(AR5K_AR5211_EEPROM_STATUS); 2513 if (status & AR5K_AR5211_EEPROM_STAT_RDDONE) { 2514 if (status & AR5K_AR5211_EEPROM_STAT_RDERR) 2515 return (EIO); 2516 *data = (u_int16_t) 2517 (AR5K_REG_READ(AR5K_AR5211_EEPROM_DATA) & 0xffff); 2518 return (0); 2519 } 2520 AR5K_DELAY(15); 2521 } 2522 2523 return (ETIMEDOUT); 2524 } 2525 2526 int 2527 ar5k_ar5211_eeprom_write(struct ath_hal *hal, u_int32_t offset, u_int16_t data) 2528 { 2529 u_int32_t status, timeout; 2530 2531 /* Enable eeprom access */ 2532 AR5K_REG_ENABLE_BITS(AR5K_AR5211_EEPROM_CMD, 2533 AR5K_AR5211_EEPROM_CMD_RESET); 2534 AR5K_REG_ENABLE_BITS(AR5K_AR5211_EEPROM_CMD, 2535 AR5K_AR5211_EEPROM_CMD_WRITE); 2536 2537 /* 2538 * Prime write pump 2539 */ 2540 AR5K_REG_WRITE(AR5K_AR5211_EEPROM_BASE, (u_int8_t)offset - 1); 2541 2542 for (timeout = 10000; timeout > 0; timeout--) { 2543 AR5K_DELAY(1); 2544 status = AR5K_REG_READ(AR5K_AR5211_EEPROM_STATUS); 2545 if (status & AR5K_AR5211_EEPROM_STAT_WRDONE) { 2546 if (status & AR5K_AR5211_EEPROM_STAT_WRERR) 2547 return (EIO); 2548 return (0); 2549 } 2550 } 2551 2552 return (ETIMEDOUT); 2553 } 2554 2555 /* 2556 * RF register settings 2557 */ 2558 2559 void 2560 ar5k_ar5211_rfregs(struct ath_hal *hal, HAL_CHANNEL *channel, u_int freq, 2561 u_int ee_mode) 2562 { 2563 struct ar5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; 2564 struct ar5k_ar5211_ini_rf rf[AR5K_ELEMENTS(ar5211_rf)]; 2565 u_int32_t ob, db, obdb, xpds, xpdp, x_gain; 2566 u_int i; 2567 2568 bcopy(ar5211_rf, rf, sizeof(rf)); 2569 obdb = 0; 2570 2571 if (freq == AR5K_INI_RFGAIN_2GHZ && 2572 hal->ah_ee_version >= AR5K_EEPROM_VERSION_3_1) { 2573 ob = ar5k_bitswap(ee->ee_ob[ee_mode][0], 3); 2574 db = ar5k_bitswap(ee->ee_db[ee_mode][0], 3); 2575 rf[25].rf_value[freq] = 2576 ((ob << 6) & 0xc0) | (rf[25].rf_value[freq] & ~0xc0); 2577 rf[26].rf_value[freq] = 2578 (((ob >> 2) & 0x1) | ((db << 1) & 0xe)) | 2579 (rf[26].rf_value[freq] & ~0xf); 2580 } 2581 2582 if (freq == AR5K_INI_RFGAIN_5GHZ) { 2583 /* For 11a and Turbo */ 2584 obdb = channel->c_channel >= 5725 ? 3 : 2585 (channel->c_channel >= 5500 ? 2 : 2586 (channel->c_channel >= 5260 ? 1 : 2587 (channel->c_channel > 4000 ? 0 : -1))); 2588 } 2589 2590 ob = ee->ee_ob[ee_mode][obdb]; 2591 db = ee->ee_db[ee_mode][obdb]; 2592 x_gain = ee->ee_x_gain[ee_mode]; 2593 xpds = ee->ee_xpd[ee_mode]; 2594 xpdp = !xpds; 2595 2596 rf[11].rf_value[freq] = (rf[11].rf_value[freq] & ~0xc0) | 2597 (((ar5k_bitswap(x_gain, 4) << 7) | (xpdp << 6)) & 0xc0); 2598 rf[12].rf_value[freq] = (rf[12].rf_value[freq] & ~0x7) | 2599 ((ar5k_bitswap(x_gain, 4) >> 1) & 0x7); 2600 rf[12].rf_value[freq] = (rf[12].rf_value[freq] & ~0x80) | 2601 ((ar5k_bitswap(ob, 3) << 7) & 0x80); 2602 rf[13].rf_value[freq] = (rf[13].rf_value[freq] & ~0x3) | 2603 ((ar5k_bitswap(ob, 3) >> 1) & 0x3); 2604 rf[13].rf_value[freq] = (rf[13].rf_value[freq] & ~0x1c) | 2605 ((ar5k_bitswap(db, 3) << 2) & 0x1c); 2606 rf[17].rf_value[freq] = (rf[17].rf_value[freq] & ~0x8) | 2607 ((xpds << 3) & 0x8); 2608 2609 for (i = 0; i < AR5K_ELEMENTS(rf); i++) { 2610 AR5K_REG_WAIT(i); 2611 AR5K_REG_WRITE((u_int32_t)rf[i].rf_register, 2612 rf[i].rf_value[freq]); 2613 } 2614 2615 hal->ah_rf_gain = HAL_RFGAIN_INACTIVE; 2616 } 2617 2618 HAL_BOOL 2619 ar5k_ar5211_set_txpower_limit(struct ath_hal *hal, u_int power) 2620 { 2621 /* Not implemented */ 2622 return (AH_FALSE); 2623 } 2624