1 /* $OpenBSD: anxdp.c,v 1.1 2020/02/21 15:49:09 patrick Exp $ */ 2 /* $NetBSD: anx_dp.c,v 1.2 2020/01/04 12:08:32 jmcneill Exp $ */ 3 /*- 4 * Copyright (c) 2019 Jonathan A. Kollasch <jakllsch@kollasch.net> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/param.h> 30 #include <sys/device.h> 31 #include <sys/systm.h> 32 33 #include <machine/bus.h> 34 35 #include <dev/ic/anxdp.h> 36 37 #include <drm/drmP.h> 38 #include <drm/drm_crtc.h> 39 #include <drm/drm_crtc_helper.h> 40 #include <drm/drm_dp_helper.h> 41 #include <drm/drm_edid.h> 42 43 #define ANXDP_DP_TX_VERSION 0x010 44 #define ANXDP_TX_SW_RESET 0x014 45 #define RESET_DP_TX (1 << 0) 46 #define ANXDP_FUNC_EN_1 0x018 47 #define MASTER_VID_FUNC_EN_N (1 << 7) 48 #define RK_VID_CAP_FUNC_EN_N (1 << 6) 49 #define SLAVE_VID_FUNC_EN_N (1 << 5) 50 #define RK_VID_FIFO_FUNC_EN_N (1 << 5) 51 #define AUD_FIFO_FUNC_EN_N (1 << 4) 52 #define AUD_FUNC_EN_N (1 << 3) 53 #define HDCP_FUNC_EN_N (1 << 2) 54 #define CRC_FUNC_EN_N (1 << 1) 55 #define SW_FUNC_EN_N (1 << 0) 56 #define ANXDP_FUNC_EN_2 0x01c 57 #define SSC_FUNC_EN_N (1 << 7) 58 #define AUX_FUNC_EN_N (1 << 2) 59 #define SERDES_FIFO_FUNC_EN_N (1 << 1) 60 #define LS_CLK_DOMAIN_FUNC_EN_N (1 << 0) 61 #define ANXDP_VIDEO_CTL_1 0x020 62 #define VIDEO_EN (1 << 7) 63 #define VIDEO_MUTE (1 << 6) 64 #define ANXDP_VIDEO_CTL_2 0x024 65 #define ANXDP_VIDEO_CTL_3 0x028 66 #define ANXDP_VIDEO_CTL_4 0x02c 67 #define ANXDP_VIDEO_CTL_8 0x03c 68 #define ANXDP_VIDEO_CTL_10 0x044 69 #define F_SEL (1 << 4) 70 #define SLAVE_I_SCAN_CFG (1 << 2) 71 #define SLAVE_VSYNC_P_CFG (1 << 1) 72 #define SLAVE_HSYNC_P_CFG (1 << 0) 73 #define ANXDP_PLL_REG_1 0x0fc 74 #define REF_CLK_24M (1 << 0) 75 #define RKANXDP_PD 0x12c 76 #define DP_INC_BG (1 << 7) 77 #define DP_EXP_PD (1 << 6) 78 #define DP_PHY_PD (1 << 5) 79 #define RK_AUX_PD (1 << 5) 80 #define AUX_PD (1 << 4) 81 #define RK_PLL_PD (1 << 4) 82 #define CHx_PD(x) (1 << x) /* 0<=x<=3 */ 83 #define DP_ALL_PD 0xff 84 #define ANXDP_LANE_MAP 0x35c 85 #define ANXDP_ANALOG_CTL_1 0x370 86 #define TX_TERMINAL_CTRL_50_OHM (1 << 4) 87 #define ANXDP_ANALOG_CTL_2 0x374 88 #define SEL_24M (1 << 3) 89 #define TX_DVDD_BIT_1_0625V 0x4 90 #define ANXDP_ANALOG_CTL_3 0x378 91 #define DRIVE_DVDD_BIT_1_0625V (0x4 << 5) 92 #define VCO_BIT_600_MICRO (0x5 << 0) 93 #define ANXDP_PLL_FILTER_CTL_1 0x37c 94 #define PD_RING_OSC (1 << 6) 95 #define AUX_TERMINAL_CTRL_50_OHM (2 << 4) 96 #define TX_CUR1_2X (1 << 2) 97 #define TX_CUR_16_MA 3 98 #define ANXDP_TX_AMP_TUNING_CTL 0x380 99 #define ANXDP_AUX_HW_RETRY_CTL 0x390 100 #define AUX_BIT_PERIOD_EXPECTED_DELAY(x) ((x) << 8) 101 #define AUX_HW_RETRY_INTERVAL_600_US (0 << 3) 102 #define AUX_HW_RETRY_INTERVAL_800_US (1 << 3) 103 #define AUX_HW_RETRY_INTERVAL_1000_US (2 << 3) 104 #define AUX_HW_RETRY_INTERVAL_1800_US (3 << 3) 105 #define AUX_HW_RETRY_COUNT_SEL(x) ((x) << 0) 106 #define ANXDP_COMMON_INT_STA_1 0x3c4 107 #define PLL_LOCK_CHG (1 << 6) 108 #define ANXDP_COMMON_INT_STA_2 0x3c8 109 #define ANXDP_COMMON_INT_STA_3 0x3cc 110 #define ANXDP_COMMON_INT_STA_4 0x3d0 111 #define ANXDP_DP_INT_STA 0x3dc 112 #define INT_HPD (1 << 6) 113 #define HW_TRAINING_FINISH (1 << 5) 114 #define RPLY_RECEIV (1 << 1) 115 #define AUX_ERR (1 << 0) 116 #define ANXDP_SYS_CTL_1 0x600 117 #define DET_STA (1 << 2) 118 #define FORCE_DET (1 << 1) 119 #define DET_CTRL (1 << 0) 120 #define ANXDP_SYS_CTL_2 0x604 121 #define ANXDP_SYS_CTL_3 0x608 122 #define HPD_STATUS (1 << 6) 123 #define F_HPD (1 << 5) 124 #define HPD_CTRL (1 << 4) 125 #define HDCP_RDY (1 << 3) 126 #define STRM_VALID (1 << 2) 127 #define F_VALID (1 << 1) 128 #define VALID_CTRL (1 << 0) 129 #define ANXDP_SYS_CTL_4 0x60c 130 #define ANXDP_PKT_SEND_CTL 0x640 131 #define ANXDP_HDCP_CTL 0x648 132 #define ANXDP_LINK_BW_SET 0x680 133 #define ANXDP_LANE_COUNT_SET 0x684 134 #define ANXDP_TRAINING_PTN_SET 0x688 135 #define SCRAMBLING_DISABLE (1 << 5) 136 #define SW_TRAINING_PATTERN_SET_PTN2 (2 << 0) 137 #define SW_TRAINING_PATTERN_SET_PTN1 (1 << 0) 138 #define ANXDP_LNx_LINK_TRAINING_CTL(x) (0x68c + 4 * (x)) /* 0 <= x <= 3 */ 139 #define MAX_PRE_REACH (1 << 5) 140 #define PRE_EMPHASIS_SET(x) ((x) << 3) 141 #define MAX_DRIVE_REACH (1 << 2) 142 #define DRIVE_CURRENT_SET(x) ((x) << 0) 143 #define ANXDP_DEBUG_CTL 0x6c0 144 #define PLL_LOCK (1 << 4) 145 #define F_PLL_LOCK (1 << 3) 146 #define PLL_LOCK_CTRL (1 << 2) 147 #define PN_INV (1 << 0) 148 #define ANXDP_LINK_DEBUG_CTL 0x6e0 149 #define ANXDP_PLL_CTL 0x71c 150 #define ANXDP_PHY_PD 0x720 151 #define ANXDP_PHY_TEST 0x724 152 #define MACRO_RST (1 << 5) 153 #define ANXDP_M_AUD_GEN_FILTER_TH 0x778 154 #define ANXDP_AUX_CH_STA 0x780 155 #define AUX_BUSY (1 << 4) 156 #define AUX_STATUS(x) (((x) >> 0) & 0xf) 157 #define ANXDP_AUX_ERR_NUM 0x784 158 #define ANXDP_AUX_CH_DEFER_CTL 0x788 159 #define DEFER_CTRL_EN (1 << 7) 160 #define DEFER_COUNT(x) ((x) << 0) 161 #define ANXDP_AUX_RX_COMM 0x78c 162 #define AUX_RX_COMM_I2C_DEFER (1 << 3) 163 #define AUX_RX_COMM_AUX_DEFER (1 << 1) 164 #define ANXDP_BUFFER_DATA_CTL 0x790 165 #define BUF_CLR (1 << 7) 166 #define BUF_DATA_COUNT(x) ((x) << 0) 167 #define ANXDP_AUX_CH_CTL_1 0x794 168 #define AUX_LENGTH(x) (((x) - 1) << 4) 169 #define AUX_TX_COMM(x) (((x) >> 0) & 0xf) 170 #define AUX_TX_COMM_DP (1 << 3) 171 #define AUX_TX_COMM_MOT (1 << 2) 172 #define AUX_TX_COMM_READ (1 << 0) 173 #define ANXDP_AUX_ADDR_7_0 0x798 174 #define AUX_ADDR_7_0(x) (((x) >> 0) & 0xff) 175 #define ANXDP_AUX_ADDR_15_8 0x79c 176 #define AUX_ADDR_15_8(x) (((x) >> 8) & 0xff) 177 #define ANXDP_AUX_ADDR_19_16 0x7a0 178 #define AUX_ADDR_19_16(x) (((x) >> 16) & 0xf) 179 #define ANXDP_AUX_CH_CTL_2 0x7a4 180 #define ADDR_ONLY (1 << 1) 181 #define AUX_EN (1 << 0) 182 #define ANXDP_BUF_DATA(x) (0x7c0 + 4 * (x)) 183 #define ANXDP_SOC_GENERAL_CTL 0x800 184 #define AUDIO_MODE_SPDIF_MODE (1 << 8) 185 #define VIDEO_MODE_SLAVE_MODE (1 << 1) 186 #define ANXDP_CRC_CON 0x890 187 #define ANXDP_PLL_REG_2 0x9e4 188 #define ANXDP_PLL_REG_3 0x9e8 189 #define ANXDP_PLL_REG_4 0x9ec 190 #define ANXDP_PLL_REG_5 0xa00 191 192 static inline const bool 193 isrockchip(struct anxdp_softc *sc) 194 { 195 return (sc->sc_flags & ANXDP_FLAG_ROCKCHIP) != 0; 196 } 197 198 enum drm_connector_status 199 anxdp_connector_detect(struct drm_connector *connector, bool force) 200 { 201 #if 0 202 struct anxdp_connector *anxdp_connector = to_anxdp_connector(connector); 203 struct anxdp_softc *sc = anxdp_connector->sc; 204 205 /* XXX HPD */ 206 #endif 207 return connector_status_connected; 208 } 209 210 void 211 anxdp_connector_destroy(struct drm_connector *connector) 212 { 213 drm_connector_unregister(connector); 214 drm_connector_cleanup(connector); 215 } 216 217 struct drm_connector_funcs anxdp_connector_funcs = { 218 .dpms = drm_helper_connector_dpms, 219 .detect = anxdp_connector_detect, 220 .fill_modes = drm_helper_probe_single_connector_modes, 221 .destroy = anxdp_connector_destroy, 222 }; 223 224 void 225 anxdp_analog_power_up_all(struct anxdp_softc *sc) 226 { 227 const bus_size_t pd_reg = isrockchip(sc) ? RKANXDP_PD : ANXDP_PHY_PD; 228 229 bus_space_write_4(sc->sc_iot, sc->sc_ioh, pd_reg, DP_ALL_PD); 230 delay(15); 231 bus_space_write_4(sc->sc_iot, sc->sc_ioh, pd_reg, 232 DP_ALL_PD & ~DP_INC_BG); 233 delay(15); 234 bus_space_write_4(sc->sc_iot, sc->sc_ioh, pd_reg, 0); 235 } 236 237 int 238 anxdp_await_pll_lock(struct anxdp_softc *sc) 239 { 240 u_int timeout; 241 242 for (timeout = 0; timeout < 100; timeout++) { 243 if ((bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_DEBUG_CTL) & 244 PLL_LOCK) != 0) 245 return 0; 246 delay(20); 247 } 248 249 return ETIMEDOUT; 250 } 251 252 void 253 anxdp_init_hpd(struct anxdp_softc *sc) 254 { 255 uint32_t sc3; 256 257 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_COMMON_INT_STA_4, 0x7); 258 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_DP_INT_STA, INT_HPD); 259 260 sc3 = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_SYS_CTL_3); 261 sc3 &= ~(F_HPD | HPD_CTRL); 262 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_SYS_CTL_3, sc3); 263 264 sc3 = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_SYS_CTL_3); 265 sc3 |= F_HPD | HPD_CTRL; 266 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_SYS_CTL_3, sc3); 267 } 268 269 void 270 anxdp_init_aux(struct anxdp_softc *sc) 271 { 272 uint32_t fe2, pd, hrc; 273 const bus_size_t pd_reg = isrockchip(sc) ? RKANXDP_PD : ANXDP_PHY_PD; 274 const uint32_t pd_mask = isrockchip(sc) ? RK_AUX_PD : AUX_PD; 275 276 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_DP_INT_STA, 277 RPLY_RECEIV | AUX_ERR); 278 279 pd = bus_space_read_4(sc->sc_iot, sc->sc_ioh, pd_reg); 280 pd |= pd_mask; 281 bus_space_write_4(sc->sc_iot, sc->sc_ioh, pd_reg, pd); 282 283 delay(11); 284 285 pd = bus_space_read_4(sc->sc_iot, sc->sc_ioh, pd_reg); 286 pd &= ~pd_mask; 287 bus_space_write_4(sc->sc_iot, sc->sc_ioh, pd_reg, pd); 288 289 fe2 = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_FUNC_EN_2); 290 fe2 |= AUX_FUNC_EN_N; 291 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_FUNC_EN_2, fe2); 292 293 hrc = AUX_HW_RETRY_COUNT_SEL(0) | AUX_HW_RETRY_INTERVAL_600_US; 294 if (!isrockchip(sc)) 295 hrc |= AUX_BIT_PERIOD_EXPECTED_DELAY(3); 296 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_AUX_HW_RETRY_CTL, hrc); 297 298 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_AUX_CH_DEFER_CTL, 299 DEFER_CTRL_EN | DEFER_COUNT(1)); 300 301 fe2 = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_FUNC_EN_2); 302 fe2 &= ~AUX_FUNC_EN_N; 303 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_FUNC_EN_2, fe2); 304 } 305 306 int 307 anxdp_connector_get_modes(struct drm_connector *connector) 308 { 309 struct anxdp_connector *anxdp_connector = to_anxdp_connector(connector); 310 struct anxdp_softc *sc = anxdp_connector->sc; 311 struct edid *pedid = NULL; 312 int error; 313 314 pedid = drm_get_edid(connector, &sc->sc_dpaux.ddc); 315 316 drm_connector_update_edid_property(connector, pedid); 317 if (pedid == NULL) 318 return 0; 319 320 error = drm_add_edid_modes(connector, pedid); 321 322 if (pedid != NULL) 323 kfree(pedid); 324 325 return error; 326 } 327 328 struct drm_encoder * 329 anxdp_connector_best_encoder(struct drm_connector *connector) 330 { 331 int enc_id = connector->encoder_ids[0]; 332 struct drm_mode_object *obj; 333 struct drm_encoder *encoder = NULL; 334 335 if (enc_id) { 336 obj = drm_mode_object_find(connector->dev, NULL, enc_id, 337 DRM_MODE_OBJECT_ENCODER); 338 if (obj == NULL) 339 return NULL; 340 encoder = obj_to_encoder(obj); 341 } 342 343 return encoder; 344 } 345 346 struct drm_connector_helper_funcs anxdp_connector_helper_funcs = { 347 .get_modes = anxdp_connector_get_modes, 348 .best_encoder = anxdp_connector_best_encoder, 349 }; 350 351 int 352 anxdp_bridge_attach(struct drm_bridge *bridge) 353 { 354 struct anxdp_softc *sc = bridge->driver_private; 355 struct anxdp_connector *anxdp_connector = &sc->sc_connector; 356 struct drm_connector *connector = &anxdp_connector->base; 357 int error; 358 359 anxdp_connector->sc = sc; 360 361 connector->polled = 362 DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT; 363 connector->interlace_allowed = 0; 364 connector->doublescan_allowed = 0; 365 366 drm_connector_init(bridge->dev, connector, &anxdp_connector_funcs, 367 connector->connector_type); 368 drm_connector_helper_add(connector, &anxdp_connector_helper_funcs); 369 370 error = drm_connector_attach_encoder(connector, bridge->encoder); 371 if (error != 0) 372 return error; 373 374 return drm_connector_register(connector); 375 } 376 377 void 378 anxdp_macro_reset(struct anxdp_softc *sc) 379 { 380 uint32_t val; 381 382 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_PHY_TEST); 383 val |= MACRO_RST; 384 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_PHY_TEST, val); 385 delay(10); 386 val &= ~MACRO_RST; 387 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_PHY_TEST, val); 388 } 389 390 void 391 anxdp_link_start(struct anxdp_softc *sc, struct drm_dp_link * const link) 392 { 393 uint8_t training[4]; 394 uint32_t val; 395 396 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_LINK_BW_SET, 397 drm_dp_link_rate_to_bw_code(link->rate)); 398 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_LANE_COUNT_SET, 399 link->num_lanes); 400 if (0 != drm_dp_link_configure(&sc->sc_dpaux, link)) 401 return; 402 403 for (u_int i = 0; i < link->num_lanes; i++) { 404 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 405 ANXDP_LNx_LINK_TRAINING_CTL(i)); 406 val &= ~(PRE_EMPHASIS_SET(3)|DRIVE_CURRENT_SET(3)); 407 val |= PRE_EMPHASIS_SET(0); 408 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 409 ANXDP_LNx_LINK_TRAINING_CTL(i), val); 410 } 411 412 if (anxdp_await_pll_lock(sc) != 0) { 413 printf("%s: PLL lock timeout\n", sc->sc_dev.dv_xname); 414 } 415 416 for (u_int i = 0; i < link->num_lanes; i++) { 417 training[i] = DP_TRAIN_PRE_EMPH_LEVEL_0 | 418 DP_TRAIN_VOLTAGE_SWING_LEVEL_0; 419 } 420 421 drm_dp_dpcd_write(&sc->sc_dpaux, DP_TRAINING_LANE0_SET, training, 422 link->num_lanes); 423 } 424 425 void 426 anxdp_process_clock_recovery(struct anxdp_softc *sc, 427 struct drm_dp_link * const link) 428 { 429 u_int i, tries; 430 uint8_t link_status[DP_LINK_STATUS_SIZE]; 431 uint8_t training[4]; 432 433 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_TRAINING_PTN_SET, 434 SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1); 435 drm_dp_dpcd_writeb(&sc->sc_dpaux, DP_TRAINING_PATTERN_SET, 436 DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_1); 437 438 tries = 0; 439 again: 440 if (tries++ >= 10) { 441 printf("%s: cr fail\n", sc->sc_dev.dv_xname); 442 return; 443 } 444 drm_dp_link_train_clock_recovery_delay(sc->sc_dpcd); 445 if (DP_LINK_STATUS_SIZE != 446 drm_dp_dpcd_read_link_status(&sc->sc_dpaux, link_status)) { 447 return; 448 } 449 if (!drm_dp_clock_recovery_ok(link_status, link->num_lanes)) { 450 goto cr_fail; 451 } 452 453 return; 454 455 cr_fail: 456 for (i = 0; i < link->num_lanes; i++) { 457 uint8_t vs, pe; 458 vs = drm_dp_get_adjust_request_voltage(link_status, i); 459 pe = drm_dp_get_adjust_request_pre_emphasis(link_status, i); 460 training[i] = vs | pe; 461 } 462 for (i = 0; i < link->num_lanes; i++) { 463 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 464 ANXDP_LNx_LINK_TRAINING_CTL(i), training[i]); 465 } 466 drm_dp_dpcd_write(&sc->sc_dpaux, DP_TRAINING_LANE0_SET, training, 467 link->num_lanes); 468 goto again; 469 } 470 471 void 472 anxdp_process_eq(struct anxdp_softc *sc, struct drm_dp_link * const link) 473 { 474 u_int i, tries; 475 uint8_t link_status[DP_LINK_STATUS_SIZE]; 476 uint8_t training[4]; 477 478 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_TRAINING_PTN_SET, 479 SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2); 480 drm_dp_dpcd_writeb(&sc->sc_dpaux, DP_TRAINING_PATTERN_SET, 481 DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_2); 482 483 tries = 0; 484 again: 485 if (tries++ >= 10) { 486 printf("%s: eq fail\n", sc->sc_dev.dv_xname); 487 return; 488 } 489 drm_dp_link_train_channel_eq_delay(sc->sc_dpcd); 490 if (DP_LINK_STATUS_SIZE != 491 drm_dp_dpcd_read_link_status(&sc->sc_dpaux, link_status)) { 492 return; 493 } 494 if (!drm_dp_channel_eq_ok(link_status, link->num_lanes)) { 495 goto eq_fail; 496 } 497 498 return; 499 500 eq_fail: 501 for (i = 0; i < link->num_lanes; i++) { 502 uint8_t vs, pe; 503 vs = drm_dp_get_adjust_request_voltage(link_status, i); 504 pe = drm_dp_get_adjust_request_pre_emphasis(link_status, i); 505 training[i] = vs | pe; 506 } 507 for (i = 0; i < link->num_lanes; i++) { 508 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 509 ANXDP_LNx_LINK_TRAINING_CTL(i), training[i]); 510 } 511 drm_dp_dpcd_write(&sc->sc_dpaux, DP_TRAINING_LANE0_SET, training, 512 link->num_lanes); 513 goto again; 514 } 515 516 void 517 anxdp_train_link(struct anxdp_softc *sc) 518 { 519 struct drm_dp_link link; 520 521 anxdp_macro_reset(sc); 522 523 if (0 != drm_dp_link_probe(&sc->sc_dpaux, &link)) { 524 printf("%s: link probe failed\n", sc->sc_dev.dv_xname); 525 return; 526 } 527 if (0 != drm_dp_link_power_up(&sc->sc_dpaux, &link)) 528 return; 529 if (DP_RECEIVER_CAP_SIZE != drm_dp_dpcd_read(&sc->sc_dpaux, DP_DPCD_REV, 530 sc->sc_dpcd, DP_RECEIVER_CAP_SIZE)) 531 return; 532 533 anxdp_link_start(sc, &link); 534 anxdp_process_clock_recovery(sc, &link); 535 anxdp_process_eq(sc, &link); 536 537 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_TRAINING_PTN_SET, 0); 538 drm_dp_dpcd_writeb(&sc->sc_dpaux, DP_TRAINING_PATTERN_SET, 539 DP_TRAINING_PATTERN_DISABLE); 540 541 } 542 543 void 544 anxdp_bringup(struct anxdp_softc *sc) 545 { 546 uint32_t val; 547 548 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_VIDEO_CTL_1); 549 val &= ~VIDEO_EN; 550 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_VIDEO_CTL_1, val); 551 552 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_VIDEO_CTL_1); 553 val &= ~VIDEO_MUTE; 554 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_VIDEO_CTL_1, val); 555 556 val = SW_FUNC_EN_N; 557 if (isrockchip(sc)) { 558 val |= RK_VID_CAP_FUNC_EN_N | RK_VID_FIFO_FUNC_EN_N; 559 } else { 560 val |= MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N | 561 AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N | HDCP_FUNC_EN_N; 562 } 563 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_FUNC_EN_1, val); 564 565 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_FUNC_EN_2, 566 SSC_FUNC_EN_N | AUX_FUNC_EN_N | SERDES_FIFO_FUNC_EN_N | 567 LS_CLK_DOMAIN_FUNC_EN_N); 568 569 delay(30); 570 571 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_M_AUD_GEN_FILTER_TH, 2); 572 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_SOC_GENERAL_CTL, 0x101); 573 574 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_TX_SW_RESET, 575 RESET_DP_TX); 576 577 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_ANALOG_CTL_1, 578 TX_TERMINAL_CTRL_50_OHM); 579 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_ANALOG_CTL_2, 580 SEL_24M | TX_DVDD_BIT_1_0625V); 581 if (isrockchip(sc)) { 582 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_PLL_REG_1, 583 REF_CLK_24M); 584 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_PLL_REG_2, 585 0x95); 586 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_PLL_REG_3, 587 0x40); 588 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_PLL_REG_4, 589 0x58); 590 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_PLL_REG_5, 591 0x22); 592 } 593 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_ANALOG_CTL_3, 594 DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO); 595 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_PLL_FILTER_CTL_1, 596 PD_RING_OSC | AUX_TERMINAL_CTRL_50_OHM | TX_CUR1_2X | TX_CUR_16_MA); 597 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_TX_AMP_TUNING_CTL, 0); 598 599 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_FUNC_EN_1); 600 val &= ~SW_FUNC_EN_N; 601 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_FUNC_EN_1, val); 602 603 anxdp_analog_power_up_all(sc); 604 605 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_COMMON_INT_STA_1, 606 PLL_LOCK_CHG); 607 608 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_DEBUG_CTL); 609 val &= ~(F_PLL_LOCK | PLL_LOCK_CTRL); 610 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_DEBUG_CTL, val); 611 612 if (anxdp_await_pll_lock(sc) != 0) { 613 printf("%s: PLL lock timeout\n", sc->sc_dev.dv_xname); 614 } 615 616 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_FUNC_EN_2); 617 val &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N | 618 AUX_FUNC_EN_N); 619 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_FUNC_EN_2, val); 620 621 anxdp_init_hpd(sc); 622 anxdp_init_aux(sc); 623 } 624 625 void 626 anxdp_bridge_enable(struct drm_bridge *bridge) 627 { 628 struct anxdp_softc *sc = bridge->driver_private; 629 uint32_t val; 630 631 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_FUNC_EN_1); 632 if (isrockchip(sc)) { 633 val &= ~(RK_VID_CAP_FUNC_EN_N | RK_VID_FIFO_FUNC_EN_N); 634 } else { 635 val &= ~(MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N); 636 val |= MASTER_VID_FUNC_EN_N; 637 } 638 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_FUNC_EN_1, val); 639 640 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_VIDEO_CTL_10); 641 val &= ~(SLAVE_I_SCAN_CFG|SLAVE_VSYNC_P_CFG|SLAVE_HSYNC_P_CFG); 642 if ((sc->sc_curmode.flags & DRM_MODE_FLAG_INTERLACE) != 0) 643 val |= SLAVE_I_SCAN_CFG; 644 if ((sc->sc_curmode.flags & DRM_MODE_FLAG_NVSYNC) != 0) 645 val |= SLAVE_VSYNC_P_CFG; 646 if ((sc->sc_curmode.flags & DRM_MODE_FLAG_NHSYNC) != 0) 647 val |= SLAVE_HSYNC_P_CFG; 648 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_VIDEO_CTL_10, val); 649 650 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_SOC_GENERAL_CTL, 651 AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE); 652 653 anxdp_train_link(sc); 654 655 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_VIDEO_CTL_1); 656 val |= VIDEO_EN; 657 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_VIDEO_CTL_1, val); 658 659 if (sc->sc_panel != NULL && 660 sc->sc_panel->funcs != NULL && 661 sc->sc_panel->funcs->enable != NULL) 662 sc->sc_panel->funcs->enable(sc->sc_panel); 663 } 664 665 void 666 anxdp_bridge_pre_enable(struct drm_bridge *bridge) 667 { 668 } 669 670 void 671 anxdp_bridge_disable(struct drm_bridge *bridge) 672 { 673 } 674 675 void 676 anxdp_bridge_post_disable(struct drm_bridge *bridge) 677 { 678 } 679 680 void 681 anxdp_bridge_mode_set(struct drm_bridge *bridge, 682 struct drm_display_mode *mode, 683 struct drm_display_mode *adjusted_mode) 684 { 685 struct anxdp_softc *sc = bridge->driver_private; 686 687 sc->sc_curmode = *adjusted_mode; 688 } 689 690 bool 691 anxdp_bridge_mode_fixup(struct drm_bridge *bridge, 692 const struct drm_display_mode *mode, 693 struct drm_display_mode *adjusted_mode) 694 { 695 return true; 696 } 697 698 const struct drm_bridge_funcs anxdp_bridge_funcs = { 699 .attach = anxdp_bridge_attach, 700 .enable = anxdp_bridge_enable, 701 .pre_enable = anxdp_bridge_pre_enable, 702 .disable = anxdp_bridge_disable, 703 .post_disable = anxdp_bridge_post_disable, 704 .mode_set = anxdp_bridge_mode_set, 705 .mode_fixup = anxdp_bridge_mode_fixup, 706 }; 707 708 ssize_t 709 anxdp_dp_aux_transfer(struct drm_dp_aux *dpaux, struct drm_dp_aux_msg *dpmsg) 710 { 711 struct anxdp_softc *sc = container_of(dpaux, struct anxdp_softc, 712 sc_dpaux); 713 size_t loop_timeout = 0; 714 uint32_t val; 715 size_t i; 716 ssize_t ret = 0; 717 718 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_BUFFER_DATA_CTL, 719 BUF_CLR); 720 721 val = AUX_LENGTH(dpmsg->size); 722 if ((dpmsg->request & DP_AUX_I2C_MOT) != 0) 723 val |= AUX_TX_COMM_MOT; 724 725 switch (dpmsg->request & ~DP_AUX_I2C_MOT) { 726 case DP_AUX_I2C_WRITE: 727 break; 728 case DP_AUX_I2C_READ: 729 val |= AUX_TX_COMM_READ; 730 break; 731 case DP_AUX_NATIVE_WRITE: 732 val |= AUX_TX_COMM_DP; 733 break; 734 case DP_AUX_NATIVE_READ: 735 val |= AUX_TX_COMM_READ | AUX_TX_COMM_DP; 736 break; 737 } 738 739 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_AUX_CH_CTL_1, val); 740 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_AUX_ADDR_7_0, 741 AUX_ADDR_7_0(dpmsg->address)); 742 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_AUX_ADDR_15_8, 743 AUX_ADDR_15_8(dpmsg->address)); 744 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_AUX_ADDR_19_16, 745 AUX_ADDR_19_16(dpmsg->address)); 746 747 if (!(dpmsg->request & DP_AUX_I2C_READ)) { 748 for (i = 0; i < dpmsg->size; i++) { 749 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 750 ANXDP_BUF_DATA(i), 751 ((const uint8_t *)(dpmsg->buffer))[i]); 752 ret++; 753 } 754 } 755 756 757 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_AUX_CH_CTL_2, 758 AUX_EN | ((dpmsg->size == 0) ? ADDR_ONLY : 0)); 759 760 loop_timeout = 0; 761 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_AUX_CH_CTL_2); 762 while ((val & AUX_EN) != 0) { 763 if (++loop_timeout > 20000) { 764 ret = -ETIMEDOUT; 765 goto out; 766 } 767 delay(25); 768 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 769 ANXDP_AUX_CH_CTL_2); 770 } 771 772 loop_timeout = 0; 773 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_DP_INT_STA); 774 while (!(val & RPLY_RECEIV)) { 775 if (++loop_timeout > 2000) { 776 ret = -ETIMEDOUT; 777 goto out; 778 } 779 delay(10); 780 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 781 ANXDP_DP_INT_STA); 782 } 783 784 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_DP_INT_STA, 785 RPLY_RECEIV); 786 787 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_DP_INT_STA); 788 if ((val & AUX_ERR) != 0) { 789 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_DP_INT_STA, 790 AUX_ERR); 791 ret = -EREMOTEIO; 792 goto out; 793 } 794 795 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_AUX_CH_STA); 796 if (AUX_STATUS(val) != 0) { 797 ret = -EREMOTEIO; 798 goto out; 799 } 800 801 if ((dpmsg->request & DP_AUX_I2C_READ)) { 802 for (i = 0; i < dpmsg->size; i++) { 803 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 804 ANXDP_BUF_DATA(i)); 805 ((uint8_t *)(dpmsg->buffer))[i] = val & 0xffU; 806 ret++; 807 } 808 } 809 810 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_AUX_RX_COMM); 811 if (val == AUX_RX_COMM_AUX_DEFER) 812 dpmsg->reply = DP_AUX_NATIVE_REPLY_DEFER; 813 else if (val == AUX_RX_COMM_I2C_DEFER) 814 dpmsg->reply = DP_AUX_I2C_REPLY_DEFER; 815 else if ((dpmsg->request & ~DP_AUX_I2C_MOT) == DP_AUX_I2C_WRITE || 816 (dpmsg->request & ~DP_AUX_I2C_MOT) == DP_AUX_I2C_READ) 817 dpmsg->reply = DP_AUX_I2C_REPLY_ACK; 818 else if ((dpmsg->request & ~DP_AUX_I2C_MOT) == DP_AUX_NATIVE_WRITE || 819 (dpmsg->request & ~DP_AUX_I2C_MOT) == DP_AUX_NATIVE_READ) 820 dpmsg->reply = DP_AUX_NATIVE_REPLY_ACK; 821 822 out: 823 if (ret < 0) 824 anxdp_init_aux(sc); 825 826 return ret; 827 } 828 829 void 830 anxdp_dpms(struct anxdp_softc *sc, int mode) 831 { 832 switch (mode) { 833 case DRM_MODE_DPMS_ON: 834 #ifdef notyet 835 pmf_event_inject(NULL, PMFE_DISPLAY_ON); 836 #endif 837 break; 838 case DRM_MODE_DPMS_STANDBY: 839 case DRM_MODE_DPMS_SUSPEND: 840 case DRM_MODE_DPMS_OFF: 841 #ifdef notyet 842 pmf_event_inject(NULL, PMFE_DISPLAY_OFF); 843 #endif 844 break; 845 } 846 } 847 848 int 849 anxdp_attach(struct anxdp_softc *sc) 850 { 851 sc->sc_dpaux.name = "DP Aux"; 852 sc->sc_dpaux.transfer = anxdp_dp_aux_transfer; 853 sc->sc_dpaux.dev = &sc->sc_dev; 854 if (drm_dp_aux_register(&sc->sc_dpaux) != 0) { 855 printf("%s: registering DP Aux failed\n", sc->sc_dev.dv_xname); 856 } 857 858 anxdp_bringup(sc); 859 860 return 0; 861 } 862 863 int 864 anxdp_bind(struct anxdp_softc *sc, struct drm_encoder *encoder) 865 { 866 int error; 867 868 sc->sc_bridge.driver_private = sc; 869 sc->sc_bridge.funcs = &anxdp_bridge_funcs; 870 sc->sc_bridge.encoder = encoder; 871 872 error = drm_bridge_attach(encoder, &sc->sc_bridge, NULL); 873 if (error != 0) 874 return EIO; 875 876 encoder->bridge = &sc->sc_bridge; 877 878 if (sc->sc_panel != NULL && sc->sc_panel->funcs != NULL && 879 sc->sc_panel->funcs->prepare != NULL) 880 sc->sc_panel->funcs->prepare(sc->sc_panel); 881 882 return 0; 883 } 884