1 /* $OpenBSD: anxdp.c,v 1.4 2020/06/08 04:47:58 jsg Exp $ */ 2 /* $NetBSD: anx_dp.c,v 1.2 2020/01/04 12:08:32 jmcneill Exp $ */ 3 /*- 4 * Copyright (c) 2019 Jonathan A. Kollasch <jakllsch@kollasch.net> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/param.h> 30 #include <sys/device.h> 31 #include <sys/systm.h> 32 33 #include <machine/bus.h> 34 35 #include <dev/ic/anxdp.h> 36 37 #include <drm/drm_atomic.h> 38 #include <drm/drm_atomic_helper.h> 39 #include <drm/drm_crtc.h> 40 #include <drm/drm_crtc_helper.h> 41 #include <drm/drm_dp_helper.h> 42 #include <drm/drm_probe_helper.h> 43 #include <drm/drm_edid.h> 44 45 #define ANXDP_DP_TX_VERSION 0x010 46 #define ANXDP_TX_SW_RESET 0x014 47 #define RESET_DP_TX (1 << 0) 48 #define ANXDP_FUNC_EN_1 0x018 49 #define MASTER_VID_FUNC_EN_N (1 << 7) 50 #define RK_VID_CAP_FUNC_EN_N (1 << 6) 51 #define SLAVE_VID_FUNC_EN_N (1 << 5) 52 #define RK_VID_FIFO_FUNC_EN_N (1 << 5) 53 #define AUD_FIFO_FUNC_EN_N (1 << 4) 54 #define AUD_FUNC_EN_N (1 << 3) 55 #define HDCP_FUNC_EN_N (1 << 2) 56 #define CRC_FUNC_EN_N (1 << 1) 57 #define SW_FUNC_EN_N (1 << 0) 58 #define ANXDP_FUNC_EN_2 0x01c 59 #define SSC_FUNC_EN_N (1 << 7) 60 #define AUX_FUNC_EN_N (1 << 2) 61 #define SERDES_FIFO_FUNC_EN_N (1 << 1) 62 #define LS_CLK_DOMAIN_FUNC_EN_N (1 << 0) 63 #define ANXDP_VIDEO_CTL_1 0x020 64 #define VIDEO_EN (1 << 7) 65 #define VIDEO_MUTE (1 << 6) 66 #define ANXDP_VIDEO_CTL_2 0x024 67 #define ANXDP_VIDEO_CTL_3 0x028 68 #define ANXDP_VIDEO_CTL_4 0x02c 69 #define ANXDP_VIDEO_CTL_8 0x03c 70 #define ANXDP_VIDEO_CTL_10 0x044 71 #define F_SEL (1 << 4) 72 #define SLAVE_I_SCAN_CFG (1 << 2) 73 #define SLAVE_VSYNC_P_CFG (1 << 1) 74 #define SLAVE_HSYNC_P_CFG (1 << 0) 75 #define ANXDP_PLL_REG_1 0x0fc 76 #define REF_CLK_24M (1 << 0) 77 #define RKANXDP_PD 0x12c 78 #define DP_INC_BG (1 << 7) 79 #define DP_EXP_PD (1 << 6) 80 #define DP_PHY_PD (1 << 5) 81 #define RK_AUX_PD (1 << 5) 82 #define AUX_PD (1 << 4) 83 #define RK_PLL_PD (1 << 4) 84 #define CHx_PD(x) (1 << x) /* 0<=x<=3 */ 85 #define DP_ALL_PD 0xff 86 #define ANXDP_LANE_MAP 0x35c 87 #define ANXDP_ANALOG_CTL_1 0x370 88 #define TX_TERMINAL_CTRL_50_OHM (1 << 4) 89 #define ANXDP_ANALOG_CTL_2 0x374 90 #define SEL_24M (1 << 3) 91 #define TX_DVDD_BIT_1_0625V 0x4 92 #define ANXDP_ANALOG_CTL_3 0x378 93 #define DRIVE_DVDD_BIT_1_0625V (0x4 << 5) 94 #define VCO_BIT_600_MICRO (0x5 << 0) 95 #define ANXDP_PLL_FILTER_CTL_1 0x37c 96 #define PD_RING_OSC (1 << 6) 97 #define AUX_TERMINAL_CTRL_50_OHM (2 << 4) 98 #define TX_CUR1_2X (1 << 2) 99 #define TX_CUR_16_MA 3 100 #define ANXDP_TX_AMP_TUNING_CTL 0x380 101 #define ANXDP_AUX_HW_RETRY_CTL 0x390 102 #define AUX_BIT_PERIOD_EXPECTED_DELAY(x) ((x) << 8) 103 #define AUX_HW_RETRY_INTERVAL_600_US (0 << 3) 104 #define AUX_HW_RETRY_INTERVAL_800_US (1 << 3) 105 #define AUX_HW_RETRY_INTERVAL_1000_US (2 << 3) 106 #define AUX_HW_RETRY_INTERVAL_1800_US (3 << 3) 107 #define AUX_HW_RETRY_COUNT_SEL(x) ((x) << 0) 108 #define ANXDP_COMMON_INT_STA_1 0x3c4 109 #define PLL_LOCK_CHG (1 << 6) 110 #define ANXDP_COMMON_INT_STA_2 0x3c8 111 #define ANXDP_COMMON_INT_STA_3 0x3cc 112 #define ANXDP_COMMON_INT_STA_4 0x3d0 113 #define ANXDP_DP_INT_STA 0x3dc 114 #define INT_HPD (1 << 6) 115 #define HW_TRAINING_FINISH (1 << 5) 116 #define RPLY_RECEIV (1 << 1) 117 #define AUX_ERR (1 << 0) 118 #define ANXDP_SYS_CTL_1 0x600 119 #define DET_STA (1 << 2) 120 #define FORCE_DET (1 << 1) 121 #define DET_CTRL (1 << 0) 122 #define ANXDP_SYS_CTL_2 0x604 123 #define ANXDP_SYS_CTL_3 0x608 124 #define HPD_STATUS (1 << 6) 125 #define F_HPD (1 << 5) 126 #define HPD_CTRL (1 << 4) 127 #define HDCP_RDY (1 << 3) 128 #define STRM_VALID (1 << 2) 129 #define F_VALID (1 << 1) 130 #define VALID_CTRL (1 << 0) 131 #define ANXDP_SYS_CTL_4 0x60c 132 #define ANXDP_PKT_SEND_CTL 0x640 133 #define ANXDP_HDCP_CTL 0x648 134 #define ANXDP_LINK_BW_SET 0x680 135 #define ANXDP_LANE_COUNT_SET 0x684 136 #define ANXDP_TRAINING_PTN_SET 0x688 137 #define SCRAMBLING_DISABLE (1 << 5) 138 #define SW_TRAINING_PATTERN_SET_PTN2 (2 << 0) 139 #define SW_TRAINING_PATTERN_SET_PTN1 (1 << 0) 140 #define ANXDP_LNx_LINK_TRAINING_CTL(x) (0x68c + 4 * (x)) /* 0 <= x <= 3 */ 141 #define MAX_PRE_REACH (1 << 5) 142 #define PRE_EMPHASIS_SET(x) ((x) << 3) 143 #define MAX_DRIVE_REACH (1 << 2) 144 #define DRIVE_CURRENT_SET(x) ((x) << 0) 145 #define ANXDP_DEBUG_CTL 0x6c0 146 #define PLL_LOCK (1 << 4) 147 #define F_PLL_LOCK (1 << 3) 148 #define PLL_LOCK_CTRL (1 << 2) 149 #define PN_INV (1 << 0) 150 #define ANXDP_LINK_DEBUG_CTL 0x6e0 151 #define ANXDP_PLL_CTL 0x71c 152 #define ANXDP_PHY_PD 0x720 153 #define ANXDP_PHY_TEST 0x724 154 #define MACRO_RST (1 << 5) 155 #define ANXDP_M_AUD_GEN_FILTER_TH 0x778 156 #define ANXDP_AUX_CH_STA 0x780 157 #define AUX_BUSY (1 << 4) 158 #define AUX_STATUS(x) (((x) >> 0) & 0xf) 159 #define ANXDP_AUX_ERR_NUM 0x784 160 #define ANXDP_AUX_CH_DEFER_CTL 0x788 161 #define DEFER_CTRL_EN (1 << 7) 162 #define DEFER_COUNT(x) ((x) << 0) 163 #define ANXDP_AUX_RX_COMM 0x78c 164 #define AUX_RX_COMM_I2C_DEFER (1 << 3) 165 #define AUX_RX_COMM_AUX_DEFER (1 << 1) 166 #define ANXDP_BUFFER_DATA_CTL 0x790 167 #define BUF_CLR (1 << 7) 168 #define BUF_DATA_COUNT(x) ((x) << 0) 169 #define ANXDP_AUX_CH_CTL_1 0x794 170 #define AUX_LENGTH(x) (((x) - 1) << 4) 171 #define AUX_TX_COMM(x) (((x) >> 0) & 0xf) 172 #define AUX_TX_COMM_DP (1 << 3) 173 #define AUX_TX_COMM_MOT (1 << 2) 174 #define AUX_TX_COMM_READ (1 << 0) 175 #define ANXDP_AUX_ADDR_7_0 0x798 176 #define AUX_ADDR_7_0(x) (((x) >> 0) & 0xff) 177 #define ANXDP_AUX_ADDR_15_8 0x79c 178 #define AUX_ADDR_15_8(x) (((x) >> 8) & 0xff) 179 #define ANXDP_AUX_ADDR_19_16 0x7a0 180 #define AUX_ADDR_19_16(x) (((x) >> 16) & 0xf) 181 #define ANXDP_AUX_CH_CTL_2 0x7a4 182 #define ADDR_ONLY (1 << 1) 183 #define AUX_EN (1 << 0) 184 #define ANXDP_BUF_DATA(x) (0x7c0 + 4 * (x)) 185 #define ANXDP_SOC_GENERAL_CTL 0x800 186 #define AUDIO_MODE_SPDIF_MODE (1 << 8) 187 #define VIDEO_MODE_SLAVE_MODE (1 << 1) 188 #define ANXDP_CRC_CON 0x890 189 #define ANXDP_PLL_REG_2 0x9e4 190 #define ANXDP_PLL_REG_3 0x9e8 191 #define ANXDP_PLL_REG_4 0x9ec 192 #define ANXDP_PLL_REG_5 0xa00 193 194 static inline const bool 195 isrockchip(struct anxdp_softc *sc) 196 { 197 return (sc->sc_flags & ANXDP_FLAG_ROCKCHIP) != 0; 198 } 199 200 enum drm_connector_status 201 anxdp_connector_detect(struct drm_connector *connector, bool force) 202 { 203 #if 0 204 struct anxdp_connector *anxdp_connector = to_anxdp_connector(connector); 205 struct anxdp_softc *sc = anxdp_connector->sc; 206 207 /* XXX HPD */ 208 #endif 209 return connector_status_connected; 210 } 211 212 void 213 anxdp_connector_destroy(struct drm_connector *connector) 214 { 215 drm_connector_unregister(connector); 216 drm_connector_cleanup(connector); 217 } 218 219 struct drm_connector_funcs anxdp_connector_funcs = { 220 .dpms = drm_helper_connector_dpms, 221 .detect = anxdp_connector_detect, 222 .fill_modes = drm_helper_probe_single_connector_modes, 223 .destroy = anxdp_connector_destroy, 224 .reset = drm_atomic_helper_connector_reset, 225 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 226 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 227 }; 228 229 void 230 anxdp_analog_power_up_all(struct anxdp_softc *sc) 231 { 232 const bus_size_t pd_reg = isrockchip(sc) ? RKANXDP_PD : ANXDP_PHY_PD; 233 234 bus_space_write_4(sc->sc_iot, sc->sc_ioh, pd_reg, DP_ALL_PD); 235 delay(15); 236 bus_space_write_4(sc->sc_iot, sc->sc_ioh, pd_reg, 237 DP_ALL_PD & ~DP_INC_BG); 238 delay(15); 239 bus_space_write_4(sc->sc_iot, sc->sc_ioh, pd_reg, 0); 240 } 241 242 int 243 anxdp_await_pll_lock(struct anxdp_softc *sc) 244 { 245 u_int timeout; 246 247 for (timeout = 0; timeout < 100; timeout++) { 248 if ((bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_DEBUG_CTL) & 249 PLL_LOCK) != 0) 250 return 0; 251 delay(20); 252 } 253 254 return ETIMEDOUT; 255 } 256 257 void 258 anxdp_init_hpd(struct anxdp_softc *sc) 259 { 260 uint32_t sc3; 261 262 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_COMMON_INT_STA_4, 0x7); 263 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_DP_INT_STA, INT_HPD); 264 265 sc3 = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_SYS_CTL_3); 266 sc3 &= ~(F_HPD | HPD_CTRL); 267 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_SYS_CTL_3, sc3); 268 269 sc3 = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_SYS_CTL_3); 270 sc3 |= F_HPD | HPD_CTRL; 271 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_SYS_CTL_3, sc3); 272 } 273 274 void 275 anxdp_init_aux(struct anxdp_softc *sc) 276 { 277 uint32_t fe2, pd, hrc; 278 const bus_size_t pd_reg = isrockchip(sc) ? RKANXDP_PD : ANXDP_PHY_PD; 279 const uint32_t pd_mask = isrockchip(sc) ? RK_AUX_PD : AUX_PD; 280 281 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_DP_INT_STA, 282 RPLY_RECEIV | AUX_ERR); 283 284 pd = bus_space_read_4(sc->sc_iot, sc->sc_ioh, pd_reg); 285 pd |= pd_mask; 286 bus_space_write_4(sc->sc_iot, sc->sc_ioh, pd_reg, pd); 287 288 delay(11); 289 290 pd = bus_space_read_4(sc->sc_iot, sc->sc_ioh, pd_reg); 291 pd &= ~pd_mask; 292 bus_space_write_4(sc->sc_iot, sc->sc_ioh, pd_reg, pd); 293 294 fe2 = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_FUNC_EN_2); 295 fe2 |= AUX_FUNC_EN_N; 296 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_FUNC_EN_2, fe2); 297 298 hrc = AUX_HW_RETRY_COUNT_SEL(0) | AUX_HW_RETRY_INTERVAL_600_US; 299 if (!isrockchip(sc)) 300 hrc |= AUX_BIT_PERIOD_EXPECTED_DELAY(3); 301 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_AUX_HW_RETRY_CTL, hrc); 302 303 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_AUX_CH_DEFER_CTL, 304 DEFER_CTRL_EN | DEFER_COUNT(1)); 305 306 fe2 = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_FUNC_EN_2); 307 fe2 &= ~AUX_FUNC_EN_N; 308 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_FUNC_EN_2, fe2); 309 } 310 311 int 312 anxdp_connector_get_modes(struct drm_connector *connector) 313 { 314 struct anxdp_connector *anxdp_connector = to_anxdp_connector(connector); 315 struct anxdp_softc *sc = anxdp_connector->sc; 316 struct edid *pedid = NULL; 317 int error; 318 319 if (sc->sc_panel) 320 return drm_panel_get_modes(sc->sc_panel, connector); 321 322 pedid = drm_get_edid(connector, &sc->sc_dpaux.ddc); 323 324 drm_connector_update_edid_property(connector, pedid); 325 if (pedid == NULL) 326 return 0; 327 328 error = drm_add_edid_modes(connector, pedid); 329 330 if (pedid != NULL) 331 kfree(pedid); 332 333 return error; 334 } 335 336 struct drm_connector_helper_funcs anxdp_connector_helper_funcs = { 337 .get_modes = anxdp_connector_get_modes, 338 }; 339 340 int 341 anxdp_bridge_attach(struct drm_bridge *bridge, 342 enum drm_bridge_attach_flags flags) 343 { 344 struct anxdp_softc *sc = bridge->driver_private; 345 struct anxdp_connector *anxdp_connector = &sc->sc_connector; 346 struct drm_connector *connector = &anxdp_connector->base; 347 int error; 348 349 anxdp_connector->sc = sc; 350 351 connector->polled = 352 DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT; 353 connector->interlace_allowed = 0; 354 connector->doublescan_allowed = 0; 355 356 drm_connector_init(bridge->dev, connector, &anxdp_connector_funcs, 357 connector->connector_type); 358 drm_connector_helper_add(connector, &anxdp_connector_helper_funcs); 359 360 error = drm_connector_attach_encoder(connector, bridge->encoder); 361 if (error != 0) 362 return error; 363 364 if (sc->sc_panel != NULL) { 365 error = drm_panel_attach(sc->sc_panel, connector); 366 if (error != 0) 367 return error; 368 } 369 370 return drm_connector_register(connector); 371 } 372 373 void 374 anxdp_macro_reset(struct anxdp_softc *sc) 375 { 376 uint32_t val; 377 378 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_PHY_TEST); 379 val |= MACRO_RST; 380 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_PHY_TEST, val); 381 delay(10); 382 val &= ~MACRO_RST; 383 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_PHY_TEST, val); 384 } 385 386 int 387 anxdp_link_configure(struct anxdp_softc *sc) 388 { 389 uint8_t values[2]; 390 int error; 391 392 values[0] = drm_dp_link_rate_to_bw_code(sc->sc_link_rate); 393 values[1] = sc->sc_num_lanes; 394 395 if (sc->sc_dpcd[2] & DP_ENHANCED_FRAME_CAP) 396 values[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 397 398 error = drm_dp_dpcd_write(&sc->sc_dpaux, DP_LINK_BW_SET, 399 values, sizeof(values)); 400 if (error < 0) 401 return error; 402 403 return 0; 404 } 405 406 int 407 anxdp_link_power_up(struct anxdp_softc *sc) 408 { 409 uint8_t value; 410 int error; 411 412 if (sc->sc_dpcd[0] < 0x11) 413 return 0; 414 415 error = drm_dp_dpcd_readb(&sc->sc_dpaux, DP_SET_POWER, &value); 416 if (error < 0) 417 return error; 418 419 value &= ~DP_SET_POWER_MASK; 420 value |= DP_SET_POWER_D0; 421 422 error = drm_dp_dpcd_writeb(&sc->sc_dpaux, DP_SET_POWER, value); 423 if (error < 0) 424 return error; 425 426 delay(1000); 427 return 0; 428 } 429 430 void 431 anxdp_link_start(struct anxdp_softc *sc) 432 { 433 uint8_t training[4]; 434 uint32_t val; 435 436 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_LINK_BW_SET, 437 drm_dp_link_rate_to_bw_code(sc->sc_link_rate)); 438 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_LANE_COUNT_SET, 439 sc->sc_num_lanes); 440 if (anxdp_link_configure(sc)) 441 return; 442 443 for (u_int i = 0; i < sc->sc_num_lanes; i++) { 444 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 445 ANXDP_LNx_LINK_TRAINING_CTL(i)); 446 val &= ~(PRE_EMPHASIS_SET(3)|DRIVE_CURRENT_SET(3)); 447 val |= PRE_EMPHASIS_SET(0); 448 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 449 ANXDP_LNx_LINK_TRAINING_CTL(i), val); 450 } 451 452 if (anxdp_await_pll_lock(sc) != 0) { 453 printf("%s: PLL lock timeout\n", sc->sc_dev.dv_xname); 454 } 455 456 for (u_int i = 0; i < sc->sc_num_lanes; i++) { 457 training[i] = DP_TRAIN_PRE_EMPH_LEVEL_0 | 458 DP_TRAIN_VOLTAGE_SWING_LEVEL_0; 459 } 460 461 drm_dp_dpcd_write(&sc->sc_dpaux, DP_TRAINING_LANE0_SET, training, 462 sc->sc_num_lanes); 463 } 464 465 void 466 anxdp_process_clock_recovery(struct anxdp_softc *sc) 467 { 468 u_int i, tries; 469 uint8_t link_status[DP_LINK_STATUS_SIZE]; 470 uint8_t training[4]; 471 472 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_TRAINING_PTN_SET, 473 SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1); 474 drm_dp_dpcd_writeb(&sc->sc_dpaux, DP_TRAINING_PATTERN_SET, 475 DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_1); 476 477 tries = 0; 478 again: 479 if (tries++ >= 10) { 480 printf("%s: cr fail\n", sc->sc_dev.dv_xname); 481 return; 482 } 483 drm_dp_link_train_clock_recovery_delay(sc->sc_dpcd); 484 if (DP_LINK_STATUS_SIZE != 485 drm_dp_dpcd_read_link_status(&sc->sc_dpaux, link_status)) { 486 return; 487 } 488 if (!drm_dp_clock_recovery_ok(link_status, sc->sc_num_lanes)) { 489 goto cr_fail; 490 } 491 492 return; 493 494 cr_fail: 495 for (i = 0; i < sc->sc_num_lanes; i++) { 496 uint8_t vs, pe; 497 vs = drm_dp_get_adjust_request_voltage(link_status, i); 498 pe = drm_dp_get_adjust_request_pre_emphasis(link_status, i); 499 training[i] = vs | pe; 500 } 501 for (i = 0; i < sc->sc_num_lanes; i++) { 502 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 503 ANXDP_LNx_LINK_TRAINING_CTL(i), training[i]); 504 } 505 drm_dp_dpcd_write(&sc->sc_dpaux, DP_TRAINING_LANE0_SET, training, 506 sc->sc_num_lanes); 507 goto again; 508 } 509 510 void 511 anxdp_process_eq(struct anxdp_softc *sc) 512 { 513 u_int i, tries; 514 uint8_t link_status[DP_LINK_STATUS_SIZE]; 515 uint8_t training[4]; 516 517 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_TRAINING_PTN_SET, 518 SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2); 519 drm_dp_dpcd_writeb(&sc->sc_dpaux, DP_TRAINING_PATTERN_SET, 520 DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_2); 521 522 tries = 0; 523 again: 524 if (tries++ >= 10) { 525 printf("%s: eq fail\n", sc->sc_dev.dv_xname); 526 return; 527 } 528 drm_dp_link_train_channel_eq_delay(sc->sc_dpcd); 529 if (DP_LINK_STATUS_SIZE != 530 drm_dp_dpcd_read_link_status(&sc->sc_dpaux, link_status)) { 531 return; 532 } 533 if (!drm_dp_channel_eq_ok(link_status, sc->sc_num_lanes)) { 534 goto eq_fail; 535 } 536 537 return; 538 539 eq_fail: 540 for (i = 0; i < sc->sc_num_lanes; i++) { 541 uint8_t vs, pe; 542 vs = drm_dp_get_adjust_request_voltage(link_status, i); 543 pe = drm_dp_get_adjust_request_pre_emphasis(link_status, i); 544 training[i] = vs | pe; 545 } 546 for (i = 0; i < sc->sc_num_lanes; i++) { 547 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 548 ANXDP_LNx_LINK_TRAINING_CTL(i), training[i]); 549 } 550 drm_dp_dpcd_write(&sc->sc_dpaux, DP_TRAINING_LANE0_SET, training, 551 sc->sc_num_lanes); 552 goto again; 553 } 554 555 void 556 anxdp_train_link(struct anxdp_softc *sc) 557 { 558 anxdp_macro_reset(sc); 559 560 if (DP_RECEIVER_CAP_SIZE != drm_dp_dpcd_read(&sc->sc_dpaux, 561 DP_DPCD_REV, sc->sc_dpcd, DP_RECEIVER_CAP_SIZE)) { 562 printf("%s: link probe failed\n", sc->sc_dev.dv_xname); 563 return; 564 } 565 566 sc->sc_link_rate = drm_dp_bw_code_to_link_rate(sc->sc_dpcd[1]); 567 sc->sc_num_lanes = sc->sc_dpcd[2] & DP_MAX_LANE_COUNT_MASK; 568 569 if (anxdp_link_power_up(sc)) 570 return; 571 572 anxdp_link_start(sc); 573 anxdp_process_clock_recovery(sc); 574 anxdp_process_eq(sc); 575 576 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_TRAINING_PTN_SET, 0); 577 drm_dp_dpcd_writeb(&sc->sc_dpaux, DP_TRAINING_PATTERN_SET, 578 DP_TRAINING_PATTERN_DISABLE); 579 } 580 581 void 582 anxdp_bringup(struct anxdp_softc *sc) 583 { 584 uint32_t val; 585 586 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_VIDEO_CTL_1); 587 val &= ~VIDEO_EN; 588 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_VIDEO_CTL_1, val); 589 590 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_VIDEO_CTL_1); 591 val &= ~VIDEO_MUTE; 592 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_VIDEO_CTL_1, val); 593 594 val = SW_FUNC_EN_N; 595 if (isrockchip(sc)) { 596 val |= RK_VID_CAP_FUNC_EN_N | RK_VID_FIFO_FUNC_EN_N; 597 } else { 598 val |= MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N | 599 AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N | HDCP_FUNC_EN_N; 600 } 601 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_FUNC_EN_1, val); 602 603 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_FUNC_EN_2, 604 SSC_FUNC_EN_N | AUX_FUNC_EN_N | SERDES_FIFO_FUNC_EN_N | 605 LS_CLK_DOMAIN_FUNC_EN_N); 606 607 delay(30); 608 609 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_M_AUD_GEN_FILTER_TH, 2); 610 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_SOC_GENERAL_CTL, 0x101); 611 612 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_TX_SW_RESET, 613 RESET_DP_TX); 614 615 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_ANALOG_CTL_1, 616 TX_TERMINAL_CTRL_50_OHM); 617 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_ANALOG_CTL_2, 618 SEL_24M | TX_DVDD_BIT_1_0625V); 619 if (isrockchip(sc)) { 620 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_PLL_REG_1, 621 REF_CLK_24M); 622 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_PLL_REG_2, 623 0x95); 624 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_PLL_REG_3, 625 0x40); 626 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_PLL_REG_4, 627 0x58); 628 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_PLL_REG_5, 629 0x22); 630 } 631 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_ANALOG_CTL_3, 632 DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO); 633 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_PLL_FILTER_CTL_1, 634 PD_RING_OSC | AUX_TERMINAL_CTRL_50_OHM | TX_CUR1_2X | TX_CUR_16_MA); 635 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_TX_AMP_TUNING_CTL, 0); 636 637 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_FUNC_EN_1); 638 val &= ~SW_FUNC_EN_N; 639 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_FUNC_EN_1, val); 640 641 anxdp_analog_power_up_all(sc); 642 643 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_COMMON_INT_STA_1, 644 PLL_LOCK_CHG); 645 646 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_DEBUG_CTL); 647 val &= ~(F_PLL_LOCK | PLL_LOCK_CTRL); 648 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_DEBUG_CTL, val); 649 650 if (anxdp_await_pll_lock(sc) != 0) { 651 printf("%s: PLL lock timeout\n", sc->sc_dev.dv_xname); 652 } 653 654 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_FUNC_EN_2); 655 val &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N | 656 AUX_FUNC_EN_N); 657 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_FUNC_EN_2, val); 658 659 anxdp_init_hpd(sc); 660 anxdp_init_aux(sc); 661 } 662 663 void 664 anxdp_bridge_enable(struct drm_bridge *bridge) 665 { 666 struct anxdp_softc *sc = bridge->driver_private; 667 uint32_t val; 668 669 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_FUNC_EN_1); 670 if (isrockchip(sc)) { 671 val &= ~(RK_VID_CAP_FUNC_EN_N | RK_VID_FIFO_FUNC_EN_N); 672 } else { 673 val &= ~(MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N); 674 val |= MASTER_VID_FUNC_EN_N; 675 } 676 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_FUNC_EN_1, val); 677 678 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_VIDEO_CTL_10); 679 val &= ~(SLAVE_I_SCAN_CFG|SLAVE_VSYNC_P_CFG|SLAVE_HSYNC_P_CFG); 680 if ((sc->sc_curmode.flags & DRM_MODE_FLAG_INTERLACE) != 0) 681 val |= SLAVE_I_SCAN_CFG; 682 if ((sc->sc_curmode.flags & DRM_MODE_FLAG_NVSYNC) != 0) 683 val |= SLAVE_VSYNC_P_CFG; 684 if ((sc->sc_curmode.flags & DRM_MODE_FLAG_NHSYNC) != 0) 685 val |= SLAVE_HSYNC_P_CFG; 686 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_VIDEO_CTL_10, val); 687 688 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_SOC_GENERAL_CTL, 689 AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE); 690 691 anxdp_train_link(sc); 692 693 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_VIDEO_CTL_1); 694 val |= VIDEO_EN; 695 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_VIDEO_CTL_1, val); 696 697 if (sc->sc_panel != NULL && 698 sc->sc_panel->funcs != NULL && 699 sc->sc_panel->funcs->enable != NULL) 700 sc->sc_panel->funcs->enable(sc->sc_panel); 701 } 702 703 void 704 anxdp_bridge_pre_enable(struct drm_bridge *bridge) 705 { 706 } 707 708 void 709 anxdp_bridge_disable(struct drm_bridge *bridge) 710 { 711 } 712 713 void 714 anxdp_bridge_post_disable(struct drm_bridge *bridge) 715 { 716 } 717 718 void 719 anxdp_bridge_mode_set(struct drm_bridge *bridge, 720 const struct drm_display_mode *mode, 721 const struct drm_display_mode *adjusted_mode) 722 { 723 struct anxdp_softc *sc = bridge->driver_private; 724 725 sc->sc_curmode = *adjusted_mode; 726 } 727 728 bool 729 anxdp_bridge_mode_fixup(struct drm_bridge *bridge, 730 const struct drm_display_mode *mode, 731 struct drm_display_mode *adjusted_mode) 732 { 733 return true; 734 } 735 736 const struct drm_bridge_funcs anxdp_bridge_funcs = { 737 .attach = anxdp_bridge_attach, 738 .enable = anxdp_bridge_enable, 739 .pre_enable = anxdp_bridge_pre_enable, 740 .disable = anxdp_bridge_disable, 741 .post_disable = anxdp_bridge_post_disable, 742 .mode_set = anxdp_bridge_mode_set, 743 .mode_fixup = anxdp_bridge_mode_fixup, 744 }; 745 746 ssize_t 747 anxdp_dp_aux_transfer(struct drm_dp_aux *dpaux, struct drm_dp_aux_msg *dpmsg) 748 { 749 struct anxdp_softc *sc = container_of(dpaux, struct anxdp_softc, 750 sc_dpaux); 751 size_t loop_timeout = 0; 752 uint32_t val; 753 size_t i; 754 ssize_t ret = 0; 755 756 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_BUFFER_DATA_CTL, 757 BUF_CLR); 758 759 val = AUX_LENGTH(dpmsg->size); 760 if ((dpmsg->request & DP_AUX_I2C_MOT) != 0) 761 val |= AUX_TX_COMM_MOT; 762 763 switch (dpmsg->request & ~DP_AUX_I2C_MOT) { 764 case DP_AUX_I2C_WRITE: 765 break; 766 case DP_AUX_I2C_READ: 767 val |= AUX_TX_COMM_READ; 768 break; 769 case DP_AUX_NATIVE_WRITE: 770 val |= AUX_TX_COMM_DP; 771 break; 772 case DP_AUX_NATIVE_READ: 773 val |= AUX_TX_COMM_READ | AUX_TX_COMM_DP; 774 break; 775 } 776 777 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_AUX_CH_CTL_1, val); 778 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_AUX_ADDR_7_0, 779 AUX_ADDR_7_0(dpmsg->address)); 780 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_AUX_ADDR_15_8, 781 AUX_ADDR_15_8(dpmsg->address)); 782 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_AUX_ADDR_19_16, 783 AUX_ADDR_19_16(dpmsg->address)); 784 785 if (!(dpmsg->request & DP_AUX_I2C_READ)) { 786 for (i = 0; i < dpmsg->size; i++) { 787 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 788 ANXDP_BUF_DATA(i), 789 ((const uint8_t *)(dpmsg->buffer))[i]); 790 ret++; 791 } 792 } 793 794 795 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_AUX_CH_CTL_2, 796 AUX_EN | ((dpmsg->size == 0) ? ADDR_ONLY : 0)); 797 798 loop_timeout = 0; 799 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_AUX_CH_CTL_2); 800 while ((val & AUX_EN) != 0) { 801 if (++loop_timeout > 20000) { 802 ret = -ETIMEDOUT; 803 goto out; 804 } 805 delay(25); 806 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 807 ANXDP_AUX_CH_CTL_2); 808 } 809 810 loop_timeout = 0; 811 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_DP_INT_STA); 812 while (!(val & RPLY_RECEIV)) { 813 if (++loop_timeout > 2000) { 814 ret = -ETIMEDOUT; 815 goto out; 816 } 817 delay(10); 818 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 819 ANXDP_DP_INT_STA); 820 } 821 822 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_DP_INT_STA, 823 RPLY_RECEIV); 824 825 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_DP_INT_STA); 826 if ((val & AUX_ERR) != 0) { 827 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_DP_INT_STA, 828 AUX_ERR); 829 ret = -EREMOTEIO; 830 goto out; 831 } 832 833 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_AUX_CH_STA); 834 if (AUX_STATUS(val) != 0) { 835 ret = -EREMOTEIO; 836 goto out; 837 } 838 839 if ((dpmsg->request & DP_AUX_I2C_READ)) { 840 for (i = 0; i < dpmsg->size; i++) { 841 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 842 ANXDP_BUF_DATA(i)); 843 ((uint8_t *)(dpmsg->buffer))[i] = val & 0xffU; 844 ret++; 845 } 846 } 847 848 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_AUX_RX_COMM); 849 if (val == AUX_RX_COMM_AUX_DEFER) 850 dpmsg->reply = DP_AUX_NATIVE_REPLY_DEFER; 851 else if (val == AUX_RX_COMM_I2C_DEFER) 852 dpmsg->reply = DP_AUX_I2C_REPLY_DEFER; 853 else if ((dpmsg->request & ~DP_AUX_I2C_MOT) == DP_AUX_I2C_WRITE || 854 (dpmsg->request & ~DP_AUX_I2C_MOT) == DP_AUX_I2C_READ) 855 dpmsg->reply = DP_AUX_I2C_REPLY_ACK; 856 else if ((dpmsg->request & ~DP_AUX_I2C_MOT) == DP_AUX_NATIVE_WRITE || 857 (dpmsg->request & ~DP_AUX_I2C_MOT) == DP_AUX_NATIVE_READ) 858 dpmsg->reply = DP_AUX_NATIVE_REPLY_ACK; 859 860 out: 861 if (ret < 0) 862 anxdp_init_aux(sc); 863 864 return ret; 865 } 866 867 void 868 anxdp_dpms(struct anxdp_softc *sc, int mode) 869 { 870 switch (mode) { 871 case DRM_MODE_DPMS_ON: 872 #ifdef notyet 873 pmf_event_inject(NULL, PMFE_DISPLAY_ON); 874 #endif 875 break; 876 case DRM_MODE_DPMS_STANDBY: 877 case DRM_MODE_DPMS_SUSPEND: 878 case DRM_MODE_DPMS_OFF: 879 #ifdef notyet 880 pmf_event_inject(NULL, PMFE_DISPLAY_OFF); 881 #endif 882 break; 883 } 884 } 885 886 int 887 anxdp_attach(struct anxdp_softc *sc) 888 { 889 sc->sc_dpaux.name = "DP Aux"; 890 sc->sc_dpaux.transfer = anxdp_dp_aux_transfer; 891 sc->sc_dpaux.dev = &sc->sc_dev; 892 if (drm_dp_aux_register(&sc->sc_dpaux) != 0) { 893 printf("%s: registering DP Aux failed\n", sc->sc_dev.dv_xname); 894 } 895 896 anxdp_bringup(sc); 897 898 return 0; 899 } 900 901 int 902 anxdp_bind(struct anxdp_softc *sc, struct drm_encoder *encoder) 903 { 904 int error; 905 906 sc->sc_bridge.driver_private = sc; 907 sc->sc_bridge.funcs = &anxdp_bridge_funcs; 908 sc->sc_bridge.encoder = encoder; 909 910 error = drm_bridge_attach(encoder, &sc->sc_bridge, NULL, 0); 911 if (error != 0) 912 return EIO; 913 914 if (sc->sc_panel != NULL && sc->sc_panel->funcs != NULL && 915 sc->sc_panel->funcs->prepare != NULL) 916 sc->sc_panel->funcs->prepare(sc->sc_panel); 917 918 return 0; 919 } 920