1 /* $OpenBSD: am7990reg.h,v 1.8 2007/05/23 09:00:17 jmc Exp $ */ 2 /* $NetBSD: am7990reg.h,v 1.1 1995/04/11 04:17:50 mycroft Exp $ */ 3 4 /*- 5 * Copyright (c) 1995 Charles M. Hannum. All rights reserved. 6 * Copyright (c) 1992, 1993 7 * The Regents of the University of California. All rights reserved. 8 * 9 * This code is derived from software contributed to Berkeley by 10 * Ralph Campbell and Rick Macklem. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * @(#)if_lereg.h 8.1 (Berkeley) 6/10/93 37 */ 38 39 /* 40 * Documentation for this chip: 41 * Am79C90 CMOS Local Area Network Controller for Ethernet 42 * AMD Publication #: 17881, Rev C, Jan 1997 43 */ 44 45 #define LEMINSIZE 60 /* should be 64 if mode DTCR is set */ 46 47 /* 48 * Receive message descriptor 49 */ 50 struct lermd { 51 u_int16_t rmd0; 52 #if BYTE_ORDER == BIG_ENDIAN 53 u_int8_t rmd1_bits; 54 u_int8_t rmd1_hadr; 55 #else 56 u_int8_t rmd1_hadr; 57 u_int8_t rmd1_bits; 58 #endif 59 int16_t rmd2; 60 u_int16_t rmd3; 61 }; 62 63 /* 64 * Transmit message descriptor 65 */ 66 struct letmd { 67 u_int16_t tmd0; 68 #if BYTE_ORDER == BIG_ENDIAN 69 u_int8_t tmd1_bits; 70 u_int8_t tmd1_hadr; 71 #else 72 u_int8_t tmd1_hadr; 73 u_int8_t tmd1_bits; 74 #endif 75 int16_t tmd2; 76 u_int16_t tmd3; 77 }; 78 79 /* 80 * Initialization block 81 */ 82 struct leinit { 83 u_int16_t init_mode; /* +0x0000 */ 84 u_int16_t init_padr[3]; /* +0x0002 */ 85 u_int16_t init_ladrf[4]; /* +0x0008 */ 86 u_int16_t init_rdra; /* +0x0010 */ 87 u_int16_t init_rlen; /* +0x0012 */ 88 u_int16_t init_tdra; /* +0x0014 */ 89 u_int16_t init_tlen; /* +0x0016 */ 90 int16_t pad0[4]; /* Pad to 16 shorts */ 91 }; 92 93 #define LE_INITADDR(sc) (sc->sc_initaddr) 94 #define LE_RMDADDR(sc, bix) (sc->sc_rmdaddr + sizeof(struct lermd) * (bix)) 95 #define LE_TMDADDR(sc, bix) (sc->sc_tmdaddr + sizeof(struct letmd) * (bix)) 96 #define LE_RBUFADDR(sc, bix) (sc->sc_rbufaddr + ETHER_MAX_DIX_LEN * (bix)) 97 #define LE_TBUFADDR(sc, bix) (sc->sc_tbufaddr + ETHER_MAX_DIX_LEN * (bix)) 98 99 /* register addresses */ 100 #define LE_CSR0 0x0000 /* Control and status register */ 101 #define LE_CSR1 0x0001 /* low address of init block */ 102 #define LE_CSR2 0x0002 /* high address of init block */ 103 #define LE_CSR3 0x0003 /* Bus master and control */ 104 105 /* Control and status register 0 (csr0) */ 106 #define LE_C0_ERR 0x8000 /* error summary */ 107 #define LE_C0_BABL 0x4000 /* transmitter timeout error */ 108 #define LE_C0_CERR 0x2000 /* collision */ 109 #define LE_C0_MISS 0x1000 /* missed a packet */ 110 #define LE_C0_MERR 0x0800 /* memory error */ 111 #define LE_C0_RINT 0x0400 /* receiver interrupt */ 112 #define LE_C0_TINT 0x0200 /* transmitter interrupt */ 113 #define LE_C0_IDON 0x0100 /* initialization done */ 114 #define LE_C0_INTR 0x0080 /* interrupt condition */ 115 #define LE_C0_INEA 0x0040 /* interrupt enable */ 116 #define LE_C0_RXON 0x0020 /* receiver on */ 117 #define LE_C0_TXON 0x0010 /* transmitter on */ 118 #define LE_C0_TDMD 0x0008 /* transmit demand */ 119 #define LE_C0_STOP 0x0004 /* disable all external activity */ 120 #define LE_C0_STRT 0x0002 /* enable external activity */ 121 #define LE_C0_INIT 0x0001 /* begin initialization */ 122 123 #define LE_C0_BITS \ 124 "\20\20ERR\17BABL\16CERR\15MISS\14MERR\13RINT\ 125 \12TINT\11IDON\10INTR\07INEA\06RXON\05TXON\04TDMD\03STOP\02STRT\01INIT" 126 127 /* Control and status register 3 (csr3) */ 128 #define LE_C3_BSWP 0x0004 /* byte swap */ 129 #define LE_C3_ACON 0x0002 /* ALE control, eh? */ 130 #define LE_C3_BCON 0x0001 /* byte control */ 131 132 /* Initialization block (mode) */ 133 #define LE_MODE_PROM 0x8000 /* promiscuous mode */ 134 /* 0x7f80 reserved, must be zero */ 135 #define LE_MODE_INTL 0x0040 /* internal loopback */ 136 #define LE_MODE_DRTY 0x0020 /* disable retry */ 137 #define LE_MODE_COLL 0x0010 /* force a collision */ 138 #define LE_MODE_DTCR 0x0008 /* disable transmit CRC */ 139 #define LE_MODE_LOOP 0x0004 /* loopback mode */ 140 #define LE_MODE_DTX 0x0002 /* disable transmitter */ 141 #define LE_MODE_DRX 0x0001 /* disable receiver */ 142 #define LE_MODE_NORMAL 0 /* none of the above */ 143 144 /* Receive message descriptor 1 (rmd1_bits) */ 145 #define LE_R1_OWN 0x80 /* LANCE owns the packet */ 146 #define LE_R1_ERR 0x40 /* error summary */ 147 #define LE_R1_FRAM 0x20 /* framing error */ 148 #define LE_R1_OFLO 0x10 /* overflow error */ 149 #define LE_R1_CRC 0x08 /* CRC error */ 150 #define LE_R1_BUFF 0x04 /* buffer error */ 151 #define LE_R1_STP 0x02 /* start of packet */ 152 #define LE_R1_ENP 0x01 /* end of packet */ 153 154 #define LE_R1_BITS \ 155 "\20\10OWN\7ERR\6FRAM\5OFLO\4CRC\3BUFF\2STP\1ENP" 156 157 /* Transmit message descriptor 1 (tmd1_bits) */ 158 #define LE_T1_OWN 0x80 /* LANCE owns the packet */ 159 #define LE_T1_ERR 0x40 /* error summary */ 160 #define LE_T1_MORE 0x10 /* multiple collisions */ 161 #define LE_T1_ONE 0x08 /* single collision */ 162 #define LE_T1_DEF 0x04 /* deferred transmit */ 163 #define LE_T1_STP 0x02 /* start of packet */ 164 #define LE_T1_ENP 0x01 /* end of packet */ 165 166 #define LE_T1_BITS \ 167 "\20\10OWN\7ERR\6RES\5MORE\4ONE\3DEF\2STP\1ENP" 168 169 /* Transmit message descriptor 3 (tmd3) */ 170 #define LE_T3_BUFF 0x8000 /* buffer error */ 171 #define LE_T3_UFLO 0x4000 /* underflow error */ 172 #define LE_T3_LCOL 0x1000 /* late collision */ 173 #define LE_T3_LCAR 0x0800 /* loss of carrier */ 174 #define LE_T3_RTRY 0x0400 /* retry error */ 175 #define LE_T3_TDR_MASK 0x03ff /* time domain reflectometry counter */ 176 177 #define LE_XMD2_ONES 0xf000 178 179 #define LE_T3_BITS \ 180 "\20\20BUFF\17UFLO\16RES\15LCOL\14LCAR\13RTRY" 181