1 /* $OpenBSD: aic6360.c,v 1.27 2014/09/14 14:17:24 jsg Exp $ */ 2 /* $NetBSD: aic6360.c,v 1.52 1996/12/10 21:27:51 thorpej Exp $ */ 3 4 #ifdef DDB 5 #define integrate 6 #else 7 #define integrate static inline 8 #endif 9 10 /* 11 * Copyright (c) 1994, 1995, 1996 Charles Hannum. All rights reserved. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 3. All advertising materials mentioning features or use of this software 22 * must display the following acknowledgement: 23 * This product includes software developed by Charles M. Hannum. 24 * 4. The name of the author may not be used to endorse or promote products 25 * derived from this software without specific prior written permission. 26 * 27 * Copyright (c) 1994 Jarle Greipsland 28 * All rights reserved. 29 * 30 * Redistribution and use in source and binary forms, with or without 31 * modification, are permitted provided that the following conditions 32 * are met: 33 * 1. Redistributions of source code must retain the above copyright 34 * notice, this list of conditions and the following disclaimer. 35 * 2. Redistributions in binary form must reproduce the above copyright 36 * notice, this list of conditions and the following disclaimer in the 37 * documentation and/or other materials provided with the distribution. 38 * 3. The name of the author may not be used to endorse or promote products 39 * derived from this software without specific prior written permission. 40 * 41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 42 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 43 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 44 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 45 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 46 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 47 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 48 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 49 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 50 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 51 * POSSIBILITY OF SUCH DAMAGE. 52 */ 53 54 /* 55 * Acknowledgements: Many of the algorithms used in this driver are 56 * inspired by the work of Julian Elischer (julian@tfs.com) and 57 * Charles Hannum (mycroft@duality.gnu.ai.mit.edu). Thanks a million! 58 */ 59 60 /* TODO list: 61 * 1) Get the DMA stuff working. 62 * 2) Get the iov/uio stuff working. Is this a good thing ??? 63 * 3) Get the synch stuff working. 64 * 4) Rewrite it to use malloc for the acb structs instead of static alloc.? 65 */ 66 67 /* 68 * A few customizable items: 69 */ 70 71 /* Use doubleword transfers to/from SCSI chip. Note: This requires 72 * motherboard support. Basicly, some motherboard chipsets are able to 73 * split a 32 bit I/O operation into two 16 bit I/O operations, 74 * transparently to the processor. This speeds up some things, notably long 75 * data transfers. 76 */ 77 #define AIC_USE_DWORDS 0 78 79 /* Synchronous data transfers? */ 80 #define AIC_USE_SYNCHRONOUS 0 81 #define AIC_SYNC_REQ_ACK_OFS 8 82 83 /* Wide data transfers? */ 84 #define AIC_USE_WIDE 0 85 #define AIC_MAX_WIDTH 0 86 87 /* Max attempts made to transmit a message */ 88 #define AIC_MSG_MAX_ATTEMPT 3 /* Not used now XXX */ 89 90 /* Use DMA (else we do programmed I/O using string instructions) (not yet!)*/ 91 #define AIC_USE_EISA_DMA 0 92 #define AIC_USE_ISA_DMA 0 93 94 /* How to behave on the (E)ISA bus when/if DMAing (on<<4) + off in us */ 95 #define EISA_BRST_TIM ((15<<4) + 1) /* 15us on, 1us off */ 96 97 /* Some spin loop parameters (essentially how long to wait some places) 98 * The problem(?) is that sometimes we expect either to be able to transmit a 99 * byte or to get a new one from the SCSI bus pretty soon. In order to avoid 100 * returning from the interrupt just to get yanked back for the next byte we 101 * may spin in the interrupt routine waiting for this byte to come. How long? 102 * This is really (SCSI) device and processor dependent. Tuneable, I guess. 103 */ 104 #define AIC_MSGIN_SPIN 1 /* Spin upto ?ms for a new msg byte */ 105 #define AIC_MSGOUT_SPIN 1 106 107 /* Include debug functions? At the end of this file there are a bunch of 108 * functions that will print out various information regarding queued SCSI 109 * commands, driver state and chip contents. You can call them from the 110 * kernel debugger. If you set AIC_DEBUG to 0 they are not included (the 111 * kernel uses less memory) but you lose the debugging facilities. 112 */ 113 #ifndef SMALL_KERNEL 114 #define AIC_DEBUG 1 115 #endif 116 117 #define AIC_ABORT_TIMEOUT 2000 /* time to wait for abort */ 118 119 /* End of customizable parameters */ 120 121 #if AIC_USE_EISA_DMA || AIC_USE_ISA_DMA 122 #error "I said not yet! Start paying attention... grumble" 123 #endif 124 125 #include <sys/types.h> 126 #include <sys/param.h> 127 #include <sys/systm.h> 128 #include <sys/kernel.h> 129 #include <sys/errno.h> 130 #include <sys/ioctl.h> 131 #include <sys/device.h> 132 #include <sys/buf.h> 133 #include <sys/queue.h> 134 135 #include <machine/bus.h> 136 #include <machine/intr.h> 137 138 #include <scsi/scsi_all.h> 139 #include <scsi/scsi_message.h> 140 #include <scsi/scsiconf.h> 141 142 #include <dev/isa/isavar.h> 143 144 #include <dev/ic/aic6360reg.h> 145 #include <dev/ic/aic6360var.h> 146 147 #ifndef DDB 148 #define Debugger() panic("should call debugger here (aic6360.c)") 149 #endif /* ! DDB */ 150 151 #ifdef AIC_DEBUG 152 int aic_debug = 0x00; /* AIC_SHOWSTART|AIC_SHOWMISC|AIC_SHOWTRACE; */ 153 #endif 154 155 void aic_minphys(struct buf *, struct scsi_link *); 156 void aic_init(struct aic_softc *); 157 void aic_done(struct aic_softc *, struct aic_acb *); 158 void aic_dequeue(struct aic_softc *, struct aic_acb *); 159 void aic_scsi_cmd(struct scsi_xfer *); 160 int aic_poll(struct aic_softc *, struct scsi_xfer *, int); 161 integrate void aic_sched_msgout(struct aic_softc *, u_char); 162 integrate void aic_setsync(struct aic_softc *, struct aic_tinfo *); 163 void aic_select(struct aic_softc *, struct aic_acb *); 164 void aic_timeout(void *); 165 void aic_sched(struct aic_softc *); 166 void aic_scsi_reset(struct aic_softc *); 167 void aic_reset(struct aic_softc *); 168 void aic_acb_free(void *, void *); 169 void *aic_acb_alloc(void *); 170 int aic_reselect(struct aic_softc *, int); 171 void aic_sense(struct aic_softc *, struct aic_acb *); 172 void aic_msgin(struct aic_softc *); 173 void aic_abort(struct aic_softc *, struct aic_acb *); 174 void aic_msgout(struct aic_softc *); 175 int aic_dataout_pio(struct aic_softc *, u_char *, int); 176 int aic_datain_pio(struct aic_softc *, u_char *, int); 177 #ifdef AIC_DEBUG 178 void aic_print_acb(struct aic_acb *); 179 void aic_dump_driver(struct aic_softc *); 180 void aic_dump6360(struct aic_softc *); 181 void aic_show_scsi_cmd(struct aic_acb *); 182 void aic_print_active_acb(void); 183 #endif 184 185 struct cfdriver aic_cd = { 186 NULL, "aic", DV_DULL 187 }; 188 189 struct scsi_adapter aic_switch = { 190 aic_scsi_cmd, 191 #ifdef notyet 192 aic_minphys, 193 #else 194 scsi_minphys, 195 #endif 196 0, 197 0, 198 }; 199 200 /* 201 * Do the real search-for-device. 202 */ 203 int 204 aic_find(bus_space_tag_t iot, bus_space_handle_t ioh) 205 { 206 char chip_id[sizeof(IDSTRING)]; /* For chips that support it */ 207 int i; 208 209 /* Remove aic6360 from possible powerdown mode */ 210 bus_space_write_1(iot, ioh, DMACNTRL0, 0); 211 212 /* Thanks to mark@aggregate.com for the new method for detecting 213 * whether the chip is present or not. Bonus: may also work for 214 * the AIC-6260! 215 */ 216 AIC_TRACE(("aic: probing for aic-chip\n")); 217 /* 218 * Linux also init's the stack to 1-16 and then clears it, 219 * 6260's don't appear to have an ID reg - mpg 220 */ 221 /* Push the sequence 0,1,..,15 on the stack */ 222 #define STSIZE 16 223 bus_space_write_1(iot, ioh, DMACNTRL1, 0); /* Reset stack pointer */ 224 for (i = 0; i < STSIZE; i++) 225 bus_space_write_1(iot, ioh, STACK, i); 226 227 /* See if we can pull out the same sequence */ 228 bus_space_write_1(iot, ioh, DMACNTRL1, 0); 229 for (i = 0; i < STSIZE && bus_space_read_1(iot, ioh, STACK) == i; i++) 230 ; 231 if (i != STSIZE) { 232 AIC_START(("STACK futzed at %d.\n", i)); 233 return (0); 234 } 235 236 /* See if we can pull the id string out of the ID register, 237 * now only used for informational purposes. 238 */ 239 bzero(chip_id, sizeof(chip_id)); 240 bus_space_read_multi_1(iot, ioh, ID, chip_id, sizeof(IDSTRING) - 1); 241 AIC_START(("AIC ID: %s ", chip_id)); 242 AIC_START(("chip revision %d\n", 243 (int)bus_space_read_1(iot, ioh, REV))); 244 245 return (1); 246 } 247 248 /* 249 * Attach the AIC6360, fill out some high and low level data structures 250 */ 251 void 252 aicattach(struct aic_softc *sc) 253 { 254 struct scsibus_attach_args saa; 255 AIC_TRACE(("aicattach ")); 256 sc->sc_state = AIC_INIT; 257 258 sc->sc_initiator = 7; 259 sc->sc_freq = 20; /* XXXX assume 20 MHz. */ 260 261 /* 262 * These are the bounds of the sync period, based on the frequency of 263 * the chip's clock input and the size and offset of the sync period 264 * register. 265 * 266 * For a 20MHz clock, this gives us 25, or 100nS, or 10MB/s, as a 267 * maximum transfer rate, and 112.5, or 450nS, or 2.22MB/s, as a 268 * minimum transfer rate. 269 */ 270 sc->sc_minsync = (2 * 250) / sc->sc_freq; 271 sc->sc_maxsync = (9 * 250) / sc->sc_freq; 272 273 aic_init(sc); /* init chip and driver */ 274 275 /* 276 * Fill in the prototype scsi_link 277 */ 278 sc->sc_link.adapter_softc = sc; 279 sc->sc_link.adapter_target = sc->sc_initiator; 280 sc->sc_link.adapter = &aic_switch; 281 sc->sc_link.openings = 2; 282 sc->sc_link.pool = &sc->sc_iopool; 283 284 bzero(&saa, sizeof(saa)); 285 saa.saa_sc_link = &sc->sc_link; 286 287 config_found(&sc->sc_dev, &saa, scsiprint); 288 } 289 290 int 291 aic_detach(struct device *self, int flags) 292 { 293 struct aic_softc *sc = (struct aic_softc *) self; 294 int rv = 0; 295 296 rv = config_detach_children(&sc->sc_dev, flags); 297 298 return (rv); 299 } 300 301 /* Initialize AIC6360 chip itself 302 * The following conditions should hold: 303 * aicprobe should have succeeded, i.e. the ioh handle in aic_softc must 304 * be valid. 305 */ 306 void 307 aic_reset(struct aic_softc *sc) 308 { 309 bus_space_tag_t iot = sc->sc_iot; 310 bus_space_handle_t ioh = sc->sc_ioh; 311 312 /* 313 * Doc. recommends to clear these two registers before operations 314 * commence 315 */ 316 bus_space_write_1(iot, ioh, SCSITEST, 0); 317 bus_space_write_1(iot, ioh, TEST, 0); 318 319 /* Reset SCSI-FIFO and abort any transfers */ 320 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN | CLRCH | CLRSTCNT); 321 322 /* Reset DMA-FIFO */ 323 bus_space_write_1(iot, ioh, DMACNTRL0, RSTFIFO); 324 bus_space_write_1(iot, ioh, DMACNTRL1, 0); 325 326 /* Disable all selection features */ 327 bus_space_write_1(iot, ioh, SCSISEQ, 0); 328 bus_space_write_1(iot, ioh, SXFRCTL1, 0); 329 330 /* Disable some interrupts */ 331 bus_space_write_1(iot, ioh, SIMODE0, 0x00); 332 /* Clear a slew of interrupts */ 333 bus_space_write_1(iot, ioh, CLRSINT0, 0x7f); 334 335 /* Disable some more interrupts */ 336 bus_space_write_1(iot, ioh, SIMODE1, 0x00); 337 /* Clear another slew of interrupts */ 338 bus_space_write_1(iot, ioh, CLRSINT1, 0xef); 339 340 /* Disable synchronous transfers */ 341 bus_space_write_1(iot, ioh, SCSIRATE, 0); 342 343 /* Haven't seen ant errors (yet) */ 344 bus_space_write_1(iot, ioh, CLRSERR, 0x07); 345 346 /* Set our SCSI-ID */ 347 bus_space_write_1(iot, ioh, SCSIID, sc->sc_initiator << OID_S); 348 bus_space_write_1(iot, ioh, BRSTCNTRL, EISA_BRST_TIM); 349 } 350 351 /* Pull the SCSI RST line for 500 us */ 352 void 353 aic_scsi_reset(struct aic_softc *sc) 354 { 355 bus_space_tag_t iot = sc->sc_iot; 356 bus_space_handle_t ioh = sc->sc_ioh; 357 358 bus_space_write_1(iot, ioh, SCSISEQ, SCSIRSTO); 359 delay(500); 360 bus_space_write_1(iot, ioh, SCSISEQ, 0); 361 delay(50); 362 } 363 364 /* 365 * Initialize aic SCSI driver. 366 */ 367 void 368 aic_init(struct aic_softc *sc) 369 { 370 bus_space_tag_t iot = sc->sc_iot; 371 bus_space_handle_t ioh = sc->sc_ioh; 372 struct aic_acb *acb; 373 int r; 374 375 aic_reset(sc); 376 aic_scsi_reset(sc); 377 aic_reset(sc); 378 379 if (sc->sc_state == AIC_INIT) { 380 /* First time through; initialize. */ 381 TAILQ_INIT(&sc->ready_list); 382 TAILQ_INIT(&sc->nexus_list); 383 TAILQ_INIT(&sc->free_list); 384 mtx_init(&sc->sc_acb_mtx, IPL_BIO); 385 scsi_iopool_init(&sc->sc_iopool, sc, aic_acb_alloc, 386 aic_acb_free); 387 sc->sc_nexus = NULL; 388 acb = sc->sc_acb; 389 bzero(acb, sizeof(sc->sc_acb)); 390 for (r = 0; r < sizeof(sc->sc_acb) / sizeof(*acb); r++) { 391 TAILQ_INSERT_TAIL(&sc->free_list, acb, chain); 392 acb++; 393 } 394 bzero(&sc->sc_tinfo, sizeof(sc->sc_tinfo)); 395 } else { 396 /* Cancel any active commands. */ 397 sc->sc_state = AIC_CLEANING; 398 if ((acb = sc->sc_nexus) != NULL) { 399 acb->xs->error = XS_DRIVER_STUFFUP; 400 timeout_del(&acb->xs->stimeout); 401 aic_done(sc, acb); 402 } 403 while ((acb = TAILQ_FIRST(&sc->nexus_list)) != NULL) { 404 acb->xs->error = XS_DRIVER_STUFFUP; 405 timeout_del(&acb->xs->stimeout); 406 aic_done(sc, acb); 407 } 408 } 409 410 sc->sc_prevphase = PH_INVALID; 411 for (r = 0; r < 8; r++) { 412 struct aic_tinfo *ti = &sc->sc_tinfo[r]; 413 414 ti->flags = 0; 415 #if AIC_USE_SYNCHRONOUS 416 ti->flags |= DO_SYNC; 417 ti->period = sc->sc_minsync; 418 ti->offset = AIC_SYNC_REQ_ACK_OFS; 419 #else 420 ti->period = ti->offset = 0; 421 #endif 422 #if AIC_USE_WIDE 423 ti->flags |= DO_WIDE; 424 ti->width = AIC_MAX_WIDTH; 425 #else 426 ti->width = 0; 427 #endif 428 } 429 430 sc->sc_state = AIC_IDLE; 431 bus_space_write_1(iot, ioh, DMACNTRL0, INTEN); 432 } 433 434 void 435 aic_acb_free(void *xsc, void *xacb) 436 { 437 struct aic_softc *sc = xsc; 438 struct aic_acb *acb = xacb; 439 440 mtx_enter(&sc->sc_acb_mtx); 441 acb->flags = 0; 442 TAILQ_INSERT_HEAD(&sc->free_list, acb, chain); 443 mtx_leave(&sc->sc_acb_mtx); 444 } 445 446 void * 447 aic_acb_alloc(void *xsc) 448 { 449 struct aic_softc *sc = xsc; 450 struct aic_acb *acb; 451 452 mtx_enter(&sc->sc_acb_mtx); 453 acb = TAILQ_FIRST(&sc->free_list); 454 if (acb) { 455 TAILQ_REMOVE(&sc->free_list, acb, chain); 456 acb->flags |= ACB_ALLOC; 457 } 458 mtx_leave(&sc->sc_acb_mtx); 459 460 return acb; 461 } 462 463 /* 464 * DRIVER FUNCTIONS CALLABLE FROM HIGHER LEVEL DRIVERS 465 */ 466 467 /* 468 * Expected sequence: 469 * 1) Command inserted into ready list 470 * 2) Command selected for execution 471 * 3) Command won arbitration and has selected target device 472 * 4) Send message out (identify message, eventually also sync.negotiations) 473 * 5) Send command 474 * 5a) Receive disconnect message, disconnect. 475 * 5b) Reselected by target 476 * 5c) Receive identify message from target. 477 * 6) Send or receive data 478 * 7) Receive status 479 * 8) Receive message (command complete etc.) 480 * 9) If status == SCSI_CHECK construct a synthetic request sense SCSI cmd. 481 * Repeat 2-8 (no disconnects please...) 482 */ 483 484 /* 485 * Start a SCSI-command 486 * This function is called by the higher level SCSI-driver to queue/run 487 * SCSI-commands. 488 */ 489 void 490 aic_scsi_cmd(struct scsi_xfer *xs) 491 { 492 struct scsi_link *sc_link = xs->sc_link; 493 struct aic_softc *sc = sc_link->adapter_softc; 494 struct aic_acb *acb; 495 int s, flags; 496 497 AIC_TRACE(("aic_scsi_cmd ")); 498 AIC_CMDS(("[0x%x, %d]->%d ", (int)xs->cmd->opcode, xs->cmdlen, 499 sc_link->target)); 500 501 flags = xs->flags; 502 acb = xs->io; 503 504 /* Initialize acb */ 505 acb->xs = xs; 506 acb->timeout = xs->timeout; 507 timeout_set(&xs->stimeout, aic_timeout, acb); 508 509 if (xs->flags & SCSI_RESET) { 510 acb->flags |= ACB_RESET; 511 acb->scsi_cmd_length = 0; 512 acb->data_length = 0; 513 } else { 514 bcopy(xs->cmd, &acb->scsi_cmd, xs->cmdlen); 515 acb->scsi_cmd_length = xs->cmdlen; 516 acb->data_addr = xs->data; 517 acb->data_length = xs->datalen; 518 } 519 acb->target_stat = 0; 520 521 s = splbio(); 522 523 TAILQ_INSERT_TAIL(&sc->ready_list, acb, chain); 524 if (sc->sc_state == AIC_IDLE) 525 aic_sched(sc); 526 527 splx(s); 528 529 if ((flags & SCSI_POLL) == 0) 530 return; 531 532 /* Not allowed to use interrupts, use polling instead */ 533 if (aic_poll(sc, xs, acb->timeout)) { 534 aic_timeout(acb); 535 if (aic_poll(sc, xs, acb->timeout)) 536 aic_timeout(acb); 537 } 538 } 539 540 #ifdef notyet 541 /* 542 * Adjust transfer size in buffer structure 543 */ 544 void 545 aic_minphys(struct buf *bp, struct scsi_link *sl) 546 { 547 548 AIC_TRACE(("aic_minphys ")); 549 if (bp->b_bcount > (AIC_NSEG << PGSHIFT)) 550 bp->b_bcount = (AIC_NSEG << PGSHIFT); 551 minphys(bp); 552 } 553 #endif 554 555 /* 556 * Used when interrupt driven I/O isn't allowed, e.g. during boot. 557 */ 558 int 559 aic_poll(struct aic_softc *sc, struct scsi_xfer *xs, int count) 560 { 561 bus_space_tag_t iot = sc->sc_iot; 562 bus_space_handle_t ioh = sc->sc_ioh; 563 int s; 564 565 AIC_TRACE(("aic_poll ")); 566 while (count) { 567 /* 568 * If we had interrupts enabled, would we 569 * have got an interrupt? 570 */ 571 if ((bus_space_read_1(iot, ioh, DMASTAT) & INTSTAT) != 0) { 572 s = splbio(); 573 aicintr(sc); 574 splx(s); 575 } 576 if ((xs->flags & ITSDONE) != 0) 577 return 0; 578 delay(1000); 579 count--; 580 } 581 return 1; 582 } 583 584 /* 585 * LOW LEVEL SCSI UTILITIES 586 */ 587 588 integrate void 589 aic_sched_msgout(struct aic_softc *sc, u_char m) 590 { 591 bus_space_tag_t iot = sc->sc_iot; 592 bus_space_handle_t ioh = sc->sc_ioh; 593 594 if (sc->sc_msgpriq == 0) 595 bus_space_write_1(iot, ioh, SCSISIG, sc->sc_phase | ATNO); 596 sc->sc_msgpriq |= m; 597 } 598 599 /* 600 * Set synchronous transfer offset and period. 601 */ 602 integrate void 603 aic_setsync(struct aic_softc *sc, struct aic_tinfo *ti) 604 { 605 #if AIC_USE_SYNCHRONOUS 606 bus_space_tag_t iot = sc->sc_iot; 607 bus_space_handle_t ioh = sc->sc_ioh; 608 609 if (ti->offset != 0) 610 bus_space_write_1(iot, ioh, SCSIRATE, 611 ((ti->period * sc->sc_freq) / 250 - 2) << 4 | ti->offset); 612 else 613 bus_space_write_1(iot, ioh, SCSIRATE, 0); 614 #endif 615 } 616 617 /* 618 * Start a selection. This is used by aic_sched() to select an idle target, 619 * and by aic_done() to immediately reselect a target to get sense information. 620 */ 621 void 622 aic_select(struct aic_softc *sc, struct aic_acb *acb) 623 { 624 bus_space_tag_t iot = sc->sc_iot; 625 bus_space_handle_t ioh = sc->sc_ioh; 626 struct scsi_link *sc_link = acb->xs->sc_link; 627 int target = sc_link->target; 628 struct aic_tinfo *ti = &sc->sc_tinfo[target]; 629 630 bus_space_write_1(iot, ioh, SCSIID, 631 sc->sc_initiator << OID_S | target); 632 aic_setsync(sc, ti); 633 bus_space_write_1(iot, ioh, SXFRCTL1, STIMO_256ms | ENSTIMER); 634 635 /* Always enable reselections. */ 636 bus_space_write_1(iot, ioh, SIMODE0, ENSELDI | ENSELDO); 637 bus_space_write_1(iot, ioh, SIMODE1, ENSCSIRST | ENSELTIMO); 638 bus_space_write_1(iot, ioh, SCSISEQ, ENRESELI | ENSELO | ENAUTOATNO); 639 640 sc->sc_state = AIC_SELECTING; 641 } 642 643 int 644 aic_reselect(struct aic_softc *sc, int message) 645 { 646 u_char selid, target, lun; 647 struct aic_acb *acb; 648 struct scsi_link *sc_link; 649 struct aic_tinfo *ti; 650 651 /* 652 * The SCSI chip made a snapshot of the data bus while the reselection 653 * was being negotiated. This enables us to determine which target did 654 * the reselect. 655 */ 656 selid = sc->sc_selid & ~(1 << sc->sc_initiator); 657 if (selid & (selid - 1)) { 658 printf("%s: reselect with invalid selid %02x; ", 659 sc->sc_dev.dv_xname, selid); 660 printf("sending DEVICE RESET\n"); 661 AIC_BREAK(); 662 goto reset; 663 } 664 665 /* Search wait queue for disconnected cmd 666 * The list should be short, so I haven't bothered with 667 * any more sophisticated structures than a simple 668 * singly linked list. 669 */ 670 target = ffs(selid) - 1; 671 lun = message & 0x07; 672 TAILQ_FOREACH(acb, &sc->nexus_list, chain) { 673 sc_link = acb->xs->sc_link; 674 if (sc_link->target == target && sc_link->lun == lun) 675 break; 676 } 677 if (acb == NULL) { 678 printf("%s: reselect from target %d lun %d with no nexus; ", 679 sc->sc_dev.dv_xname, target, lun); 680 printf("sending ABORT\n"); 681 AIC_BREAK(); 682 goto abort; 683 } 684 685 /* Make this nexus active again. */ 686 TAILQ_REMOVE(&sc->nexus_list, acb, chain); 687 sc->sc_state = AIC_CONNECTED; 688 sc->sc_nexus = acb; 689 ti = &sc->sc_tinfo[target]; 690 ti->lubusy |= (1 << lun); 691 aic_setsync(sc, ti); 692 693 if (acb->flags & ACB_RESET) 694 aic_sched_msgout(sc, SEND_DEV_RESET); 695 else if (acb->flags & ACB_ABORT) 696 aic_sched_msgout(sc, SEND_ABORT); 697 698 /* Do an implicit RESTORE POINTERS. */ 699 sc->sc_dp = acb->data_addr; 700 sc->sc_dleft = acb->data_length; 701 sc->sc_cp = (u_char *)&acb->scsi_cmd; 702 sc->sc_cleft = acb->scsi_cmd_length; 703 704 return (0); 705 706 reset: 707 aic_sched_msgout(sc, SEND_DEV_RESET); 708 return (1); 709 710 abort: 711 aic_sched_msgout(sc, SEND_ABORT); 712 return (1); 713 } 714 715 /* 716 * Schedule a SCSI operation. This has now been pulled out of the interrupt 717 * handler so that we may call it from aic_scsi_cmd and aic_done. This may 718 * save us an unnecessary interrupt just to get things going. Should only be 719 * called when state == AIC_IDLE and at bio pl. 720 */ 721 void 722 aic_sched(struct aic_softc *sc) 723 { 724 bus_space_tag_t iot = sc->sc_iot; 725 bus_space_handle_t ioh = sc->sc_ioh; 726 struct aic_acb *acb; 727 struct scsi_link *sc_link; 728 struct aic_tinfo *ti; 729 730 /* 731 * Find first acb in ready queue that is for a target/lunit pair that 732 * is not busy. 733 */ 734 bus_space_write_1(iot, ioh, CLRSINT1, 735 CLRSELTIMO | CLRBUSFREE | CLRSCSIPERR); 736 TAILQ_FOREACH(acb, &sc->ready_list, chain) { 737 sc_link = acb->xs->sc_link; 738 ti = &sc->sc_tinfo[sc_link->target]; 739 if ((ti->lubusy & (1 << sc_link->lun)) == 0) { 740 AIC_MISC(("selecting %d:%d ", 741 sc_link->target, sc_link->lun)); 742 TAILQ_REMOVE(&sc->ready_list, acb, chain); 743 sc->sc_nexus = acb; 744 aic_select(sc, acb); 745 return; 746 } else 747 AIC_MISC(("%d:%d busy\n", 748 sc_link->target, sc_link->lun)); 749 } 750 AIC_MISC(("idle ")); 751 /* Nothing to start; just enable reselections and wait. */ 752 bus_space_write_1(iot, ioh, SIMODE0, ENSELDI); 753 bus_space_write_1(iot, ioh, SIMODE1, ENSCSIRST); 754 bus_space_write_1(iot, ioh, SCSISEQ, ENRESELI); 755 } 756 757 void 758 aic_sense(struct aic_softc *sc, struct aic_acb *acb) 759 { 760 struct scsi_xfer *xs = acb->xs; 761 struct scsi_link *sc_link = xs->sc_link; 762 struct aic_tinfo *ti = &sc->sc_tinfo[sc_link->target]; 763 struct scsi_sense *ss = (void *)&acb->scsi_cmd; 764 765 AIC_MISC(("requesting sense ")); 766 /* Next, setup a request sense command block */ 767 bzero(ss, sizeof(*ss)); 768 ss->opcode = REQUEST_SENSE; 769 ss->byte2 = sc_link->lun << 5; 770 ss->length = sizeof(struct scsi_sense_data); 771 acb->scsi_cmd_length = sizeof(*ss); 772 acb->data_addr = (char *)&xs->sense; 773 acb->data_length = sizeof(struct scsi_sense_data); 774 acb->flags |= ACB_SENSE; 775 ti->senses++; 776 if (acb->flags & ACB_NEXUS) 777 ti->lubusy &= ~(1 << sc_link->lun); 778 if (acb == sc->sc_nexus) { 779 aic_select(sc, acb); 780 } else { 781 aic_dequeue(sc, acb); 782 TAILQ_INSERT_HEAD(&sc->ready_list, acb, chain); 783 if (sc->sc_state == AIC_IDLE) 784 aic_sched(sc); 785 } 786 } 787 788 /* 789 * POST PROCESSING OF SCSI_CMD (usually current) 790 */ 791 void 792 aic_done(struct aic_softc *sc, struct aic_acb *acb) 793 { 794 struct scsi_xfer *xs = acb->xs; 795 struct scsi_link *sc_link = xs->sc_link; 796 struct aic_tinfo *ti = &sc->sc_tinfo[sc_link->target]; 797 798 AIC_TRACE(("aic_done ")); 799 800 /* 801 * Now, if we've come here with no error code, i.e. we've kept the 802 * initial XS_NOERROR, and the status code signals that we should 803 * check sense, we'll need to set up a request sense cmd block and 804 * push the command back into the ready queue *before* any other 805 * commands for this target/lunit, else we lose the sense info. 806 * We don't support chk sense conditions for the request sense cmd. 807 */ 808 if (xs->error == XS_NOERROR) { 809 if (acb->flags & ACB_ABORT) { 810 xs->error = XS_DRIVER_STUFFUP; 811 } else if (acb->flags & ACB_SENSE) { 812 xs->error = XS_SENSE; 813 } else if (acb->target_stat == SCSI_CHECK) { 814 /* First, save the return values */ 815 xs->resid = acb->data_length; 816 xs->status = acb->target_stat; 817 aic_sense(sc, acb); 818 return; 819 } else { 820 xs->resid = acb->data_length; 821 } 822 } 823 824 #ifdef AIC_DEBUG 825 if ((aic_debug & AIC_SHOWMISC) != 0) { 826 if (xs->resid != 0) 827 printf("resid=%lu ", (u_long)xs->resid); 828 if (xs->error == XS_SENSE) 829 printf("sense=0x%02x\n", xs->sense.error_code); 830 else 831 printf("error=%d\n", xs->error); 832 } 833 #endif 834 835 /* 836 * Remove the ACB from whatever queue it happens to be on. 837 */ 838 if (acb->flags & ACB_NEXUS) 839 ti->lubusy &= ~(1 << sc_link->lun); 840 if (acb == sc->sc_nexus) { 841 sc->sc_nexus = NULL; 842 sc->sc_state = AIC_IDLE; 843 aic_sched(sc); 844 } else 845 aic_dequeue(sc, acb); 846 847 ti->cmds++; 848 scsi_done(xs); 849 } 850 851 void 852 aic_dequeue(struct aic_softc *sc, struct aic_acb *acb) 853 { 854 855 if (acb->flags & ACB_NEXUS) { 856 TAILQ_REMOVE(&sc->nexus_list, acb, chain); 857 } else { 858 TAILQ_REMOVE(&sc->ready_list, acb, chain); 859 } 860 } 861 862 /* 863 * INTERRUPT/PROTOCOL ENGINE 864 */ 865 866 /* 867 * Precondition: 868 * The SCSI bus is already in the MSGI phase and there is a message byte 869 * on the bus, along with an asserted REQ signal. 870 */ 871 void 872 aic_msgin(struct aic_softc *sc) 873 { 874 bus_space_tag_t iot = sc->sc_iot; 875 bus_space_handle_t ioh = sc->sc_ioh; 876 u_char sstat1; 877 int n; 878 879 AIC_TRACE(("aic_msgin ")); 880 881 if (sc->sc_prevphase == PH_MSGIN) { 882 /* This is a continuation of the previous message. */ 883 n = sc->sc_imp - sc->sc_imess; 884 goto nextbyte; 885 } 886 887 /* This is a new MESSAGE IN phase. Clean up our state. */ 888 sc->sc_flags &= ~AIC_DROP_MSGIN; 889 890 nextmsg: 891 n = 0; 892 sc->sc_imp = &sc->sc_imess[n]; 893 894 nextbyte: 895 /* 896 * Read a whole message, but don't ack the last byte. If we reject the 897 * message, we have to assert ATN during the message transfer phase 898 * itself. 899 */ 900 for (;;) { 901 for (;;) { 902 sstat1 = bus_space_read_1(iot, ioh, SSTAT1); 903 if ((sstat1 & (REQINIT | PHASECHG | BUSFREE)) != 0) 904 break; 905 /* Wait for REQINIT. XXX Need timeout. */ 906 } 907 if ((sstat1 & (PHASECHG | BUSFREE)) != 0) { 908 /* 909 * Target left MESSAGE IN, probably because it 910 * a) noticed our ATN signal, or 911 * b) ran out of messages. 912 */ 913 goto out; 914 } 915 916 /* If parity error, just dump everything on the floor. */ 917 if ((sstat1 & SCSIPERR) != 0) { 918 sc->sc_flags |= AIC_DROP_MSGIN; 919 aic_sched_msgout(sc, SEND_PARITY_ERROR); 920 } 921 922 /* Gather incoming message bytes if needed. */ 923 if ((sc->sc_flags & AIC_DROP_MSGIN) == 0) { 924 if (n >= AIC_MAX_MSG_LEN) { 925 (void) bus_space_read_1(iot, ioh, SCSIDAT); 926 sc->sc_flags |= AIC_DROP_MSGIN; 927 aic_sched_msgout(sc, SEND_REJECT); 928 } else { 929 *sc->sc_imp++ = bus_space_read_1(iot, ioh, 930 SCSIDAT); 931 n++; 932 /* 933 * This testing is suboptimal, but most 934 * messages will be of the one byte variety, so 935 * it should not affect performance 936 * significantly. 937 */ 938 if (n == 1 && IS1BYTEMSG(sc->sc_imess[0])) 939 break; 940 if (n == 2 && IS2BYTEMSG(sc->sc_imess[0])) 941 break; 942 if (n >= 3 && ISEXTMSG(sc->sc_imess[0]) && 943 n == sc->sc_imess[1] + 2) 944 break; 945 } 946 } else 947 (void) bus_space_read_1(iot, ioh, SCSIDAT); 948 949 /* 950 * If we reach this spot we're either: 951 * a) in the middle of a multi-byte message, or 952 * b) dropping bytes. 953 */ 954 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN | SPIOEN); 955 /* Ack the last byte read. */ 956 (void) bus_space_read_1(iot, ioh, SCSIDAT); 957 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN); 958 while ((bus_space_read_1(iot, ioh, SCSISIG) & ACKI) != 0) 959 ; 960 } 961 962 AIC_MISC(("n=%d imess=0x%02x ", n, sc->sc_imess[0])); 963 964 /* We now have a complete message. Parse it. */ 965 switch (sc->sc_state) { 966 struct aic_acb *acb; 967 struct scsi_link *sc_link; 968 struct aic_tinfo *ti; 969 970 case AIC_CONNECTED: 971 AIC_ASSERT(sc->sc_nexus != NULL); 972 acb = sc->sc_nexus; 973 ti = &sc->sc_tinfo[acb->xs->sc_link->target]; 974 975 switch (sc->sc_imess[0]) { 976 case MSG_CMDCOMPLETE: 977 if ((long)sc->sc_dleft < 0) { 978 sc_link = acb->xs->sc_link; 979 printf("%s: %lu extra bytes from %d:%d\n", 980 sc->sc_dev.dv_xname, (u_long)-sc->sc_dleft, 981 sc_link->target, sc_link->lun); 982 acb->data_length = 0; 983 } 984 acb->xs->resid = acb->data_length = sc->sc_dleft; 985 sc->sc_state = AIC_CMDCOMPLETE; 986 break; 987 988 case MSG_PARITY_ERROR: 989 /* Resend the last message. */ 990 aic_sched_msgout(sc, sc->sc_lastmsg); 991 break; 992 993 case MSG_MESSAGE_REJECT: 994 AIC_MISC(("message rejected %02x ", sc->sc_lastmsg)); 995 switch (sc->sc_lastmsg) { 996 #if AIC_USE_SYNCHRONOUS + AIC_USE_WIDE 997 case SEND_IDENTIFY: 998 ti->flags &= ~(DO_SYNC | DO_WIDE); 999 ti->period = ti->offset = 0; 1000 aic_setsync(sc, ti); 1001 ti->width = 0; 1002 break; 1003 #endif 1004 #if AIC_USE_SYNCHRONOUS 1005 case SEND_SDTR: 1006 ti->flags &= ~DO_SYNC; 1007 ti->period = ti->offset = 0; 1008 aic_setsync(sc, ti); 1009 break; 1010 #endif 1011 #if AIC_USE_WIDE 1012 case SEND_WDTR: 1013 ti->flags &= ~DO_WIDE; 1014 ti->width = 0; 1015 break; 1016 #endif 1017 case SEND_INIT_DET_ERR: 1018 aic_sched_msgout(sc, SEND_ABORT); 1019 break; 1020 } 1021 break; 1022 1023 case MSG_NOOP: 1024 break; 1025 1026 case MSG_DISCONNECT: 1027 ti->dconns++; 1028 sc->sc_state = AIC_DISCONNECT; 1029 break; 1030 1031 case MSG_SAVEDATAPOINTER: 1032 acb->data_addr = sc->sc_dp; 1033 acb->data_length = sc->sc_dleft; 1034 break; 1035 1036 case MSG_RESTOREPOINTERS: 1037 sc->sc_dp = acb->data_addr; 1038 sc->sc_dleft = acb->data_length; 1039 sc->sc_cp = (u_char *)&acb->scsi_cmd; 1040 sc->sc_cleft = acb->scsi_cmd_length; 1041 break; 1042 1043 case MSG_EXTENDED: 1044 switch (sc->sc_imess[2]) { 1045 #if AIC_USE_SYNCHRONOUS 1046 case MSG_EXT_SDTR: 1047 if (sc->sc_imess[1] != 3) 1048 goto reject; 1049 ti->period = sc->sc_imess[3]; 1050 ti->offset = sc->sc_imess[4]; 1051 ti->flags &= ~DO_SYNC; 1052 if (ti->offset == 0) { 1053 } else if (ti->period < sc->sc_minsync || 1054 ti->period > sc->sc_maxsync || 1055 ti->offset > 8) { 1056 ti->period = ti->offset = 0; 1057 aic_sched_msgout(sc, SEND_SDTR); 1058 } else { 1059 sc_print_addr(acb->xs->sc_link); 1060 printf("sync, offset %d, ", 1061 ti->offset); 1062 printf("period %dnsec\n", 1063 ti->period * 4); 1064 } 1065 aic_setsync(sc, ti); 1066 break; 1067 #endif 1068 1069 #if AIC_USE_WIDE 1070 case MSG_EXT_WDTR: 1071 if (sc->sc_imess[1] != 2) 1072 goto reject; 1073 ti->width = sc->sc_imess[3]; 1074 ti->flags &= ~DO_WIDE; 1075 if (ti->width == 0) { 1076 } else if (ti->width > AIC_MAX_WIDTH) { 1077 ti->width = 0; 1078 aic_sched_msgout(sc, SEND_WDTR); 1079 } else { 1080 sc_print_addr(acb->xs->sc_link); 1081 printf("wide, width %d\n", 1082 1 << (3 + ti->width)); 1083 } 1084 break; 1085 #endif 1086 1087 default: 1088 printf("%s: unrecognized MESSAGE EXTENDED; ", 1089 sc->sc_dev.dv_xname); 1090 printf("sending REJECT\n"); 1091 AIC_BREAK(); 1092 goto reject; 1093 } 1094 break; 1095 1096 default: 1097 printf("%s: unrecognized MESSAGE; sending REJECT\n", 1098 sc->sc_dev.dv_xname); 1099 AIC_BREAK(); 1100 reject: 1101 aic_sched_msgout(sc, SEND_REJECT); 1102 break; 1103 } 1104 break; 1105 1106 case AIC_RESELECTED: 1107 if (!MSG_ISIDENTIFY(sc->sc_imess[0])) { 1108 printf("%s: reselect without IDENTIFY; ", 1109 sc->sc_dev.dv_xname); 1110 printf("sending DEVICE RESET\n"); 1111 AIC_BREAK(); 1112 goto reset; 1113 } 1114 1115 (void) aic_reselect(sc, sc->sc_imess[0]); 1116 break; 1117 1118 default: 1119 printf("%s: unexpected MESSAGE IN; sending DEVICE RESET\n", 1120 sc->sc_dev.dv_xname); 1121 AIC_BREAK(); 1122 reset: 1123 aic_sched_msgout(sc, SEND_DEV_RESET); 1124 break; 1125 1126 #ifdef notdef 1127 abort: 1128 aic_sched_msgout(sc, SEND_ABORT); 1129 break; 1130 #endif 1131 } 1132 1133 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN | SPIOEN); 1134 /* Ack the last message byte. */ 1135 (void) bus_space_read_1(iot, ioh, SCSIDAT); 1136 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN); 1137 while ((bus_space_read_1(iot, ioh, SCSISIG) & ACKI) != 0) 1138 ; 1139 1140 /* Go get the next message, if any. */ 1141 goto nextmsg; 1142 1143 out: 1144 AIC_MISC(("n=%d imess=0x%02x ", n, sc->sc_imess[0])); 1145 } 1146 1147 /* 1148 * Send the highest priority, scheduled message. 1149 */ 1150 void 1151 aic_msgout(struct aic_softc *sc) 1152 { 1153 bus_space_tag_t iot = sc->sc_iot; 1154 bus_space_handle_t ioh = sc->sc_ioh; 1155 #if AIC_USE_SYNCHRONOUS 1156 struct aic_tinfo *ti; 1157 #endif 1158 u_char sstat1; 1159 int n; 1160 1161 AIC_TRACE(("aic_msgout ")); 1162 1163 /* Reset the FIFO. */ 1164 bus_space_write_1(iot, ioh, DMACNTRL0, RSTFIFO); 1165 /* Enable REQ/ACK protocol. */ 1166 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN | SPIOEN); 1167 1168 if (sc->sc_prevphase == PH_MSGOUT) { 1169 if (sc->sc_omp == sc->sc_omess) { 1170 /* 1171 * This is a retransmission. 1172 * 1173 * We get here if the target stayed in MESSAGE OUT 1174 * phase. Section 5.1.9.2 of the SCSI 2 spec indicates 1175 * that all of the previously transmitted messages must 1176 * be sent again, in the same order. Therefore, we 1177 * requeue all the previously transmitted messages, and 1178 * start again from the top. Our simple priority 1179 * scheme keeps the messages in the right order. 1180 */ 1181 AIC_MISC(("retransmitting ")); 1182 sc->sc_msgpriq |= sc->sc_msgoutq; 1183 /* 1184 * Set ATN. If we're just sending a trivial 1-byte 1185 * message, we'll clear ATN later on anyway. 1186 */ 1187 bus_space_write_1(iot, ioh, SCSISIG, PH_MSGOUT | ATNO); 1188 } else { 1189 /* This is a continuation of the previous message. */ 1190 n = sc->sc_omp - sc->sc_omess; 1191 goto nextbyte; 1192 } 1193 } 1194 1195 /* No messages transmitted so far. */ 1196 sc->sc_msgoutq = 0; 1197 sc->sc_lastmsg = 0; 1198 1199 nextmsg: 1200 /* Pick up highest priority message. */ 1201 sc->sc_currmsg = sc->sc_msgpriq & -sc->sc_msgpriq; 1202 sc->sc_msgpriq &= ~sc->sc_currmsg; 1203 sc->sc_msgoutq |= sc->sc_currmsg; 1204 1205 /* Build the outgoing message data. */ 1206 switch (sc->sc_currmsg) { 1207 case SEND_IDENTIFY: 1208 AIC_ASSERT(sc->sc_nexus != NULL); 1209 sc->sc_omess[0] = 1210 MSG_IDENTIFY(sc->sc_nexus->xs->sc_link->lun, 1); 1211 n = 1; 1212 break; 1213 1214 #if AIC_USE_SYNCHRONOUS 1215 case SEND_SDTR: 1216 AIC_ASSERT(sc->sc_nexus != NULL); 1217 ti = &sc->sc_tinfo[sc->sc_nexus->xs->sc_link->target]; 1218 sc->sc_omess[4] = MSG_EXTENDED; 1219 sc->sc_omess[3] = 3; 1220 sc->sc_omess[2] = MSG_EXT_SDTR; 1221 sc->sc_omess[1] = ti->period >> 2; 1222 sc->sc_omess[0] = ti->offset; 1223 n = 5; 1224 break; 1225 #endif 1226 1227 #if AIC_USE_WIDE 1228 case SEND_WDTR: 1229 AIC_ASSERT(sc->sc_nexus != NULL); 1230 ti = &sc->sc_tinfo[sc->sc_nexus->xs->sc_link->target]; 1231 sc->sc_omess[3] = MSG_EXTENDED; 1232 sc->sc_omess[2] = 2; 1233 sc->sc_omess[1] = MSG_EXT_WDTR; 1234 sc->sc_omess[0] = ti->width; 1235 n = 4; 1236 break; 1237 #endif 1238 1239 case SEND_DEV_RESET: 1240 sc->sc_flags |= AIC_ABORTING; 1241 sc->sc_omess[0] = MSG_BUS_DEV_RESET; 1242 n = 1; 1243 break; 1244 1245 case SEND_REJECT: 1246 sc->sc_omess[0] = MSG_MESSAGE_REJECT; 1247 n = 1; 1248 break; 1249 1250 case SEND_PARITY_ERROR: 1251 sc->sc_omess[0] = MSG_PARITY_ERROR; 1252 n = 1; 1253 break; 1254 1255 case SEND_INIT_DET_ERR: 1256 sc->sc_omess[0] = MSG_INITIATOR_DET_ERR; 1257 n = 1; 1258 break; 1259 1260 case SEND_ABORT: 1261 sc->sc_flags |= AIC_ABORTING; 1262 sc->sc_omess[0] = MSG_ABORT; 1263 n = 1; 1264 break; 1265 1266 default: 1267 printf("%s: unexpected MESSAGE OUT; sending NOOP\n", 1268 sc->sc_dev.dv_xname); 1269 AIC_BREAK(); 1270 sc->sc_omess[0] = MSG_NOOP; 1271 n = 1; 1272 break; 1273 } 1274 sc->sc_omp = &sc->sc_omess[n]; 1275 1276 nextbyte: 1277 /* Send message bytes. */ 1278 for (;;) { 1279 for (;;) { 1280 sstat1 = bus_space_read_1(iot, ioh, SSTAT1); 1281 if ((sstat1 & (REQINIT | PHASECHG | BUSFREE)) != 0) 1282 break; 1283 /* Wait for REQINIT. XXX Need timeout. */ 1284 } 1285 if ((sstat1 & (PHASECHG | BUSFREE)) != 0) { 1286 /* 1287 * Target left MESSAGE OUT, possibly to reject 1288 * our message. 1289 * 1290 * If this is the last message being sent, then we 1291 * deassert ATN, since either the target is going to 1292 * ignore this message, or it's going to ask for a 1293 * retransmission via MESSAGE PARITY ERROR (in which 1294 * case we reassert ATN anyway). 1295 */ 1296 if (sc->sc_msgpriq == 0) 1297 bus_space_write_1(iot, ioh, CLRSINT1, CLRATNO); 1298 goto out; 1299 } 1300 1301 /* Clear ATN before last byte if this is the last message. */ 1302 if (n == 1 && sc->sc_msgpriq == 0) 1303 bus_space_write_1(iot, ioh, CLRSINT1, CLRATNO); 1304 /* Send message byte. */ 1305 bus_space_write_1(iot, ioh, SCSIDAT, *--sc->sc_omp); 1306 --n; 1307 /* Keep track of the last message we've sent any bytes of. */ 1308 sc->sc_lastmsg = sc->sc_currmsg; 1309 /* Wait for ACK to be negated. XXX Need timeout. */ 1310 while ((bus_space_read_1(iot, ioh, SCSISIG) & ACKI) != 0) 1311 ; 1312 1313 if (n == 0) 1314 break; 1315 } 1316 1317 /* We get here only if the entire message has been transmitted. */ 1318 if (sc->sc_msgpriq != 0) { 1319 /* There are more outgoing messages. */ 1320 goto nextmsg; 1321 } 1322 1323 /* 1324 * The last message has been transmitted. We need to remember the last 1325 * message transmitted (in case the target switches to MESSAGE IN phase 1326 * and sends a MESSAGE REJECT), and the list of messages transmitted 1327 * this time around (in case the target stays in MESSAGE OUT phase to 1328 * request a retransmit). 1329 */ 1330 1331 out: 1332 /* Disable REQ/ACK protocol. */ 1333 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN); 1334 } 1335 1336 /* aic_dataout_pio: perform a data transfer using the FIFO datapath in the aic6360 1337 * Precondition: The SCSI bus should be in the DOUT phase, with REQ asserted 1338 * and ACK deasserted (i.e. waiting for a data byte). 1339 * This new revision has been optimized (I tried) to make the common case fast, 1340 * and the rarer cases (as a result) somewhat more complex. 1341 */ 1342 int 1343 aic_dataout_pio(struct aic_softc *sc, u_char *p, int n) 1344 { 1345 bus_space_tag_t iot = sc->sc_iot; 1346 bus_space_handle_t ioh = sc->sc_ioh; 1347 u_char dmastat = 0; 1348 int out = 0; 1349 #define DOUTAMOUNT 128 /* Full FIFO */ 1350 1351 AIC_MISC(("%02x%02x ", bus_space_read_1(iot, ioh, FIFOSTAT), 1352 bus_space_read_1(iot, ioh, SSTAT2))); 1353 1354 /* Clear host FIFO and counter. */ 1355 bus_space_write_1(iot, ioh, DMACNTRL0, RSTFIFO | WRITE); 1356 /* Enable FIFOs. */ 1357 bus_space_write_1(iot, ioh, DMACNTRL0, ENDMA | DWORDPIO | WRITE); 1358 bus_space_write_1(iot, ioh, SXFRCTL0, SCSIEN | DMAEN | CHEN); 1359 1360 /* Turn off ENREQINIT for now. */ 1361 bus_space_write_1(iot, ioh, SIMODE1, 1362 ENSCSIRST | ENSCSIPERR | ENBUSFREE | ENPHASECHG); 1363 1364 /* I have tried to make the main loop as tight as possible. This 1365 * means that some of the code following the loop is a bit more 1366 * complex than otherwise. 1367 */ 1368 while (n > 0) { 1369 for (;;) { 1370 dmastat = bus_space_read_1(iot, ioh, DMASTAT); 1371 if ((dmastat & (DFIFOEMP | INTSTAT)) != 0) 1372 break; 1373 } 1374 1375 if ((dmastat & INTSTAT) != 0) 1376 goto phasechange; 1377 1378 if (n >= DOUTAMOUNT) { 1379 n -= DOUTAMOUNT; 1380 out += DOUTAMOUNT; 1381 1382 #if AIC_USE_DWORDS 1383 bus_space_write_multi_4(iot, ioh, DMADATALONG, 1384 (u_int32_t *)p, DOUTAMOUNT >> 2); 1385 #else 1386 bus_space_write_multi_2(iot, ioh, DMADATA, 1387 (u_int16_t *)p, DOUTAMOUNT >> 1); 1388 #endif 1389 1390 p += DOUTAMOUNT; 1391 } else { 1392 int xfer; 1393 1394 xfer = n; 1395 AIC_MISC(("%d> ", xfer)); 1396 1397 n -= xfer; 1398 out += xfer; 1399 1400 #if AIC_USE_DWORDS 1401 if (xfer >= 12) { 1402 bus_space_write_multi_4(iot, ioh, DMADATALONG, 1403 (u_int32_t *)p, xfer >> 2); 1404 p += xfer & ~3; 1405 xfer &= 3; 1406 } 1407 #else 1408 if (xfer >= 8) { 1409 bus_space_write_multi_2(iot, ioh, DMADATA, 1410 (u_int16_t *)p, xfer >> 1); 1411 p += xfer & ~1; 1412 xfer &= 1; 1413 } 1414 #endif 1415 1416 if (xfer > 0) { 1417 bus_space_write_1(iot, ioh, DMACNTRL0, 1418 ENDMA | B8MODE | WRITE); 1419 bus_space_write_multi_1(iot, ioh, DMADATA, p, 1420 xfer); 1421 p += xfer; 1422 bus_space_write_1(iot, ioh, DMACNTRL0, 1423 ENDMA | DWORDPIO | WRITE); 1424 } 1425 } 1426 } 1427 1428 if (out == 0) { 1429 bus_space_write_1(iot, ioh, SXFRCTL1, BITBUCKET); 1430 for (;;) { 1431 if ((bus_space_read_1(iot, ioh, DMASTAT) & INTSTAT) != 1432 0) 1433 break; 1434 } 1435 bus_space_write_1(iot, ioh, SXFRCTL1, 0); 1436 AIC_MISC(("extra data ")); 1437 } else { 1438 /* See the bytes off chip */ 1439 for (;;) { 1440 dmastat = bus_space_read_1(iot, ioh, DMASTAT); 1441 if ((dmastat & INTSTAT) != 0) 1442 goto phasechange; 1443 if ((dmastat & DFIFOEMP) != 0 && 1444 (bus_space_read_1(iot, ioh, SSTAT2) & SEMPTY) != 0) 1445 break; 1446 } 1447 } 1448 1449 phasechange: 1450 if ((dmastat & INTSTAT) != 0) { 1451 /* Some sort of phase change. */ 1452 int amount; 1453 1454 /* Stop transfers, do some accounting */ 1455 amount = bus_space_read_1(iot, ioh, FIFOSTAT) + 1456 (bus_space_read_1(iot, ioh, SSTAT2) & 15); 1457 if (amount > 0) { 1458 out -= amount; 1459 bus_space_write_1(iot, ioh, DMACNTRL0, 1460 RSTFIFO | WRITE); 1461 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN | CLRCH); 1462 AIC_MISC(("+%d ", amount)); 1463 } 1464 } 1465 1466 /* Turn on ENREQINIT again. */ 1467 bus_space_write_1(iot, ioh, SIMODE1, 1468 ENSCSIRST | ENSCSIPERR | ENBUSFREE | ENREQINIT | ENPHASECHG); 1469 1470 /* Stop the FIFO data path. */ 1471 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN); 1472 bus_space_write_1(iot, ioh, DMACNTRL0, 0); 1473 1474 return out; 1475 } 1476 1477 /* aic_datain_pio: perform data transfers using the FIFO datapath in the aic6360 1478 * Precondition: The SCSI bus should be in the DIN phase, with REQ asserted 1479 * and ACK deasserted (i.e. at least one byte is ready). 1480 * For now, uses a pretty dumb algorithm, hangs around until all data has been 1481 * transferred. This, is OK for fast targets, but not so smart for slow 1482 * targets which don't disconnect or for huge transfers. 1483 */ 1484 int 1485 aic_datain_pio(struct aic_softc *sc, u_char *p, int n) 1486 { 1487 bus_space_tag_t iot = sc->sc_iot; 1488 bus_space_handle_t ioh = sc->sc_ioh; 1489 u_char dmastat; 1490 int in = 0; 1491 #define DINAMOUNT 128 /* Full FIFO */ 1492 1493 AIC_MISC(("%02x%02x ", bus_space_read_1(iot, ioh, FIFOSTAT), 1494 bus_space_read_1(iot, ioh, SSTAT2))); 1495 1496 /* Clear host FIFO and counter. */ 1497 bus_space_write_1(iot, ioh, DMACNTRL0, RSTFIFO); 1498 /* Enable FIFOs. */ 1499 bus_space_write_1(iot, ioh, DMACNTRL0, ENDMA | DWORDPIO); 1500 bus_space_write_1(iot, ioh, SXFRCTL0, SCSIEN | DMAEN | CHEN); 1501 1502 /* Turn off ENREQINIT for now. */ 1503 bus_space_write_1(iot, ioh, SIMODE1, 1504 ENSCSIRST | ENSCSIPERR | ENBUSFREE | ENPHASECHG); 1505 1506 /* We leave this loop if one or more of the following is true: 1507 * a) phase != PH_DATAIN && FIFOs are empty 1508 * b) SCSIRSTI is set (a reset has occurred) or busfree is detected. 1509 */ 1510 while (n > 0) { 1511 /* Wait for fifo half full or phase mismatch */ 1512 for (;;) { 1513 dmastat = bus_space_read_1(iot, ioh, DMASTAT); 1514 if ((dmastat & (DFIFOFULL | INTSTAT)) != 0) 1515 break; 1516 } 1517 1518 if ((dmastat & DFIFOFULL) != 0) { 1519 n -= DINAMOUNT; 1520 in += DINAMOUNT; 1521 1522 #if AIC_USE_DWORDS 1523 bus_space_read_multi_4(iot, ioh, DMADATALONG, 1524 (u_int32_t *)p, DINAMOUNT >> 2); 1525 #else 1526 bus_space_read_multi_2(iot, ioh, DMADATA, 1527 (u_int16_t *)p, DINAMOUNT >> 1); 1528 #endif 1529 1530 p += DINAMOUNT; 1531 } else { 1532 int xfer; 1533 1534 xfer = min(bus_space_read_1(iot, ioh, FIFOSTAT), n); 1535 AIC_MISC((">%d ", xfer)); 1536 1537 n -= xfer; 1538 in += xfer; 1539 1540 #if AIC_USE_DWORDS 1541 if (xfer >= 12) { 1542 bus_space_read_multi_4(iot, ioh, DMADATALONG, 1543 (u_int32_t *)p, xfer >> 2); 1544 p += xfer & ~3; 1545 xfer &= 3; 1546 } 1547 #else 1548 if (xfer >= 8) { 1549 bus_space_read_multi_2(iot, ioh, DMADATA, 1550 (u_int16_t *)p, xfer >> 1); 1551 p += xfer & ~1; 1552 xfer &= 1; 1553 } 1554 #endif 1555 1556 if (xfer > 0) { 1557 bus_space_write_1(iot, ioh, DMACNTRL0, 1558 ENDMA | B8MODE); 1559 bus_space_read_multi_1(iot, ioh, DMADATA, p, 1560 xfer); 1561 p += xfer; 1562 bus_space_write_1(iot, ioh, DMACNTRL0, 1563 ENDMA | DWORDPIO); 1564 } 1565 } 1566 1567 if ((dmastat & INTSTAT) != 0) 1568 goto phasechange; 1569 } 1570 1571 /* Some SCSI-devices are rude enough to transfer more data than what 1572 * was requested, e.g. 2048 bytes from a CD-ROM instead of the 1573 * requested 512. Test for progress, i.e. real transfers. If no real 1574 * transfers have been performed (n is probably already zero) and the 1575 * FIFO is not empty, waste some bytes.... 1576 */ 1577 if (in == 0) { 1578 bus_space_write_1(iot, ioh, SXFRCTL1, BITBUCKET); 1579 for (;;) { 1580 if ((bus_space_read_1(iot, ioh, DMASTAT) & INTSTAT) != 1581 0) 1582 break; 1583 } 1584 bus_space_write_1(iot, ioh, SXFRCTL1, 0); 1585 AIC_MISC(("extra data ")); 1586 } 1587 1588 phasechange: 1589 /* Turn on ENREQINIT again. */ 1590 bus_space_write_1(iot, ioh, SIMODE1, 1591 ENSCSIRST | ENSCSIPERR | ENBUSFREE | ENREQINIT | ENPHASECHG); 1592 1593 /* Stop the FIFO data path. */ 1594 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN); 1595 bus_space_write_1(iot, ioh, DMACNTRL0, 0); 1596 1597 return in; 1598 } 1599 1600 /* 1601 * This is the workhorse routine of the driver. 1602 * Deficiencies (for now): 1603 * 1) always uses programmed I/O 1604 */ 1605 int 1606 aicintr(void *arg) 1607 { 1608 struct aic_softc *sc = arg; 1609 bus_space_tag_t iot = sc->sc_iot; 1610 bus_space_handle_t ioh = sc->sc_ioh; 1611 u_char sstat0, sstat1; 1612 struct aic_acb *acb; 1613 struct scsi_link *sc_link; 1614 struct aic_tinfo *ti; 1615 int n; 1616 1617 /* 1618 * Clear INTEN. We enable it again before returning. This makes the 1619 * interrupt esssentially level-triggered. 1620 */ 1621 bus_space_write_1(iot, ioh, DMACNTRL0, 0); 1622 1623 AIC_TRACE(("aicintr ")); 1624 1625 loop: 1626 /* 1627 * First check for abnormal conditions, such as reset. 1628 */ 1629 sstat1 = bus_space_read_1(iot, ioh, SSTAT1); 1630 AIC_MISC(("sstat1:0x%02x ", sstat1)); 1631 1632 if ((sstat1 & SCSIRSTI) != 0) { 1633 printf("%s: SCSI bus reset\n", sc->sc_dev.dv_xname); 1634 goto reset; 1635 } 1636 1637 /* 1638 * Check for less serious errors. 1639 */ 1640 if ((sstat1 & SCSIPERR) != 0) { 1641 printf("%s: SCSI bus parity error\n", sc->sc_dev.dv_xname); 1642 bus_space_write_1(iot, ioh, CLRSINT1, CLRSCSIPERR); 1643 if (sc->sc_prevphase == PH_MSGIN) { 1644 sc->sc_flags |= AIC_DROP_MSGIN; 1645 aic_sched_msgout(sc, SEND_PARITY_ERROR); 1646 } else 1647 aic_sched_msgout(sc, SEND_INIT_DET_ERR); 1648 } 1649 1650 /* 1651 * If we're not already busy doing something test for the following 1652 * conditions: 1653 * 1) We have been reselected by something 1654 * 2) We have selected something successfully 1655 * 3) Our selection process has timed out 1656 * 4) This is really a bus free interrupt just to get a new command 1657 * going? 1658 * 5) Spurious interrupt? 1659 */ 1660 switch (sc->sc_state) { 1661 case AIC_IDLE: 1662 case AIC_SELECTING: 1663 sstat0 = bus_space_read_1(iot, ioh, SSTAT0); 1664 AIC_MISC(("sstat0:0x%02x ", sstat0)); 1665 1666 if ((sstat0 & TARGET) != 0) { 1667 /* 1668 * We don't currently support target mode. 1669 */ 1670 printf("%s: target mode selected; going to BUS FREE\n", 1671 sc->sc_dev.dv_xname); 1672 bus_space_write_1(iot, ioh, SCSISIG, 0); 1673 1674 goto sched; 1675 } else if ((sstat0 & SELDI) != 0) { 1676 AIC_MISC(("reselected ")); 1677 1678 /* 1679 * If we're trying to select a target ourselves, 1680 * push our command back into the ready list. 1681 */ 1682 if (sc->sc_state == AIC_SELECTING) { 1683 AIC_MISC(("backoff selector ")); 1684 AIC_ASSERT(sc->sc_nexus != NULL); 1685 acb = sc->sc_nexus; 1686 sc->sc_nexus = NULL; 1687 TAILQ_INSERT_HEAD(&sc->ready_list, acb, chain); 1688 } 1689 1690 /* Save reselection ID. */ 1691 sc->sc_selid = bus_space_read_1(iot, ioh, SELID); 1692 1693 sc->sc_state = AIC_RESELECTED; 1694 } else if ((sstat0 & SELDO) != 0) { 1695 AIC_MISC(("selected ")); 1696 1697 /* We have selected a target. Things to do: 1698 * a) Determine what message(s) to send. 1699 * b) Verify that we're still selecting the target. 1700 * c) Mark device as busy. 1701 */ 1702 if (sc->sc_state != AIC_SELECTING) { 1703 printf("%s: selection out while idle; ", 1704 sc->sc_dev.dv_xname); 1705 printf("resetting\n"); 1706 AIC_BREAK(); 1707 goto reset; 1708 } 1709 AIC_ASSERT(sc->sc_nexus != NULL); 1710 acb = sc->sc_nexus; 1711 sc_link = acb->xs->sc_link; 1712 ti = &sc->sc_tinfo[sc_link->target]; 1713 1714 sc->sc_msgpriq = SEND_IDENTIFY; 1715 if (acb->flags & ACB_RESET) 1716 sc->sc_msgpriq |= SEND_DEV_RESET; 1717 else if (acb->flags & ACB_ABORT) 1718 sc->sc_msgpriq |= SEND_ABORT; 1719 else { 1720 #if AIC_USE_SYNCHRONOUS 1721 if ((ti->flags & DO_SYNC) != 0) 1722 sc->sc_msgpriq |= SEND_SDTR; 1723 #endif 1724 #if AIC_USE_WIDE 1725 if ((ti->flags & DO_WIDE) != 0) 1726 sc->sc_msgpriq |= SEND_WDTR; 1727 #endif 1728 } 1729 1730 acb->flags |= ACB_NEXUS; 1731 ti->lubusy |= (1 << sc_link->lun); 1732 1733 /* Do an implicit RESTORE POINTERS. */ 1734 sc->sc_dp = acb->data_addr; 1735 sc->sc_dleft = acb->data_length; 1736 sc->sc_cp = (u_char *)&acb->scsi_cmd; 1737 sc->sc_cleft = acb->scsi_cmd_length; 1738 1739 /* On our first connection, schedule a timeout. */ 1740 if ((acb->xs->flags & SCSI_POLL) == 0) 1741 timeout_add_msec(&acb->xs->stimeout, acb->timeout); 1742 1743 sc->sc_state = AIC_CONNECTED; 1744 } else if ((sstat1 & SELTO) != 0) { 1745 AIC_MISC(("selection timeout ")); 1746 1747 if (sc->sc_state != AIC_SELECTING) { 1748 printf("%s: selection timeout while idle; ", 1749 sc->sc_dev.dv_xname); 1750 printf("resetting\n"); 1751 AIC_BREAK(); 1752 goto reset; 1753 } 1754 AIC_ASSERT(sc->sc_nexus != NULL); 1755 acb = sc->sc_nexus; 1756 1757 bus_space_write_1(iot, ioh, SXFRCTL1, 0); 1758 bus_space_write_1(iot, ioh, SCSISEQ, ENRESELI); 1759 bus_space_write_1(iot, ioh, CLRSINT1, CLRSELTIMO); 1760 delay(250); 1761 1762 acb->xs->error = XS_SELTIMEOUT; 1763 goto finish; 1764 } else { 1765 if (sc->sc_state != AIC_IDLE) { 1766 printf("%s: BUS FREE while not idle; ", 1767 sc->sc_dev.dv_xname); 1768 printf("state=%d\n", sc->sc_state); 1769 AIC_BREAK(); 1770 goto out; 1771 } 1772 1773 goto sched; 1774 } 1775 1776 /* 1777 * Turn off selection stuff, and prepare to catch bus free 1778 * interrupts, parity errors, and phase changes. 1779 */ 1780 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN | CLRSTCNT | CLRCH); 1781 bus_space_write_1(iot, ioh, SXFRCTL1, 0); 1782 bus_space_write_1(iot, ioh, SCSISEQ, ENAUTOATNP); 1783 bus_space_write_1(iot, ioh, CLRSINT0, CLRSELDI | CLRSELDO); 1784 bus_space_write_1(iot, ioh, CLRSINT1, 1785 CLRBUSFREE | CLRPHASECHG); 1786 bus_space_write_1(iot, ioh, SIMODE0, 0); 1787 bus_space_write_1(iot, ioh, SIMODE1, 1788 ENSCSIRST | ENSCSIPERR | ENBUSFREE | ENREQINIT | 1789 ENPHASECHG); 1790 1791 sc->sc_flags = 0; 1792 sc->sc_prevphase = PH_INVALID; 1793 goto dophase; 1794 } 1795 1796 if ((sstat1 & BUSFREE) != 0) { 1797 /* We've gone to BUS FREE phase. */ 1798 bus_space_write_1(iot, ioh, CLRSINT1, 1799 CLRBUSFREE | CLRPHASECHG); 1800 1801 switch (sc->sc_state) { 1802 case AIC_RESELECTED: 1803 goto sched; 1804 1805 case AIC_CONNECTED: 1806 AIC_ASSERT(sc->sc_nexus != NULL); 1807 acb = sc->sc_nexus; 1808 1809 #if AIC_USE_SYNCHRONOUS + AIC_USE_WIDE 1810 if (sc->sc_prevphase == PH_MSGOUT) { 1811 /* 1812 * If the target went to BUS FREE phase during 1813 * or immediately after sending a SDTR or WDTR 1814 * message, disable negotiation. 1815 */ 1816 sc_link = acb->xs->sc_link; 1817 ti = &sc->sc_tinfo[sc_link->target]; 1818 switch (sc->sc_lastmsg) { 1819 #if AIC_USE_SYNCHRONOUS 1820 case SEND_SDTR: 1821 ti->flags &= ~DO_SYNC; 1822 ti->period = ti->offset = 0; 1823 break; 1824 #endif 1825 #if AIC_USE_WIDE 1826 case SEND_WDTR: 1827 ti->flags &= ~DO_WIDE; 1828 ti->width = 0; 1829 break; 1830 #endif 1831 } 1832 } 1833 #endif 1834 1835 if ((sc->sc_flags & AIC_ABORTING) == 0) { 1836 /* 1837 * Section 5.1.1 of the SCSI 2 spec suggests 1838 * issuing a REQUEST SENSE following an 1839 * unexpected disconnect. Some devices go into 1840 * a contingent allegiance condition when 1841 * disconnecting, and this is necessary to 1842 * clean up their state. 1843 */ 1844 printf("%s: unexpected disconnect; ", 1845 sc->sc_dev.dv_xname); 1846 printf("sending REQUEST SENSE\n"); 1847 AIC_BREAK(); 1848 aic_sense(sc, acb); 1849 goto out; 1850 } 1851 1852 acb->xs->error = XS_DRIVER_STUFFUP; 1853 goto finish; 1854 1855 case AIC_DISCONNECT: 1856 AIC_ASSERT(sc->sc_nexus != NULL); 1857 acb = sc->sc_nexus; 1858 #if 1 /* XXXX */ 1859 acb->data_addr = sc->sc_dp; 1860 acb->data_length = sc->sc_dleft; 1861 #endif 1862 TAILQ_INSERT_HEAD(&sc->nexus_list, acb, chain); 1863 sc->sc_nexus = NULL; 1864 goto sched; 1865 1866 case AIC_CMDCOMPLETE: 1867 AIC_ASSERT(sc->sc_nexus != NULL); 1868 acb = sc->sc_nexus; 1869 goto finish; 1870 } 1871 } 1872 1873 bus_space_write_1(iot, ioh, CLRSINT1, CLRPHASECHG); 1874 1875 dophase: 1876 if ((sstat1 & REQINIT) == 0) { 1877 /* Wait for REQINIT. */ 1878 goto out; 1879 } 1880 1881 sc->sc_phase = bus_space_read_1(iot, ioh, SCSISIG) & PH_MASK; 1882 bus_space_write_1(iot, ioh, SCSISIG, sc->sc_phase); 1883 1884 switch (sc->sc_phase) { 1885 case PH_MSGOUT: 1886 if (sc->sc_state != AIC_CONNECTED && 1887 sc->sc_state != AIC_RESELECTED) 1888 break; 1889 aic_msgout(sc); 1890 sc->sc_prevphase = PH_MSGOUT; 1891 goto loop; 1892 1893 case PH_MSGIN: 1894 if (sc->sc_state != AIC_CONNECTED && 1895 sc->sc_state != AIC_RESELECTED) 1896 break; 1897 aic_msgin(sc); 1898 sc->sc_prevphase = PH_MSGIN; 1899 goto loop; 1900 1901 case PH_CMD: 1902 if (sc->sc_state != AIC_CONNECTED) 1903 break; 1904 #ifdef AIC_DEBUG 1905 if ((aic_debug & AIC_SHOWMISC) != 0) { 1906 AIC_ASSERT(sc->sc_nexus != NULL); 1907 acb = sc->sc_nexus; 1908 printf("cmd=0x%02x+%d ", 1909 acb->scsi_cmd.opcode, acb->scsi_cmd_length-1); 1910 } 1911 #endif 1912 n = aic_dataout_pio(sc, sc->sc_cp, sc->sc_cleft); 1913 sc->sc_cp += n; 1914 sc->sc_cleft -= n; 1915 sc->sc_prevphase = PH_CMD; 1916 goto loop; 1917 1918 case PH_DATAOUT: 1919 if (sc->sc_state != AIC_CONNECTED) 1920 break; 1921 AIC_MISC(("dataout dleft=%lu ", (u_long)sc->sc_dleft)); 1922 n = aic_dataout_pio(sc, sc->sc_dp, sc->sc_dleft); 1923 sc->sc_dp += n; 1924 sc->sc_dleft -= n; 1925 sc->sc_prevphase = PH_DATAOUT; 1926 goto loop; 1927 1928 case PH_DATAIN: 1929 if (sc->sc_state != AIC_CONNECTED) 1930 break; 1931 AIC_MISC(("datain %lu ", (u_long)sc->sc_dleft)); 1932 n = aic_datain_pio(sc, sc->sc_dp, sc->sc_dleft); 1933 sc->sc_dp += n; 1934 sc->sc_dleft -= n; 1935 sc->sc_prevphase = PH_DATAIN; 1936 goto loop; 1937 1938 case PH_STAT: 1939 if (sc->sc_state != AIC_CONNECTED) 1940 break; 1941 AIC_ASSERT(sc->sc_nexus != NULL); 1942 acb = sc->sc_nexus; 1943 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN | SPIOEN); 1944 acb->target_stat = bus_space_read_1(iot, ioh, SCSIDAT); 1945 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN); 1946 AIC_MISC(("target_stat=0x%02x ", acb->target_stat)); 1947 sc->sc_prevphase = PH_STAT; 1948 goto loop; 1949 } 1950 1951 printf("%s: unexpected bus phase; resetting\n", sc->sc_dev.dv_xname); 1952 AIC_BREAK(); 1953 reset: 1954 aic_init(sc); 1955 return 1; 1956 1957 finish: 1958 timeout_del(&acb->xs->stimeout); 1959 aic_done(sc, acb); 1960 goto out; 1961 1962 sched: 1963 sc->sc_state = AIC_IDLE; 1964 aic_sched(sc); 1965 goto out; 1966 1967 out: 1968 bus_space_write_1(iot, ioh, DMACNTRL0, INTEN); 1969 return 1; 1970 } 1971 1972 void 1973 aic_abort(struct aic_softc *sc, struct aic_acb *acb) 1974 { 1975 1976 /* 2 secs for the abort */ 1977 acb->timeout = AIC_ABORT_TIMEOUT; 1978 acb->flags |= ACB_ABORT; 1979 1980 if (acb == sc->sc_nexus) { 1981 /* 1982 * If we're still selecting, the message will be scheduled 1983 * after selection is complete. 1984 */ 1985 if (sc->sc_state == AIC_CONNECTED) 1986 aic_sched_msgout(sc, SEND_ABORT); 1987 } else { 1988 aic_dequeue(sc, acb); 1989 TAILQ_INSERT_HEAD(&sc->ready_list, acb, chain); 1990 if (sc->sc_state == AIC_IDLE) 1991 aic_sched(sc); 1992 } 1993 } 1994 1995 void 1996 aic_timeout(void *arg) 1997 { 1998 struct aic_acb *acb = arg; 1999 struct scsi_xfer *xs = acb->xs; 2000 struct scsi_link *sc_link = xs->sc_link; 2001 struct aic_softc *sc = sc_link->adapter_softc; 2002 int s; 2003 2004 sc_print_addr(sc_link); 2005 printf("timed out"); 2006 2007 s = splbio(); 2008 2009 if (acb->flags & ACB_ABORT) { 2010 /* abort timed out */ 2011 printf(" AGAIN\n"); 2012 /* XXX Must reset! */ 2013 } else { 2014 /* abort the operation that has timed out */ 2015 printf("\n"); 2016 acb->xs->error = XS_TIMEOUT; 2017 aic_abort(sc, acb); 2018 } 2019 2020 splx(s); 2021 } 2022 2023 #ifdef AIC_DEBUG 2024 /* 2025 * The following functions are mostly used for debugging purposes, either 2026 * directly called from the driver or from the kernel debugger. 2027 */ 2028 2029 void 2030 aic_show_scsi_cmd(struct aic_acb *acb) 2031 { 2032 u_char *b = (u_char *)&acb->scsi_cmd; 2033 struct scsi_link *sc_link = acb->xs->sc_link; 2034 int i; 2035 2036 sc_print_addr(sc_link); 2037 if ((acb->xs->flags & SCSI_RESET) == 0) { 2038 for (i = 0; i < acb->scsi_cmd_length; i++) { 2039 if (i) 2040 printf(","); 2041 printf("%x", b[i]); 2042 } 2043 printf("\n"); 2044 } else 2045 printf("RESET\n"); 2046 } 2047 2048 void 2049 aic_print_acb(struct aic_acb *acb) 2050 { 2051 2052 printf("acb@%p xs=%p flags=%x", acb, acb->xs, acb->flags); 2053 printf(" dp=%p dleft=%d target_stat=%x\n", 2054 acb->data_addr, acb->data_length, acb->target_stat); 2055 aic_show_scsi_cmd(acb); 2056 } 2057 2058 void 2059 aic_print_active_acb(void) 2060 { 2061 struct aic_acb *acb; 2062 struct aic_softc *sc = aic_cd.cd_devs[0]; 2063 2064 printf("ready list:\n"); 2065 TAILQ_FOREACH(acb, &sc->ready_list, chain) 2066 aic_print_acb(acb); 2067 printf("nexus:\n"); 2068 if (sc->sc_nexus != NULL) 2069 aic_print_acb(sc->sc_nexus); 2070 printf("nexus list:\n"); 2071 TAILQ_FOREACH(acb, &sc->nexus_list, chain) 2072 aic_print_acb(acb); 2073 } 2074 2075 void 2076 aic_dump6360(struct aic_softc *sc) 2077 { 2078 bus_space_tag_t iot = sc->sc_iot; 2079 bus_space_handle_t ioh = sc->sc_ioh; 2080 2081 printf("aic6360: SCSISEQ=%x SXFRCTL0=%x SXFRCTL1=%x SCSISIG=%x\n", 2082 bus_space_read_1(iot, ioh, SCSISEQ), 2083 bus_space_read_1(iot, ioh, SXFRCTL0), 2084 bus_space_read_1(iot, ioh, SXFRCTL1), 2085 bus_space_read_1(iot, ioh, SCSISIG)); 2086 printf(" SSTAT0=%x SSTAT1=%x SSTAT2=%x SSTAT3=%x SSTAT4=%x\n", 2087 bus_space_read_1(iot, ioh, SSTAT0), 2088 bus_space_read_1(iot, ioh, SSTAT1), 2089 bus_space_read_1(iot, ioh, SSTAT2), 2090 bus_space_read_1(iot, ioh, SSTAT3), 2091 bus_space_read_1(iot, ioh, SSTAT4)); 2092 printf(" SIMODE0=%x SIMODE1=%x ", 2093 bus_space_read_1(iot, ioh, SIMODE0), 2094 bus_space_read_1(iot, ioh, SIMODE1)); 2095 printf("DMACNTRL0=%x DMACNTRL1=%x DMASTAT=%x\n", 2096 bus_space_read_1(iot, ioh, DMACNTRL0), 2097 bus_space_read_1(iot, ioh, DMACNTRL1), 2098 bus_space_read_1(iot, ioh, DMASTAT)); 2099 printf(" FIFOSTAT=%d SCSIBUS=0x%x\n", 2100 bus_space_read_1(iot, ioh, FIFOSTAT), 2101 bus_space_read_1(iot, ioh, SCSIBUS)); 2102 } 2103 2104 void 2105 aic_dump_driver(struct aic_softc *sc) 2106 { 2107 struct aic_tinfo *ti; 2108 int i; 2109 2110 printf("nexus=%p prevphase=%x\n", sc->sc_nexus, sc->sc_prevphase); 2111 printf("state=%x msgin=%x ", sc->sc_state, sc->sc_imess[0]); 2112 printf("msgpriq=%x msgoutq=%x lastmsg=%x currmsg=%x\n", sc->sc_msgpriq, 2113 sc->sc_msgoutq, sc->sc_lastmsg, sc->sc_currmsg); 2114 for (i = 0; i < 7; i++) { 2115 ti = &sc->sc_tinfo[i]; 2116 printf("tinfo%d: %d cmds %d disconnects %d timeouts", 2117 i, ti->cmds, ti->dconns, ti->touts); 2118 printf(" %d senses flags=%x\n", ti->senses, ti->flags); 2119 } 2120 } 2121 #endif 2122