1 /* $OpenBSD: adwlib.c,v 1.14 2001/07/11 17:31:25 krw Exp $ */ 2 /* $NetBSD: adwlib.c,v 1.20 2000/07/04 04:17:03 itojun Exp $ */ 3 4 /* 5 * Low level routines for the Advanced Systems Inc. SCSI controllers chips 6 * 7 * Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc. 8 * All rights reserved. 9 * 10 * Author: Baldassare Dante Profeta <dante@mclink.it> 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the NetBSD 23 * Foundation, Inc. and its contributors. 24 * 4. Neither the name of The NetBSD Foundation nor the names of its 25 * contributors may be used to endorse or promote products derived 26 * from this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 29 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 30 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 31 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 32 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 33 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 34 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 35 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 36 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 37 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGE. 39 */ 40 /* 41 * Ported from: 42 */ 43 /* 44 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters 45 * 46 * Copyright (c) 1995-2000 Advanced System Products, Inc. 47 * All Rights Reserved. 48 * 49 * Redistribution and use in source and binary forms, with or without 50 * modification, are permitted provided that redistributions of source 51 * code retain the above copyright notice and this comment without 52 * modification. 53 */ 54 55 #include <sys/types.h> 56 #include <sys/param.h> 57 #include <sys/systm.h> 58 #include <sys/malloc.h> 59 #include <sys/kernel.h> 60 #include <sys/queue.h> 61 #include <sys/device.h> 62 63 #include <machine/bus.h> 64 #include <machine/intr.h> 65 66 #include <scsi/scsi_all.h> 67 #include <scsi/scsiconf.h> 68 69 #include <dev/pci/pcidevs.h> 70 71 #include <vm/vm.h> 72 73 #include <dev/ic/adwlib.h> 74 #include <dev/microcode/adw/adwmcode.h> 75 #include <dev/ic/adw.h> 76 77 78 int AdwRamSelfTest __P((bus_space_tag_t, bus_space_handle_t, u_int8_t)); 79 int AdwLoadMCode __P((bus_space_tag_t, bus_space_handle_t, u_int16_t *, 80 u_int8_t)); 81 int AdwASC3550Cabling __P((bus_space_tag_t, bus_space_handle_t, ADW_DVC_CFG *)); 82 int AdwASC38C0800Cabling __P((bus_space_tag_t, bus_space_handle_t, 83 ADW_DVC_CFG *)); 84 int AdwASC38C1600Cabling __P((bus_space_tag_t, bus_space_handle_t, 85 ADW_DVC_CFG *)); 86 87 u_int16_t AdwGetEEPROMConfig __P((bus_space_tag_t, bus_space_handle_t, 88 ADW_EEPROM *)); 89 void AdwSetEEPROMConfig __P((bus_space_tag_t, bus_space_handle_t, 90 ADW_EEPROM *)); 91 u_int16_t AdwReadEEPWord __P((bus_space_tag_t, bus_space_handle_t, int)); 92 void AdwWaitEEPCmd __P((bus_space_tag_t, bus_space_handle_t)); 93 94 void AdwInquiryHandling __P((ADW_SOFTC *, ADW_SCSI_REQ_Q *)); 95 96 void AdwSleepMilliSecond __P((u_int32_t)); 97 void AdwDelayMicroSecond __P((u_int32_t)); 98 99 100 /* 101 * EEPROM Configuration. 102 * 103 * All drivers should use this structure to set the default EEPROM 104 * configuration. The BIOS now uses this structure when it is built. 105 * Additional structure information can be found in adwlib.h where 106 * the structure is defined. 107 */ 108 const static ADW_EEPROM adw_3550_Default_EEPROM = { 109 ADW_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */ 110 0x0000, /* 01 cfg_msw */ 111 0xFFFF, /* 02 disc_enable */ 112 0xFFFF, /* 03 wdtr_able */ 113 { 0xFFFF }, /* 04 sdtr_able */ 114 0xFFFF, /* 05 start_motor */ 115 0xFFFF, /* 06 tagqng_able */ 116 0xFFFF, /* 07 bios_scan */ 117 0, /* 08 scam_tolerant */ 118 7, /* 09 adapter_scsi_id */ 119 0, /* bios_boot_delay */ 120 3, /* 10 scsi_reset_delay */ 121 0, /* bios_id_lun */ 122 0, /* 11 termination */ 123 0, /* reserved1 */ 124 0xFFE7, /* 12 bios_ctrl */ 125 { 0xFFFF }, /* 13 ultra_able */ 126 { 0 }, /* 14 reserved2 */ 127 ADW_DEF_MAX_HOST_QNG, /* 15 max_host_qng */ 128 ADW_DEF_MAX_DVC_QNG, /* max_dvc_qng */ 129 0, /* 16 dvc_cntl */ 130 { 0 }, /* 17 bug_fix */ 131 { 0,0,0 }, /* 18-20 serial_number[3] */ 132 0, /* 21 check_sum */ 133 { /* 22-29 oem_name[16] */ 134 0,0,0,0,0,0,0,0, 135 0,0,0,0,0,0,0,0 136 }, 137 0, /* 30 dvc_err_code */ 138 0, /* 31 adw_err_code */ 139 0, /* 32 adw_err_addr */ 140 0, /* 33 saved_dvc_err_code */ 141 0, /* 34 saved_adw_err_code */ 142 0 /* 35 saved_adw_err_addr */ 143 }; 144 145 const static ADW_EEPROM adw_38C0800_Default_EEPROM = { 146 ADW_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */ 147 0x0000, /* 01 cfg_msw */ 148 0xFFFF, /* 02 disc_enable */ 149 0xFFFF, /* 03 wdtr_able */ 150 { 0x4444 }, /* 04 sdtr_speed1 */ 151 0xFFFF, /* 05 start_motor */ 152 0xFFFF, /* 06 tagqng_able */ 153 0xFFFF, /* 07 bios_scan */ 154 0, /* 08 scam_tolerant */ 155 7, /* 09 adapter_scsi_id */ 156 0, /* bios_boot_delay */ 157 3, /* 10 scsi_reset_delay */ 158 0, /* bios_id_lun */ 159 0, /* 11 termination_se */ 160 0, /* termination_lvd */ 161 0xFFE7, /* 12 bios_ctrl */ 162 { 0x4444 }, /* 13 sdtr_speed2 */ 163 { 0x4444 }, /* 14 sdtr_speed3 */ 164 ADW_DEF_MAX_HOST_QNG, /* 15 max_host_qng */ 165 ADW_DEF_MAX_DVC_QNG, /* max_dvc_qng */ 166 0, /* 16 dvc_cntl */ 167 { 0x4444 }, /* 17 sdtr_speed4 */ 168 { 0,0,0 }, /* 18-20 serial_number[3] */ 169 0, /* 21 check_sum */ 170 { /* 22-29 oem_name[16] */ 171 0,0,0,0,0,0,0,0, 172 0,0,0,0,0,0,0,0 173 }, 174 0, /* 30 dvc_err_code */ 175 0, /* 31 adw_err_code */ 176 0, /* 32 adw_err_addr */ 177 0, /* 33 saved_dvc_err_code */ 178 0, /* 34 saved_adw_err_code */ 179 0, /* 35 saved_adw_err_addr */ 180 { /* 36-55 reserved1[16] */ 181 0,0,0,0,0,0,0,0,0,0, 182 0,0,0,0,0,0,0,0,0,0 183 }, 184 0, /* 56 cisptr_lsw */ 185 0, /* 57 cisprt_msw */ 186 PCI_VENDOR_ADVSYS, /* 58 subsysvid */ 187 PCI_PRODUCT_ADVSYS_U2W, /* 59 subsysid */ 188 { 0,0,0,0 } /* 60-63 reserved2[4] */ 189 }; 190 191 const static ADW_EEPROM adw_38C1600_Default_EEPROM = { 192 ADW_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */ 193 0x0000, /* 01 cfg_msw */ 194 0xFFFF, /* 02 disc_enable */ 195 0xFFFF, /* 03 wdtr_able */ 196 { 0x5555 }, /* 04 sdtr_speed1 */ 197 0xFFFF, /* 05 start_motor */ 198 0xFFFF, /* 06 tagqng_able */ 199 0xFFFF, /* 07 bios_scan */ 200 0, /* 08 scam_tolerant */ 201 7, /* 09 adapter_scsi_id */ 202 0, /* bios_boot_delay */ 203 3, /* 10 scsi_reset_delay */ 204 0, /* bios_id_lun */ 205 0, /* 11 termination_se */ 206 0, /* termination_lvd */ 207 0xFFE7, /* 12 bios_ctrl */ 208 { 0x5555 }, /* 13 sdtr_speed2 */ 209 { 0x5555 }, /* 14 sdtr_speed3 */ 210 ADW_DEF_MAX_HOST_QNG, /* 15 max_host_qng */ 211 ADW_DEF_MAX_DVC_QNG, /* max_dvc_qng */ 212 0, /* 16 dvc_cntl */ 213 { 0x5555 }, /* 17 sdtr_speed4 */ 214 { 0,0,0 }, /* 18-20 serial_number[3] */ 215 0, /* 21 check_sum */ 216 { /* 22-29 oem_name[16] */ 217 0,0,0,0,0,0,0,0, 218 0,0,0,0,0,0,0,0 219 }, 220 0, /* 30 dvc_err_code */ 221 0, /* 31 adw_err_code */ 222 0, /* 32 adw_err_addr */ 223 0, /* 33 saved_dvc_err_code */ 224 0, /* 34 saved_adw_err_code */ 225 0, /* 35 saved_adw_err_addr */ 226 { /* 36-55 reserved1[16] */ 227 0,0,0,0,0,0,0,0,0,0, 228 0,0,0,0,0,0,0,0,0,0 229 }, 230 0, /* 56 cisptr_lsw */ 231 0, /* 57 cisprt_msw */ 232 PCI_VENDOR_ADVSYS, /* 58 subsysvid */ 233 PCI_PRODUCT_ADVSYS_U3W, /* 59 subsysid */ 234 { 0,0,0,0 } /* 60-63 reserved2[4] */ 235 }; 236 237 238 /* 239 * Read the board's EEPROM configuration. Set fields in ADW_SOFTC and 240 * ADW_DVC_CFG based on the EEPROM settings. The chip is stopped while 241 * all of this is done. 242 * 243 * For a non-fatal error return a warning code. If there are no warnings 244 * then 0 is returned. 245 * 246 * Note: Chip is stopped on entry. 247 */ 248 int 249 AdwInitFromEEPROM(sc) 250 ADW_SOFTC *sc; 251 { 252 bus_space_tag_t iot = sc->sc_iot; 253 bus_space_handle_t ioh = sc->sc_ioh; 254 ADW_EEPROM eep_config; 255 u_int16_t warn_code; 256 u_int16_t sdtr_speed = 0; 257 u_int8_t tid, termination; 258 int i, j; 259 260 261 warn_code = 0; 262 263 /* 264 * Read the board's EEPROM configuration. 265 * 266 * Set default values if a bad checksum is found. 267 * 268 * XXX - Don't handle big-endian access to EEPROM yet. 269 */ 270 if (AdwGetEEPROMConfig(iot, ioh, &eep_config) != eep_config.check_sum) { 271 warn_code |= ADW_WARN_EEPROM_CHKSUM; 272 273 /* 274 * Set EEPROM default values. 275 */ 276 switch(sc->chip_type) { 277 case ADW_CHIP_ASC3550: 278 eep_config = adw_3550_Default_EEPROM; 279 break; 280 case ADW_CHIP_ASC38C0800: 281 eep_config = adw_38C0800_Default_EEPROM; 282 break; 283 case ADW_CHIP_ASC38C1600: 284 eep_config = adw_38C1600_Default_EEPROM; 285 286 // XXX TODO!!! if (ASC_PCI_ID2FUNC(sc->cfg.pci_slot_info) != 0) { 287 if (sc->cfg.pci_slot_info != 0) { 288 u_int8_t lsw_msb; 289 290 lsw_msb = eep_config.cfg_lsw >> 8; 291 /* 292 * Set Function 1 EEPROM Word 0 MSB 293 * 294 * Clear the BIOS_ENABLE (bit 14) and 295 * INTAB (bit 11) EEPROM bits. 296 * 297 * Disable Bit 14 (BIOS_ENABLE) to fix 298 * SPARC Ultra 60 and old Mac system booting 299 * problem. The Expansion ROM must 300 * be disabled in Function 1 for these systems. 301 */ 302 lsw_msb &= ~(((ADW_EEPROM_BIOS_ENABLE | 303 ADW_EEPROM_INTAB) >> 8) & 0xFF); 304 /* 305 * Set the INTAB (bit 11) if the GPIO 0 input 306 * indicates the Function 1 interrupt line is 307 * wired to INTA. 308 * 309 * Set/Clear Bit 11 (INTAB) from 310 * the GPIO bit 0 input: 311 * 1 - Function 1 intr line wired to INT A. 312 * 0 - Function 1 intr line wired to INT B. 313 * 314 * Note: Adapter boards always have Function 0 315 * wired to INTA. 316 * Put all 5 GPIO bits in input mode and then 317 * read their input values. 318 */ 319 ADW_WRITE_BYTE_REGISTER(iot, ioh, 320 IOPB_GPIO_CNTL, 0); 321 if (ADW_READ_BYTE_REGISTER(iot, ioh, 322 IOPB_GPIO_DATA) & 0x01) { 323 /* 324 * Function 1 interrupt wired to INTA; 325 * Set EEPROM bit. 326 */ 327 lsw_msb |= (ADW_EEPROM_INTAB >> 8) 328 & 0xFF; 329 } 330 eep_config.cfg_lsw &= 0x00FF; 331 eep_config.cfg_lsw |= lsw_msb << 8; 332 } 333 break; 334 } 335 336 /* 337 * Assume the 6 byte board serial number that was read 338 * from EEPROM is correct even if the EEPROM checksum 339 * failed. 340 */ 341 for (i=2, j=1; i>=0; i--, j++) { 342 eep_config.serial_number[i] = 343 AdwReadEEPWord(iot, ioh, ADW_EEP_DVC_CFG_END - j); 344 } 345 346 AdwSetEEPROMConfig(iot, ioh, &eep_config); 347 } 348 /* 349 * Set sc and sc->cfg variables from the EEPROM configuration 350 * that was read. 351 * 352 * This is the mapping of EEPROM fields to Adw Library fields. 353 */ 354 sc->wdtr_able = eep_config.wdtr_able; 355 if (sc->chip_type == ADW_CHIP_ASC3550) { 356 sc->sdtr_able = eep_config.sdtr1.sdtr_able; 357 sc->ultra_able = eep_config.sdtr2.ultra_able; 358 } else { 359 sc->sdtr_speed1 = eep_config.sdtr1.sdtr_speed1; 360 sc->sdtr_speed2 = eep_config.sdtr2.sdtr_speed2; 361 sc->sdtr_speed3 = eep_config.sdtr3.sdtr_speed3; 362 sc->sdtr_speed4 = eep_config.sdtr4.sdtr_speed4; 363 } 364 sc->ppr_able = 0; 365 sc->tagqng_able = eep_config.tagqng_able; 366 sc->cfg.disc_enable = eep_config.disc_enable; 367 sc->max_host_qng = eep_config.max_host_qng; 368 sc->max_dvc_qng = eep_config.max_dvc_qng; 369 sc->chip_scsi_id = (eep_config.adapter_scsi_id & ADW_MAX_TID); 370 sc->start_motor = eep_config.start_motor; 371 sc->scsi_reset_wait = eep_config.scsi_reset_delay; 372 sc->bios_ctrl = eep_config.bios_ctrl; 373 sc->no_scam = eep_config.scam_tolerant; 374 sc->cfg.serial1 = eep_config.serial_number[0]; 375 sc->cfg.serial2 = eep_config.serial_number[1]; 376 sc->cfg.serial3 = eep_config.serial_number[2]; 377 378 if (sc->chip_type == ADW_CHIP_ASC38C0800 || 379 sc->chip_type == ADW_CHIP_ASC38C1600) { 380 sc->sdtr_able = 0; 381 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 382 if (tid == 0) { 383 sdtr_speed = sc->sdtr_speed1; 384 } else if (tid == 4) { 385 sdtr_speed = sc->sdtr_speed2; 386 } else if (tid == 8) { 387 sdtr_speed = sc->sdtr_speed3; 388 } else if (tid == 12) { 389 sdtr_speed = sc->sdtr_speed4; 390 } 391 if (sdtr_speed & ADW_MAX_TID) { 392 sc->sdtr_able |= (1 << tid); 393 } 394 sdtr_speed >>= 4; 395 } 396 } 397 398 /* 399 * Set the host maximum queuing (max. 253, min. 16) and the per device 400 * maximum queuing (max. 63, min. 4). 401 */ 402 if (eep_config.max_host_qng > ADW_DEF_MAX_HOST_QNG) { 403 eep_config.max_host_qng = ADW_DEF_MAX_HOST_QNG; 404 } else if (eep_config.max_host_qng < ADW_DEF_MIN_HOST_QNG) 405 { 406 /* If the value is zero, assume it is uninitialized. */ 407 if (eep_config.max_host_qng == 0) { 408 eep_config.max_host_qng = ADW_DEF_MAX_HOST_QNG; 409 } else { 410 eep_config.max_host_qng = ADW_DEF_MIN_HOST_QNG; 411 } 412 } 413 414 if (eep_config.max_dvc_qng > ADW_DEF_MAX_DVC_QNG) { 415 eep_config.max_dvc_qng = ADW_DEF_MAX_DVC_QNG; 416 } else if (eep_config.max_dvc_qng < ADW_DEF_MIN_DVC_QNG) { 417 /* If the value is zero, assume it is uninitialized. */ 418 if (eep_config.max_dvc_qng == 0) { 419 eep_config.max_dvc_qng = ADW_DEF_MAX_DVC_QNG; 420 } else { 421 eep_config.max_dvc_qng = ADW_DEF_MIN_DVC_QNG; 422 } 423 } 424 425 /* 426 * If 'max_dvc_qng' is greater than 'max_host_qng', then 427 * set 'max_dvc_qng' to 'max_host_qng'. 428 */ 429 if (eep_config.max_dvc_qng > eep_config.max_host_qng) { 430 eep_config.max_dvc_qng = eep_config.max_host_qng; 431 } 432 433 /* 434 * Set ADW_SOFTC 'max_host_qng' and 'max_dvc_qng' 435 * values based on possibly adjusted EEPROM values. 436 */ 437 sc->max_host_qng = eep_config.max_host_qng; 438 sc->max_dvc_qng = eep_config.max_dvc_qng; 439 440 441 /* 442 * If the EEPROM 'termination' field is set to automatic (0), then set 443 * the ADW_SOFTC.cfg 'termination' field to automatic also. 444 * 445 * If the termination is specified with a non-zero 'termination' 446 * value check that a legal value is set and set the ADW_SOFTC.cfg 447 * 'termination' field appropriately. 448 */ 449 450 switch(sc->chip_type) { 451 case ADW_CHIP_ASC3550: 452 sc->cfg.termination = 0; /* auto termination */ 453 switch(eep_config.termination_se) { 454 case 3: 455 /* Enable manual control with low on / high on. */ 456 sc->cfg.termination |= ADW_TERM_CTL_L; 457 case 2: 458 /* Enable manual control with low off / high on. */ 459 sc->cfg.termination |= ADW_TERM_CTL_H; 460 case 1: 461 /* Enable manual control with low off / high off. */ 462 sc->cfg.termination |= ADW_TERM_CTL_SEL; 463 case 0: 464 break; 465 default: 466 warn_code |= ADW_WARN_EEPROM_TERMINATION; 467 } 468 break; 469 470 case ADW_CHIP_ASC38C0800: 471 case ADW_CHIP_ASC38C1600: 472 switch(eep_config.termination_se) { 473 case 0: 474 /* auto termination for SE */ 475 termination = 0; 476 break; 477 case 1: 478 /* Enable manual control with low off / high off. */ 479 termination = 0; 480 break; 481 case 2: 482 /* Enable manual control with low off / high on. */ 483 termination = ADW_TERM_SE_HI; 484 break; 485 case 3: 486 /* Enable manual control with low on / high on. */ 487 termination = ADW_TERM_SE; 488 break; 489 default: 490 /* 491 * The EEPROM 'termination_se' field contains a 492 * bad value. Use automatic termination instead. 493 */ 494 termination = 0; 495 warn_code |= ADW_WARN_EEPROM_TERMINATION; 496 } 497 498 switch(eep_config.termination_lvd) { 499 case 0: 500 /* auto termination for LVD */ 501 sc->cfg.termination = termination; 502 break; 503 case 1: 504 /* Enable manual control with low off / high off. */ 505 sc->cfg.termination = termination; 506 break; 507 case 2: 508 /* Enable manual control with low off / high on. */ 509 sc->cfg.termination = termination | ADW_TERM_LVD_HI; 510 break; 511 case 3: 512 /* Enable manual control with low on / high on. */ 513 sc->cfg.termination = termination | ADW_TERM_LVD; 514 break; 515 default: 516 /* 517 * The EEPROM 'termination_lvd' field contains a 518 * bad value. Use automatic termination instead. 519 */ 520 sc->cfg.termination = termination; 521 warn_code |= ADW_WARN_EEPROM_TERMINATION; 522 } 523 break; 524 } 525 526 return warn_code; 527 } 528 529 530 /* 531 * Initialize the ASC-3550/ASC-38C0800/ASC-38C1600. 532 * 533 * On failure return the error code. 534 */ 535 int 536 AdwInitDriver(sc) 537 ADW_SOFTC *sc; 538 { 539 bus_space_tag_t iot = sc->sc_iot; 540 bus_space_handle_t ioh = sc->sc_ioh; 541 u_int16_t error_code; 542 int word; 543 int i; 544 u_int16_t bios_mem[ADW_MC_BIOSLEN/2]; /* BIOS RISC Memory 545 0x40-0x8F. */ 546 u_int16_t wdtr_able = 0, sdtr_able, ppr_able, tagqng_able; 547 u_int8_t max_cmd[ADW_MAX_TID + 1]; 548 u_int8_t tid; 549 550 551 error_code = 0; 552 553 /* 554 * Save the RISC memory BIOS region before writing the microcode. 555 * The BIOS may already be loaded and using its RISC LRAM region 556 * so its region must be saved and restored. 557 * 558 * Note: This code makes the assumption, which is currently true, 559 * that a chip reset does not clear RISC LRAM. 560 */ 561 for (i = 0; i < ADW_MC_BIOSLEN/2; i++) { 562 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_BIOSMEM+(2*i), bios_mem[i]); 563 } 564 565 /* 566 * Save current per TID negotiated values. 567 */ 568 switch (sc->chip_type) { 569 case ADW_CHIP_ASC3550: 570 if (bios_mem[(ADW_MC_BIOS_SIGNATURE-ADW_MC_BIOSMEM)/2]==0x55AA){ 571 572 u_int16_t bios_version, major, minor; 573 574 bios_version = bios_mem[(ADW_MC_BIOS_VERSION - 575 ADW_MC_BIOSMEM) / 2]; 576 major = (bios_version >> 12) & 0xF; 577 minor = (bios_version >> 8) & 0xF; 578 if (major < 3 || (major == 3 && minor == 1)) { 579 /* 580 * BIOS 3.1 and earlier location of 581 * 'wdtr_able' variable. 582 */ 583 ADW_READ_WORD_LRAM(iot, ioh, 0x120, wdtr_able); 584 } else { 585 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, 586 wdtr_able); 587 } 588 } 589 break; 590 591 case ADW_CHIP_ASC38C1600: 592 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, ppr_able); 593 /* FALLTHROUGH */ 594 case ADW_CHIP_ASC38C0800: 595 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, wdtr_able); 596 break; 597 } 598 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sdtr_able); 599 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, tagqng_able); 600 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 601 ADW_READ_BYTE_LRAM(iot, ioh, ADW_MC_NUMBER_OF_MAX_CMD + tid, 602 max_cmd[tid]); 603 } 604 605 /* 606 * Perform a RAM Built-In Self Test 607 */ 608 if((error_code = AdwRamSelfTest(iot, ioh, sc->chip_type))) { 609 return error_code; 610 } 611 612 /* 613 * Load the Microcode 614 */ 615 ; 616 if((error_code = AdwLoadMCode(iot, ioh, bios_mem, sc->chip_type))) { 617 return error_code; 618 } 619 620 /* 621 * Read microcode version and date. 622 */ 623 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_VERSION_DATE, sc->cfg.mcode_date); 624 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_VERSION_NUM, sc->cfg.mcode_version); 625 626 /* 627 * If the PCI Configuration Command Register "Parity Error Response 628 * Control" Bit was clear (0), then set the microcode variable 629 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode 630 * to ignore DMA parity errors. 631 */ 632 if (sc->cfg.control_flag & CONTROL_FLAG_IGNORE_PERR) { 633 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CONTROL_FLAG, word); 634 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_CONTROL_FLAG, 635 word | CONTROL_FLAG_IGNORE_PERR); 636 } 637 638 switch (sc->chip_type) { 639 case ADW_CHIP_ASC3550: 640 /* 641 * For ASC-3550, setting the START_CTL_EMFU [3:2] bits sets a 642 * FIFO threshold of 128 bytes. 643 * This register is only accessible to the host. 644 */ 645 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_DMA_CFG0, 646 START_CTL_EMFU | READ_CMD_MRM); 647 break; 648 649 case ADW_CHIP_ASC38C0800: 650 /* 651 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register. 652 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current 653 * cable detection and then we are able to read C_DET[3:0]. 654 * 655 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1 656 * Microcode Default Value' section below. 657 */ 658 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1, 659 ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1) 660 | ADW_DIS_TERM_DRV); 661 662 /* 663 * For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and 664 * START_CTL_TH [3:2] bits for the default FIFO threshold. 665 * 666 * Note: ASC-38C0800 FIFO threshold has been changed to 667 * 256 bytes. 668 * 669 * For DMA Errata #4 set the BC_THRESH_ENB bit. 670 */ 671 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_DMA_CFG0, 672 BC_THRESH_ENB | FIFO_THRESH_80B 673 | START_CTL_TH | READ_CMD_MRM); 674 break; 675 676 case ADW_CHIP_ASC38C1600: 677 /* 678 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register. 679 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current 680 * cable detection and then we are able to read C_DET[3:0]. 681 * 682 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1 683 * Microcode Default Value' section below. 684 */ 685 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1, 686 ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1) 687 | ADW_DIS_TERM_DRV); 688 689 /* 690 * If the BIOS control flag AIPP (Asynchronous Information 691 * Phase Protection) disable bit is not set, then set the 692 * firmware 'control_flag' CONTROL_FLAG_ENABLE_AIPP bit to 693 * enable AIPP checking and encoding. 694 */ 695 if ((sc->bios_ctrl & BIOS_CTRL_AIPP_DIS) == 0) { 696 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CONTROL_FLAG, word); 697 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_CONTROL_FLAG, 698 word | CONTROL_FLAG_ENABLE_AIPP); 699 } 700 701 /* 702 * For ASC-38C1600 use DMA_CFG0 default values: 703 * FIFO_THRESH_80B [6:4], and START_CTL_TH [3:2]. 704 */ 705 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_DMA_CFG0, 706 FIFO_THRESH_80B | START_CTL_TH | READ_CMD_MRM); 707 break; 708 } 709 710 /* 711 * Microcode operating variables for WDTR, SDTR, and command tag 712 * queuing will be set in AdwInquiryHandling() based on what a 713 * device reports it is capable of in Inquiry byte 7. 714 * 715 * If SCSI Bus Resets have been disabled, then directly set 716 * SDTR and WDTR from the EEPROM configuration. This will allow 717 * the BIOS and warm boot to work without a SCSI bus hang on 718 * the Inquiry caused by host and target mismatched DTR values. 719 * Without the SCSI Bus Reset, before an Inquiry a device can't 720 * be assumed to be in Asynchronous, Narrow mode. 721 */ 722 if ((sc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) { 723 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, sc->wdtr_able); 724 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sc->sdtr_able); 725 } 726 727 /* 728 * Set microcode operating variables for SDTR_SPEED1, SDTR_SPEED2, 729 * SDTR_SPEED3, and SDTR_SPEED4 based on the ULTRA EEPROM per TID 730 * bitmask. These values determine the maximum SDTR speed negotiated 731 * with a device. 732 * 733 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2, 734 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them 735 * without determining here whether the device supports SDTR. 736 */ 737 switch (sc->chip_type) { 738 case ADW_CHIP_ASC3550: 739 word = 0; 740 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 741 if (ADW_TID_TO_TIDMASK(tid) & sc->ultra_able) { 742 /* Set Ultra speed for TID 'tid'. */ 743 word |= (0x3 << (4 * (tid % 4))); 744 } else { 745 /* Set Fast speed for TID 'tid'. */ 746 word |= (0x2 << (4 * (tid % 4))); 747 } 748 /* Check if done with sdtr_speed1. */ 749 if (tid == 3) { 750 ADW_WRITE_WORD_LRAM(iot, ioh, 751 ADW_MC_SDTR_SPEED1, word); 752 word = 0; 753 /* Check if done with sdtr_speed2. */ 754 } else if (tid == 7) { 755 ADW_WRITE_WORD_LRAM(iot, ioh, 756 ADW_MC_SDTR_SPEED2, word); 757 word = 0; 758 /* Check if done with sdtr_speed3. */ 759 } else if (tid == 11) { 760 ADW_WRITE_WORD_LRAM(iot, ioh, 761 ADW_MC_SDTR_SPEED3, word); 762 word = 0; 763 /* Check if done with sdtr_speed4. */ 764 } else if (tid == 15) { 765 ADW_WRITE_WORD_LRAM(iot, ioh, 766 ADW_MC_SDTR_SPEED4, word); 767 /* End of loop. */ 768 } 769 } 770 771 /* 772 * Set microcode operating variable for the 773 * disconnect per TID bitmask. 774 */ 775 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DISC_ENABLE, 776 sc->cfg.disc_enable); 777 break; 778 779 case ADW_CHIP_ASC38C0800: 780 /* FALLTHROUGH */ 781 case ADW_CHIP_ASC38C1600: 782 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DISC_ENABLE, 783 sc->cfg.disc_enable); 784 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED1, 785 sc->sdtr_speed1); 786 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED2, 787 sc->sdtr_speed2); 788 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED3, 789 sc->sdtr_speed3); 790 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED4, 791 sc->sdtr_speed4); 792 break; 793 } 794 795 796 /* 797 * Set SCSI_CFG0 Microcode Default Value. 798 * 799 * The microcode will set the SCSI_CFG0 register using this value 800 * after it is started below. 801 */ 802 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SCSI_CFG0, 803 ADW_PARITY_EN | ADW_QUEUE_128 | ADW_SEL_TMO_LONG | 804 ADW_OUR_ID_EN | sc->chip_scsi_id); 805 806 807 switch(sc->chip_type) { 808 case ADW_CHIP_ASC3550: 809 error_code = AdwASC3550Cabling(iot, ioh, &sc->cfg); 810 break; 811 812 case ADW_CHIP_ASC38C0800: 813 error_code = AdwASC38C0800Cabling(iot, ioh, &sc->cfg); 814 break; 815 816 case ADW_CHIP_ASC38C1600: 817 error_code = AdwASC38C1600Cabling(iot, ioh, &sc->cfg); 818 break; 819 } 820 if(error_code) { 821 return error_code; 822 } 823 824 /* 825 * Set SEL_MASK Microcode Default Value 826 * 827 * The microcode will set the SEL_MASK register using this value 828 * after it is started below. 829 */ 830 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SEL_MASK, 831 ADW_TID_TO_TIDMASK(sc->chip_scsi_id)); 832 833 /* 834 * Create and Initialize Host->RISC Carrier lists 835 */ 836 sc->carr_freelist = AdwInitCarriers(sc->sc_dmamap_carrier, 837 sc->sc_control->carriers); 838 839 /* 840 * Set-up the Host->RISC Initiator Command Queue (ICQ). 841 */ 842 843 if ((sc->icq_sp = sc->carr_freelist) == NULL) { 844 return ADW_IERR_NO_CARRIER; 845 } 846 sc->carr_freelist = ADW_CARRIER_VADDR(sc, 847 ADW_GET_CARRP(sc->icq_sp->next_ba)); 848 849 /* 850 * The first command issued will be placed in the stopper carrier. 851 */ 852 sc->icq_sp->next_ba = ADW_CQ_STOPPER; 853 854 /* 855 * Set RISC ICQ physical address start value. 856 */ 857 ADW_WRITE_DWORD_LRAM(iot, ioh, ADW_MC_ICQ, sc->icq_sp->carr_ba); 858 859 /* 860 * Initialize the COMMA register to the same value otherwise 861 * the RISC will prematurely detect a command is available. 862 */ 863 if(sc->chip_type == ADW_CHIP_ASC38C1600) { 864 ADW_WRITE_DWORD_REGISTER(iot, ioh, IOPDW_COMMA, 865 sc->icq_sp->carr_ba); 866 } 867 868 /* 869 * Set-up the RISC->Host Initiator Response Queue (IRQ). 870 */ 871 if ((sc->irq_sp = sc->carr_freelist) == NULL) { 872 return ADW_IERR_NO_CARRIER; 873 } 874 sc->carr_freelist = ADW_CARRIER_VADDR(sc, 875 ADW_GET_CARRP(sc->irq_sp->next_ba)); 876 877 /* 878 * The first command completed by the RISC will be placed in 879 * the stopper. 880 * 881 * Note: Set 'next_ba' to ADW_CQ_STOPPER. When the request is 882 * completed the RISC will set the ADW_RQ_DONE bit. 883 */ 884 sc->irq_sp->next_ba = ADW_CQ_STOPPER; 885 886 /* 887 * Set RISC IRQ physical address start value. 888 */ 889 ADW_WRITE_DWORD_LRAM(iot, ioh, ADW_MC_IRQ, sc->irq_sp->carr_ba); 890 sc->carr_pending_cnt = 0; 891 892 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_INTR_ENABLES, 893 (ADW_INTR_ENABLE_HOST_INTR | ADW_INTR_ENABLE_GLOBAL_INTR)); 894 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CODE_BEGIN_ADDR, word); 895 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_PC, word); 896 897 /* finally, finally, gentlemen, start your engine */ 898 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RISC_CSR, ADW_RISC_CSR_RUN); 899 900 /* 901 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus 902 * Resets should be performed. The RISC has to be running 903 * to issue a SCSI Bus Reset. 904 */ 905 if (sc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) 906 { 907 /* 908 * If the BIOS Signature is present in memory, restore the 909 * BIOS Handshake Configuration Table and do not perform 910 * a SCSI Bus Reset. 911 */ 912 if (bios_mem[(ADW_MC_BIOS_SIGNATURE - ADW_MC_BIOSMEM)/2] == 913 0x55AA) { 914 /* 915 * Restore per TID negotiated values. 916 */ 917 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, 918 wdtr_able); 919 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, 920 sdtr_able); 921 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, 922 tagqng_able); 923 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 924 ADW_WRITE_BYTE_LRAM(iot, ioh, 925 ADW_MC_NUMBER_OF_MAX_CMD + tid, 926 max_cmd[tid]); 927 } 928 } else { 929 if (AdwResetCCB(sc) != ADW_TRUE) { 930 error_code = ADW_WARN_BUSRESET_ERROR; 931 } 932 } 933 } 934 935 return error_code; 936 } 937 938 939 int 940 AdwRamSelfTest(iot, ioh, chip_type) 941 bus_space_tag_t iot; 942 bus_space_handle_t ioh; 943 u_int8_t chip_type; 944 { 945 int i; 946 u_int8_t byte; 947 948 949 if ((chip_type == ADW_CHIP_ASC38C0800) || 950 (chip_type == ADW_CHIP_ASC38C1600)) { 951 /* 952 * RAM BIST (RAM Built-In Self Test) 953 * 954 * Address : I/O base + offset 0x38h register (byte). 955 * Function: Bit 7-6(RW) : RAM mode 956 * Normal Mode : 0x00 957 * Pre-test Mode : 0x40 958 * RAM Test Mode : 0x80 959 * Bit 5 : unused 960 * Bit 4(RO) : Done bit 961 * Bit 3-0(RO) : Status 962 * Host Error : 0x08 963 * Int_RAM Error : 0x04 964 * RISC Error : 0x02 965 * SCSI Error : 0x01 966 * No Error : 0x00 967 * 968 * Note: RAM BIST code should be put right here, before loading 969 * the microcode and after saving the RISC memory BIOS region. 970 */ 971 972 /* 973 * LRAM Pre-test 974 * 975 * Write PRE_TEST_MODE (0x40) to register and wait for 976 * 10 milliseconds. 977 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), 978 * return an error. Reset to NORMAL_MODE (0x00) and do again. 979 * If cannot reset to NORMAL_MODE, return an error too. 980 */ 981 for (i = 0; i < 2; i++) { 982 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, 983 PRE_TEST_MODE); 984 /* Wait for 10ms before reading back. */ 985 AdwSleepMilliSecond(10); 986 byte = ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST); 987 if ((byte & RAM_TEST_DONE) == 0 || (byte & 0x0F) != 988 PRE_TEST_VALUE) { 989 return ADW_IERR_BIST_PRE_TEST; 990 } 991 992 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, 993 NORMAL_MODE); 994 /* Wait for 10ms before reading back. */ 995 AdwSleepMilliSecond(10); 996 if (ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST) 997 != NORMAL_VALUE) { 998 return ADW_IERR_BIST_PRE_TEST; 999 } 1000 } 1001 1002 /* 1003 * LRAM Test - It takes about 1.5 ms to run through the test. 1004 * 1005 * Write RAM_TEST_MODE (0x80) to register and wait for 1006 * 10 milliseconds. 1007 * If Done bit not set or Status not 0, save register byte, 1008 * set the err_code, and return an error. 1009 */ 1010 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, RAM_TEST_MODE); 1011 /* Wait for 10ms before checking status. */ 1012 AdwSleepMilliSecond(10); 1013 1014 byte = ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST); 1015 if ((byte & RAM_TEST_DONE)==0 || (byte & RAM_TEST_STATUS)!=0) { 1016 /* Get here if Done bit not set or Status not 0. */ 1017 return ADW_IERR_BIST_RAM_TEST; 1018 } 1019 1020 /* We need to reset back to normal mode after LRAM test passes*/ 1021 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, NORMAL_MODE); 1022 } 1023 1024 return 0; 1025 } 1026 1027 1028 int 1029 AdwLoadMCode(iot, ioh, bios_mem, chip_type) 1030 bus_space_tag_t iot; 1031 bus_space_handle_t ioh; 1032 u_int16_t *bios_mem; 1033 u_int8_t chip_type; 1034 { 1035 u_int8_t *mcode_data; 1036 u_int32_t mcode_chksum; 1037 u_int16_t mcode_size; 1038 u_int32_t sum; 1039 u_int16_t code_sum; 1040 int begin_addr; 1041 int end_addr; 1042 int word; 1043 int adw_memsize; 1044 int adw_mcode_expanded_size; 1045 int i, j; 1046 1047 1048 switch(chip_type) { 1049 case ADW_CHIP_ASC3550: 1050 mcode_data = (u_int8_t *)adw_asc3550_mcode_data.mcode_data; 1051 mcode_chksum = (u_int32_t)adw_asc3550_mcode_data.mcode_chksum; 1052 mcode_size = (u_int16_t)adw_asc3550_mcode_data.mcode_size; 1053 adw_memsize = ADW_3550_MEMSIZE; 1054 break; 1055 1056 case ADW_CHIP_ASC38C0800: 1057 mcode_data = (u_int8_t *)adw_asc38C0800_mcode_data.mcode_data; 1058 mcode_chksum =(u_int32_t)adw_asc38C0800_mcode_data.mcode_chksum; 1059 mcode_size = (u_int16_t)adw_asc38C0800_mcode_data.mcode_size; 1060 adw_memsize = ADW_38C0800_MEMSIZE; 1061 break; 1062 1063 case ADW_CHIP_ASC38C1600: 1064 mcode_data = (u_int8_t *)adw_asc38C1600_mcode_data.mcode_data; 1065 mcode_chksum =(u_int32_t)adw_asc38C1600_mcode_data.mcode_chksum; 1066 mcode_size = (u_int16_t)adw_asc38C1600_mcode_data.mcode_size; 1067 adw_memsize = ADW_38C1600_MEMSIZE; 1068 break; 1069 } 1070 1071 /* 1072 * Write the microcode image to RISC memory starting at address 0. 1073 */ 1074 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, 0); 1075 1076 /* Assume the following compressed format of the microcode buffer: 1077 * 1078 * 254 word (508 byte) table indexed by byte code followed 1079 * by the following byte codes: 1080 * 1081 * 1-Byte Code: 1082 * 00: Emit word 0 in table. 1083 * 01: Emit word 1 in table. 1084 * . 1085 * FD: Emit word 253 in table. 1086 * 1087 * Multi-Byte Code: 1088 * FE WW WW: (3 byte code) Word to emit is the next word WW WW. 1089 * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW. 1090 */ 1091 word = 0; 1092 for (i = 253 * 2; i < mcode_size; i++) { 1093 if (mcode_data[i] == 0xff) { 1094 for (j = 0; j < mcode_data[i + 1]; j++) { 1095 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, 1096 (((u_int16_t)mcode_data[i + 3] << 8) | 1097 mcode_data[i + 2])); 1098 word++; 1099 } 1100 i += 3; 1101 } else if (mcode_data[i] == 0xfe) { 1102 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, 1103 (((u_int16_t)mcode_data[i + 2] << 8) | 1104 mcode_data[i + 1])); 1105 i += 2; 1106 word++; 1107 } else { 1108 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, (((u_int16_t) 1109 mcode_data[(mcode_data[i] * 2) + 1] <<8) | 1110 mcode_data[mcode_data[i] * 2])); 1111 word++; 1112 } 1113 } 1114 1115 /* 1116 * Set 'word' for later use to clear the rest of memory and save 1117 * the expanded mcode size. 1118 */ 1119 word *= 2; 1120 adw_mcode_expanded_size = word; 1121 1122 /* 1123 * Clear the rest of the Internal RAM. 1124 */ 1125 for (; word < adw_memsize; word += 2) { 1126 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, 0); 1127 } 1128 1129 /* 1130 * Verify the microcode checksum. 1131 */ 1132 sum = 0; 1133 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, 0); 1134 1135 for (word = 0; word < adw_mcode_expanded_size; word += 2) { 1136 sum += ADW_READ_WORD_AUTO_INC_LRAM(iot, ioh); 1137 } 1138 1139 if (sum != mcode_chksum) { 1140 return ADW_IERR_MCODE_CHKSUM; 1141 } 1142 1143 /* 1144 * Restore the RISC memory BIOS region. 1145 */ 1146 for (i = 0; i < ADW_MC_BIOSLEN/2; i++) { 1147 if(chip_type == ADW_CHIP_ASC3550) { 1148 ADW_WRITE_BYTE_LRAM(iot, ioh, ADW_MC_BIOSMEM + (2 * i), 1149 bios_mem[i]); 1150 } else { 1151 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_BIOSMEM + (2 * i), 1152 bios_mem[i]); 1153 } 1154 } 1155 1156 /* 1157 * Calculate and write the microcode code checksum to the microcode 1158 * code checksum location ADW_MC_CODE_CHK_SUM (0x2C). 1159 */ 1160 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CODE_BEGIN_ADDR, begin_addr); 1161 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CODE_END_ADDR, end_addr); 1162 code_sum = 0; 1163 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, begin_addr); 1164 for (word = begin_addr; word < end_addr; word += 2) { 1165 code_sum += ADW_READ_WORD_AUTO_INC_LRAM(iot, ioh); 1166 } 1167 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_CODE_CHK_SUM, code_sum); 1168 1169 /* 1170 * Set the chip type. 1171 */ 1172 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_CHIP_TYPE, chip_type); 1173 1174 return 0; 1175 } 1176 1177 1178 int 1179 AdwASC3550Cabling(iot, ioh, cfg) 1180 bus_space_tag_t iot; 1181 bus_space_handle_t ioh; 1182 ADW_DVC_CFG *cfg; 1183 { 1184 u_int16_t scsi_cfg1; 1185 1186 1187 /* 1188 * Determine SCSI_CFG1 Microcode Default Value. 1189 * 1190 * The microcode will set the SCSI_CFG1 register using this value 1191 * after it is started below. 1192 */ 1193 1194 /* Read current SCSI_CFG1 Register value. */ 1195 scsi_cfg1 = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1); 1196 1197 /* 1198 * If all three connectors are in use in ASC3550, return an error. 1199 */ 1200 if ((scsi_cfg1 & CABLE_ILLEGAL_A) == 0 || 1201 (scsi_cfg1 & CABLE_ILLEGAL_B) == 0) { 1202 return ADW_IERR_ILLEGAL_CONNECTION; 1203 } 1204 1205 /* 1206 * If the cable is reversed all of the SCSI_CTRL register signals 1207 * will be set. Check for and return an error if this condition is 1208 * found. 1209 */ 1210 if ((ADW_READ_WORD_REGISTER(iot,ioh, IOPW_SCSI_CTRL) & 0x3F07)==0x3F07){ 1211 return ADW_IERR_REVERSED_CABLE; 1212 } 1213 1214 /* 1215 * If this is a differential board and a single-ended device 1216 * is attached to one of the connectors, return an error. 1217 */ 1218 if ((scsi_cfg1 & ADW_DIFF_MODE) && 1219 (scsi_cfg1 & ADW_DIFF_SENSE) == 0) { 1220 return ADW_IERR_SINGLE_END_DEVICE; 1221 } 1222 1223 /* 1224 * If automatic termination control is enabled, then set the 1225 * termination value based on a table listed in a_condor.h. 1226 * 1227 * If manual termination was specified with an EEPROM setting 1228 * then 'termination' was set-up in AdwInitFromEEPROM() and 1229 * is ready to be 'ored' into SCSI_CFG1. 1230 */ 1231 if (cfg->termination == 0) { 1232 /* 1233 * The software always controls termination by setting 1234 * TERM_CTL_SEL. 1235 * If TERM_CTL_SEL were set to 0, the hardware would set 1236 * termination. 1237 */ 1238 cfg->termination |= ADW_TERM_CTL_SEL; 1239 1240 switch(scsi_cfg1 & ADW_CABLE_DETECT) { 1241 /* TERM_CTL_H: on, TERM_CTL_L: on */ 1242 case 0x3: case 0x7: case 0xB: 1243 case 0xD: case 0xE: case 0xF: 1244 cfg->termination |= 1245 (ADW_TERM_CTL_H | ADW_TERM_CTL_L); 1246 break; 1247 1248 /* TERM_CTL_H: on, TERM_CTL_L: off */ 1249 case 0x1: case 0x5: case 0x9: 1250 case 0xA: case 0xC: 1251 cfg->termination |= ADW_TERM_CTL_H; 1252 break; 1253 1254 /* TERM_CTL_H: off, TERM_CTL_L: off */ 1255 case 0x2: case 0x6: 1256 break; 1257 } 1258 } 1259 1260 /* 1261 * Clear any set TERM_CTL_H and TERM_CTL_L bits. 1262 */ 1263 scsi_cfg1 &= ~ADW_TERM_CTL; 1264 1265 /* 1266 * Invert the TERM_CTL_H and TERM_CTL_L bits and then 1267 * set 'scsi_cfg1'. The TERM_POL bit does not need to be 1268 * referenced, because the hardware internally inverts 1269 * the Termination High and Low bits if TERM_POL is set. 1270 */ 1271 scsi_cfg1 |= (ADW_TERM_CTL_SEL | (~cfg->termination & ADW_TERM_CTL)); 1272 1273 /* 1274 * Set SCSI_CFG1 Microcode Default Value 1275 * 1276 * Set filter value and possibly modified termination control 1277 * bits in the Microcode SCSI_CFG1 Register Value. 1278 * 1279 * The microcode will set the SCSI_CFG1 register using this value 1280 * after it is started below. 1281 */ 1282 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SCSI_CFG1, 1283 ADW_FLTR_DISABLE | scsi_cfg1); 1284 1285 /* 1286 * Set MEM_CFG Microcode Default Value 1287 * 1288 * The microcode will set the MEM_CFG register using this value 1289 * after it is started below. 1290 * 1291 * MEM_CFG may be accessed as a word or byte, but only bits 0-7 1292 * are defined. 1293 * 1294 * ASC-3550 has 8KB internal memory. 1295 */ 1296 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_MEM_CFG, 1297 ADW_BIOS_EN | ADW_RAM_SZ_8KB); 1298 1299 return 0; 1300 } 1301 1302 1303 int 1304 AdwASC38C0800Cabling(iot, ioh, cfg) 1305 bus_space_tag_t iot; 1306 bus_space_handle_t ioh; 1307 ADW_DVC_CFG *cfg; 1308 { 1309 u_int16_t scsi_cfg1; 1310 1311 1312 /* 1313 * Determine SCSI_CFG1 Microcode Default Value. 1314 * 1315 * The microcode will set the SCSI_CFG1 register using this value 1316 * after it is started below. 1317 */ 1318 1319 /* Read current SCSI_CFG1 Register value. */ 1320 scsi_cfg1 = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1); 1321 1322 /* 1323 * If the cable is reversed all of the SCSI_CTRL register signals 1324 * will be set. Check for and return an error if this condition is 1325 * found. 1326 */ 1327 if ((ADW_READ_WORD_REGISTER(iot,ioh, IOPW_SCSI_CTRL) & 0x3F07)==0x3F07){ 1328 return ADW_IERR_REVERSED_CABLE; 1329 } 1330 1331 /* 1332 * All kind of combinations of devices attached to one of four 1333 * connectors are acceptable except HVD device attached. 1334 * For example, LVD device can be attached to SE connector while 1335 * SE device attached to LVD connector. 1336 * If LVD device attached to SE connector, it only runs up to 1337 * Ultra speed. 1338 * 1339 * If an HVD device is attached to one of LVD connectors, return 1340 * an error. 1341 * However, there is no way to detect HVD device attached to 1342 * SE connectors. 1343 */ 1344 if (scsi_cfg1 & ADW_HVD) { 1345 return ADW_IERR_HVD_DEVICE; 1346 } 1347 1348 /* 1349 * If either SE or LVD automatic termination control is enabled, then 1350 * set the termination value based on a table listed in a_condor.h. 1351 * 1352 * If manual termination was specified with an EEPROM setting then 1353 * 'termination' was set-up in AdwInitFromEEPROM() and is ready 1354 * to be 'ored' into SCSI_CFG1. 1355 */ 1356 if ((cfg->termination & ADW_TERM_SE) == 0) { 1357 /* SE automatic termination control is enabled. */ 1358 switch(scsi_cfg1 & ADW_C_DET_SE) { 1359 /* TERM_SE_HI: on, TERM_SE_LO: on */ 1360 case 0x1: case 0x2: case 0x3: 1361 cfg->termination |= ADW_TERM_SE; 1362 break; 1363 1364 /* TERM_SE_HI: on, TERM_SE_LO: off */ 1365 case 0x0: 1366 cfg->termination |= ADW_TERM_SE_HI; 1367 break; 1368 } 1369 } 1370 1371 if ((cfg->termination & ADW_TERM_LVD) == 0) { 1372 /* LVD automatic termination control is enabled. */ 1373 switch(scsi_cfg1 & ADW_C_DET_LVD) { 1374 /* TERM_LVD_HI: on, TERM_LVD_LO: on */ 1375 case 0x4: case 0x8: case 0xC: 1376 cfg->termination |= ADW_TERM_LVD; 1377 break; 1378 1379 /* TERM_LVD_HI: off, TERM_LVD_LO: off */ 1380 case 0x0: 1381 break; 1382 } 1383 } 1384 1385 /* 1386 * Clear any set TERM_SE and TERM_LVD bits. 1387 */ 1388 scsi_cfg1 &= (~ADW_TERM_SE & ~ADW_TERM_LVD); 1389 1390 /* 1391 * Invert the TERM_SE and TERM_LVD bits and then set 'scsi_cfg1'. 1392 */ 1393 scsi_cfg1 |= (~cfg->termination & 0xF0); 1394 1395 /* 1396 * Clear BIG_ENDIAN, DIS_TERM_DRV, Terminator Polarity and 1397 * HVD/LVD/SE bits and set possibly modified termination control bits 1398 * in the Microcode SCSI_CFG1 Register Value. 1399 */ 1400 scsi_cfg1 &= (~ADW_BIG_ENDIAN & ~ADW_DIS_TERM_DRV & 1401 ~ADW_TERM_POL & ~ADW_HVD_LVD_SE); 1402 1403 /* 1404 * Set SCSI_CFG1 Microcode Default Value 1405 * 1406 * Set possibly modified termination control and reset DIS_TERM_DRV 1407 * bits in the Microcode SCSI_CFG1 Register Value. 1408 * 1409 * The microcode will set the SCSI_CFG1 register using this value 1410 * after it is started below. 1411 */ 1412 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SCSI_CFG1, scsi_cfg1); 1413 1414 /* 1415 * Set MEM_CFG Microcode Default Value 1416 * 1417 * The microcode will set the MEM_CFG register using this value 1418 * after it is started below. 1419 * 1420 * MEM_CFG may be accessed as a word or byte, but only bits 0-7 1421 * are defined. 1422 * 1423 * ASC-38C0800 has 16KB internal memory. 1424 */ 1425 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_MEM_CFG, 1426 ADW_BIOS_EN | ADW_RAM_SZ_16KB); 1427 1428 return 0; 1429 } 1430 1431 1432 int 1433 AdwASC38C1600Cabling(iot, ioh, cfg) 1434 bus_space_tag_t iot; 1435 bus_space_handle_t ioh; 1436 ADW_DVC_CFG *cfg; 1437 { 1438 u_int16_t scsi_cfg1; 1439 1440 1441 /* 1442 * Determine SCSI_CFG1 Microcode Default Value. 1443 * 1444 * The microcode will set the SCSI_CFG1 register using this value 1445 * after it is started below. 1446 * Each ASC-38C1600 function has only two cable detect bits. 1447 * The bus mode override bits are in IOPB_SOFT_OVER_WR. 1448 */ 1449 1450 /* Read current SCSI_CFG1 Register value. */ 1451 scsi_cfg1 = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1); 1452 1453 /* 1454 * If the cable is reversed all of the SCSI_CTRL register signals 1455 * will be set. Check for and return an error if this condition is 1456 * found. 1457 */ 1458 if ((ADW_READ_WORD_REGISTER(iot,ioh, IOPW_SCSI_CTRL) & 0x3F07)==0x3F07){ 1459 return ADW_IERR_REVERSED_CABLE; 1460 } 1461 1462 /* 1463 * Each ASC-38C1600 function has two connectors. Only an HVD device 1464 * can not be connected to either connector. An LVD device or SE device 1465 * may be connected to either connecor. If an SE device is connected, 1466 * then at most Ultra speed (20 Mhz) can be used on both connectors. 1467 * 1468 * If an HVD device is attached, return an error. 1469 */ 1470 if (scsi_cfg1 & ADW_HVD) { 1471 return ADW_IERR_HVD_DEVICE; 1472 } 1473 1474 /* 1475 * Each function in the ASC-38C1600 uses only the SE cable detect and 1476 * termination because there are two connectors for each function. 1477 * Each function may use either LVD or SE mode. 1478 * Corresponding the SE automatic termination control EEPROM bits are 1479 * used for each function. 1480 * Each function has its own EEPROM. If SE automatic control is enabled 1481 * for the function, then set the termination value based on a table 1482 * listed in adwlib.h. 1483 * 1484 * If manual termination is specified in the EEPROM for the function, 1485 * then 'termination' was set-up in AdwInitFromEEPROM() and is 1486 * ready to be 'ored' into SCSI_CFG1. 1487 */ 1488 if ((cfg->termination & ADW_TERM_SE) == 0) { 1489 /* SE automatic termination control is enabled. */ 1490 switch(scsi_cfg1 & ADW_C_DET_SE) { 1491 /* TERM_SE_HI: on, TERM_SE_LO: on */ 1492 case 0x1: case 0x2: case 0x3: 1493 cfg->termination |= ADW_TERM_SE; 1494 break; 1495 1496 case 0x0: 1497 /* !!!!TODO!!!! */ 1498 // if (ASC_PCI_ID2FUNC(cfg->pci_slot_info) == 0) { 1499 /* Function 0 - TERM_SE_HI: off, TERM_SE_LO: off */ 1500 // } 1501 // else 1502 // { 1503 /* Function 1 - TERM_SE_HI: on, TERM_SE_LO: off */ 1504 cfg->termination |= ADW_TERM_SE_HI; 1505 // } 1506 break; 1507 } 1508 } 1509 1510 /* 1511 * Clear any set TERM_SE bits. 1512 */ 1513 scsi_cfg1 &= ~ADW_TERM_SE; 1514 1515 /* 1516 * Invert the TERM_SE bits and then set 'scsi_cfg1'. 1517 */ 1518 scsi_cfg1 |= (~cfg->termination & ADW_TERM_SE); 1519 1520 /* 1521 * Clear Big Endian and Terminator Polarity bits and set possibly 1522 * modified termination control bits in the Microcode SCSI_CFG1 1523 * Register Value. 1524 */ 1525 scsi_cfg1 &= (~ADW_BIG_ENDIAN & ~ADW_DIS_TERM_DRV & ~ADW_TERM_POL); 1526 1527 /* 1528 * Set SCSI_CFG1 Microcode Default Value 1529 * 1530 * Set possibly modified termination control bits in the Microcode 1531 * SCSI_CFG1 Register Value. 1532 * 1533 * The microcode will set the SCSI_CFG1 register using this value 1534 * after it is started below. 1535 */ 1536 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SCSI_CFG1, scsi_cfg1); 1537 1538 /* 1539 * Set MEM_CFG Microcode Default Value 1540 * 1541 * The microcode will set the MEM_CFG register using this value 1542 * after it is started below. 1543 * 1544 * MEM_CFG may be accessed as a word or byte, but only bits 0-7 1545 * are defined. 1546 * 1547 * ASC-38C1600 has 32KB internal memory. 1548 */ 1549 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_MEM_CFG, 1550 ADW_BIOS_EN | ADW_RAM_SZ_32KB); 1551 1552 return 0; 1553 } 1554 1555 1556 /* 1557 * Read EEPROM configuration into the specified buffer. 1558 * 1559 * Return a checksum based on the EEPROM configuration read. 1560 */ 1561 u_int16_t 1562 AdwGetEEPROMConfig(iot, ioh, cfg_buf) 1563 bus_space_tag_t iot; 1564 bus_space_handle_t ioh; 1565 ADW_EEPROM *cfg_buf; 1566 { 1567 u_int16_t wval, chksum; 1568 u_int16_t *wbuf; 1569 int eep_addr; 1570 1571 1572 wbuf = (u_int16_t *) cfg_buf; 1573 chksum = 0; 1574 1575 for (eep_addr = ADW_EEP_DVC_CFG_BEGIN; 1576 eep_addr < ADW_EEP_DVC_CFG_END; 1577 eep_addr++, wbuf++) { 1578 wval = AdwReadEEPWord(iot, ioh, eep_addr); 1579 chksum += wval; 1580 *wbuf = wval; 1581 } 1582 1583 *wbuf = AdwReadEEPWord(iot, ioh, eep_addr); 1584 wbuf++; 1585 for (eep_addr = ADW_EEP_DVC_CTL_BEGIN; 1586 eep_addr < ADW_EEP_MAX_WORD_ADDR; 1587 eep_addr++, wbuf++) { 1588 *wbuf = AdwReadEEPWord(iot, ioh, eep_addr); 1589 } 1590 1591 return chksum; 1592 } 1593 1594 1595 /* 1596 * Read the EEPROM from specified location 1597 */ 1598 u_int16_t 1599 AdwReadEEPWord(iot, ioh, eep_word_addr) 1600 bus_space_tag_t iot; 1601 bus_space_handle_t ioh; 1602 int eep_word_addr; 1603 { 1604 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 1605 ADW_EEP_CMD_READ | eep_word_addr); 1606 AdwWaitEEPCmd(iot, ioh); 1607 1608 return ADW_READ_WORD_REGISTER(iot, ioh, IOPW_EE_DATA); 1609 } 1610 1611 1612 /* 1613 * Wait for EEPROM command to complete 1614 */ 1615 void 1616 AdwWaitEEPCmd(iot, ioh) 1617 bus_space_tag_t iot; 1618 bus_space_handle_t ioh; 1619 { 1620 int eep_delay_ms; 1621 1622 1623 for (eep_delay_ms = 0; eep_delay_ms < ADW_EEP_DELAY_MS; eep_delay_ms++){ 1624 if (ADW_READ_WORD_REGISTER(iot, ioh, IOPW_EE_CMD) & 1625 ADW_EEP_CMD_DONE) { 1626 break; 1627 } 1628 AdwSleepMilliSecond(1); 1629 } 1630 1631 ADW_READ_WORD_REGISTER(iot, ioh, IOPW_EE_CMD); 1632 } 1633 1634 1635 /* 1636 * Write the EEPROM from 'cfg_buf'. 1637 */ 1638 void 1639 AdwSetEEPROMConfig(iot, ioh, cfg_buf) 1640 bus_space_tag_t iot; 1641 bus_space_handle_t ioh; 1642 ADW_EEPROM *cfg_buf; 1643 { 1644 u_int16_t *wbuf; 1645 u_int16_t addr, chksum; 1646 1647 1648 wbuf = (u_int16_t *) cfg_buf; 1649 chksum = 0; 1650 1651 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, ADW_EEP_CMD_WRITE_ABLE); 1652 AdwWaitEEPCmd(iot, ioh); 1653 1654 /* 1655 * Write EEPROM from word 0 to word 20 1656 */ 1657 for (addr = ADW_EEP_DVC_CFG_BEGIN; 1658 addr < ADW_EEP_DVC_CFG_END; addr++, wbuf++) { 1659 chksum += *wbuf; 1660 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, *wbuf); 1661 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 1662 ADW_EEP_CMD_WRITE | addr); 1663 AdwWaitEEPCmd(iot, ioh); 1664 AdwSleepMilliSecond(ADW_EEP_DELAY_MS); 1665 } 1666 1667 /* 1668 * Write EEPROM checksum at word 21 1669 */ 1670 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, chksum); 1671 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 1672 ADW_EEP_CMD_WRITE | addr); 1673 AdwWaitEEPCmd(iot, ioh); 1674 wbuf++; /* skip over check_sum */ 1675 1676 /* 1677 * Write EEPROM OEM name at words 22 to 29 1678 */ 1679 for (addr = ADW_EEP_DVC_CTL_BEGIN; 1680 addr < ADW_EEP_MAX_WORD_ADDR; addr++, wbuf++) { 1681 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, *wbuf); 1682 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 1683 ADW_EEP_CMD_WRITE | addr); 1684 AdwWaitEEPCmd(iot, ioh); 1685 } 1686 1687 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 1688 ADW_EEP_CMD_WRITE_DISABLE); 1689 AdwWaitEEPCmd(iot, ioh); 1690 1691 return; 1692 } 1693 1694 1695 /* 1696 * AdwExeScsiQueue() - Send a request to the RISC microcode program. 1697 * 1698 * Allocate a carrier structure, point the carrier to the ADW_SCSI_REQ_Q, 1699 * add the carrier to the ICQ (Initiator Command Queue), and tickle the 1700 * RISC to notify it a new command is ready to be executed. 1701 * 1702 * If 'done_status' is not set to QD_DO_RETRY, then 'error_retry' will be 1703 * set to SCSI_MAX_RETRY. 1704 * 1705 * Return: 1706 * ADW_SUCCESS(1) - The request was successfully queued. 1707 * ADW_BUSY(0) - Resource unavailable; Retry again after pending 1708 * request completes. 1709 * ADW_ERROR(-1) - Invalid ADW_SCSI_REQ_Q request structure 1710 * host IC error. 1711 */ 1712 int 1713 AdwExeScsiQueue(sc, scsiq) 1714 ADW_SOFTC *sc; 1715 ADW_SCSI_REQ_Q *scsiq; 1716 { 1717 bus_space_tag_t iot = sc->sc_iot; 1718 bus_space_handle_t ioh = sc->sc_ioh; 1719 ADW_CCB *ccb; 1720 long req_size; 1721 u_int32_t req_paddr; 1722 ADW_CARRIER *new_carrp; 1723 1724 /* 1725 * The ADW_SCSI_REQ_Q 'target_id' field should never exceed ADW_MAX_TID. 1726 */ 1727 if (scsiq->target_id > ADW_MAX_TID) { 1728 scsiq->host_status = QHSTA_M_INVALID_DEVICE; 1729 scsiq->done_status = QD_WITH_ERROR; 1730 return ADW_ERROR; 1731 } 1732 1733 /* 1734 * Beginning of CRITICAL SECTION: ASSUME splbio() in effect 1735 */ 1736 1737 ccb = adw_ccb_phys_kv(sc, scsiq->ccb_ptr); 1738 1739 /* 1740 * Allocate a carrier and initialize fields. 1741 */ 1742 if ((new_carrp = sc->carr_freelist) == NULL) { 1743 return ADW_BUSY; 1744 } 1745 sc->carr_freelist = ADW_CARRIER_VADDR(sc, 1746 ADW_GET_CARRP(new_carrp->next_ba)); 1747 sc->carr_pending_cnt++; 1748 1749 /* 1750 * Set the carrier to be a stopper by setting 'next_ba' 1751 * to the stopper value. The current stopper will be changed 1752 * below to point to the new stopper. 1753 */ 1754 new_carrp->next_ba = ADW_CQ_STOPPER; 1755 1756 req_size = sizeof(ADW_SCSI_REQ_Q); 1757 req_paddr = sc->sc_dmamap_control->dm_segs[0].ds_addr + 1758 ADW_CCB_OFF(ccb) + offsetof(struct adw_ccb, scsiq); 1759 1760 /* Save physical address of ADW_SCSI_REQ_Q and Carrier. */ 1761 scsiq->scsiq_rptr = req_paddr; 1762 1763 /* 1764 * Every ADW_SCSI_REQ_Q.carr_ba is byte swapped to little-endian 1765 * order during initialization. 1766 */ 1767 scsiq->carr_ba = sc->icq_sp->carr_ba; 1768 scsiq->carr_va = sc->icq_sp->carr_ba; 1769 1770 /* 1771 * Use the current stopper to send the ADW_SCSI_REQ_Q command to 1772 * the microcode. The newly allocated stopper will become the new 1773 * stopper. 1774 */ 1775 sc->icq_sp->areq_ba = req_paddr; 1776 1777 /* 1778 * Set the 'next_ba' pointer for the old stopper to be the 1779 * physical address of the new stopper. The RISC can only 1780 * follow physical addresses. 1781 */ 1782 sc->icq_sp->next_ba = new_carrp->carr_ba; 1783 1784 #if ADW_DEBUG 1785 printf("icq 0x%x, 0x%x, 0x%x, 0x%x\n", 1786 sc->icq_sp->carr_id, 1787 sc->icq_sp->carr_ba, 1788 sc->icq_sp->areq_ba, 1789 sc->icq_sp->next_ba); 1790 #endif 1791 /* 1792 * Set the host adapter stopper pointer to point to the new carrier. 1793 */ 1794 sc->icq_sp = new_carrp; 1795 1796 if (sc->chip_type == ADW_CHIP_ASC3550 || 1797 sc->chip_type == ADW_CHIP_ASC38C0800) { 1798 /* 1799 * Tickle the RISC to tell it to read its Command Queue Head 1800 * pointer. 1801 */ 1802 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, ADW_TICKLE_A); 1803 if (sc->chip_type == ADW_CHIP_ASC3550) { 1804 /* 1805 * Clear the tickle value. In the ASC-3550 the RISC flag 1806 * command 'clr_tickle_a' does not work unless the host 1807 * value is cleared. 1808 */ 1809 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, 1810 ADW_TICKLE_NOP); 1811 } 1812 } else if (sc->chip_type == ADW_CHIP_ASC38C1600) { 1813 /* 1814 * Notify the RISC a carrier is ready by writing the physical 1815 * address of the new carrier stopper to the COMMA register. 1816 */ 1817 ADW_WRITE_DWORD_REGISTER(iot, ioh, IOPDW_COMMA, 1818 new_carrp->carr_ba); 1819 } 1820 1821 /* 1822 * End of CRITICAL SECTION: Must be protected within splbio/splx pair 1823 */ 1824 1825 return ADW_SUCCESS; 1826 } 1827 1828 1829 void 1830 AdwResetChip(iot, ioh) 1831 bus_space_tag_t iot; 1832 bus_space_handle_t ioh; 1833 { 1834 1835 /* 1836 * Reset Chip. 1837 */ 1838 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG, 1839 ADW_CTRL_REG_CMD_RESET); 1840 AdwSleepMilliSecond(100); 1841 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG, 1842 ADW_CTRL_REG_CMD_WR_IO_REG); 1843 } 1844 1845 1846 /* 1847 * Reset SCSI Bus and purge all outstanding requests. 1848 * 1849 * Return Value: 1850 * ADW_TRUE(1) - All requests are purged and SCSI Bus is reset. 1851 * ADW_FALSE(0) - Microcode command failed. 1852 * ADW_ERROR(-1) - Microcode command timed-out. Microcode or IC 1853 * may be hung which requires driver recovery. 1854 */ 1855 int 1856 AdwResetCCB(sc) 1857 ADW_SOFTC *sc; 1858 { 1859 int status; 1860 1861 /* 1862 * Send the SCSI Bus Reset idle start idle command which asserts 1863 * the SCSI Bus Reset signal. 1864 */ 1865 status = AdwSendIdleCmd(sc, (u_int16_t) IDLE_CMD_SCSI_RESET_START, 0L); 1866 if (status != ADW_TRUE) { 1867 return status; 1868 } 1869 1870 /* 1871 * Delay for the specified SCSI Bus Reset hold time. 1872 * 1873 * The hold time delay is done on the host because the RISC has no 1874 * microsecond accurate timer. 1875 */ 1876 AdwDelayMicroSecond((u_int16_t) ADW_SCSI_RESET_HOLD_TIME_US); 1877 1878 /* 1879 * Send the SCSI Bus Reset end idle command which de-asserts 1880 * the SCSI Bus Reset signal and purges any pending requests. 1881 */ 1882 status = AdwSendIdleCmd(sc, (u_int16_t) IDLE_CMD_SCSI_RESET_END, 0L); 1883 if (status != ADW_TRUE) { 1884 return status; 1885 } 1886 1887 AdwSleepMilliSecond((u_int32_t) sc->scsi_reset_wait * 1000); 1888 1889 return status; 1890 } 1891 1892 1893 /* 1894 * Reset chip and SCSI Bus. 1895 * 1896 * Return Value: 1897 * ADW_TRUE(1) - Chip re-initialization and SCSI Bus Reset successful. 1898 * ADW_FALSE(0) - Chip re-initialization and SCSI Bus Reset failure. 1899 */ 1900 int 1901 AdwResetSCSIBus(sc) 1902 ADW_SOFTC *sc; 1903 { 1904 bus_space_tag_t iot = sc->sc_iot; 1905 bus_space_handle_t ioh = sc->sc_ioh; 1906 int status; 1907 u_int16_t wdtr_able, sdtr_able, ppr_able, tagqng_able; 1908 u_int8_t tid, max_cmd[ADW_MAX_TID + 1]; 1909 u_int16_t bios_sig; 1910 1911 1912 /* 1913 * Save current per TID negotiated values. 1914 */ 1915 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, wdtr_able); 1916 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sdtr_able); 1917 if (sc->chip_type == ADW_CHIP_ASC38C1600) { 1918 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, ppr_able); 1919 } 1920 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, tagqng_able); 1921 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 1922 ADW_READ_BYTE_LRAM(iot, ioh, ADW_MC_NUMBER_OF_MAX_CMD + tid, 1923 max_cmd[tid]); 1924 } 1925 1926 /* 1927 * Force the AdwInitAscDriver() function to perform a SCSI Bus Reset 1928 * by clearing the BIOS signature word. 1929 * The initialization functions assumes a SCSI Bus Reset is not 1930 * needed if the BIOS signature word is present. 1931 */ 1932 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_BIOS_SIGNATURE, bios_sig); 1933 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_BIOS_SIGNATURE, 0); 1934 1935 /* 1936 * Stop chip and reset it. 1937 */ 1938 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RISC_CSR, ADW_RISC_CSR_STOP); 1939 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG, 1940 ADW_CTRL_REG_CMD_RESET); 1941 AdwSleepMilliSecond(100); 1942 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG, 1943 ADW_CTRL_REG_CMD_WR_IO_REG); 1944 1945 /* 1946 * Reset Adw Library error code, if any, and try 1947 * re-initializing the chip. 1948 * Then translate initialization return value to status value. 1949 */ 1950 status = (AdwInitDriver(sc) == 0)? ADW_TRUE : ADW_FALSE; 1951 1952 /* 1953 * Restore the BIOS signature word. 1954 */ 1955 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_BIOS_SIGNATURE, bios_sig); 1956 1957 /* 1958 * Restore per TID negotiated values. 1959 */ 1960 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, wdtr_able); 1961 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sdtr_able); 1962 if (sc->chip_type == ADW_CHIP_ASC38C1600) { 1963 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, ppr_able); 1964 } 1965 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, tagqng_able); 1966 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 1967 ADW_WRITE_BYTE_LRAM(iot, ioh, ADW_MC_NUMBER_OF_MAX_CMD + tid, 1968 max_cmd[tid]); 1969 } 1970 1971 return status; 1972 } 1973 1974 1975 /* 1976 * Adw Library Interrupt Service Routine 1977 * 1978 * This function is called by a driver's interrupt service routine. 1979 * The function disables and re-enables interrupts. 1980 * 1981 * Note: AdwISR() can be called when interrupts are disabled or even 1982 * when there is no hardware interrupt condition present. It will 1983 * always check for completed idle commands and microcode requests. 1984 * This is an important feature that shouldn't be changed because it 1985 * allows commands to be completed from polling mode loops. 1986 * 1987 * Return: 1988 * ADW_TRUE(1) - interrupt was pending 1989 * ADW_FALSE(0) - no interrupt was pending 1990 */ 1991 int 1992 AdwISR(sc) 1993 ADW_SOFTC *sc; 1994 { 1995 bus_space_tag_t iot = sc->sc_iot; 1996 bus_space_handle_t ioh = sc->sc_ioh; 1997 u_int8_t int_stat; 1998 u_int16_t target_bit; 1999 ADW_CARRIER *free_carrp/*, *ccb_carr*/; 2000 u_int32_t irq_next_pa; 2001 ADW_SCSI_REQ_Q *scsiq; 2002 ADW_CCB *ccb; 2003 int s; 2004 2005 2006 s = splbio(); 2007 2008 /* Reading the register clears the interrupt. */ 2009 int_stat = ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_INTR_STATUS_REG); 2010 2011 if ((int_stat & (ADW_INTR_STATUS_INTRA | ADW_INTR_STATUS_INTRB | 2012 ADW_INTR_STATUS_INTRC)) == 0) { 2013 splx(s); 2014 return ADW_FALSE; 2015 } 2016 2017 /* 2018 * Notify the driver of an asynchronous microcode condition by 2019 * calling the ADW_SOFTC.async_callback function. The function 2020 * is passed the microcode ADW_MC_INTRB_CODE byte value. 2021 */ 2022 if (int_stat & ADW_INTR_STATUS_INTRB) { 2023 u_int8_t intrb_code; 2024 2025 ADW_READ_BYTE_LRAM(iot, ioh, ADW_MC_INTRB_CODE, intrb_code); 2026 2027 if (sc->chip_type == ADW_CHIP_ASC3550 || 2028 sc->chip_type == ADW_CHIP_ASC38C0800) { 2029 if (intrb_code == ADW_ASYNC_CARRIER_READY_FAILURE && 2030 sc->carr_pending_cnt != 0) { 2031 ADW_WRITE_BYTE_REGISTER(iot, ioh, 2032 IOPB_TICKLE, ADW_TICKLE_A); 2033 if (sc->chip_type == ADW_CHIP_ASC3550) { 2034 ADW_WRITE_BYTE_REGISTER(iot, ioh, 2035 IOPB_TICKLE, ADW_TICKLE_NOP); 2036 } 2037 } 2038 } 2039 2040 if (sc->async_callback != 0) { 2041 (*(ADW_ASYNC_CALLBACK)sc->async_callback)(sc, intrb_code); 2042 } 2043 } 2044 2045 /* 2046 * Check if the IRQ stopper carrier contains a completed request. 2047 */ 2048 while (((irq_next_pa = sc->irq_sp->next_ba) & ADW_RQ_DONE) != 0) 2049 { 2050 #if ADW_DEBUG 2051 printf("irq 0x%x, 0x%x, 0x%x, 0x%x\n", 2052 sc->irq_sp->carr_id, 2053 sc->irq_sp->carr_ba, 2054 sc->irq_sp->areq_ba, 2055 sc->irq_sp->next_ba); 2056 #endif 2057 /* 2058 * Get a pointer to the newly completed ADW_SCSI_REQ_Q 2059 * structure. 2060 * The RISC will have set 'areq_ba' to a virtual address. 2061 * 2062 * The firmware will have copied the ADW_SCSI_REQ_Q.ccb_ptr 2063 * field to the carrier ADW_CARRIER.areq_ba field. 2064 * The conversion below complements the conversion of 2065 * ADW_SCSI_REQ_Q.ccb_ptr' in AdwExeScsiQueue(). 2066 */ 2067 ccb = adw_ccb_phys_kv(sc, sc->irq_sp->areq_ba); 2068 scsiq = &ccb->scsiq; 2069 scsiq->ccb_ptr = sc->irq_sp->areq_ba; 2070 2071 /* 2072 * Request finished with good status and the queue was not 2073 * DMAed to host memory by the firmware. Set all status fields 2074 * to indicate good status. 2075 */ 2076 if ((irq_next_pa & ADW_RQ_GOOD) != 0) { 2077 scsiq->done_status = QD_NO_ERROR; 2078 scsiq->host_status = scsiq->scsi_status = 0; 2079 scsiq->data_cnt = 0L; 2080 } 2081 2082 /* 2083 * Advance the stopper pointer to the next carrier 2084 * ignoring the lower four bits. Free the previous 2085 * stopper carrier. 2086 */ 2087 free_carrp = sc->irq_sp; 2088 sc->irq_sp = ADW_CARRIER_VADDR(sc, ADW_GET_CARRP(irq_next_pa)); 2089 2090 free_carrp->next_ba = (sc->carr_freelist == NULL)? NULL 2091 : sc->carr_freelist->carr_ba; 2092 sc->carr_freelist = free_carrp; 2093 sc->carr_pending_cnt--; 2094 2095 target_bit = ADW_TID_TO_TIDMASK(scsiq->target_id); 2096 2097 /* 2098 * Clear request microcode control flag. 2099 */ 2100 scsiq->cntl = 0; 2101 2102 /* 2103 * Check Condition handling 2104 */ 2105 /* 2106 * If the command that completed was a SCSI INQUIRY and 2107 * LUN 0 was sent the command, then process the INQUIRY 2108 * command information for the device. 2109 */ 2110 if (scsiq->done_status == QD_NO_ERROR && 2111 scsiq->cdb[0] == INQUIRY && 2112 scsiq->target_lun == 0) { 2113 AdwInquiryHandling(sc, scsiq); 2114 } 2115 2116 /* 2117 * Notify the driver of the completed request by passing 2118 * the ADW_SCSI_REQ_Q pointer to its callback function. 2119 */ 2120 (*(ADW_ISR_CALLBACK)sc->isr_callback)(sc, scsiq); 2121 /* 2122 * Note: After the driver callback function is called, 'scsiq' 2123 * can no longer be referenced. 2124 * 2125 * Fall through and continue processing other completed 2126 * requests... 2127 */ 2128 } 2129 2130 splx(s); 2131 2132 return ADW_TRUE; 2133 } 2134 2135 2136 /* 2137 * Send an idle command to the chip and wait for completion. 2138 * 2139 * Command completion is polled for once per microsecond. 2140 * 2141 * The function can be called from anywhere including an interrupt handler. 2142 * But the function is not re-entrant, so it uses the splbio/splx() 2143 * functions to prevent reentrancy. 2144 * 2145 * Return Values: 2146 * ADW_TRUE - command completed successfully 2147 * ADW_FALSE - command failed 2148 * ADW_ERROR - command timed out 2149 */ 2150 int 2151 AdwSendIdleCmd(sc, idle_cmd, idle_cmd_parameter) 2152 ADW_SOFTC *sc; 2153 u_int16_t idle_cmd; 2154 u_int32_t idle_cmd_parameter; 2155 { 2156 bus_space_tag_t iot = sc->sc_iot; 2157 bus_space_handle_t ioh = sc->sc_ioh; 2158 u_int16_t result; 2159 u_int32_t i, j, s; 2160 2161 s = splbio(); 2162 2163 /* 2164 * Clear the idle command status which is set by the microcode 2165 * to a non-zero value to indicate when the command is completed. 2166 */ 2167 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_IDLE_CMD_STATUS, (u_int16_t) 0); 2168 2169 /* 2170 * Write the idle command value after the idle command parameter 2171 * has been written to avoid a race condition. If the order is not 2172 * followed, the microcode may process the idle command before the 2173 * parameters have been written to LRAM. 2174 */ 2175 ADW_WRITE_DWORD_LRAM(iot, ioh, ADW_MC_IDLE_CMD_PARAMETER, 2176 idle_cmd_parameter); 2177 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_IDLE_CMD, idle_cmd); 2178 2179 /* 2180 * Tickle the RISC to tell it to process the idle command. 2181 */ 2182 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, ADW_TICKLE_B); 2183 if (sc->chip_type == ADW_CHIP_ASC3550) { 2184 /* 2185 * Clear the tickle value. In the ASC-3550 the RISC flag 2186 * command 'clr_tickle_b' does not work unless the host 2187 * value is cleared. 2188 */ 2189 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, ADW_TICKLE_NOP); 2190 } 2191 2192 /* Wait for up to 100 millisecond for the idle command to timeout. */ 2193 for (i = 0; i < SCSI_WAIT_100_MSEC; i++) { 2194 /* Poll once each microsecond for command completion. */ 2195 for (j = 0; j < SCSI_US_PER_MSEC; j++) { 2196 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_IDLE_CMD_STATUS, 2197 result); 2198 if (result != 0) { 2199 splx(s); 2200 return result; 2201 } 2202 AdwDelayMicroSecond(1); 2203 } 2204 } 2205 2206 splx(s); 2207 return ADW_ERROR; 2208 } 2209 2210 2211 /* 2212 * Inquiry Information Byte 7 Handling 2213 * 2214 * Handle SCSI Inquiry Command information for a device by setting 2215 * microcode operating variables that affect WDTR, SDTR, and Tag 2216 * Queuing. 2217 */ 2218 void 2219 AdwInquiryHandling(sc, scsiq) 2220 ADW_SOFTC *sc; 2221 ADW_SCSI_REQ_Q *scsiq; 2222 { 2223 #ifndef FAILSAFE 2224 bus_space_tag_t iot = sc->sc_iot; 2225 bus_space_handle_t ioh = sc->sc_ioh; 2226 u_int8_t tid; 2227 ADW_SCSI_INQUIRY *inq; 2228 u_int16_t tidmask; 2229 u_int16_t cfg_word; 2230 2231 2232 /* 2233 * AdwInquiryHandling() requires up to INQUIRY information Byte 7 2234 * to be available. 2235 * 2236 * If less than 8 bytes of INQUIRY information were requested or less 2237 * than 8 bytes were transferred, then return. cdb[4] is the request 2238 * length and the ADW_SCSI_REQ_Q 'data_cnt' field is set by the 2239 * microcode to the transfer residual count. 2240 */ 2241 2242 if (scsiq->cdb[4] < 8 || (scsiq->cdb[4] - scsiq->data_cnt) < 8) { 2243 return; 2244 } 2245 2246 tid = scsiq->target_id; 2247 2248 inq = (ADW_SCSI_INQUIRY *) scsiq->vdata_addr; 2249 2250 /* 2251 * WDTR, SDTR, and Tag Queuing cannot be enabled for old devices. 2252 */ 2253 if ((inq->rsp_data_fmt < 2) /*SCSI-1 | CCS*/ && 2254 (inq->ansi_apr_ver < 2)) { 2255 return; 2256 } else { 2257 /* 2258 * INQUIRY Byte 7 Handling 2259 * 2260 * Use a device's INQUIRY byte 7 to determine whether it 2261 * supports WDTR, SDTR, and Tag Queuing. If the feature 2262 * is enabled in the EEPROM and the device supports the 2263 * feature, then enable it in the microcode. 2264 */ 2265 2266 tidmask = ADW_TID_TO_TIDMASK(tid); 2267 2268 /* 2269 * Wide Transfers 2270 * 2271 * If the EEPROM enabled WDTR for the device and the device 2272 * supports wide bus (16 bit) transfers, then turn on the 2273 * device's 'wdtr_able' bit and write the new value to the 2274 * microcode. 2275 */ 2276 #ifdef SCSI_ADW_WDTR_DISABLE 2277 if(!(tidmask & SCSI_ADW_WDTR_DISABLE)) 2278 #endif /* SCSI_ADW_WDTR_DISABLE */ 2279 if ((sc->wdtr_able & tidmask) && inq->WBus16) { 2280 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, 2281 cfg_word); 2282 if ((cfg_word & tidmask) == 0) { 2283 cfg_word |= tidmask; 2284 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, 2285 cfg_word); 2286 2287 /* 2288 * Clear the microcode "SDTR negotiation" and 2289 * "WDTR negotiation" done indicators for the 2290 * target to cause it to negotiate with the new 2291 * setting set above. 2292 * WDTR when accepted causes the target to enter 2293 * asynchronous mode, so SDTR must be negotiated 2294 */ 2295 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE, 2296 cfg_word); 2297 cfg_word &= ~tidmask; 2298 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE, 2299 cfg_word); 2300 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_DONE, 2301 cfg_word); 2302 cfg_word &= ~tidmask; 2303 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_DONE, 2304 cfg_word); 2305 } 2306 } 2307 2308 /* 2309 * Synchronous Transfers 2310 * 2311 * If the EEPROM enabled SDTR for the device and the device 2312 * supports synchronous transfers, then turn on the device's 2313 * 'sdtr_able' bit. Write the new value to the microcode. 2314 */ 2315 #ifdef SCSI_ADW_SDTR_DISABLE 2316 if(!(tidmask & SCSI_ADW_SDTR_DISABLE)) 2317 #endif /* SCSI_ADW_SDTR_DISABLE */ 2318 if ((sc->sdtr_able & tidmask) && inq->Sync) { 2319 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE,cfg_word); 2320 if ((cfg_word & tidmask) == 0) { 2321 cfg_word |= tidmask; 2322 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, 2323 cfg_word); 2324 2325 /* 2326 * Clear the microcode "SDTR negotiation" 2327 * done indicator for the target to cause it 2328 * to negotiate with the new setting set above. 2329 */ 2330 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE, 2331 cfg_word); 2332 cfg_word &= ~tidmask; 2333 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE, 2334 cfg_word); 2335 } 2336 } 2337 /* 2338 * If the Inquiry data included enough space for the SPI-3 2339 * Clocking field, then check if DT mode is supported. 2340 */ 2341 if (sc->chip_type == ADW_CHIP_ASC38C1600 && 2342 (scsiq->cdb[4] >= 57 || 2343 (scsiq->cdb[4] - scsiq->data_cnt) >= 57)) { 2344 /* 2345 * PPR (Parallel Protocol Request) Capable 2346 * 2347 * If the device supports DT mode, then it must be 2348 * PPR capable. 2349 * The PPR message will be used in place of the SDTR 2350 * and WDTR messages to negotiate synchronous speed 2351 * and offset, transfer width, and protocol options. 2352 */ 2353 if((inq->Clocking) & INQ_CLOCKING_DT_ONLY){ 2354 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, 2355 sc->ppr_able); 2356 sc->ppr_able |= tidmask; 2357 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, 2358 sc->ppr_able); 2359 } 2360 } 2361 2362 /* 2363 * If the EEPROM enabled Tag Queuing for the device and the 2364 * device supports Tag Queueing, then turn on the device's 2365 * 'tagqng_enable' bit in the microcode and set the microcode 2366 * maximum command count to the ADW_SOFTC 'max_dvc_qng' 2367 * value. 2368 * 2369 * Tag Queuing is disabled for the BIOS which runs in polled 2370 * mode and would see no benefit from Tag Queuing. Also by 2371 * disabling Tag Queuing in the BIOS devices with Tag Queuing 2372 * bugs will at least work with the BIOS. 2373 */ 2374 #ifdef SCSI_ADW_TAGQ_DISABLE 2375 if(!(tidmask & SCSI_ADW_TAGQ_DISABLE)) 2376 #endif /* SCSI_ADW_TAGQ_DISABLE */ 2377 if ((sc->tagqng_able & tidmask) && inq->CmdQue) { 2378 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, 2379 cfg_word); 2380 cfg_word |= tidmask; 2381 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, 2382 cfg_word); 2383 2384 ADW_WRITE_BYTE_LRAM(iot, ioh, 2385 ADW_MC_NUMBER_OF_MAX_CMD + tid, 2386 sc->max_dvc_qng); 2387 } 2388 } 2389 #endif /* FAILSAFE */ 2390 } 2391 2392 2393 void 2394 AdwSleepMilliSecond(n) 2395 u_int32_t n; 2396 { 2397 2398 DELAY(n * 1000); 2399 } 2400 2401 2402 void 2403 AdwDelayMicroSecond(n) 2404 u_int32_t n; 2405 { 2406 2407 DELAY(n); 2408 } 2409 2410