1 /* $OpenBSD: adw.c,v 1.52 2015/03/14 03:38:47 jsg Exp $ */ 2 /* $NetBSD: adw.c,v 1.23 2000/05/27 18:24:50 dante Exp $ */ 3 4 /* 5 * Generic driver for the Advanced Systems Inc. SCSI controllers 6 * 7 * Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc. 8 * All rights reserved. 9 * 10 * Author: Baldassare Dante Profeta <dante@mclink.it> 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/types.h> 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/errno.h> 39 #include <sys/device.h> 40 #include <sys/malloc.h> 41 #include <sys/buf.h> 42 #include <sys/timeout.h> 43 44 #include <machine/bus.h> 45 #include <machine/intr.h> 46 47 #include <scsi/scsi_all.h> 48 #include <scsi/scsiconf.h> 49 50 #include <dev/ic/adwlib.h> 51 #include <dev/microcode/adw/adwmcode.h> 52 #include <dev/ic/adw.h> 53 54 /******************************************************************************/ 55 56 57 int adw_alloc_controls(ADW_SOFTC *); 58 int adw_alloc_carriers(ADW_SOFTC *); 59 int adw_create_ccbs(ADW_SOFTC *, ADW_CCB *, int); 60 void adw_ccb_free(void *, void *); 61 void adw_reset_ccb(ADW_CCB *); 62 int adw_init_ccb(ADW_SOFTC *, ADW_CCB *); 63 void *adw_ccb_alloc(void *); 64 int adw_queue_ccb(ADW_SOFTC *, ADW_CCB *, int); 65 66 void adw_scsi_cmd(struct scsi_xfer *); 67 int adw_build_req(struct scsi_xfer *, ADW_CCB *, int); 68 void adw_build_sglist(ADW_CCB *, ADW_SCSI_REQ_Q *, ADW_SG_BLOCK *); 69 void adw_minphys(struct buf *, struct scsi_link *); 70 void adw_isr_callback(ADW_SOFTC *, ADW_SCSI_REQ_Q *); 71 void adw_async_callback(ADW_SOFTC *, u_int8_t); 72 73 void adw_print_info(ADW_SOFTC *, int); 74 75 int adw_poll(ADW_SOFTC *, struct scsi_xfer *, int); 76 void adw_timeout(void *); 77 void adw_reset_bus(ADW_SOFTC *); 78 79 80 /******************************************************************************/ 81 82 83 struct cfdriver adw_cd = { 84 NULL, "adw", DV_DULL 85 }; 86 87 /******************************************************************************/ 88 /* DMA Mapping for Control Blocks */ 89 /******************************************************************************/ 90 91 92 int 93 adw_alloc_controls(ADW_SOFTC *sc) 94 { 95 bus_dma_segment_t seg; 96 int error, rseg; 97 98 /* 99 * Allocate the control structure. 100 */ 101 if ((error = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct adw_control), 102 NBPG, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT | BUS_DMA_ZERO)) != 0) { 103 printf("%s: unable to allocate control structures," 104 " error = %d\n", sc->sc_dev.dv_xname, error); 105 return (error); 106 } 107 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 108 sizeof(struct adw_control), (caddr_t *) & sc->sc_control, 109 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 110 printf("%s: unable to map control structures, error = %d\n", 111 sc->sc_dev.dv_xname, error); 112 return (error); 113 } 114 115 /* 116 * Create and load the DMA map used for the control blocks. 117 */ 118 if ((error = bus_dmamap_create(sc->sc_dmat, sizeof(struct adw_control), 119 1, sizeof(struct adw_control), 0, BUS_DMA_NOWAIT, 120 &sc->sc_dmamap_control)) != 0) { 121 printf("%s: unable to create control DMA map, error = %d\n", 122 sc->sc_dev.dv_xname, error); 123 return (error); 124 } 125 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap_control, 126 sc->sc_control, sizeof(struct adw_control), NULL, 127 BUS_DMA_NOWAIT)) != 0) { 128 printf("%s: unable to load control DMA map, error = %d\n", 129 sc->sc_dev.dv_xname, error); 130 return (error); 131 } 132 133 return (0); 134 } 135 136 137 int 138 adw_alloc_carriers(ADW_SOFTC *sc) 139 { 140 bus_dma_segment_t seg; 141 int error, rseg; 142 143 /* 144 * Allocate the control structure. 145 */ 146 sc->sc_control->carriers = 147 malloc(sizeof(ADW_CARRIER) * ADW_MAX_CARRIER, M_DEVBUF, 148 M_NOWAIT); 149 if (sc->sc_control->carriers == NULL) 150 return (ENOMEM); 151 152 153 if ((error = bus_dmamem_alloc(sc->sc_dmat, 154 sizeof(ADW_CARRIER) * ADW_MAX_CARRIER, 155 0x10, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 156 printf("%s: unable to allocate carrier structures," 157 " error = %d\n", sc->sc_dev.dv_xname, error); 158 return (error); 159 } 160 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 161 sizeof(ADW_CARRIER) * ADW_MAX_CARRIER, 162 (caddr_t *) &sc->sc_control->carriers, 163 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 164 printf("%s: unable to map carrier structures," 165 " error = %d\n", sc->sc_dev.dv_xname, error); 166 return (error); 167 } 168 169 /* 170 * Create and load the DMA map used for the control blocks. 171 */ 172 if ((error = bus_dmamap_create(sc->sc_dmat, 173 sizeof(ADW_CARRIER) * ADW_MAX_CARRIER, 1, 174 sizeof(ADW_CARRIER) * ADW_MAX_CARRIER, 0,BUS_DMA_NOWAIT, 175 &sc->sc_dmamap_carrier)) != 0) { 176 printf("%s: unable to create carriers DMA map," 177 " error = %d\n", sc->sc_dev.dv_xname, error); 178 return (error); 179 } 180 if ((error = bus_dmamap_load(sc->sc_dmat, 181 sc->sc_dmamap_carrier, sc->sc_control->carriers, 182 sizeof(ADW_CARRIER) * ADW_MAX_CARRIER, NULL, 183 BUS_DMA_NOWAIT)) != 0) { 184 printf("%s: unable to load carriers DMA map," 185 " error = %d\n", sc->sc_dev.dv_xname, error); 186 return (error); 187 } 188 189 return (0); 190 } 191 192 193 /******************************************************************************/ 194 /* Control Blocks routines */ 195 /******************************************************************************/ 196 197 198 /* 199 * Create a set of ccbs and add them to the free list. Called once 200 * by adw_init(). We return the number of CCBs successfully created. 201 */ 202 int 203 adw_create_ccbs(ADW_SOFTC *sc, ADW_CCB *ccbstore, int count) 204 { 205 ADW_CCB *ccb; 206 int i, error; 207 208 for (i = 0; i < count; i++) { 209 ccb = &ccbstore[i]; 210 if ((error = adw_init_ccb(sc, ccb)) != 0) { 211 printf("%s: unable to initialize ccb, error = %d\n", 212 sc->sc_dev.dv_xname, error); 213 return (i); 214 } 215 TAILQ_INSERT_TAIL(&sc->sc_free_ccb, ccb, chain); 216 } 217 218 return (i); 219 } 220 221 222 /* 223 * A ccb is put onto the free list. 224 */ 225 void 226 adw_ccb_free(void *xsc, void *xccb) 227 { 228 ADW_SOFTC *sc = xsc; 229 ADW_CCB *ccb = xccb; 230 231 adw_reset_ccb(ccb); 232 233 mtx_enter(&sc->sc_ccb_mtx); 234 TAILQ_INSERT_HEAD(&sc->sc_free_ccb, ccb, chain); 235 mtx_leave(&sc->sc_ccb_mtx); 236 } 237 238 239 void 240 adw_reset_ccb(ADW_CCB *ccb) 241 { 242 243 ccb->flags = 0; 244 } 245 246 247 int 248 adw_init_ccb(ADW_SOFTC *sc, ADW_CCB *ccb) 249 { 250 int hashnum, error; 251 252 /* 253 * Create the DMA map for this CCB. 254 */ 255 error = bus_dmamap_create(sc->sc_dmat, 256 (ADW_MAX_SG_LIST - 1) * PAGE_SIZE, 257 ADW_MAX_SG_LIST, (ADW_MAX_SG_LIST - 1) * PAGE_SIZE, 258 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &ccb->dmamap_xfer); 259 if (error) { 260 printf("%s: unable to create CCB DMA map, error = %d\n", 261 sc->sc_dev.dv_xname, error); 262 return (error); 263 } 264 265 /* 266 * put in the phystokv hash table 267 * Never gets taken out. 268 */ 269 ccb->hashkey = sc->sc_dmamap_control->dm_segs[0].ds_addr + 270 ADW_CCB_OFF(ccb); 271 hashnum = CCB_HASH(ccb->hashkey); 272 ccb->nexthash = sc->sc_ccbhash[hashnum]; 273 sc->sc_ccbhash[hashnum] = ccb; 274 adw_reset_ccb(ccb); 275 return (0); 276 } 277 278 279 /* 280 * Get a free ccb 281 * 282 * If there are none, see if we can allocate a new one 283 */ 284 void * 285 adw_ccb_alloc(void *xsc) 286 { 287 ADW_SOFTC *sc = xsc; 288 ADW_CCB *ccb; 289 290 mtx_enter(&sc->sc_ccb_mtx); 291 ccb = TAILQ_FIRST(&sc->sc_free_ccb); 292 if (ccb) { 293 TAILQ_REMOVE(&sc->sc_free_ccb, ccb, chain); 294 ccb->flags |= CCB_ALLOC; 295 } 296 mtx_leave(&sc->sc_ccb_mtx); 297 298 return (ccb); 299 } 300 301 302 /* 303 * Given a physical address, find the ccb that it corresponds to. 304 */ 305 ADW_CCB * 306 adw_ccb_phys_kv(ADW_SOFTC *sc, u_int32_t ccb_phys) 307 { 308 int hashnum = CCB_HASH(ccb_phys); 309 ADW_CCB *ccb = sc->sc_ccbhash[hashnum]; 310 311 while (ccb) { 312 if (ccb->hashkey == ccb_phys) 313 break; 314 ccb = ccb->nexthash; 315 } 316 return (ccb); 317 } 318 319 320 /* 321 * Queue a CCB to be sent to the controller, and send it if possible. 322 */ 323 int 324 adw_queue_ccb(ADW_SOFTC *sc, ADW_CCB *ccb, int retry) 325 { 326 int errcode = ADW_SUCCESS; 327 328 if(!retry) { 329 TAILQ_INSERT_TAIL(&sc->sc_waiting_ccb, ccb, chain); 330 } 331 332 while ((ccb = TAILQ_FIRST(&sc->sc_waiting_ccb)) != NULL) { 333 334 errcode = AdwExeScsiQueue(sc, &ccb->scsiq); 335 switch(errcode) { 336 case ADW_SUCCESS: 337 break; 338 339 case ADW_BUSY: 340 printf("ADW_BUSY\n"); 341 return(ADW_BUSY); 342 343 case ADW_ERROR: 344 printf("ADW_ERROR\n"); 345 TAILQ_REMOVE(&sc->sc_waiting_ccb, ccb, chain); 346 return(ADW_ERROR); 347 } 348 349 TAILQ_REMOVE(&sc->sc_waiting_ccb, ccb, chain); 350 TAILQ_INSERT_TAIL(&sc->sc_pending_ccb, ccb, chain); 351 352 /* ALWAYS initialize stimeout, lest it contain garbage! */ 353 timeout_set(&ccb->xs->stimeout, adw_timeout, ccb); 354 if ((ccb->xs->flags & SCSI_POLL) == 0) 355 timeout_add_msec(&ccb->xs->stimeout, ccb->timeout); 356 } 357 358 return(errcode); 359 } 360 361 362 /******************************************************************************/ 363 /* SCSI layer interfacing routines */ 364 /******************************************************************************/ 365 366 367 int 368 adw_init(ADW_SOFTC *sc) 369 { 370 u_int16_t warn_code; 371 372 373 sc->cfg.lib_version = (ADW_LIB_VERSION_MAJOR << 8) | 374 ADW_LIB_VERSION_MINOR; 375 sc->cfg.chip_version = 376 ADW_GET_CHIP_VERSION(sc->sc_iot, sc->sc_ioh, sc->bus_type); 377 378 /* 379 * Reset the chip to start and allow register writes. 380 */ 381 if (ADW_FIND_SIGNATURE(sc->sc_iot, sc->sc_ioh) == 0) { 382 panic("adw_init: adw_find_signature failed"); 383 } else { 384 AdwResetChip(sc->sc_iot, sc->sc_ioh); 385 386 warn_code = AdwInitFromEEPROM(sc); 387 388 if (warn_code & ADW_WARN_EEPROM_CHKSUM) 389 printf("%s: Bad checksum found. " 390 "Setting default values\n", 391 sc->sc_dev.dv_xname); 392 if (warn_code & ADW_WARN_EEPROM_TERMINATION) 393 printf("%s: Bad bus termination setting." 394 "Using automatic termination.\n", 395 sc->sc_dev.dv_xname); 396 } 397 398 sc->isr_callback = (ADW_CALLBACK) adw_isr_callback; 399 sc->async_callback = (ADW_CALLBACK) adw_async_callback; 400 401 return 0; 402 } 403 404 405 void 406 adw_attach(ADW_SOFTC *sc) 407 { 408 struct scsibus_attach_args saa; 409 int i, error; 410 411 412 TAILQ_INIT(&sc->sc_free_ccb); 413 TAILQ_INIT(&sc->sc_waiting_ccb); 414 TAILQ_INIT(&sc->sc_pending_ccb); 415 416 mtx_init(&sc->sc_ccb_mtx, IPL_BIO); 417 scsi_iopool_init(&sc->sc_iopool, sc, adw_ccb_alloc, adw_ccb_free); 418 419 /* 420 * Allocate the Control Blocks. 421 */ 422 error = adw_alloc_controls(sc); 423 if (error) 424 return; /* (error) */ ; 425 426 /* 427 * Create and initialize the Control Blocks. 428 */ 429 i = adw_create_ccbs(sc, sc->sc_control->ccbs, ADW_MAX_CCB); 430 if (i == 0) { 431 printf("%s: unable to create Control Blocks\n", 432 sc->sc_dev.dv_xname); 433 return; /* (ENOMEM) */ ; 434 } else if (i != ADW_MAX_CCB) { 435 printf("%s: WARNING: only %d of %d Control Blocks" 436 " created\n", 437 sc->sc_dev.dv_xname, i, ADW_MAX_CCB); 438 } 439 440 /* 441 * Create and initialize the Carriers. 442 */ 443 error = adw_alloc_carriers(sc); 444 if (error) 445 return; /* (error) */ ; 446 447 /* 448 * Zero's the freeze_device status 449 */ 450 bzero(sc->sc_freeze_dev, sizeof(sc->sc_freeze_dev)); 451 452 /* 453 * Initialize the adapter 454 */ 455 switch (AdwInitDriver(sc)) { 456 case ADW_IERR_BIST_PRE_TEST: 457 panic("%s: BIST pre-test error", 458 sc->sc_dev.dv_xname); 459 break; 460 461 case ADW_IERR_BIST_RAM_TEST: 462 panic("%s: BIST RAM test error", 463 sc->sc_dev.dv_xname); 464 break; 465 466 case ADW_IERR_MCODE_CHKSUM: 467 panic("%s: Microcode checksum error", 468 sc->sc_dev.dv_xname); 469 break; 470 471 case ADW_IERR_ILLEGAL_CONNECTION: 472 panic("%s: All three connectors are in use", 473 sc->sc_dev.dv_xname); 474 break; 475 476 case ADW_IERR_REVERSED_CABLE: 477 panic("%s: Cable is reversed", 478 sc->sc_dev.dv_xname); 479 break; 480 481 case ADW_IERR_HVD_DEVICE: 482 panic("%s: HVD attached to LVD connector", 483 sc->sc_dev.dv_xname); 484 break; 485 486 case ADW_IERR_SINGLE_END_DEVICE: 487 panic("%s: single-ended device is attached to" 488 " one of the connectors", 489 sc->sc_dev.dv_xname); 490 break; 491 492 case ADW_IERR_NO_CARRIER: 493 panic("%s: unable to create Carriers", 494 sc->sc_dev.dv_xname); 495 break; 496 497 case ADW_WARN_BUSRESET_ERROR: 498 printf("%s: WARNING: Bus Reset Error\n", 499 sc->sc_dev.dv_xname); 500 break; 501 } 502 503 /* 504 * Fill in the adapter. 505 */ 506 sc->sc_adapter.scsi_cmd = adw_scsi_cmd; 507 sc->sc_adapter.scsi_minphys = adw_minphys; 508 509 /* 510 * fill in the prototype scsi_link. 511 */ 512 sc->sc_link.adapter_softc = sc; 513 sc->sc_link.adapter_target = sc->chip_scsi_id; 514 sc->sc_link.adapter = &sc->sc_adapter; 515 sc->sc_link.openings = 4; 516 sc->sc_link.adapter_buswidth = ADW_MAX_TID+1; 517 sc->sc_link.pool = &sc->sc_iopool; 518 519 bzero(&saa, sizeof(saa)); 520 saa.saa_sc_link = &sc->sc_link; 521 522 config_found(&sc->sc_dev, &saa, scsiprint); 523 } 524 525 526 void 527 adw_minphys(struct buf *bp, struct scsi_link *sl) 528 { 529 530 if (bp->b_bcount > ((ADW_MAX_SG_LIST - 1) * PAGE_SIZE)) 531 bp->b_bcount = ((ADW_MAX_SG_LIST - 1) * PAGE_SIZE); 532 minphys(bp); 533 } 534 535 536 /* 537 * start a scsi operation given the command and the data address. 538 * Also needs the unit, target and lu. 539 */ 540 void 541 adw_scsi_cmd(struct scsi_xfer *xs) 542 { 543 struct scsi_link *sc_link = xs->sc_link; 544 ADW_SOFTC *sc = sc_link->adapter_softc; 545 ADW_CCB *ccb; 546 int s, nowait = 0, retry = 0; 547 int flags; 548 549 /* 550 * get a ccb to use. If the transfer 551 * is from a buf (possibly from interrupt time) 552 * then we can't allow it to sleep 553 */ 554 555 flags = xs->flags; 556 if (nowait) 557 flags |= SCSI_NOSLEEP; 558 ccb = xs->io; 559 560 ccb->xs = xs; 561 ccb->timeout = xs->timeout; 562 563 if (adw_build_req(xs, ccb, flags)) { 564 retryagain: 565 s = splbio(); 566 retry = adw_queue_ccb(sc, ccb, retry); 567 splx(s); 568 569 switch(retry) { 570 case ADW_BUSY: 571 goto retryagain; 572 573 case ADW_ERROR: 574 xs->error = XS_DRIVER_STUFFUP; 575 scsi_done(xs); 576 return; 577 } 578 579 /* 580 * Usually return SUCCESSFULLY QUEUED 581 */ 582 if ((xs->flags & SCSI_POLL) == 0) 583 return; 584 585 /* 586 * If we can't use interrupts, poll on completion 587 */ 588 if (adw_poll(sc, xs, ccb->timeout)) { 589 adw_timeout(ccb); 590 if (adw_poll(sc, xs, ccb->timeout)) 591 adw_timeout(ccb); 592 } 593 } else { 594 /* adw_build_req() has set xs->error already */ 595 scsi_done(xs); 596 } 597 } 598 599 600 /* 601 * Build a request structure for the Wide Boards. 602 */ 603 int 604 adw_build_req(struct scsi_xfer *xs, ADW_CCB *ccb, int flags) 605 { 606 struct scsi_link *sc_link = xs->sc_link; 607 ADW_SOFTC *sc = sc_link->adapter_softc; 608 bus_dma_tag_t dmat = sc->sc_dmat; 609 ADW_SCSI_REQ_Q *scsiqp; 610 int error; 611 612 scsiqp = &ccb->scsiq; 613 bzero(scsiqp, sizeof(ADW_SCSI_REQ_Q)); 614 615 /* 616 * Set the ADW_SCSI_REQ_Q 'ccb_ptr' to point to the 617 * physical CCB structure. 618 */ 619 scsiqp->ccb_ptr = ccb->hashkey; 620 621 /* 622 * Build the ADW_SCSI_REQ_Q request. 623 */ 624 625 /* 626 * Set CDB length and copy it to the request structure. 627 * For wide boards a CDB length maximum of 16 bytes 628 * is supported. 629 */ 630 scsiqp->cdb_len = xs->cmdlen; 631 bcopy((caddr_t)xs->cmd, &scsiqp->cdb, 12); 632 bcopy((caddr_t)xs->cmd + 12, &scsiqp->cdb16, 4); 633 634 scsiqp->target_id = sc_link->target; 635 scsiqp->target_lun = sc_link->lun; 636 637 scsiqp->vsense_addr = &ccb->scsi_sense; 638 scsiqp->sense_addr = sc->sc_dmamap_control->dm_segs[0].ds_addr + 639 ADW_CCB_OFF(ccb) + offsetof(struct adw_ccb, scsi_sense); 640 scsiqp->sense_len = sizeof(struct scsi_sense_data); 641 642 /* 643 * Build ADW_SCSI_REQ_Q for a scatter-gather buffer command. 644 */ 645 if (xs->datalen) { 646 /* 647 * Map the DMA transfer. 648 */ 649 error = bus_dmamap_load(dmat, 650 ccb->dmamap_xfer, xs->data, xs->datalen, NULL, 651 (flags & SCSI_NOSLEEP) ? 652 BUS_DMA_NOWAIT : BUS_DMA_WAITOK); 653 654 if (error) { 655 if (error == EFBIG) { 656 printf("%s: adw_scsi_cmd, more than %d dma" 657 " segments\n", 658 sc->sc_dev.dv_xname, ADW_MAX_SG_LIST); 659 } else { 660 printf("%s: adw_scsi_cmd, error %d loading" 661 " dma map\n", 662 sc->sc_dev.dv_xname, error); 663 } 664 665 xs->error = XS_DRIVER_STUFFUP; 666 return (0); 667 } 668 bus_dmamap_sync(dmat, ccb->dmamap_xfer, 669 0, ccb->dmamap_xfer->dm_mapsize, 670 (xs->flags & SCSI_DATA_IN) ? 671 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 672 673 /* 674 * Build scatter-gather list. 675 */ 676 scsiqp->data_cnt = xs->datalen; 677 scsiqp->vdata_addr = xs->data; 678 scsiqp->data_addr = ccb->dmamap_xfer->dm_segs[0].ds_addr; 679 bzero(ccb->sg_block, sizeof(ADW_SG_BLOCK) * ADW_NUM_SG_BLOCK); 680 adw_build_sglist(ccb, scsiqp, ccb->sg_block); 681 } else { 682 /* 683 * No data xfer, use non S/G values. 684 */ 685 scsiqp->data_cnt = 0; 686 scsiqp->vdata_addr = 0; 687 scsiqp->data_addr = 0; 688 } 689 690 return (1); 691 } 692 693 694 /* 695 * Build scatter-gather list for Wide Boards. 696 */ 697 void 698 adw_build_sglist(ADW_CCB *ccb, ADW_SCSI_REQ_Q *scsiqp, ADW_SG_BLOCK *sg_block) 699 { 700 u_long sg_block_next_addr; /* block and its next */ 701 u_int32_t sg_block_physical_addr; 702 int i; /* how many SG entries */ 703 bus_dma_segment_t *sg_list = &ccb->dmamap_xfer->dm_segs[0]; 704 int sg_elem_cnt = ccb->dmamap_xfer->dm_nsegs; 705 706 707 sg_block_next_addr = (u_long) sg_block; /* allow math operation */ 708 sg_block_physical_addr = ccb->hashkey + 709 offsetof(struct adw_ccb, sg_block[0]); 710 scsiqp->sg_real_addr = sg_block_physical_addr; 711 712 /* 713 * If there are more than NO_OF_SG_PER_BLOCK dma segments (hw sg-list) 714 * then split the request into multiple sg-list blocks. 715 */ 716 717 do { 718 for (i = 0; i < NO_OF_SG_PER_BLOCK; i++) { 719 sg_block->sg_list[i].sg_addr = sg_list->ds_addr; 720 sg_block->sg_list[i].sg_count = sg_list->ds_len; 721 722 if (--sg_elem_cnt == 0) { 723 /* last entry, get out */ 724 sg_block->sg_cnt = i + 1; 725 sg_block->sg_ptr = 0; /* next link = NULL */ 726 return; 727 } 728 sg_list++; 729 } 730 sg_block_next_addr += sizeof(ADW_SG_BLOCK); 731 sg_block_physical_addr += sizeof(ADW_SG_BLOCK); 732 733 sg_block->sg_cnt = NO_OF_SG_PER_BLOCK; 734 sg_block->sg_ptr = sg_block_physical_addr; 735 sg_block = (ADW_SG_BLOCK *) sg_block_next_addr; /* virt. addr */ 736 } while (1); 737 } 738 739 740 /******************************************************************************/ 741 /* Interrupts and TimeOut routines */ 742 /******************************************************************************/ 743 744 745 int 746 adw_intr(void *arg) 747 { 748 ADW_SOFTC *sc = arg; 749 750 751 if(AdwISR(sc) != ADW_FALSE) { 752 return (1); 753 } 754 755 return (0); 756 } 757 758 759 /* 760 * Poll a particular unit, looking for a particular xs 761 */ 762 int 763 adw_poll(ADW_SOFTC *sc, struct scsi_xfer *xs, int count) 764 { 765 int s; 766 767 /* timeouts are in msec, so we loop in 1000 usec cycles */ 768 while (count > 0) { 769 s = splbio(); 770 adw_intr(sc); 771 splx(s); 772 if (xs->flags & ITSDONE) { 773 if ((xs->cmd->opcode == INQUIRY) 774 && (xs->sc_link->lun == 0) 775 && (xs->error == XS_NOERROR)) 776 adw_print_info(sc, xs->sc_link->target); 777 return (0); 778 } 779 delay(1000); /* only happens in boot so ok */ 780 count--; 781 } 782 return (1); 783 } 784 785 786 void 787 adw_timeout(void *arg) 788 { 789 ADW_CCB *ccb = arg; 790 struct scsi_xfer *xs = ccb->xs; 791 struct scsi_link *sc_link = xs->sc_link; 792 ADW_SOFTC *sc = sc_link->adapter_softc; 793 int s; 794 795 sc_print_addr(sc_link); 796 printf("timed out"); 797 798 s = splbio(); 799 800 if (ccb->flags & CCB_ABORTED) { 801 /* 802 * Abort Timed Out 803 * 804 * No more opportunities. Lets try resetting the bus and 805 * reinitialize the host adapter. 806 */ 807 timeout_del(&xs->stimeout); 808 printf(" AGAIN. Resetting SCSI Bus\n"); 809 adw_reset_bus(sc); 810 splx(s); 811 return; 812 } else if (ccb->flags & CCB_ABORTING) { 813 /* 814 * Abort the operation that has timed out. 815 * 816 * Second opportunity. 817 */ 818 printf("\n"); 819 xs->error = XS_TIMEOUT; 820 ccb->flags |= CCB_ABORTED; 821 #if 0 822 /* 823 * - XXX - 3.3a microcode is BROKEN!!! 824 * 825 * We cannot abort a CCB, so we can only hope the command 826 * get completed before the next timeout, otherwise a 827 * Bus Reset will arrive inexorably. 828 */ 829 /* 830 * ADW_ABORT_CCB() makes the board to generate an interrupt 831 * 832 * - XXX - The above assertion MUST be verified (and this 833 * code changed as well [callout_*()]), when the 834 * ADW_ABORT_CCB will be working again 835 */ 836 ADW_ABORT_CCB(sc, ccb); 837 #endif 838 /* 839 * waiting for multishot callout_reset() let's restart it 840 * by hand so the next time a timeout event will occur 841 * we will reset the bus. 842 */ 843 timeout_add_msec(&xs->stimeout, ccb->timeout); 844 } else { 845 /* 846 * Abort the operation that has timed out. 847 * 848 * First opportunity. 849 */ 850 printf("\n"); 851 xs->error = XS_TIMEOUT; 852 ccb->flags |= CCB_ABORTING; 853 #if 0 854 /* 855 * - XXX - 3.3a microcode is BROKEN!!! 856 * 857 * We cannot abort a CCB, so we can only hope the command 858 * get completed before the next 2 timeout, otherwise a 859 * Bus Reset will arrive inexorably. 860 */ 861 /* 862 * ADW_ABORT_CCB() makes the board to generate an interrupt 863 * 864 * - XXX - The above assertion MUST be verified (and this 865 * code changed as well [callout_*()]), when the 866 * ADW_ABORT_CCB will be working again 867 */ 868 ADW_ABORT_CCB(sc, ccb); 869 #endif 870 /* 871 * waiting for multishot callout_reset() let's restart it 872 * by hand so to give a second opportunity to the command 873 * which timed-out. 874 */ 875 timeout_add_msec(&xs->stimeout, ccb->timeout); 876 } 877 878 splx(s); 879 } 880 881 882 void 883 adw_reset_bus(ADW_SOFTC *sc) 884 { 885 ADW_CCB *ccb; 886 int s; 887 888 s = splbio(); 889 AdwResetSCSIBus(sc); /* XXX - should check return value? */ 890 while((ccb = TAILQ_LAST(&sc->sc_pending_ccb, 891 adw_pending_ccb)) != NULL) { 892 timeout_del(&ccb->xs->stimeout); 893 TAILQ_REMOVE(&sc->sc_pending_ccb, ccb, chain); 894 TAILQ_INSERT_HEAD(&sc->sc_waiting_ccb, ccb, chain); 895 } 896 897 bzero(sc->sc_freeze_dev, sizeof(sc->sc_freeze_dev)); 898 adw_queue_ccb(sc, TAILQ_FIRST(&sc->sc_waiting_ccb), 1); 899 900 splx(s); 901 } 902 903 904 /******************************************************************************/ 905 /* Host Adapter and Peripherals Information Routines */ 906 /******************************************************************************/ 907 908 909 void 910 adw_print_info(ADW_SOFTC *sc, int tid) 911 { 912 bus_space_handle_t ioh = sc->sc_ioh; 913 bus_space_tag_t iot = sc->sc_iot; 914 u_int16_t hshk_cfg, able_mask, period = 0; 915 916 /* hshk/HSHK means 'handskake' */ 917 918 ADW_READ_WORD_LRAM(iot, ioh, 919 ADW_MC_DEVICE_HSHK_CFG_TABLE + (2 * tid), hshk_cfg); 920 921 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, able_mask); 922 if ((able_mask & ADW_TID_TO_TIDMASK(tid)) == 0) 923 hshk_cfg &= ~HSHK_CFG_WIDE_XFR; 924 925 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, able_mask); 926 if ((able_mask & ADW_TID_TO_TIDMASK(tid)) == 0) 927 hshk_cfg &= ~HSHK_CFG_OFFSET; 928 929 printf("%s: target %d using %d bit ", sc->sc_dev.dv_xname, tid, 930 (hshk_cfg & HSHK_CFG_WIDE_XFR) ? 16 : 8); 931 932 if ((hshk_cfg & HSHK_CFG_OFFSET) == 0) 933 printf("async "); 934 else { 935 period = (hshk_cfg & 0x1f00) >> 8; 936 switch (period) { 937 case 0x11: 938 printf("80.0 "); 939 break; 940 case 0x10: 941 printf("40.0 "); 942 break; 943 default: 944 period = (period * 25) + 50; 945 printf("%d.%d ", 1000/period, ADW_TENTHS(1000, period)); 946 break; 947 } 948 printf("MHz %d REQ/ACK offset ", hshk_cfg & HSHK_CFG_OFFSET); 949 } 950 951 printf("xfers\n"); 952 } 953 954 955 /******************************************************************************/ 956 /* WIDE boards Interrupt callbacks */ 957 /******************************************************************************/ 958 959 960 /* 961 * adw_isr_callback() - Second Level Interrupt Handler called by AdwISR() 962 * 963 * Interrupt callback function for the Wide SCSI Adw Library. 964 * 965 * Notice: 966 * Interrupts are disabled by the caller (AdwISR() function), and will be 967 * enabled at the end of the caller. 968 */ 969 void 970 adw_isr_callback(ADW_SOFTC *sc, ADW_SCSI_REQ_Q *scsiq) 971 { 972 bus_dma_tag_t dmat; 973 ADW_CCB *ccb; 974 struct scsi_xfer *xs; 975 struct scsi_sense_data *s1, *s2; 976 977 978 ccb = adw_ccb_phys_kv(sc, scsiq->ccb_ptr); 979 TAILQ_REMOVE(&sc->sc_pending_ccb, ccb, chain); 980 981 if ((ccb->flags & CCB_ALLOC) == 0) { 982 panic("%s: unallocated ccb found on pending list!", 983 sc->sc_dev.dv_xname); 984 return; 985 } 986 987 xs = ccb->xs; 988 timeout_del(&xs->stimeout); 989 990 /* 991 * If we were a data transfer, unload the map that described 992 * the data buffer. 993 */ 994 dmat = sc->sc_dmat; 995 if (xs->datalen) { 996 bus_dmamap_sync(dmat, ccb->dmamap_xfer, 997 0, ccb->dmamap_xfer->dm_mapsize, 998 ((xs->flags & SCSI_DATA_IN) ? 999 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE)); 1000 bus_dmamap_unload(dmat, ccb->dmamap_xfer); 1001 } 1002 1003 /* 1004 * 'done_status' contains the command's ending status. 1005 * 'host_status' contains the host adapter status. 1006 * 'scsi_status' contains the scsi peripheral status. 1007 */ 1008 1009 sc->sc_freeze_dev[scsiq->target_id] = 0; 1010 xs->status = scsiq->scsi_status; 1011 1012 switch (scsiq->done_status) { 1013 case QD_NO_ERROR: /* (scsi_status == 0) && (host_status == 0) */ 1014 NO_ERROR: 1015 xs->resid = scsiq->data_cnt; 1016 xs->error = XS_NOERROR; 1017 break; 1018 1019 case QD_WITH_ERROR: 1020 switch (scsiq->host_status) { 1021 case QHSTA_NO_ERROR: 1022 switch (scsiq->scsi_status) { 1023 case SCSI_COND_MET: 1024 case SCSI_INTERM: 1025 case SCSI_INTERM_COND_MET: 1026 /* 1027 * These non-zero status values are 1028 * not really error conditions. 1029 * 1030 * XXX - would it be too paranoid to 1031 * add SCSI_OK here in 1032 * case the docs are wrong re 1033 * QD_NO_ERROR? 1034 */ 1035 goto NO_ERROR; 1036 1037 case SCSI_CHECK: 1038 case SCSI_TERMINATED: 1039 case SCSI_ACA_ACTIVE: 1040 s1 = &ccb->scsi_sense; 1041 s2 = &xs->sense; 1042 *s2 = *s1; 1043 xs->error = XS_SENSE; 1044 break; 1045 1046 case SCSI_BUSY: 1047 case SCSI_QUEUE_FULL: 1048 case SCSI_RESV_CONFLICT: 1049 sc->sc_freeze_dev[scsiq->target_id] = 1; 1050 xs->error = XS_BUSY; 1051 break; 1052 1053 default: /* scsiq->scsi_status value */ 1054 printf("%s: bad scsi_status: 0x%02x.\n" 1055 ,sc->sc_dev.dv_xname 1056 ,scsiq->scsi_status); 1057 xs->error = XS_DRIVER_STUFFUP; 1058 break; 1059 } 1060 break; 1061 1062 case QHSTA_M_SEL_TIMEOUT: 1063 xs->error = XS_SELTIMEOUT; 1064 break; 1065 1066 case QHSTA_M_DIRECTION_ERR: 1067 case QHSTA_M_SXFR_OFF_UFLW: 1068 case QHSTA_M_SXFR_OFF_OFLW: 1069 case QHSTA_M_SXFR_XFR_OFLW: 1070 case QHSTA_M_QUEUE_ABORTED: 1071 case QHSTA_M_INVALID_DEVICE: 1072 case QHSTA_M_SGBACKUP_ERROR: 1073 case QHSTA_M_SXFR_DESELECTED: 1074 case QHSTA_M_SXFR_XFR_PH_ERR: 1075 case QHSTA_M_BUS_DEVICE_RESET: 1076 case QHSTA_M_NO_AUTO_REQ_SENSE: 1077 case QHSTA_M_BAD_CMPL_STATUS_IN: 1078 case QHSTA_M_SXFR_UNKNOWN_ERROR: 1079 case QHSTA_M_AUTO_REQ_SENSE_FAIL: 1080 case QHSTA_M_UNEXPECTED_BUS_FREE: 1081 printf("%s: host adapter error 0x%02x." 1082 " See adw(4).\n" 1083 ,sc->sc_dev.dv_xname, scsiq->host_status); 1084 xs->error = XS_DRIVER_STUFFUP; 1085 break; 1086 1087 case QHSTA_M_RDMA_PERR: 1088 case QHSTA_M_SXFR_WD_TMO: 1089 case QHSTA_M_WTM_TIMEOUT: 1090 case QHSTA_M_FROZEN_TIDQ: 1091 case QHSTA_M_SXFR_SDMA_ERR: 1092 case QHSTA_M_SXFR_SXFR_PERR: 1093 case QHSTA_M_SCSI_BUS_RESET: 1094 case QHSTA_M_DIRECTION_ERR_HUNG: 1095 case QHSTA_M_SCSI_BUS_RESET_UNSOL: 1096 /* 1097 * XXX - are all these cases really asking 1098 * for a card reset? _BUS_RESET and 1099 * _BUS_RESET_UNSOL added just to make 1100 * sure the pending queue is cleared out 1101 * in case card has lost track of them. 1102 */ 1103 printf("%s: host adapter error 0x%02x," 1104 " resetting bus. See adw(4).\n" 1105 ,sc->sc_dev.dv_xname, scsiq->host_status); 1106 adw_reset_bus(sc); 1107 xs->error = XS_RESET; 1108 break; 1109 1110 default: /* scsiq->host_status value */ 1111 /* 1112 * XXX - is a panic really appropriate here? If 1113 * not, would it be better to make the 1114 * XS_DRIVER_STUFFUP case above the 1115 * default behaviour? Or XS_RESET? 1116 */ 1117 panic("%s: bad host_status: 0x%02x" 1118 ,sc->sc_dev.dv_xname, scsiq->host_status); 1119 break; 1120 } 1121 break; 1122 1123 case QD_ABORTED_BY_HOST: 1124 xs->error = XS_DRIVER_STUFFUP; 1125 break; 1126 1127 default: /* scsiq->done_status value */ 1128 /* 1129 * XXX - would QD_NO_STATUS really mean the I/O is not 1130 * done? and would that mean it should somehow be 1131 * put back as a pending I/O? 1132 */ 1133 printf("%s: bad done_status: 0x%02x" 1134 " (host_status: 0x%02x, scsi_status: 0x%02x)\n" 1135 ,sc->sc_dev.dv_xname 1136 ,scsiq->done_status 1137 ,scsiq->host_status 1138 ,scsiq->scsi_status); 1139 xs->error = XS_DRIVER_STUFFUP; 1140 break; 1141 } 1142 1143 scsi_done(xs); 1144 } 1145 1146 1147 /* 1148 * adw_async_callback() - Adw Library asynchronous event callback function. 1149 */ 1150 void 1151 adw_async_callback(ADW_SOFTC *sc, u_int8_t code) 1152 { 1153 switch (code) { 1154 case ADW_ASYNC_SCSI_BUS_RESET_DET: 1155 /* The firmware detected a SCSI Bus reset. */ 1156 printf("%s: SCSI Bus reset detected\n", sc->sc_dev.dv_xname); 1157 break; 1158 1159 case ADW_ASYNC_RDMA_FAILURE: 1160 /* 1161 * Handle RDMA failure by resetting the SCSI Bus and 1162 * possibly the chip if it is unresponsive. 1163 */ 1164 printf("%s: RDMA failure. Resetting the SCSI Bus and" 1165 " the adapter\n", sc->sc_dev.dv_xname); 1166 adw_reset_bus(sc); 1167 break; 1168 1169 case ADW_HOST_SCSI_BUS_RESET: 1170 /* Host generated SCSI bus reset occurred. */ 1171 printf("%s: Host generated SCSI bus reset occurred\n", 1172 sc->sc_dev.dv_xname); 1173 break; 1174 1175 1176 case ADW_ASYNC_CARRIER_READY_FAILURE: 1177 /* 1178 * Carrier Ready failure. 1179 * 1180 * A warning only - RISC too busy to realize it's been 1181 * tickled. Occurs in normal operation under heavy 1182 * load, so a message is printed only when ADW_DEBUG'ing 1183 */ 1184 #ifdef ADW_DEBUG 1185 printf("%s: Carrier Ready failure!\n", sc->sc_dev.dv_xname); 1186 #endif 1187 break; 1188 1189 default: 1190 printf("%s: Unknown Async callback code (ignored): 0x%02x\n", 1191 sc->sc_dev.dv_xname, code); 1192 break; 1193 } 1194 } 1195