1 /* $OpenBSD: adw.c,v 1.38 2009/02/16 21:19:06 miod Exp $ */ 2 /* $NetBSD: adw.c,v 1.23 2000/05/27 18:24:50 dante Exp $ */ 3 4 /* 5 * Generic driver for the Advanced Systems Inc. SCSI controllers 6 * 7 * Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc. 8 * All rights reserved. 9 * 10 * Author: Baldassare Dante Profeta <dante@mclink.it> 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/types.h> 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/errno.h> 39 #include <sys/ioctl.h> 40 #include <sys/device.h> 41 #include <sys/malloc.h> 42 #include <sys/buf.h> 43 #include <sys/proc.h> 44 #include <sys/user.h> 45 #include <sys/timeout.h> 46 47 #include <machine/bus.h> 48 #include <machine/intr.h> 49 50 #include <scsi/scsi_all.h> 51 #include <scsi/scsiconf.h> 52 53 #include <dev/ic/adwlib.h> 54 #include <dev/microcode/adw/adwmcode.h> 55 #include <dev/ic/adw.h> 56 57 #ifndef DDB 58 #define Debugger() panic("should call debugger here (adw.c)") 59 #endif /* ! DDB */ 60 61 /******************************************************************************/ 62 63 64 int adw_alloc_controls(ADW_SOFTC *); 65 int adw_alloc_carriers(ADW_SOFTC *); 66 int adw_create_ccbs(ADW_SOFTC *, ADW_CCB *, int); 67 void adw_free_ccb(ADW_SOFTC *, ADW_CCB *); 68 void adw_reset_ccb(ADW_CCB *); 69 int adw_init_ccb(ADW_SOFTC *, ADW_CCB *); 70 ADW_CCB *adw_get_ccb(ADW_SOFTC *, int); 71 int adw_queue_ccb(ADW_SOFTC *, ADW_CCB *, int); 72 73 int adw_scsi_cmd(struct scsi_xfer *); 74 int adw_build_req(struct scsi_xfer *, ADW_CCB *, int); 75 void adw_build_sglist(ADW_CCB *, ADW_SCSI_REQ_Q *, ADW_SG_BLOCK *); 76 void adw_minphys(struct buf *, struct scsi_link *); 77 void adw_isr_callback(ADW_SOFTC *, ADW_SCSI_REQ_Q *); 78 void adw_async_callback(ADW_SOFTC *, u_int8_t); 79 80 void adw_print_info(ADW_SOFTC *, int); 81 82 int adw_poll(ADW_SOFTC *, struct scsi_xfer *, int); 83 void adw_timeout(void *); 84 void adw_reset_bus(ADW_SOFTC *); 85 86 87 /******************************************************************************/ 88 89 90 struct cfdriver adw_cd = { 91 NULL, "adw", DV_DULL 92 }; 93 94 /* the below structure is so we have a default dev struct for our link struct */ 95 struct scsi_device adw_dev = 96 { 97 NULL, /* Use default error handler */ 98 NULL, /* have a queue, served by this */ 99 NULL, /* have no async handler */ 100 NULL, /* Use default 'done' routine */ 101 }; 102 103 104 /******************************************************************************/ 105 /* DMA Mapping for Control Blocks */ 106 /******************************************************************************/ 107 108 109 int 110 adw_alloc_controls(sc) 111 ADW_SOFTC *sc; 112 { 113 bus_dma_segment_t seg; 114 int error, rseg; 115 116 /* 117 * Allocate the control structure. 118 */ 119 if ((error = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct adw_control), 120 NBPG, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 121 printf("%s: unable to allocate control structures," 122 " error = %d\n", sc->sc_dev.dv_xname, error); 123 return (error); 124 } 125 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 126 sizeof(struct adw_control), (caddr_t *) & sc->sc_control, 127 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 128 printf("%s: unable to map control structures, error = %d\n", 129 sc->sc_dev.dv_xname, error); 130 return (error); 131 } 132 133 /* 134 * Create and load the DMA map used for the control blocks. 135 */ 136 if ((error = bus_dmamap_create(sc->sc_dmat, sizeof(struct adw_control), 137 1, sizeof(struct adw_control), 0, BUS_DMA_NOWAIT, 138 &sc->sc_dmamap_control)) != 0) { 139 printf("%s: unable to create control DMA map, error = %d\n", 140 sc->sc_dev.dv_xname, error); 141 return (error); 142 } 143 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap_control, 144 sc->sc_control, sizeof(struct adw_control), NULL, 145 BUS_DMA_NOWAIT)) != 0) { 146 printf("%s: unable to load control DMA map, error = %d\n", 147 sc->sc_dev.dv_xname, error); 148 return (error); 149 } 150 151 return (0); 152 } 153 154 155 int 156 adw_alloc_carriers(sc) 157 ADW_SOFTC *sc; 158 { 159 bus_dma_segment_t seg; 160 int error, rseg; 161 162 /* 163 * Allocate the control structure. 164 */ 165 sc->sc_control->carriers = 166 malloc(sizeof(ADW_CARRIER) * ADW_MAX_CARRIER, M_DEVBUF, 167 M_NOWAIT); 168 if (sc->sc_control->carriers == NULL) 169 return (ENOMEM); 170 171 172 if ((error = bus_dmamem_alloc(sc->sc_dmat, 173 sizeof(ADW_CARRIER) * ADW_MAX_CARRIER, 174 0x10, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 175 printf("%s: unable to allocate carrier structures," 176 " error = %d\n", sc->sc_dev.dv_xname, error); 177 return (error); 178 } 179 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 180 sizeof(ADW_CARRIER) * ADW_MAX_CARRIER, 181 (caddr_t *) &sc->sc_control->carriers, 182 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 183 printf("%s: unable to map carrier structures," 184 " error = %d\n", sc->sc_dev.dv_xname, error); 185 return (error); 186 } 187 188 /* 189 * Create and load the DMA map used for the control blocks. 190 */ 191 if ((error = bus_dmamap_create(sc->sc_dmat, 192 sizeof(ADW_CARRIER) * ADW_MAX_CARRIER, 1, 193 sizeof(ADW_CARRIER) * ADW_MAX_CARRIER, 0,BUS_DMA_NOWAIT, 194 &sc->sc_dmamap_carrier)) != 0) { 195 printf("%s: unable to create carriers DMA map," 196 " error = %d\n", sc->sc_dev.dv_xname, error); 197 return (error); 198 } 199 if ((error = bus_dmamap_load(sc->sc_dmat, 200 sc->sc_dmamap_carrier, sc->sc_control->carriers, 201 sizeof(ADW_CARRIER) * ADW_MAX_CARRIER, NULL, 202 BUS_DMA_NOWAIT)) != 0) { 203 printf("%s: unable to load carriers DMA map," 204 " error = %d\n", sc->sc_dev.dv_xname, error); 205 return (error); 206 } 207 208 return (0); 209 } 210 211 212 /******************************************************************************/ 213 /* Control Blocks routines */ 214 /******************************************************************************/ 215 216 217 /* 218 * Create a set of ccbs and add them to the free list. Called once 219 * by adw_init(). We return the number of CCBs successfully created. 220 */ 221 int 222 adw_create_ccbs(sc, ccbstore, count) 223 ADW_SOFTC *sc; 224 ADW_CCB *ccbstore; 225 int count; 226 { 227 ADW_CCB *ccb; 228 int i, error; 229 230 for (i = 0; i < count; i++) { 231 ccb = &ccbstore[i]; 232 if ((error = adw_init_ccb(sc, ccb)) != 0) { 233 printf("%s: unable to initialize ccb, error = %d\n", 234 sc->sc_dev.dv_xname, error); 235 return (i); 236 } 237 TAILQ_INSERT_TAIL(&sc->sc_free_ccb, ccb, chain); 238 } 239 240 return (i); 241 } 242 243 244 /* 245 * A ccb is put onto the free list. 246 */ 247 void 248 adw_free_ccb(sc, ccb) 249 ADW_SOFTC *sc; 250 ADW_CCB *ccb; 251 { 252 int s; 253 254 s = splbio(); 255 256 adw_reset_ccb(ccb); 257 TAILQ_INSERT_HEAD(&sc->sc_free_ccb, ccb, chain); 258 259 /* 260 * If there were none, wake anybody waiting for one to come free, 261 * starting with queued entries. 262 */ 263 if (TAILQ_NEXT(ccb, chain) == NULL) 264 wakeup(&sc->sc_free_ccb); 265 266 splx(s); 267 } 268 269 270 void 271 adw_reset_ccb(ccb) 272 ADW_CCB *ccb; 273 { 274 275 ccb->flags = 0; 276 } 277 278 279 int 280 adw_init_ccb(sc, ccb) 281 ADW_SOFTC *sc; 282 ADW_CCB *ccb; 283 { 284 int hashnum, error; 285 286 /* 287 * Create the DMA map for this CCB. 288 */ 289 error = bus_dmamap_create(sc->sc_dmat, 290 (ADW_MAX_SG_LIST - 1) * PAGE_SIZE, 291 ADW_MAX_SG_LIST, (ADW_MAX_SG_LIST - 1) * PAGE_SIZE, 292 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &ccb->dmamap_xfer); 293 if (error) { 294 printf("%s: unable to create CCB DMA map, error = %d\n", 295 sc->sc_dev.dv_xname, error); 296 return (error); 297 } 298 299 /* 300 * put in the phystokv hash table 301 * Never gets taken out. 302 */ 303 ccb->hashkey = sc->sc_dmamap_control->dm_segs[0].ds_addr + 304 ADW_CCB_OFF(ccb); 305 hashnum = CCB_HASH(ccb->hashkey); 306 ccb->nexthash = sc->sc_ccbhash[hashnum]; 307 sc->sc_ccbhash[hashnum] = ccb; 308 adw_reset_ccb(ccb); 309 return (0); 310 } 311 312 313 /* 314 * Get a free ccb 315 * 316 * If there are none, see if we can allocate a new one 317 */ 318 ADW_CCB * 319 adw_get_ccb(sc, flags) 320 ADW_SOFTC *sc; 321 int flags; 322 { 323 ADW_CCB *ccb = 0; 324 int s; 325 326 s = splbio(); 327 328 /* 329 * If we can and have to, sleep waiting for one to come free 330 * but only if we can't allocate a new one. 331 */ 332 for (;;) { 333 ccb = TAILQ_FIRST(&sc->sc_free_ccb); 334 if (ccb) { 335 TAILQ_REMOVE(&sc->sc_free_ccb, ccb, chain); 336 break; 337 } 338 if ((flags & SCSI_NOSLEEP) != 0) 339 goto out; 340 341 tsleep(&sc->sc_free_ccb, PRIBIO, "adwccb", 0); 342 } 343 344 ccb->flags |= CCB_ALLOC; 345 346 out: 347 splx(s); 348 return (ccb); 349 } 350 351 352 /* 353 * Given a physical address, find the ccb that it corresponds to. 354 */ 355 ADW_CCB * 356 adw_ccb_phys_kv(sc, ccb_phys) 357 ADW_SOFTC *sc; 358 u_int32_t ccb_phys; 359 { 360 int hashnum = CCB_HASH(ccb_phys); 361 ADW_CCB *ccb = sc->sc_ccbhash[hashnum]; 362 363 while (ccb) { 364 if (ccb->hashkey == ccb_phys) 365 break; 366 ccb = ccb->nexthash; 367 } 368 return (ccb); 369 } 370 371 372 /* 373 * Queue a CCB to be sent to the controller, and send it if possible. 374 */ 375 int 376 adw_queue_ccb(sc, ccb, retry) 377 ADW_SOFTC *sc; 378 ADW_CCB *ccb; 379 int retry; 380 { 381 int errcode = ADW_SUCCESS; 382 383 if(!retry) { 384 TAILQ_INSERT_TAIL(&sc->sc_waiting_ccb, ccb, chain); 385 } 386 387 while ((ccb = TAILQ_FIRST(&sc->sc_waiting_ccb)) != NULL) { 388 389 errcode = AdwExeScsiQueue(sc, &ccb->scsiq); 390 switch(errcode) { 391 case ADW_SUCCESS: 392 break; 393 394 case ADW_BUSY: 395 printf("ADW_BUSY\n"); 396 return(ADW_BUSY); 397 398 case ADW_ERROR: 399 printf("ADW_ERROR\n"); 400 TAILQ_REMOVE(&sc->sc_waiting_ccb, ccb, chain); 401 return(ADW_ERROR); 402 } 403 404 TAILQ_REMOVE(&sc->sc_waiting_ccb, ccb, chain); 405 TAILQ_INSERT_TAIL(&sc->sc_pending_ccb, ccb, chain); 406 407 /* ALWAYS initialize stimeout, lest it contain garbage! */ 408 timeout_set(&ccb->xs->stimeout, adw_timeout, ccb); 409 if ((ccb->xs->flags & SCSI_POLL) == 0) 410 timeout_add_msec(&ccb->xs->stimeout, ccb->timeout); 411 } 412 413 return(errcode); 414 } 415 416 417 /******************************************************************************/ 418 /* SCSI layer interfacing routines */ 419 /******************************************************************************/ 420 421 422 int 423 adw_init(sc) 424 ADW_SOFTC *sc; 425 { 426 u_int16_t warn_code; 427 428 429 sc->cfg.lib_version = (ADW_LIB_VERSION_MAJOR << 8) | 430 ADW_LIB_VERSION_MINOR; 431 sc->cfg.chip_version = 432 ADW_GET_CHIP_VERSION(sc->sc_iot, sc->sc_ioh, sc->bus_type); 433 434 /* 435 * Reset the chip to start and allow register writes. 436 */ 437 if (ADW_FIND_SIGNATURE(sc->sc_iot, sc->sc_ioh) == 0) { 438 panic("adw_init: adw_find_signature failed"); 439 } else { 440 AdwResetChip(sc->sc_iot, sc->sc_ioh); 441 442 warn_code = AdwInitFromEEPROM(sc); 443 444 if (warn_code & ADW_WARN_EEPROM_CHKSUM) 445 printf("%s: Bad checksum found. " 446 "Setting default values\n", 447 sc->sc_dev.dv_xname); 448 if (warn_code & ADW_WARN_EEPROM_TERMINATION) 449 printf("%s: Bad bus termination setting." 450 "Using automatic termination.\n", 451 sc->sc_dev.dv_xname); 452 } 453 454 sc->isr_callback = (ADW_CALLBACK) adw_isr_callback; 455 sc->async_callback = (ADW_CALLBACK) adw_async_callback; 456 457 return 0; 458 } 459 460 461 void 462 adw_attach(sc) 463 ADW_SOFTC *sc; 464 { 465 struct scsibus_attach_args saa; 466 int i, error; 467 468 469 TAILQ_INIT(&sc->sc_free_ccb); 470 TAILQ_INIT(&sc->sc_waiting_ccb); 471 TAILQ_INIT(&sc->sc_pending_ccb); 472 473 474 /* 475 * Allocate the Control Blocks. 476 */ 477 error = adw_alloc_controls(sc); 478 if (error) 479 return; /* (error) */ ; 480 481 bzero(sc->sc_control, sizeof(struct adw_control)); 482 483 /* 484 * Create and initialize the Control Blocks. 485 */ 486 i = adw_create_ccbs(sc, sc->sc_control->ccbs, ADW_MAX_CCB); 487 if (i == 0) { 488 printf("%s: unable to create Control Blocks\n", 489 sc->sc_dev.dv_xname); 490 return; /* (ENOMEM) */ ; 491 } else if (i != ADW_MAX_CCB) { 492 printf("%s: WARNING: only %d of %d Control Blocks" 493 " created\n", 494 sc->sc_dev.dv_xname, i, ADW_MAX_CCB); 495 } 496 497 /* 498 * Create and initialize the Carriers. 499 */ 500 error = adw_alloc_carriers(sc); 501 if (error) 502 return; /* (error) */ ; 503 504 /* 505 * Zero's the freeze_device status 506 */ 507 bzero(sc->sc_freeze_dev, sizeof(sc->sc_freeze_dev)); 508 509 /* 510 * Initialize the adapter 511 */ 512 switch (AdwInitDriver(sc)) { 513 case ADW_IERR_BIST_PRE_TEST: 514 panic("%s: BIST pre-test error", 515 sc->sc_dev.dv_xname); 516 break; 517 518 case ADW_IERR_BIST_RAM_TEST: 519 panic("%s: BIST RAM test error", 520 sc->sc_dev.dv_xname); 521 break; 522 523 case ADW_IERR_MCODE_CHKSUM: 524 panic("%s: Microcode checksum error", 525 sc->sc_dev.dv_xname); 526 break; 527 528 case ADW_IERR_ILLEGAL_CONNECTION: 529 panic("%s: All three connectors are in use", 530 sc->sc_dev.dv_xname); 531 break; 532 533 case ADW_IERR_REVERSED_CABLE: 534 panic("%s: Cable is reversed", 535 sc->sc_dev.dv_xname); 536 break; 537 538 case ADW_IERR_HVD_DEVICE: 539 panic("%s: HVD attached to LVD connector", 540 sc->sc_dev.dv_xname); 541 break; 542 543 case ADW_IERR_SINGLE_END_DEVICE: 544 panic("%s: single-ended device is attached to" 545 " one of the connectors", 546 sc->sc_dev.dv_xname); 547 break; 548 549 case ADW_IERR_NO_CARRIER: 550 panic("%s: unable to create Carriers", 551 sc->sc_dev.dv_xname); 552 break; 553 554 case ADW_WARN_BUSRESET_ERROR: 555 printf("%s: WARNING: Bus Reset Error\n", 556 sc->sc_dev.dv_xname); 557 break; 558 } 559 560 /* 561 * Fill in the adapter. 562 */ 563 sc->sc_adapter.scsi_cmd = adw_scsi_cmd; 564 sc->sc_adapter.scsi_minphys = adw_minphys; 565 566 /* 567 * fill in the prototype scsi_link. 568 */ 569 sc->sc_link.adapter_softc = sc; 570 sc->sc_link.adapter_target = sc->chip_scsi_id; 571 sc->sc_link.adapter = &sc->sc_adapter; 572 sc->sc_link.device = &adw_dev; 573 sc->sc_link.openings = 4; 574 sc->sc_link.adapter_buswidth = ADW_MAX_TID+1; 575 576 bzero(&saa, sizeof(saa)); 577 saa.saa_sc_link = &sc->sc_link; 578 579 config_found(&sc->sc_dev, &saa, scsiprint); 580 } 581 582 583 void 584 adw_minphys(struct buf *bp, struct scsi_link *sl) 585 { 586 587 if (bp->b_bcount > ((ADW_MAX_SG_LIST - 1) * PAGE_SIZE)) 588 bp->b_bcount = ((ADW_MAX_SG_LIST - 1) * PAGE_SIZE); 589 minphys(bp); 590 } 591 592 593 /* 594 * start a scsi operation given the command and the data address. 595 * Also needs the unit, target and lu. 596 */ 597 int 598 adw_scsi_cmd(xs) 599 struct scsi_xfer *xs; 600 { 601 struct scsi_link *sc_link = xs->sc_link; 602 ADW_SOFTC *sc = sc_link->adapter_softc; 603 ADW_CCB *ccb; 604 int s, nowait = 0, retry = 0; 605 int flags; 606 607 s = splbio(); /* protect the queue */ 608 609 /* 610 * get a ccb to use. If the transfer 611 * is from a buf (possibly from interrupt time) 612 * then we can't allow it to sleep 613 */ 614 615 flags = xs->flags; 616 if (nowait) 617 flags |= SCSI_NOSLEEP; 618 if ((ccb = adw_get_ccb(sc, flags)) == NULL) { 619 splx(s); 620 return (NO_CCB); 621 } 622 splx(s); /* done playing with the queue */ 623 624 ccb->xs = xs; 625 ccb->timeout = xs->timeout; 626 627 if (adw_build_req(xs, ccb, flags)) { 628 retryagain: 629 s = splbio(); 630 retry = adw_queue_ccb(sc, ccb, retry); 631 splx(s); 632 633 switch(retry) { 634 case ADW_BUSY: 635 goto retryagain; 636 637 case ADW_ERROR: 638 xs->error = XS_DRIVER_STUFFUP; 639 return (COMPLETE); 640 } 641 642 /* 643 * Usually return SUCCESSFULLY QUEUED 644 */ 645 if ((xs->flags & SCSI_POLL) == 0) 646 return (SUCCESSFULLY_QUEUED); 647 648 /* 649 * If we can't use interrupts, poll on completion 650 */ 651 if (adw_poll(sc, xs, ccb->timeout)) { 652 adw_timeout(ccb); 653 if (adw_poll(sc, xs, ccb->timeout)) 654 adw_timeout(ccb); 655 } 656 } 657 return (COMPLETE); 658 } 659 660 661 /* 662 * Build a request structure for the Wide Boards. 663 */ 664 int 665 adw_build_req(xs, ccb, flags) 666 struct scsi_xfer *xs; 667 ADW_CCB *ccb; 668 int flags; 669 { 670 struct scsi_link *sc_link = xs->sc_link; 671 ADW_SOFTC *sc = sc_link->adapter_softc; 672 bus_dma_tag_t dmat = sc->sc_dmat; 673 ADW_SCSI_REQ_Q *scsiqp; 674 int error; 675 676 scsiqp = &ccb->scsiq; 677 bzero(scsiqp, sizeof(ADW_SCSI_REQ_Q)); 678 679 /* 680 * Set the ADW_SCSI_REQ_Q 'ccb_ptr' to point to the 681 * physical CCB structure. 682 */ 683 scsiqp->ccb_ptr = ccb->hashkey; 684 685 /* 686 * Build the ADW_SCSI_REQ_Q request. 687 */ 688 689 /* 690 * Set CDB length and copy it to the request structure. 691 * For wide boards a CDB length maximum of 16 bytes 692 * is supported. 693 */ 694 bcopy(xs->cmd, &scsiqp->cdb, ((scsiqp->cdb_len = xs->cmdlen) <= 12)? 695 xs->cmdlen : 12 ); 696 if(xs->cmdlen > 12) 697 bcopy(&(xs->cmd[12]), &scsiqp->cdb16, xs->cmdlen - 12); 698 699 scsiqp->target_id = sc_link->target; 700 scsiqp->target_lun = sc_link->lun; 701 702 scsiqp->vsense_addr = &ccb->scsi_sense; 703 scsiqp->sense_addr = sc->sc_dmamap_control->dm_segs[0].ds_addr + 704 ADW_CCB_OFF(ccb) + offsetof(struct adw_ccb, scsi_sense); 705 scsiqp->sense_len = sizeof(struct scsi_sense_data); 706 707 /* 708 * Build ADW_SCSI_REQ_Q for a scatter-gather buffer command. 709 */ 710 if (xs->datalen) { 711 /* 712 * Map the DMA transfer. 713 */ 714 error = bus_dmamap_load(dmat, 715 ccb->dmamap_xfer, xs->data, xs->datalen, NULL, 716 (flags & SCSI_NOSLEEP) ? 717 BUS_DMA_NOWAIT : BUS_DMA_WAITOK); 718 719 if (error) { 720 if (error == EFBIG) { 721 printf("%s: adw_scsi_cmd, more than %d dma" 722 " segments\n", 723 sc->sc_dev.dv_xname, ADW_MAX_SG_LIST); 724 } else { 725 printf("%s: adw_scsi_cmd, error %d loading" 726 " dma map\n", 727 sc->sc_dev.dv_xname, error); 728 } 729 730 xs->error = XS_DRIVER_STUFFUP; 731 adw_free_ccb(sc, ccb); 732 return (0); 733 } 734 bus_dmamap_sync(dmat, ccb->dmamap_xfer, 735 0, ccb->dmamap_xfer->dm_mapsize, 736 (xs->flags & SCSI_DATA_IN) ? 737 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 738 739 /* 740 * Build scatter-gather list. 741 */ 742 scsiqp->data_cnt = xs->datalen; 743 scsiqp->vdata_addr = xs->data; 744 scsiqp->data_addr = ccb->dmamap_xfer->dm_segs[0].ds_addr; 745 bzero(ccb->sg_block, sizeof(ADW_SG_BLOCK) * ADW_NUM_SG_BLOCK); 746 adw_build_sglist(ccb, scsiqp, ccb->sg_block); 747 } else { 748 /* 749 * No data xfer, use non S/G values. 750 */ 751 scsiqp->data_cnt = 0; 752 scsiqp->vdata_addr = 0; 753 scsiqp->data_addr = 0; 754 } 755 756 return (1); 757 } 758 759 760 /* 761 * Build scatter-gather list for Wide Boards. 762 */ 763 void 764 adw_build_sglist(ccb, scsiqp, sg_block) 765 ADW_CCB *ccb; 766 ADW_SCSI_REQ_Q *scsiqp; 767 ADW_SG_BLOCK *sg_block; 768 { 769 u_long sg_block_next_addr; /* block and its next */ 770 u_int32_t sg_block_physical_addr; 771 int i; /* how many SG entries */ 772 bus_dma_segment_t *sg_list = &ccb->dmamap_xfer->dm_segs[0]; 773 int sg_elem_cnt = ccb->dmamap_xfer->dm_nsegs; 774 775 776 sg_block_next_addr = (u_long) sg_block; /* allow math operation */ 777 sg_block_physical_addr = ccb->hashkey + 778 offsetof(struct adw_ccb, sg_block[0]); 779 scsiqp->sg_real_addr = sg_block_physical_addr; 780 781 /* 782 * If there are more than NO_OF_SG_PER_BLOCK dma segments (hw sg-list) 783 * then split the request into multiple sg-list blocks. 784 */ 785 786 do { 787 for (i = 0; i < NO_OF_SG_PER_BLOCK; i++) { 788 sg_block->sg_list[i].sg_addr = sg_list->ds_addr; 789 sg_block->sg_list[i].sg_count = sg_list->ds_len; 790 791 if (--sg_elem_cnt == 0) { 792 /* last entry, get out */ 793 sg_block->sg_cnt = i + 1; 794 sg_block->sg_ptr = NULL; /* next link = NULL */ 795 return; 796 } 797 sg_list++; 798 } 799 sg_block_next_addr += sizeof(ADW_SG_BLOCK); 800 sg_block_physical_addr += sizeof(ADW_SG_BLOCK); 801 802 sg_block->sg_cnt = NO_OF_SG_PER_BLOCK; 803 sg_block->sg_ptr = sg_block_physical_addr; 804 sg_block = (ADW_SG_BLOCK *) sg_block_next_addr; /* virt. addr */ 805 } while (1); 806 } 807 808 809 /******************************************************************************/ 810 /* Interrupts and TimeOut routines */ 811 /******************************************************************************/ 812 813 814 int 815 adw_intr(arg) 816 void *arg; 817 { 818 ADW_SOFTC *sc = arg; 819 820 821 if(AdwISR(sc) != ADW_FALSE) { 822 return (1); 823 } 824 825 return (0); 826 } 827 828 829 /* 830 * Poll a particular unit, looking for a particular xs 831 */ 832 int 833 adw_poll(sc, xs, count) 834 ADW_SOFTC *sc; 835 struct scsi_xfer *xs; 836 int count; 837 { 838 int s; 839 840 /* timeouts are in msec, so we loop in 1000 usec cycles */ 841 while (count > 0) { 842 s = splbio(); 843 adw_intr(sc); 844 splx(s); 845 if (xs->flags & ITSDONE) { 846 if ((xs->cmd->opcode == INQUIRY) 847 && (xs->sc_link->lun == 0) 848 && (xs->error == XS_NOERROR)) 849 adw_print_info(sc, xs->sc_link->target); 850 return (0); 851 } 852 delay(1000); /* only happens in boot so ok */ 853 count--; 854 } 855 return (1); 856 } 857 858 859 void 860 adw_timeout(arg) 861 void *arg; 862 { 863 ADW_CCB *ccb = arg; 864 struct scsi_xfer *xs = ccb->xs; 865 struct scsi_link *sc_link = xs->sc_link; 866 ADW_SOFTC *sc = sc_link->adapter_softc; 867 int s; 868 869 sc_print_addr(sc_link); 870 printf("timed out"); 871 872 s = splbio(); 873 874 if (ccb->flags & CCB_ABORTED) { 875 /* 876 * Abort Timed Out 877 * 878 * No more opportunities. Lets try resetting the bus and 879 * reinitialize the host adapter. 880 */ 881 timeout_del(&xs->stimeout); 882 printf(" AGAIN. Resetting SCSI Bus\n"); 883 adw_reset_bus(sc); 884 splx(s); 885 return; 886 } else if (ccb->flags & CCB_ABORTING) { 887 /* 888 * Abort the operation that has timed out. 889 * 890 * Second opportunity. 891 */ 892 printf("\n"); 893 xs->error = XS_TIMEOUT; 894 ccb->flags |= CCB_ABORTED; 895 #if 0 896 /* 897 * - XXX - 3.3a microcode is BROKEN!!! 898 * 899 * We cannot abort a CCB, so we can only hope the command 900 * get completed before the next timeout, otherwise a 901 * Bus Reset will arrive inexorably. 902 */ 903 /* 904 * ADW_ABORT_CCB() makes the board to generate an interrupt 905 * 906 * - XXX - The above assertion MUST be verified (and this 907 * code changed as well [callout_*()]), when the 908 * ADW_ABORT_CCB will be working again 909 */ 910 ADW_ABORT_CCB(sc, ccb); 911 #endif 912 /* 913 * waiting for multishot callout_reset() let's restart it 914 * by hand so the next time a timeout event will occur 915 * we will reset the bus. 916 */ 917 timeout_add_msec(&xs->stimeout, ccb->timeout); 918 } else { 919 /* 920 * Abort the operation that has timed out. 921 * 922 * First opportunity. 923 */ 924 printf("\n"); 925 xs->error = XS_TIMEOUT; 926 ccb->flags |= CCB_ABORTING; 927 #if 0 928 /* 929 * - XXX - 3.3a microcode is BROKEN!!! 930 * 931 * We cannot abort a CCB, so we can only hope the command 932 * get completed before the next 2 timeout, otherwise a 933 * Bus Reset will arrive inexorably. 934 */ 935 /* 936 * ADW_ABORT_CCB() makes the board to generate an interrupt 937 * 938 * - XXX - The above assertion MUST be verified (and this 939 * code changed as well [callout_*()]), when the 940 * ADW_ABORT_CCB will be working again 941 */ 942 ADW_ABORT_CCB(sc, ccb); 943 #endif 944 /* 945 * waiting for multishot callout_reset() let's restart it 946 * by hand so to give a second opportunity to the command 947 * which timed-out. 948 */ 949 timeout_add_msec(&xs->stimeout, ccb->timeout); 950 } 951 952 splx(s); 953 } 954 955 956 void 957 adw_reset_bus(sc) 958 ADW_SOFTC *sc; 959 { 960 ADW_CCB *ccb; 961 int s; 962 963 s = splbio(); 964 AdwResetSCSIBus(sc); /* XXX - should check return value? */ 965 while((ccb = TAILQ_LAST(&sc->sc_pending_ccb, 966 adw_pending_ccb)) != NULL) { 967 timeout_del(&ccb->xs->stimeout); 968 TAILQ_REMOVE(&sc->sc_pending_ccb, ccb, chain); 969 TAILQ_INSERT_HEAD(&sc->sc_waiting_ccb, ccb, chain); 970 } 971 972 bzero(sc->sc_freeze_dev, sizeof(sc->sc_freeze_dev)); 973 adw_queue_ccb(sc, TAILQ_FIRST(&sc->sc_waiting_ccb), 1); 974 975 splx(s); 976 } 977 978 979 /******************************************************************************/ 980 /* Host Adapter and Peripherals Information Routines */ 981 /******************************************************************************/ 982 983 984 void 985 adw_print_info(sc, tid) 986 ADW_SOFTC *sc; 987 int tid; 988 { 989 bus_space_handle_t ioh = sc->sc_ioh; 990 bus_space_tag_t iot = sc->sc_iot; 991 u_int16_t hshk_cfg, able_mask, period = 0; 992 993 /* hshk/HSHK means 'handskake' */ 994 995 ADW_READ_WORD_LRAM(iot, ioh, 996 ADW_MC_DEVICE_HSHK_CFG_TABLE + (2 * tid), hshk_cfg); 997 998 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, able_mask); 999 if ((able_mask & ADW_TID_TO_TIDMASK(tid)) == 0) 1000 hshk_cfg &= ~HSHK_CFG_WIDE_XFR; 1001 1002 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, able_mask); 1003 if ((able_mask & ADW_TID_TO_TIDMASK(tid)) == 0) 1004 hshk_cfg &= ~HSHK_CFG_OFFSET; 1005 1006 printf("%s: target %d using %d bit ", sc->sc_dev.dv_xname, tid, 1007 (hshk_cfg & HSHK_CFG_WIDE_XFR) ? 16 : 8); 1008 1009 if ((hshk_cfg & HSHK_CFG_OFFSET) == 0) 1010 printf("async "); 1011 else { 1012 period = (hshk_cfg & 0x1f00) >> 8; 1013 switch (period) { 1014 case 0x11: 1015 printf("80.0 "); 1016 break; 1017 case 0x10: 1018 printf("40.0 "); 1019 break; 1020 default: 1021 period = (period * 25) + 50; 1022 printf("%d.%d ", 1000/period, ADW_TENTHS(1000, period)); 1023 break; 1024 } 1025 printf("MHz %d REQ/ACK offset ", hshk_cfg & HSHK_CFG_OFFSET); 1026 } 1027 1028 printf("xfers\n"); 1029 } 1030 1031 1032 /******************************************************************************/ 1033 /* WIDE boards Interrupt callbacks */ 1034 /******************************************************************************/ 1035 1036 1037 /* 1038 * adw_isr_callback() - Second Level Interrupt Handler called by AdwISR() 1039 * 1040 * Interrupt callback function for the Wide SCSI Adw Library. 1041 * 1042 * Notice: 1043 * Interrupts are disabled by the caller (AdwISR() function), and will be 1044 * enabled at the end of the caller. 1045 */ 1046 void 1047 adw_isr_callback(sc, scsiq) 1048 ADW_SOFTC *sc; 1049 ADW_SCSI_REQ_Q *scsiq; 1050 { 1051 bus_dma_tag_t dmat; 1052 ADW_CCB *ccb; 1053 struct scsi_xfer *xs; 1054 struct scsi_sense_data *s1, *s2; 1055 1056 1057 ccb = adw_ccb_phys_kv(sc, scsiq->ccb_ptr); 1058 TAILQ_REMOVE(&sc->sc_pending_ccb, ccb, chain); 1059 1060 if ((ccb->flags & CCB_ALLOC) == 0) { 1061 printf("%s: unallocated ccb found on pending list!\n", 1062 sc->sc_dev.dv_xname); 1063 Debugger(); 1064 adw_free_ccb(sc, ccb); 1065 return; 1066 } 1067 1068 xs = ccb->xs; 1069 timeout_del(&xs->stimeout); 1070 1071 /* 1072 * If we were a data transfer, unload the map that described 1073 * the data buffer. 1074 */ 1075 dmat = sc->sc_dmat; 1076 if (xs->datalen) { 1077 bus_dmamap_sync(dmat, ccb->dmamap_xfer, 1078 0, ccb->dmamap_xfer->dm_mapsize, 1079 ((xs->flags & SCSI_DATA_IN) ? 1080 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE)); 1081 bus_dmamap_unload(dmat, ccb->dmamap_xfer); 1082 } 1083 1084 /* 1085 * 'done_status' contains the command's ending status. 1086 * 'host_status' contains the host adapter status. 1087 * 'scsi_status' contains the scsi peripheral status. 1088 */ 1089 1090 sc->sc_freeze_dev[scsiq->target_id] = 0; 1091 xs->status = scsiq->scsi_status; 1092 1093 switch (scsiq->done_status) { 1094 case QD_NO_ERROR: /* (scsi_status == 0) && (host_status == 0) */ 1095 NO_ERROR: 1096 xs->resid = scsiq->data_cnt; 1097 xs->error = XS_NOERROR; 1098 break; 1099 1100 case QD_WITH_ERROR: 1101 switch (scsiq->host_status) { 1102 case QHSTA_NO_ERROR: 1103 switch (scsiq->scsi_status) { 1104 case SCSI_COND_MET: 1105 case SCSI_INTERM: 1106 case SCSI_INTERM_COND_MET: 1107 /* 1108 * These non-zero status values are 1109 * not really error conditions. 1110 * 1111 * XXX - would it be too paranoid to 1112 * add SCSI_OK here in 1113 * case the docs are wrong re 1114 * QD_NO_ERROR? 1115 */ 1116 goto NO_ERROR; 1117 1118 case SCSI_CHECK: 1119 case SCSI_TERMINATED: 1120 case SCSI_ACA_ACTIVE: 1121 s1 = &ccb->scsi_sense; 1122 s2 = &xs->sense; 1123 *s2 = *s1; 1124 xs->error = XS_SENSE; 1125 break; 1126 1127 case SCSI_BUSY: 1128 case SCSI_QUEUE_FULL: 1129 case SCSI_RESV_CONFLICT: 1130 sc->sc_freeze_dev[scsiq->target_id] = 1; 1131 xs->error = XS_BUSY; 1132 break; 1133 1134 default: /* scsiq->scsi_status value */ 1135 printf("%s: bad scsi_status: 0x%02x.\n" 1136 ,sc->sc_dev.dv_xname 1137 ,scsiq->scsi_status); 1138 xs->error = XS_DRIVER_STUFFUP; 1139 break; 1140 } 1141 break; 1142 1143 case QHSTA_M_SEL_TIMEOUT: 1144 xs->error = XS_SELTIMEOUT; 1145 break; 1146 1147 case QHSTA_M_DIRECTION_ERR: 1148 case QHSTA_M_SXFR_OFF_UFLW: 1149 case QHSTA_M_SXFR_OFF_OFLW: 1150 case QHSTA_M_SXFR_XFR_OFLW: 1151 case QHSTA_M_QUEUE_ABORTED: 1152 case QHSTA_M_INVALID_DEVICE: 1153 case QHSTA_M_SGBACKUP_ERROR: 1154 case QHSTA_M_SXFR_DESELECTED: 1155 case QHSTA_M_SXFR_XFR_PH_ERR: 1156 case QHSTA_M_BUS_DEVICE_RESET: 1157 case QHSTA_M_NO_AUTO_REQ_SENSE: 1158 case QHSTA_M_BAD_CMPL_STATUS_IN: 1159 case QHSTA_M_SXFR_UNKNOWN_ERROR: 1160 case QHSTA_M_AUTO_REQ_SENSE_FAIL: 1161 case QHSTA_M_UNEXPECTED_BUS_FREE: 1162 printf("%s: host adapter error 0x%02x." 1163 " See adw(4).\n" 1164 ,sc->sc_dev.dv_xname, scsiq->host_status); 1165 xs->error = XS_DRIVER_STUFFUP; 1166 break; 1167 1168 case QHSTA_M_RDMA_PERR: 1169 case QHSTA_M_SXFR_WD_TMO: 1170 case QHSTA_M_WTM_TIMEOUT: 1171 case QHSTA_M_FROZEN_TIDQ: 1172 case QHSTA_M_SXFR_SDMA_ERR: 1173 case QHSTA_M_SXFR_SXFR_PERR: 1174 case QHSTA_M_SCSI_BUS_RESET: 1175 case QHSTA_M_DIRECTION_ERR_HUNG: 1176 case QHSTA_M_SCSI_BUS_RESET_UNSOL: 1177 /* 1178 * XXX - are all these cases really asking 1179 * for a card reset? _BUS_RESET and 1180 * _BUS_RESET_UNSOL added just to make 1181 * sure the pending queue is cleared out 1182 * in case card has lost track of them. 1183 */ 1184 printf("%s: host adapter error 0x%02x," 1185 " resetting bus. See adw(4).\n" 1186 ,sc->sc_dev.dv_xname, scsiq->host_status); 1187 adw_reset_bus(sc); 1188 xs->error = XS_RESET; 1189 break; 1190 1191 default: /* scsiq->host_status value */ 1192 /* 1193 * XXX - is a panic really appropriate here? If 1194 * not, would it be better to make the 1195 * XS_DRIVER_STUFFUP case above the 1196 * default behaviour? Or XS_RESET? 1197 */ 1198 panic("%s: bad host_status: 0x%02x" 1199 ,sc->sc_dev.dv_xname, scsiq->host_status); 1200 break; 1201 } 1202 break; 1203 1204 case QD_ABORTED_BY_HOST: 1205 xs->error = XS_DRIVER_STUFFUP; 1206 break; 1207 1208 default: /* scsiq->done_status value */ 1209 /* 1210 * XXX - would QD_NO_STATUS really mean the I/O is not 1211 * done? and would that mean it should somehow be 1212 * put back as a pending I/O? 1213 */ 1214 printf("%s: bad done_status: 0x%02x" 1215 " (host_status: 0x%02x, scsi_status: 0x%02x)\n" 1216 ,sc->sc_dev.dv_xname 1217 ,scsiq->done_status 1218 ,scsiq->host_status 1219 ,scsiq->scsi_status); 1220 xs->error = XS_DRIVER_STUFFUP; 1221 break; 1222 } 1223 1224 adw_free_ccb(sc, ccb); 1225 1226 xs->flags |= ITSDONE; 1227 scsi_done(xs); 1228 } 1229 1230 1231 /* 1232 * adw_async_callback() - Adw Library asynchronous event callback function. 1233 */ 1234 void 1235 adw_async_callback(sc, code) 1236 ADW_SOFTC *sc; 1237 u_int8_t code; 1238 { 1239 switch (code) { 1240 case ADW_ASYNC_SCSI_BUS_RESET_DET: 1241 /* The firmware detected a SCSI Bus reset. */ 1242 printf("%s: SCSI Bus reset detected\n", sc->sc_dev.dv_xname); 1243 break; 1244 1245 case ADW_ASYNC_RDMA_FAILURE: 1246 /* 1247 * Handle RDMA failure by resetting the SCSI Bus and 1248 * possibly the chip if it is unresponsive. 1249 */ 1250 printf("%s: RDMA failure. Resetting the SCSI Bus and" 1251 " the adapter\n", sc->sc_dev.dv_xname); 1252 adw_reset_bus(sc); 1253 break; 1254 1255 case ADW_HOST_SCSI_BUS_RESET: 1256 /* Host generated SCSI bus reset occurred. */ 1257 printf("%s: Host generated SCSI bus reset occurred\n", 1258 sc->sc_dev.dv_xname); 1259 break; 1260 1261 1262 case ADW_ASYNC_CARRIER_READY_FAILURE: 1263 /* 1264 * Carrier Ready failure. 1265 * 1266 * A warning only - RISC too busy to realize it's been 1267 * tickled. Occurs in normal operation under heavy 1268 * load, so a message is printed only when ADW_DEBUG'ing 1269 */ 1270 #ifdef ADW_DEBUG 1271 printf("%s: Carrier Ready failure!\n", sc->sc_dev.dv_xname); 1272 #endif 1273 break; 1274 1275 default: 1276 printf("%s: Unknown Async callback code (ignored): 0x%02x\n", 1277 sc->sc_dev.dv_xname, code); 1278 break; 1279 } 1280 } 1281