1 /* $OpenBSD: adw.c,v 1.50 2012/01/11 16:22:32 dhill Exp $ */ 2 /* $NetBSD: adw.c,v 1.23 2000/05/27 18:24:50 dante Exp $ */ 3 4 /* 5 * Generic driver for the Advanced Systems Inc. SCSI controllers 6 * 7 * Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc. 8 * All rights reserved. 9 * 10 * Author: Baldassare Dante Profeta <dante@mclink.it> 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/types.h> 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/errno.h> 39 #include <sys/ioctl.h> 40 #include <sys/device.h> 41 #include <sys/malloc.h> 42 #include <sys/buf.h> 43 #include <sys/proc.h> 44 #include <sys/timeout.h> 45 46 #include <machine/bus.h> 47 #include <machine/intr.h> 48 49 #include <scsi/scsi_all.h> 50 #include <scsi/scsiconf.h> 51 52 #include <dev/ic/adwlib.h> 53 #include <dev/microcode/adw/adwmcode.h> 54 #include <dev/ic/adw.h> 55 56 /******************************************************************************/ 57 58 59 int adw_alloc_controls(ADW_SOFTC *); 60 int adw_alloc_carriers(ADW_SOFTC *); 61 int adw_create_ccbs(ADW_SOFTC *, ADW_CCB *, int); 62 void adw_ccb_free(void *, void *); 63 void adw_reset_ccb(ADW_CCB *); 64 int adw_init_ccb(ADW_SOFTC *, ADW_CCB *); 65 void *adw_ccb_alloc(void *); 66 int adw_queue_ccb(ADW_SOFTC *, ADW_CCB *, int); 67 68 void adw_scsi_cmd(struct scsi_xfer *); 69 int adw_build_req(struct scsi_xfer *, ADW_CCB *, int); 70 void adw_build_sglist(ADW_CCB *, ADW_SCSI_REQ_Q *, ADW_SG_BLOCK *); 71 void adw_minphys(struct buf *, struct scsi_link *); 72 void adw_isr_callback(ADW_SOFTC *, ADW_SCSI_REQ_Q *); 73 void adw_async_callback(ADW_SOFTC *, u_int8_t); 74 75 void adw_print_info(ADW_SOFTC *, int); 76 77 int adw_poll(ADW_SOFTC *, struct scsi_xfer *, int); 78 void adw_timeout(void *); 79 void adw_reset_bus(ADW_SOFTC *); 80 81 82 /******************************************************************************/ 83 84 85 struct cfdriver adw_cd = { 86 NULL, "adw", DV_DULL 87 }; 88 89 /******************************************************************************/ 90 /* DMA Mapping for Control Blocks */ 91 /******************************************************************************/ 92 93 94 int 95 adw_alloc_controls(ADW_SOFTC *sc) 96 { 97 bus_dma_segment_t seg; 98 int error, rseg; 99 100 /* 101 * Allocate the control structure. 102 */ 103 if ((error = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct adw_control), 104 NBPG, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT | BUS_DMA_ZERO)) != 0) { 105 printf("%s: unable to allocate control structures," 106 " error = %d\n", sc->sc_dev.dv_xname, error); 107 return (error); 108 } 109 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 110 sizeof(struct adw_control), (caddr_t *) & sc->sc_control, 111 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 112 printf("%s: unable to map control structures, error = %d\n", 113 sc->sc_dev.dv_xname, error); 114 return (error); 115 } 116 117 /* 118 * Create and load the DMA map used for the control blocks. 119 */ 120 if ((error = bus_dmamap_create(sc->sc_dmat, sizeof(struct adw_control), 121 1, sizeof(struct adw_control), 0, BUS_DMA_NOWAIT, 122 &sc->sc_dmamap_control)) != 0) { 123 printf("%s: unable to create control DMA map, error = %d\n", 124 sc->sc_dev.dv_xname, error); 125 return (error); 126 } 127 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap_control, 128 sc->sc_control, sizeof(struct adw_control), NULL, 129 BUS_DMA_NOWAIT)) != 0) { 130 printf("%s: unable to load control DMA map, error = %d\n", 131 sc->sc_dev.dv_xname, error); 132 return (error); 133 } 134 135 return (0); 136 } 137 138 139 int 140 adw_alloc_carriers(ADW_SOFTC *sc) 141 { 142 bus_dma_segment_t seg; 143 int error, rseg; 144 145 /* 146 * Allocate the control structure. 147 */ 148 sc->sc_control->carriers = 149 malloc(sizeof(ADW_CARRIER) * ADW_MAX_CARRIER, M_DEVBUF, 150 M_NOWAIT); 151 if (sc->sc_control->carriers == NULL) 152 return (ENOMEM); 153 154 155 if ((error = bus_dmamem_alloc(sc->sc_dmat, 156 sizeof(ADW_CARRIER) * ADW_MAX_CARRIER, 157 0x10, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 158 printf("%s: unable to allocate carrier structures," 159 " error = %d\n", sc->sc_dev.dv_xname, error); 160 return (error); 161 } 162 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 163 sizeof(ADW_CARRIER) * ADW_MAX_CARRIER, 164 (caddr_t *) &sc->sc_control->carriers, 165 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 166 printf("%s: unable to map carrier structures," 167 " error = %d\n", sc->sc_dev.dv_xname, error); 168 return (error); 169 } 170 171 /* 172 * Create and load the DMA map used for the control blocks. 173 */ 174 if ((error = bus_dmamap_create(sc->sc_dmat, 175 sizeof(ADW_CARRIER) * ADW_MAX_CARRIER, 1, 176 sizeof(ADW_CARRIER) * ADW_MAX_CARRIER, 0,BUS_DMA_NOWAIT, 177 &sc->sc_dmamap_carrier)) != 0) { 178 printf("%s: unable to create carriers DMA map," 179 " error = %d\n", sc->sc_dev.dv_xname, error); 180 return (error); 181 } 182 if ((error = bus_dmamap_load(sc->sc_dmat, 183 sc->sc_dmamap_carrier, sc->sc_control->carriers, 184 sizeof(ADW_CARRIER) * ADW_MAX_CARRIER, NULL, 185 BUS_DMA_NOWAIT)) != 0) { 186 printf("%s: unable to load carriers DMA map," 187 " error = %d\n", sc->sc_dev.dv_xname, error); 188 return (error); 189 } 190 191 return (0); 192 } 193 194 195 /******************************************************************************/ 196 /* Control Blocks routines */ 197 /******************************************************************************/ 198 199 200 /* 201 * Create a set of ccbs and add them to the free list. Called once 202 * by adw_init(). We return the number of CCBs successfully created. 203 */ 204 int 205 adw_create_ccbs(ADW_SOFTC *sc, ADW_CCB *ccbstore, int count) 206 { 207 ADW_CCB *ccb; 208 int i, error; 209 210 for (i = 0; i < count; i++) { 211 ccb = &ccbstore[i]; 212 if ((error = adw_init_ccb(sc, ccb)) != 0) { 213 printf("%s: unable to initialize ccb, error = %d\n", 214 sc->sc_dev.dv_xname, error); 215 return (i); 216 } 217 TAILQ_INSERT_TAIL(&sc->sc_free_ccb, ccb, chain); 218 } 219 220 return (i); 221 } 222 223 224 /* 225 * A ccb is put onto the free list. 226 */ 227 void 228 adw_ccb_free(void *xsc, void *xccb) 229 { 230 ADW_SOFTC *sc = xsc; 231 ADW_CCB *ccb = xccb; 232 233 adw_reset_ccb(ccb); 234 235 mtx_enter(&sc->sc_ccb_mtx); 236 TAILQ_INSERT_HEAD(&sc->sc_free_ccb, ccb, chain); 237 mtx_leave(&sc->sc_ccb_mtx); 238 } 239 240 241 void 242 adw_reset_ccb(ADW_CCB *ccb) 243 { 244 245 ccb->flags = 0; 246 } 247 248 249 int 250 adw_init_ccb(ADW_SOFTC *sc, ADW_CCB *ccb) 251 { 252 int hashnum, error; 253 254 /* 255 * Create the DMA map for this CCB. 256 */ 257 error = bus_dmamap_create(sc->sc_dmat, 258 (ADW_MAX_SG_LIST - 1) * PAGE_SIZE, 259 ADW_MAX_SG_LIST, (ADW_MAX_SG_LIST - 1) * PAGE_SIZE, 260 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &ccb->dmamap_xfer); 261 if (error) { 262 printf("%s: unable to create CCB DMA map, error = %d\n", 263 sc->sc_dev.dv_xname, error); 264 return (error); 265 } 266 267 /* 268 * put in the phystokv hash table 269 * Never gets taken out. 270 */ 271 ccb->hashkey = sc->sc_dmamap_control->dm_segs[0].ds_addr + 272 ADW_CCB_OFF(ccb); 273 hashnum = CCB_HASH(ccb->hashkey); 274 ccb->nexthash = sc->sc_ccbhash[hashnum]; 275 sc->sc_ccbhash[hashnum] = ccb; 276 adw_reset_ccb(ccb); 277 return (0); 278 } 279 280 281 /* 282 * Get a free ccb 283 * 284 * If there are none, see if we can allocate a new one 285 */ 286 void * 287 adw_ccb_alloc(void *xsc) 288 { 289 ADW_SOFTC *sc = xsc; 290 ADW_CCB *ccb; 291 292 mtx_enter(&sc->sc_ccb_mtx); 293 ccb = TAILQ_FIRST(&sc->sc_free_ccb); 294 if (ccb) { 295 TAILQ_REMOVE(&sc->sc_free_ccb, ccb, chain); 296 ccb->flags |= CCB_ALLOC; 297 } 298 mtx_leave(&sc->sc_ccb_mtx); 299 300 return (ccb); 301 } 302 303 304 /* 305 * Given a physical address, find the ccb that it corresponds to. 306 */ 307 ADW_CCB * 308 adw_ccb_phys_kv(ADW_SOFTC *sc, u_int32_t ccb_phys) 309 { 310 int hashnum = CCB_HASH(ccb_phys); 311 ADW_CCB *ccb = sc->sc_ccbhash[hashnum]; 312 313 while (ccb) { 314 if (ccb->hashkey == ccb_phys) 315 break; 316 ccb = ccb->nexthash; 317 } 318 return (ccb); 319 } 320 321 322 /* 323 * Queue a CCB to be sent to the controller, and send it if possible. 324 */ 325 int 326 adw_queue_ccb(ADW_SOFTC *sc, ADW_CCB *ccb, int retry) 327 { 328 int errcode = ADW_SUCCESS; 329 330 if(!retry) { 331 TAILQ_INSERT_TAIL(&sc->sc_waiting_ccb, ccb, chain); 332 } 333 334 while ((ccb = TAILQ_FIRST(&sc->sc_waiting_ccb)) != NULL) { 335 336 errcode = AdwExeScsiQueue(sc, &ccb->scsiq); 337 switch(errcode) { 338 case ADW_SUCCESS: 339 break; 340 341 case ADW_BUSY: 342 printf("ADW_BUSY\n"); 343 return(ADW_BUSY); 344 345 case ADW_ERROR: 346 printf("ADW_ERROR\n"); 347 TAILQ_REMOVE(&sc->sc_waiting_ccb, ccb, chain); 348 return(ADW_ERROR); 349 } 350 351 TAILQ_REMOVE(&sc->sc_waiting_ccb, ccb, chain); 352 TAILQ_INSERT_TAIL(&sc->sc_pending_ccb, ccb, chain); 353 354 /* ALWAYS initialize stimeout, lest it contain garbage! */ 355 timeout_set(&ccb->xs->stimeout, adw_timeout, ccb); 356 if ((ccb->xs->flags & SCSI_POLL) == 0) 357 timeout_add_msec(&ccb->xs->stimeout, ccb->timeout); 358 } 359 360 return(errcode); 361 } 362 363 364 /******************************************************************************/ 365 /* SCSI layer interfacing routines */ 366 /******************************************************************************/ 367 368 369 int 370 adw_init(ADW_SOFTC *sc) 371 { 372 u_int16_t warn_code; 373 374 375 sc->cfg.lib_version = (ADW_LIB_VERSION_MAJOR << 8) | 376 ADW_LIB_VERSION_MINOR; 377 sc->cfg.chip_version = 378 ADW_GET_CHIP_VERSION(sc->sc_iot, sc->sc_ioh, sc->bus_type); 379 380 /* 381 * Reset the chip to start and allow register writes. 382 */ 383 if (ADW_FIND_SIGNATURE(sc->sc_iot, sc->sc_ioh) == 0) { 384 panic("adw_init: adw_find_signature failed"); 385 } else { 386 AdwResetChip(sc->sc_iot, sc->sc_ioh); 387 388 warn_code = AdwInitFromEEPROM(sc); 389 390 if (warn_code & ADW_WARN_EEPROM_CHKSUM) 391 printf("%s: Bad checksum found. " 392 "Setting default values\n", 393 sc->sc_dev.dv_xname); 394 if (warn_code & ADW_WARN_EEPROM_TERMINATION) 395 printf("%s: Bad bus termination setting." 396 "Using automatic termination.\n", 397 sc->sc_dev.dv_xname); 398 } 399 400 sc->isr_callback = (ADW_CALLBACK) adw_isr_callback; 401 sc->async_callback = (ADW_CALLBACK) adw_async_callback; 402 403 return 0; 404 } 405 406 407 void 408 adw_attach(ADW_SOFTC *sc) 409 { 410 struct scsibus_attach_args saa; 411 int i, error; 412 413 414 TAILQ_INIT(&sc->sc_free_ccb); 415 TAILQ_INIT(&sc->sc_waiting_ccb); 416 TAILQ_INIT(&sc->sc_pending_ccb); 417 418 mtx_init(&sc->sc_ccb_mtx, IPL_BIO); 419 scsi_iopool_init(&sc->sc_iopool, sc, adw_ccb_alloc, adw_ccb_free); 420 421 /* 422 * Allocate the Control Blocks. 423 */ 424 error = adw_alloc_controls(sc); 425 if (error) 426 return; /* (error) */ ; 427 428 /* 429 * Create and initialize the Control Blocks. 430 */ 431 i = adw_create_ccbs(sc, sc->sc_control->ccbs, ADW_MAX_CCB); 432 if (i == 0) { 433 printf("%s: unable to create Control Blocks\n", 434 sc->sc_dev.dv_xname); 435 return; /* (ENOMEM) */ ; 436 } else if (i != ADW_MAX_CCB) { 437 printf("%s: WARNING: only %d of %d Control Blocks" 438 " created\n", 439 sc->sc_dev.dv_xname, i, ADW_MAX_CCB); 440 } 441 442 /* 443 * Create and initialize the Carriers. 444 */ 445 error = adw_alloc_carriers(sc); 446 if (error) 447 return; /* (error) */ ; 448 449 /* 450 * Zero's the freeze_device status 451 */ 452 bzero(sc->sc_freeze_dev, sizeof(sc->sc_freeze_dev)); 453 454 /* 455 * Initialize the adapter 456 */ 457 switch (AdwInitDriver(sc)) { 458 case ADW_IERR_BIST_PRE_TEST: 459 panic("%s: BIST pre-test error", 460 sc->sc_dev.dv_xname); 461 break; 462 463 case ADW_IERR_BIST_RAM_TEST: 464 panic("%s: BIST RAM test error", 465 sc->sc_dev.dv_xname); 466 break; 467 468 case ADW_IERR_MCODE_CHKSUM: 469 panic("%s: Microcode checksum error", 470 sc->sc_dev.dv_xname); 471 break; 472 473 case ADW_IERR_ILLEGAL_CONNECTION: 474 panic("%s: All three connectors are in use", 475 sc->sc_dev.dv_xname); 476 break; 477 478 case ADW_IERR_REVERSED_CABLE: 479 panic("%s: Cable is reversed", 480 sc->sc_dev.dv_xname); 481 break; 482 483 case ADW_IERR_HVD_DEVICE: 484 panic("%s: HVD attached to LVD connector", 485 sc->sc_dev.dv_xname); 486 break; 487 488 case ADW_IERR_SINGLE_END_DEVICE: 489 panic("%s: single-ended device is attached to" 490 " one of the connectors", 491 sc->sc_dev.dv_xname); 492 break; 493 494 case ADW_IERR_NO_CARRIER: 495 panic("%s: unable to create Carriers", 496 sc->sc_dev.dv_xname); 497 break; 498 499 case ADW_WARN_BUSRESET_ERROR: 500 printf("%s: WARNING: Bus Reset Error\n", 501 sc->sc_dev.dv_xname); 502 break; 503 } 504 505 /* 506 * Fill in the adapter. 507 */ 508 sc->sc_adapter.scsi_cmd = adw_scsi_cmd; 509 sc->sc_adapter.scsi_minphys = adw_minphys; 510 511 /* 512 * fill in the prototype scsi_link. 513 */ 514 sc->sc_link.adapter_softc = sc; 515 sc->sc_link.adapter_target = sc->chip_scsi_id; 516 sc->sc_link.adapter = &sc->sc_adapter; 517 sc->sc_link.openings = 4; 518 sc->sc_link.adapter_buswidth = ADW_MAX_TID+1; 519 sc->sc_link.pool = &sc->sc_iopool; 520 521 bzero(&saa, sizeof(saa)); 522 saa.saa_sc_link = &sc->sc_link; 523 524 config_found(&sc->sc_dev, &saa, scsiprint); 525 } 526 527 528 void 529 adw_minphys(struct buf *bp, struct scsi_link *sl) 530 { 531 532 if (bp->b_bcount > ((ADW_MAX_SG_LIST - 1) * PAGE_SIZE)) 533 bp->b_bcount = ((ADW_MAX_SG_LIST - 1) * PAGE_SIZE); 534 minphys(bp); 535 } 536 537 538 /* 539 * start a scsi operation given the command and the data address. 540 * Also needs the unit, target and lu. 541 */ 542 void 543 adw_scsi_cmd(struct scsi_xfer *xs) 544 { 545 struct scsi_link *sc_link = xs->sc_link; 546 ADW_SOFTC *sc = sc_link->adapter_softc; 547 ADW_CCB *ccb; 548 int s, nowait = 0, retry = 0; 549 int flags; 550 551 /* 552 * get a ccb to use. If the transfer 553 * is from a buf (possibly from interrupt time) 554 * then we can't allow it to sleep 555 */ 556 557 flags = xs->flags; 558 if (nowait) 559 flags |= SCSI_NOSLEEP; 560 ccb = xs->io; 561 562 ccb->xs = xs; 563 ccb->timeout = xs->timeout; 564 565 if (adw_build_req(xs, ccb, flags)) { 566 retryagain: 567 s = splbio(); 568 retry = adw_queue_ccb(sc, ccb, retry); 569 splx(s); 570 571 switch(retry) { 572 case ADW_BUSY: 573 goto retryagain; 574 575 case ADW_ERROR: 576 xs->error = XS_DRIVER_STUFFUP; 577 scsi_done(xs); 578 return; 579 } 580 581 /* 582 * Usually return SUCCESSFULLY QUEUED 583 */ 584 if ((xs->flags & SCSI_POLL) == 0) 585 return; 586 587 /* 588 * If we can't use interrupts, poll on completion 589 */ 590 if (adw_poll(sc, xs, ccb->timeout)) { 591 adw_timeout(ccb); 592 if (adw_poll(sc, xs, ccb->timeout)) 593 adw_timeout(ccb); 594 } 595 } else { 596 /* adw_build_req() has set xs->error already */ 597 scsi_done(xs); 598 } 599 } 600 601 602 /* 603 * Build a request structure for the Wide Boards. 604 */ 605 int 606 adw_build_req(struct scsi_xfer *xs, ADW_CCB *ccb, int flags) 607 { 608 struct scsi_link *sc_link = xs->sc_link; 609 ADW_SOFTC *sc = sc_link->adapter_softc; 610 bus_dma_tag_t dmat = sc->sc_dmat; 611 ADW_SCSI_REQ_Q *scsiqp; 612 int error; 613 614 scsiqp = &ccb->scsiq; 615 bzero(scsiqp, sizeof(ADW_SCSI_REQ_Q)); 616 617 /* 618 * Set the ADW_SCSI_REQ_Q 'ccb_ptr' to point to the 619 * physical CCB structure. 620 */ 621 scsiqp->ccb_ptr = ccb->hashkey; 622 623 /* 624 * Build the ADW_SCSI_REQ_Q request. 625 */ 626 627 /* 628 * Set CDB length and copy it to the request structure. 629 * For wide boards a CDB length maximum of 16 bytes 630 * is supported. 631 */ 632 scsiqp->cdb_len = xs->cmdlen; 633 bcopy((caddr_t)xs->cmd, &scsiqp->cdb, 12); 634 bcopy((caddr_t)xs->cmd + 12, &scsiqp->cdb16, 4); 635 636 scsiqp->target_id = sc_link->target; 637 scsiqp->target_lun = sc_link->lun; 638 639 scsiqp->vsense_addr = &ccb->scsi_sense; 640 scsiqp->sense_addr = sc->sc_dmamap_control->dm_segs[0].ds_addr + 641 ADW_CCB_OFF(ccb) + offsetof(struct adw_ccb, scsi_sense); 642 scsiqp->sense_len = sizeof(struct scsi_sense_data); 643 644 /* 645 * Build ADW_SCSI_REQ_Q for a scatter-gather buffer command. 646 */ 647 if (xs->datalen) { 648 /* 649 * Map the DMA transfer. 650 */ 651 error = bus_dmamap_load(dmat, 652 ccb->dmamap_xfer, xs->data, xs->datalen, NULL, 653 (flags & SCSI_NOSLEEP) ? 654 BUS_DMA_NOWAIT : BUS_DMA_WAITOK); 655 656 if (error) { 657 if (error == EFBIG) { 658 printf("%s: adw_scsi_cmd, more than %d dma" 659 " segments\n", 660 sc->sc_dev.dv_xname, ADW_MAX_SG_LIST); 661 } else { 662 printf("%s: adw_scsi_cmd, error %d loading" 663 " dma map\n", 664 sc->sc_dev.dv_xname, error); 665 } 666 667 xs->error = XS_DRIVER_STUFFUP; 668 return (0); 669 } 670 bus_dmamap_sync(dmat, ccb->dmamap_xfer, 671 0, ccb->dmamap_xfer->dm_mapsize, 672 (xs->flags & SCSI_DATA_IN) ? 673 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 674 675 /* 676 * Build scatter-gather list. 677 */ 678 scsiqp->data_cnt = xs->datalen; 679 scsiqp->vdata_addr = xs->data; 680 scsiqp->data_addr = ccb->dmamap_xfer->dm_segs[0].ds_addr; 681 bzero(ccb->sg_block, sizeof(ADW_SG_BLOCK) * ADW_NUM_SG_BLOCK); 682 adw_build_sglist(ccb, scsiqp, ccb->sg_block); 683 } else { 684 /* 685 * No data xfer, use non S/G values. 686 */ 687 scsiqp->data_cnt = 0; 688 scsiqp->vdata_addr = 0; 689 scsiqp->data_addr = 0; 690 } 691 692 return (1); 693 } 694 695 696 /* 697 * Build scatter-gather list for Wide Boards. 698 */ 699 void 700 adw_build_sglist(ADW_CCB *ccb, ADW_SCSI_REQ_Q *scsiqp, ADW_SG_BLOCK *sg_block) 701 { 702 u_long sg_block_next_addr; /* block and its next */ 703 u_int32_t sg_block_physical_addr; 704 int i; /* how many SG entries */ 705 bus_dma_segment_t *sg_list = &ccb->dmamap_xfer->dm_segs[0]; 706 int sg_elem_cnt = ccb->dmamap_xfer->dm_nsegs; 707 708 709 sg_block_next_addr = (u_long) sg_block; /* allow math operation */ 710 sg_block_physical_addr = ccb->hashkey + 711 offsetof(struct adw_ccb, sg_block[0]); 712 scsiqp->sg_real_addr = sg_block_physical_addr; 713 714 /* 715 * If there are more than NO_OF_SG_PER_BLOCK dma segments (hw sg-list) 716 * then split the request into multiple sg-list blocks. 717 */ 718 719 do { 720 for (i = 0; i < NO_OF_SG_PER_BLOCK; i++) { 721 sg_block->sg_list[i].sg_addr = sg_list->ds_addr; 722 sg_block->sg_list[i].sg_count = sg_list->ds_len; 723 724 if (--sg_elem_cnt == 0) { 725 /* last entry, get out */ 726 sg_block->sg_cnt = i + 1; 727 sg_block->sg_ptr = 0; /* next link = NULL */ 728 return; 729 } 730 sg_list++; 731 } 732 sg_block_next_addr += sizeof(ADW_SG_BLOCK); 733 sg_block_physical_addr += sizeof(ADW_SG_BLOCK); 734 735 sg_block->sg_cnt = NO_OF_SG_PER_BLOCK; 736 sg_block->sg_ptr = sg_block_physical_addr; 737 sg_block = (ADW_SG_BLOCK *) sg_block_next_addr; /* virt. addr */ 738 } while (1); 739 } 740 741 742 /******************************************************************************/ 743 /* Interrupts and TimeOut routines */ 744 /******************************************************************************/ 745 746 747 int 748 adw_intr(void *arg) 749 { 750 ADW_SOFTC *sc = arg; 751 752 753 if(AdwISR(sc) != ADW_FALSE) { 754 return (1); 755 } 756 757 return (0); 758 } 759 760 761 /* 762 * Poll a particular unit, looking for a particular xs 763 */ 764 int 765 adw_poll(ADW_SOFTC *sc, struct scsi_xfer *xs, int count) 766 { 767 int s; 768 769 /* timeouts are in msec, so we loop in 1000 usec cycles */ 770 while (count > 0) { 771 s = splbio(); 772 adw_intr(sc); 773 splx(s); 774 if (xs->flags & ITSDONE) { 775 if ((xs->cmd->opcode == INQUIRY) 776 && (xs->sc_link->lun == 0) 777 && (xs->error == XS_NOERROR)) 778 adw_print_info(sc, xs->sc_link->target); 779 return (0); 780 } 781 delay(1000); /* only happens in boot so ok */ 782 count--; 783 } 784 return (1); 785 } 786 787 788 void 789 adw_timeout(void *arg) 790 { 791 ADW_CCB *ccb = arg; 792 struct scsi_xfer *xs = ccb->xs; 793 struct scsi_link *sc_link = xs->sc_link; 794 ADW_SOFTC *sc = sc_link->adapter_softc; 795 int s; 796 797 sc_print_addr(sc_link); 798 printf("timed out"); 799 800 s = splbio(); 801 802 if (ccb->flags & CCB_ABORTED) { 803 /* 804 * Abort Timed Out 805 * 806 * No more opportunities. Lets try resetting the bus and 807 * reinitialize the host adapter. 808 */ 809 timeout_del(&xs->stimeout); 810 printf(" AGAIN. Resetting SCSI Bus\n"); 811 adw_reset_bus(sc); 812 splx(s); 813 return; 814 } else if (ccb->flags & CCB_ABORTING) { 815 /* 816 * Abort the operation that has timed out. 817 * 818 * Second opportunity. 819 */ 820 printf("\n"); 821 xs->error = XS_TIMEOUT; 822 ccb->flags |= CCB_ABORTED; 823 #if 0 824 /* 825 * - XXX - 3.3a microcode is BROKEN!!! 826 * 827 * We cannot abort a CCB, so we can only hope the command 828 * get completed before the next timeout, otherwise a 829 * Bus Reset will arrive inexorably. 830 */ 831 /* 832 * ADW_ABORT_CCB() makes the board to generate an interrupt 833 * 834 * - XXX - The above assertion MUST be verified (and this 835 * code changed as well [callout_*()]), when the 836 * ADW_ABORT_CCB will be working again 837 */ 838 ADW_ABORT_CCB(sc, ccb); 839 #endif 840 /* 841 * waiting for multishot callout_reset() let's restart it 842 * by hand so the next time a timeout event will occur 843 * we will reset the bus. 844 */ 845 timeout_add_msec(&xs->stimeout, ccb->timeout); 846 } else { 847 /* 848 * Abort the operation that has timed out. 849 * 850 * First opportunity. 851 */ 852 printf("\n"); 853 xs->error = XS_TIMEOUT; 854 ccb->flags |= CCB_ABORTING; 855 #if 0 856 /* 857 * - XXX - 3.3a microcode is BROKEN!!! 858 * 859 * We cannot abort a CCB, so we can only hope the command 860 * get completed before the next 2 timeout, otherwise a 861 * Bus Reset will arrive inexorably. 862 */ 863 /* 864 * ADW_ABORT_CCB() makes the board to generate an interrupt 865 * 866 * - XXX - The above assertion MUST be verified (and this 867 * code changed as well [callout_*()]), when the 868 * ADW_ABORT_CCB will be working again 869 */ 870 ADW_ABORT_CCB(sc, ccb); 871 #endif 872 /* 873 * waiting for multishot callout_reset() let's restart it 874 * by hand so to give a second opportunity to the command 875 * which timed-out. 876 */ 877 timeout_add_msec(&xs->stimeout, ccb->timeout); 878 } 879 880 splx(s); 881 } 882 883 884 void 885 adw_reset_bus(ADW_SOFTC *sc) 886 { 887 ADW_CCB *ccb; 888 int s; 889 890 s = splbio(); 891 AdwResetSCSIBus(sc); /* XXX - should check return value? */ 892 while((ccb = TAILQ_LAST(&sc->sc_pending_ccb, 893 adw_pending_ccb)) != NULL) { 894 timeout_del(&ccb->xs->stimeout); 895 TAILQ_REMOVE(&sc->sc_pending_ccb, ccb, chain); 896 TAILQ_INSERT_HEAD(&sc->sc_waiting_ccb, ccb, chain); 897 } 898 899 bzero(sc->sc_freeze_dev, sizeof(sc->sc_freeze_dev)); 900 adw_queue_ccb(sc, TAILQ_FIRST(&sc->sc_waiting_ccb), 1); 901 902 splx(s); 903 } 904 905 906 /******************************************************************************/ 907 /* Host Adapter and Peripherals Information Routines */ 908 /******************************************************************************/ 909 910 911 void 912 adw_print_info(ADW_SOFTC *sc, int tid) 913 { 914 bus_space_handle_t ioh = sc->sc_ioh; 915 bus_space_tag_t iot = sc->sc_iot; 916 u_int16_t hshk_cfg, able_mask, period = 0; 917 918 /* hshk/HSHK means 'handskake' */ 919 920 ADW_READ_WORD_LRAM(iot, ioh, 921 ADW_MC_DEVICE_HSHK_CFG_TABLE + (2 * tid), hshk_cfg); 922 923 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, able_mask); 924 if ((able_mask & ADW_TID_TO_TIDMASK(tid)) == 0) 925 hshk_cfg &= ~HSHK_CFG_WIDE_XFR; 926 927 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, able_mask); 928 if ((able_mask & ADW_TID_TO_TIDMASK(tid)) == 0) 929 hshk_cfg &= ~HSHK_CFG_OFFSET; 930 931 printf("%s: target %d using %d bit ", sc->sc_dev.dv_xname, tid, 932 (hshk_cfg & HSHK_CFG_WIDE_XFR) ? 16 : 8); 933 934 if ((hshk_cfg & HSHK_CFG_OFFSET) == 0) 935 printf("async "); 936 else { 937 period = (hshk_cfg & 0x1f00) >> 8; 938 switch (period) { 939 case 0x11: 940 printf("80.0 "); 941 break; 942 case 0x10: 943 printf("40.0 "); 944 break; 945 default: 946 period = (period * 25) + 50; 947 printf("%d.%d ", 1000/period, ADW_TENTHS(1000, period)); 948 break; 949 } 950 printf("MHz %d REQ/ACK offset ", hshk_cfg & HSHK_CFG_OFFSET); 951 } 952 953 printf("xfers\n"); 954 } 955 956 957 /******************************************************************************/ 958 /* WIDE boards Interrupt callbacks */ 959 /******************************************************************************/ 960 961 962 /* 963 * adw_isr_callback() - Second Level Interrupt Handler called by AdwISR() 964 * 965 * Interrupt callback function for the Wide SCSI Adw Library. 966 * 967 * Notice: 968 * Interrupts are disabled by the caller (AdwISR() function), and will be 969 * enabled at the end of the caller. 970 */ 971 void 972 adw_isr_callback(ADW_SOFTC *sc, ADW_SCSI_REQ_Q *scsiq) 973 { 974 bus_dma_tag_t dmat; 975 ADW_CCB *ccb; 976 struct scsi_xfer *xs; 977 struct scsi_sense_data *s1, *s2; 978 979 980 ccb = adw_ccb_phys_kv(sc, scsiq->ccb_ptr); 981 TAILQ_REMOVE(&sc->sc_pending_ccb, ccb, chain); 982 983 if ((ccb->flags & CCB_ALLOC) == 0) { 984 panic("%s: unallocated ccb found on pending list!", 985 sc->sc_dev.dv_xname); 986 return; 987 } 988 989 xs = ccb->xs; 990 timeout_del(&xs->stimeout); 991 992 /* 993 * If we were a data transfer, unload the map that described 994 * the data buffer. 995 */ 996 dmat = sc->sc_dmat; 997 if (xs->datalen) { 998 bus_dmamap_sync(dmat, ccb->dmamap_xfer, 999 0, ccb->dmamap_xfer->dm_mapsize, 1000 ((xs->flags & SCSI_DATA_IN) ? 1001 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE)); 1002 bus_dmamap_unload(dmat, ccb->dmamap_xfer); 1003 } 1004 1005 /* 1006 * 'done_status' contains the command's ending status. 1007 * 'host_status' contains the host adapter status. 1008 * 'scsi_status' contains the scsi peripheral status. 1009 */ 1010 1011 sc->sc_freeze_dev[scsiq->target_id] = 0; 1012 xs->status = scsiq->scsi_status; 1013 1014 switch (scsiq->done_status) { 1015 case QD_NO_ERROR: /* (scsi_status == 0) && (host_status == 0) */ 1016 NO_ERROR: 1017 xs->resid = scsiq->data_cnt; 1018 xs->error = XS_NOERROR; 1019 break; 1020 1021 case QD_WITH_ERROR: 1022 switch (scsiq->host_status) { 1023 case QHSTA_NO_ERROR: 1024 switch (scsiq->scsi_status) { 1025 case SCSI_COND_MET: 1026 case SCSI_INTERM: 1027 case SCSI_INTERM_COND_MET: 1028 /* 1029 * These non-zero status values are 1030 * not really error conditions. 1031 * 1032 * XXX - would it be too paranoid to 1033 * add SCSI_OK here in 1034 * case the docs are wrong re 1035 * QD_NO_ERROR? 1036 */ 1037 goto NO_ERROR; 1038 1039 case SCSI_CHECK: 1040 case SCSI_TERMINATED: 1041 case SCSI_ACA_ACTIVE: 1042 s1 = &ccb->scsi_sense; 1043 s2 = &xs->sense; 1044 *s2 = *s1; 1045 xs->error = XS_SENSE; 1046 break; 1047 1048 case SCSI_BUSY: 1049 case SCSI_QUEUE_FULL: 1050 case SCSI_RESV_CONFLICT: 1051 sc->sc_freeze_dev[scsiq->target_id] = 1; 1052 xs->error = XS_BUSY; 1053 break; 1054 1055 default: /* scsiq->scsi_status value */ 1056 printf("%s: bad scsi_status: 0x%02x.\n" 1057 ,sc->sc_dev.dv_xname 1058 ,scsiq->scsi_status); 1059 xs->error = XS_DRIVER_STUFFUP; 1060 break; 1061 } 1062 break; 1063 1064 case QHSTA_M_SEL_TIMEOUT: 1065 xs->error = XS_SELTIMEOUT; 1066 break; 1067 1068 case QHSTA_M_DIRECTION_ERR: 1069 case QHSTA_M_SXFR_OFF_UFLW: 1070 case QHSTA_M_SXFR_OFF_OFLW: 1071 case QHSTA_M_SXFR_XFR_OFLW: 1072 case QHSTA_M_QUEUE_ABORTED: 1073 case QHSTA_M_INVALID_DEVICE: 1074 case QHSTA_M_SGBACKUP_ERROR: 1075 case QHSTA_M_SXFR_DESELECTED: 1076 case QHSTA_M_SXFR_XFR_PH_ERR: 1077 case QHSTA_M_BUS_DEVICE_RESET: 1078 case QHSTA_M_NO_AUTO_REQ_SENSE: 1079 case QHSTA_M_BAD_CMPL_STATUS_IN: 1080 case QHSTA_M_SXFR_UNKNOWN_ERROR: 1081 case QHSTA_M_AUTO_REQ_SENSE_FAIL: 1082 case QHSTA_M_UNEXPECTED_BUS_FREE: 1083 printf("%s: host adapter error 0x%02x." 1084 " See adw(4).\n" 1085 ,sc->sc_dev.dv_xname, scsiq->host_status); 1086 xs->error = XS_DRIVER_STUFFUP; 1087 break; 1088 1089 case QHSTA_M_RDMA_PERR: 1090 case QHSTA_M_SXFR_WD_TMO: 1091 case QHSTA_M_WTM_TIMEOUT: 1092 case QHSTA_M_FROZEN_TIDQ: 1093 case QHSTA_M_SXFR_SDMA_ERR: 1094 case QHSTA_M_SXFR_SXFR_PERR: 1095 case QHSTA_M_SCSI_BUS_RESET: 1096 case QHSTA_M_DIRECTION_ERR_HUNG: 1097 case QHSTA_M_SCSI_BUS_RESET_UNSOL: 1098 /* 1099 * XXX - are all these cases really asking 1100 * for a card reset? _BUS_RESET and 1101 * _BUS_RESET_UNSOL added just to make 1102 * sure the pending queue is cleared out 1103 * in case card has lost track of them. 1104 */ 1105 printf("%s: host adapter error 0x%02x," 1106 " resetting bus. See adw(4).\n" 1107 ,sc->sc_dev.dv_xname, scsiq->host_status); 1108 adw_reset_bus(sc); 1109 xs->error = XS_RESET; 1110 break; 1111 1112 default: /* scsiq->host_status value */ 1113 /* 1114 * XXX - is a panic really appropriate here? If 1115 * not, would it be better to make the 1116 * XS_DRIVER_STUFFUP case above the 1117 * default behaviour? Or XS_RESET? 1118 */ 1119 panic("%s: bad host_status: 0x%02x" 1120 ,sc->sc_dev.dv_xname, scsiq->host_status); 1121 break; 1122 } 1123 break; 1124 1125 case QD_ABORTED_BY_HOST: 1126 xs->error = XS_DRIVER_STUFFUP; 1127 break; 1128 1129 default: /* scsiq->done_status value */ 1130 /* 1131 * XXX - would QD_NO_STATUS really mean the I/O is not 1132 * done? and would that mean it should somehow be 1133 * put back as a pending I/O? 1134 */ 1135 printf("%s: bad done_status: 0x%02x" 1136 " (host_status: 0x%02x, scsi_status: 0x%02x)\n" 1137 ,sc->sc_dev.dv_xname 1138 ,scsiq->done_status 1139 ,scsiq->host_status 1140 ,scsiq->scsi_status); 1141 xs->error = XS_DRIVER_STUFFUP; 1142 break; 1143 } 1144 1145 scsi_done(xs); 1146 } 1147 1148 1149 /* 1150 * adw_async_callback() - Adw Library asynchronous event callback function. 1151 */ 1152 void 1153 adw_async_callback(ADW_SOFTC *sc, u_int8_t code) 1154 { 1155 switch (code) { 1156 case ADW_ASYNC_SCSI_BUS_RESET_DET: 1157 /* The firmware detected a SCSI Bus reset. */ 1158 printf("%s: SCSI Bus reset detected\n", sc->sc_dev.dv_xname); 1159 break; 1160 1161 case ADW_ASYNC_RDMA_FAILURE: 1162 /* 1163 * Handle RDMA failure by resetting the SCSI Bus and 1164 * possibly the chip if it is unresponsive. 1165 */ 1166 printf("%s: RDMA failure. Resetting the SCSI Bus and" 1167 " the adapter\n", sc->sc_dev.dv_xname); 1168 adw_reset_bus(sc); 1169 break; 1170 1171 case ADW_HOST_SCSI_BUS_RESET: 1172 /* Host generated SCSI bus reset occurred. */ 1173 printf("%s: Host generated SCSI bus reset occurred\n", 1174 sc->sc_dev.dv_xname); 1175 break; 1176 1177 1178 case ADW_ASYNC_CARRIER_READY_FAILURE: 1179 /* 1180 * Carrier Ready failure. 1181 * 1182 * A warning only - RISC too busy to realize it's been 1183 * tickled. Occurs in normal operation under heavy 1184 * load, so a message is printed only when ADW_DEBUG'ing 1185 */ 1186 #ifdef ADW_DEBUG 1187 printf("%s: Carrier Ready failure!\n", sc->sc_dev.dv_xname); 1188 #endif 1189 break; 1190 1191 default: 1192 printf("%s: Unknown Async callback code (ignored): 0x%02x\n", 1193 sc->sc_dev.dv_xname, code); 1194 break; 1195 } 1196 } 1197