1 /* $OpenBSD: advlib.c,v 1.6 2001/08/12 20:33:50 mickey Exp $ */ 2 /* $NetBSD: advlib.c,v 1.7 1998/10/28 20:39:46 dante Exp $ */ 3 4 /* 5 * Low level routines for the Advanced Systems Inc. SCSI controllers chips 6 * 7 * Copyright (c) 1998 The NetBSD Foundation, Inc. 8 * All rights reserved. 9 * 10 * Author: Baldassare Dante Profeta <dante@mclink.it> 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the NetBSD 23 * Foundation, Inc. and its contributors. 24 * 4. Neither the name of The NetBSD Foundation nor the names of its 25 * contributors may be used to endorse or promote products derived 26 * from this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 29 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 30 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 31 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 32 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 33 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 34 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 35 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 36 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 37 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGE. 39 */ 40 /* 41 * Ported from: 42 */ 43 /* 44 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters 45 * 46 * Copyright (c) 1995-1998 Advanced System Products, Inc. 47 * All Rights Reserved. 48 * 49 * Redistribution and use in source and binary forms, with or without 50 * modification, are permitted provided that redistributions of source 51 * code retain the above copyright notice and this comment without 52 * modification. 53 * 54 */ 55 56 #include <sys/types.h> 57 #include <sys/param.h> 58 #include <sys/systm.h> 59 #include <sys/malloc.h> 60 #include <sys/kernel.h> 61 #include <sys/queue.h> 62 #include <sys/device.h> 63 64 #include <machine/bus.h> 65 #include <machine/intr.h> 66 67 #include <scsi/scsi_all.h> 68 #include <scsi/scsiconf.h> 69 70 #include <vm/vm.h> 71 72 #include <dev/ic/adv.h> 73 #include <dev/ic/advlib.h> 74 #include <dev/ic/advmcode.h> 75 76 77 /* #define ASC_DEBUG */ 78 79 /******************************************************************************/ 80 /* Static functions */ 81 /******************************************************************************/ 82 83 /* Initializzation routines */ 84 static u_int32_t AscLoadMicroCode __P((bus_space_tag_t, bus_space_handle_t, 85 u_int16_t, u_int16_t *, u_int16_t)); 86 static void AscInitLram __P((ASC_SOFTC *)); 87 static void AscInitQLinkVar __P((ASC_SOFTC *)); 88 static int AscResetChipAndScsiBus __P((bus_space_tag_t, bus_space_handle_t)); 89 static u_int16_t AscGetChipBusType __P((bus_space_tag_t, bus_space_handle_t)); 90 91 /* Chip register routines */ 92 static void AscSetBank __P((bus_space_tag_t, bus_space_handle_t, u_int8_t)); 93 94 /* RISC Chip routines */ 95 static int AscStartChip __P((bus_space_tag_t, bus_space_handle_t)); 96 static int AscStopChip __P((bus_space_tag_t, bus_space_handle_t)); 97 static u_int8_t AscSetChipScsiID __P((bus_space_tag_t, bus_space_handle_t, 98 u_int8_t)); 99 static u_int8_t AscGetChipScsiCtrl __P((bus_space_tag_t, bus_space_handle_t)); 100 static u_int8_t AscGetChipVersion __P((bus_space_tag_t, bus_space_handle_t, 101 u_int16_t)); 102 static int AscSetRunChipSynRegAtID __P((bus_space_tag_t, bus_space_handle_t, 103 u_int8_t, u_int8_t)); 104 static int AscSetChipSynRegAtID __P((bus_space_tag_t, bus_space_handle_t, 105 u_int8_t, u_int8_t)); 106 static int AscHostReqRiscHalt __P((bus_space_tag_t, bus_space_handle_t)); 107 static int AscIsChipHalted __P((bus_space_tag_t, bus_space_handle_t)); 108 static void AscSetChipIH __P((bus_space_tag_t, bus_space_handle_t, u_int16_t)); 109 110 /* Lram routines */ 111 static u_int8_t AscReadLramByte __P((bus_space_tag_t, bus_space_handle_t, 112 u_int16_t)); 113 static void AscWriteLramByte __P((bus_space_tag_t, bus_space_handle_t, 114 u_int16_t, u_int8_t)); 115 static u_int16_t AscReadLramWord __P((bus_space_tag_t, bus_space_handle_t, 116 u_int16_t)); 117 static void AscWriteLramWord __P((bus_space_tag_t, bus_space_handle_t, 118 u_int16_t, u_int16_t)); 119 static u_int32_t AscReadLramDWord __P((bus_space_tag_t, bus_space_handle_t, 120 u_int16_t)); 121 static void AscWriteLramDWord __P((bus_space_tag_t, bus_space_handle_t, 122 u_int16_t, u_int32_t)); 123 static void AscMemWordSetLram __P((bus_space_tag_t, bus_space_handle_t, 124 u_int16_t, u_int16_t, int)); 125 static void AscMemWordCopyToLram __P((bus_space_tag_t, bus_space_handle_t, 126 u_int16_t, u_int16_t *, int)); 127 static void AscMemWordCopyFromLram __P((bus_space_tag_t, bus_space_handle_t, 128 u_int16_t, u_int16_t *, int)); 129 static void AscMemDWordCopyToLram __P((bus_space_tag_t, bus_space_handle_t, 130 u_int16_t, u_int32_t *, int)); 131 static u_int32_t AscMemSumLramWord __P((bus_space_tag_t, bus_space_handle_t, 132 u_int16_t, int)); 133 static int AscTestExternalLram __P((bus_space_tag_t, bus_space_handle_t)); 134 135 /* MicroCode routines */ 136 static u_int16_t AscInitMicroCodeVar __P((ASC_SOFTC *)); 137 static u_int32_t AscGetOnePhyAddr __P((ASC_SOFTC *, u_int8_t *, u_int32_t)); 138 static u_int32_t AscGetSGList __P((ASC_SOFTC *, u_int8_t *, u_int32_t, 139 ASC_SG_HEAD *)); 140 141 /* EEProm routines */ 142 static int AscWriteEEPCmdReg __P((bus_space_tag_t, bus_space_handle_t, 143 u_int8_t)); 144 static int AscWriteEEPDataReg __P((bus_space_tag_t, bus_space_handle_t, 145 u_int16_t)); 146 static void AscWaitEEPRead __P((void)); 147 static void AscWaitEEPWrite __P((void)); 148 static u_int16_t AscReadEEPWord __P((bus_space_tag_t, bus_space_handle_t, 149 u_int8_t)); 150 static u_int16_t AscWriteEEPWord __P((bus_space_tag_t, bus_space_handle_t, 151 u_int8_t, u_int16_t)); 152 static u_int16_t AscGetEEPConfig __P((bus_space_tag_t, bus_space_handle_t, 153 ASCEEP_CONFIG *, u_int16_t)); 154 static int AscSetEEPConfig __P((bus_space_tag_t, bus_space_handle_t, 155 ASCEEP_CONFIG *, u_int16_t)); 156 static int AscSetEEPConfigOnce __P((bus_space_tag_t, bus_space_handle_t, 157 ASCEEP_CONFIG *, u_int16_t)); 158 #ifdef ASC_DEBUG 159 static void AscPrintEEPConfig __P((ASCEEP_CONFIG *, u_int16_t)); 160 #endif 161 162 /* Interrupt routines */ 163 static void AscIsrChipHalted __P((ASC_SOFTC *)); 164 static int AscIsrQDone __P((ASC_SOFTC *)); 165 static int AscWaitTixISRDone __P((ASC_SOFTC *, u_int8_t)); 166 static int AscWaitISRDone __P((ASC_SOFTC *)); 167 static u_int8_t _AscCopyLramScsiDoneQ __P((bus_space_tag_t, bus_space_handle_t, 168 u_int16_t, ASC_QDONE_INFO *, 169 u_int32_t)); 170 static void AscGetQDoneInfo __P((bus_space_tag_t, bus_space_handle_t, u_int16_t, 171 ASC_QDONE_INFO *)); 172 static void AscToggleIRQAct __P((bus_space_tag_t, bus_space_handle_t)); 173 static void AscDisableInterrupt __P((bus_space_tag_t, bus_space_handle_t)); 174 static void AscEnableInterrupt __P((bus_space_tag_t, bus_space_handle_t)); 175 static u_int8_t AscGetChipIRQ __P((bus_space_tag_t, bus_space_handle_t, 176 u_int16_t)); 177 static u_int8_t AscSetChipIRQ __P((bus_space_tag_t, bus_space_handle_t, 178 u_int8_t, u_int16_t)); 179 static void AscAckInterrupt __P((bus_space_tag_t, bus_space_handle_t)); 180 static u_int32_t AscGetMaxDmaCount __P((u_int16_t)); 181 static u_int16_t AscGetIsaDmaChannel __P((bus_space_tag_t, bus_space_handle_t)); 182 static u_int16_t AscSetIsaDmaChannel __P((bus_space_tag_t, bus_space_handle_t, 183 u_int16_t)); 184 static u_int8_t AscGetIsaDmaSpeed __P((bus_space_tag_t, bus_space_handle_t)); 185 static u_int8_t AscSetIsaDmaSpeed __P((bus_space_tag_t, bus_space_handle_t, 186 u_int8_t)); 187 188 /* Messages routines */ 189 static void AscHandleExtMsgIn __P((ASC_SOFTC *, u_int16_t, u_int8_t, 190 ASC_SCSI_BIT_ID_TYPE, int, u_int8_t)); 191 static u_int8_t AscMsgOutSDTR __P((ASC_SOFTC *, u_int8_t, u_int8_t)); 192 193 /* SDTR routines */ 194 static void AscSetChipSDTR __P((bus_space_tag_t, bus_space_handle_t, 195 u_int8_t, u_int8_t)); 196 static u_int8_t AscCalSDTRData __P((ASC_SOFTC *, u_int8_t, u_int8_t)); 197 static u_int8_t AscGetSynPeriodIndex __P((ASC_SOFTC *, u_int8_t)); 198 199 /* Queue routines */ 200 static int AscSendScsiQueue __P((ASC_SOFTC *, ASC_SCSI_Q *, u_int8_t)); 201 static int AscSgListToQueue __P((int)); 202 static u_int AscGetNumOfFreeQueue __P((ASC_SOFTC *, u_int8_t, u_int8_t)); 203 static int AscPutReadyQueue __P((ASC_SOFTC *, ASC_SCSI_Q *, u_int8_t)); 204 static void AscPutSCSIQ __P((bus_space_tag_t, bus_space_handle_t, 205 u_int16_t, ASC_SCSI_Q *)); 206 static int AscPutReadySgListQueue __P((ASC_SOFTC *, ASC_SCSI_Q *, u_int8_t)); 207 static u_int8_t AscAllocFreeQueue __P((bus_space_tag_t, bus_space_handle_t, 208 u_int8_t)); 209 static u_int8_t AscAllocMultipleFreeQueue __P((bus_space_tag_t, 210 bus_space_handle_t, 211 u_int8_t, u_int8_t)); 212 static int AscStopQueueExe __P((bus_space_tag_t, bus_space_handle_t)); 213 static void AscStartQueueExe __P((bus_space_tag_t, bus_space_handle_t)); 214 static void AscCleanUpBusyQueue __P((bus_space_tag_t, bus_space_handle_t)); 215 static int _AscWaitQDone __P((bus_space_tag_t, bus_space_handle_t, 216 ASC_SCSI_Q *)); 217 static int AscCleanUpDiscQueue __P((bus_space_tag_t, bus_space_handle_t)); 218 219 /* Abort and Reset CCB routines */ 220 static int AscRiscHaltedAbortCCB __P((ASC_SOFTC *, u_int32_t)); 221 static int AscRiscHaltedAbortTIX __P((ASC_SOFTC *, u_int8_t)); 222 223 /* Error Handling routines */ 224 static int AscSetLibErrorCode __P((ASC_SOFTC *, u_int16_t)); 225 226 /* Handle bugged borads routines */ 227 static int AscTagQueuingSafe __P((ASC_SCSI_INQUIRY *)); 228 static void AscAsyncFix __P((ASC_SOFTC *, u_int8_t, ASC_SCSI_INQUIRY *)); 229 230 /* Miscellaneous routines */ 231 static int AscCompareString __P((u_char *, u_char *, int)); 232 233 /* Device oriented routines */ 234 static int DvcEnterCritical __P((void)); 235 static void DvcLeaveCritical __P((int)); 236 static void DvcSleepMilliSecond __P((u_int32_t)); 237 //static void DvcDelayMicroSecond __P((u_int32_t)); 238 static void DvcDelayNanoSecond __P((u_int32_t)); 239 240 241 /******************************************************************************/ 242 /* Initializzation routines */ 243 /******************************************************************************/ 244 245 /* 246 * This function perform the following steps: 247 * - initialize ASC_SOFTC structure with defaults values. 248 * - inquire board registers to know what kind of board it is. 249 * - keep track of bugged borads. 250 */ 251 void 252 AscInitASC_SOFTC(sc) 253 ASC_SOFTC *sc; 254 { 255 bus_space_tag_t iot = sc->sc_iot; 256 bus_space_handle_t ioh = sc->sc_ioh; 257 int i; 258 u_int8_t chip_version; 259 260 261 ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_HALT); 262 ASC_SET_CHIP_STATUS(iot, ioh, 0); 263 264 sc->bug_fix_cntl = 0; 265 sc->pci_fix_asyn_xfer = 0; 266 sc->pci_fix_asyn_xfer_always = 0; 267 sc->sdtr_done = 0; 268 sc->cur_total_qng = 0; 269 sc->last_q_shortage = 0; 270 sc->use_tagged_qng = 0; 271 sc->unit_not_ready = 0; 272 sc->queue_full_or_busy = 0; 273 sc->host_init_sdtr_index = 0; 274 sc->can_tagged_qng = 0; 275 sc->cmd_qng_enabled = 0; 276 sc->dvc_cntl = ASC_DEF_DVC_CNTL; 277 sc->init_sdtr = 0; 278 sc->max_total_qng = ASC_DEF_MAX_TOTAL_QNG; 279 sc->scsi_reset_wait = 3; 280 sc->start_motor = ASC_SCSI_WIDTH_BIT_SET; 281 sc->max_dma_count = AscGetMaxDmaCount(sc->bus_type); 282 sc->sdtr_enable = ASC_SCSI_WIDTH_BIT_SET; 283 sc->disc_enable = ASC_SCSI_WIDTH_BIT_SET; 284 sc->chip_scsi_id = ASC_DEF_CHIP_SCSI_ID; 285 sc->lib_serial_no = ASC_LIB_SERIAL_NUMBER; 286 sc->lib_version = (ASC_LIB_VERSION_MAJOR << 8) | ASC_LIB_VERSION_MINOR; 287 chip_version = AscGetChipVersion(iot, ioh, sc->bus_type); 288 sc->chip_version = chip_version; 289 if ((sc->bus_type & ASC_IS_PCI) && 290 (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3150)) { 291 sc->bus_type = ASC_IS_PCI_ULTRA; 292 sc->sdtr_period_tbl[0] = SYN_ULTRA_XFER_NS_0; 293 sc->sdtr_period_tbl[1] = SYN_ULTRA_XFER_NS_1; 294 sc->sdtr_period_tbl[2] = SYN_ULTRA_XFER_NS_2; 295 sc->sdtr_period_tbl[3] = SYN_ULTRA_XFER_NS_3; 296 sc->sdtr_period_tbl[4] = SYN_ULTRA_XFER_NS_4; 297 sc->sdtr_period_tbl[5] = SYN_ULTRA_XFER_NS_5; 298 sc->sdtr_period_tbl[6] = SYN_ULTRA_XFER_NS_6; 299 sc->sdtr_period_tbl[7] = SYN_ULTRA_XFER_NS_7; 300 sc->sdtr_period_tbl[8] = SYN_ULTRA_XFER_NS_8; 301 sc->sdtr_period_tbl[9] = SYN_ULTRA_XFER_NS_9; 302 sc->sdtr_period_tbl[10] = SYN_ULTRA_XFER_NS_10; 303 sc->sdtr_period_tbl[11] = SYN_ULTRA_XFER_NS_11; 304 sc->sdtr_period_tbl[12] = SYN_ULTRA_XFER_NS_12; 305 sc->sdtr_period_tbl[13] = SYN_ULTRA_XFER_NS_13; 306 sc->sdtr_period_tbl[14] = SYN_ULTRA_XFER_NS_14; 307 sc->sdtr_period_tbl[15] = SYN_ULTRA_XFER_NS_15; 308 sc->max_sdtr_index = 15; 309 if (chip_version == ASC_CHIP_VER_PCI_ULTRA_3150) 310 ASC_SET_EXTRA_CONTROL(iot, ioh, 311 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE)); 312 else if (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3050) 313 ASC_SET_EXTRA_CONTROL(iot, ioh, 314 (SEC_ACTIVE_NEGATE | SEC_ENABLE_FILTER)); 315 } else { 316 sc->sdtr_period_tbl[0] = SYN_XFER_NS_0; 317 sc->sdtr_period_tbl[1] = SYN_XFER_NS_1; 318 sc->sdtr_period_tbl[2] = SYN_XFER_NS_2; 319 sc->sdtr_period_tbl[3] = SYN_XFER_NS_3; 320 sc->sdtr_period_tbl[4] = SYN_XFER_NS_4; 321 sc->sdtr_period_tbl[5] = SYN_XFER_NS_5; 322 sc->sdtr_period_tbl[6] = SYN_XFER_NS_6; 323 sc->sdtr_period_tbl[7] = SYN_XFER_NS_7; 324 sc->max_sdtr_index = 7; 325 } 326 327 if (sc->bus_type == ASC_IS_PCI) 328 ASC_SET_EXTRA_CONTROL(iot, ioh, 329 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE)); 330 331 sc->isa_dma_speed = ASC_DEF_ISA_DMA_SPEED; 332 if (AscGetChipBusType(iot, ioh) == ASC_IS_ISAPNP) { 333 ASC_SET_CHIP_IFC(iot, ioh, ASC_IFC_INIT_DEFAULT); 334 sc->bus_type = ASC_IS_ISAPNP; 335 } 336 if ((sc->bus_type & ASC_IS_ISA) != 0) 337 sc->isa_dma_channel = AscGetIsaDmaChannel(iot, ioh); 338 339 for (i = 0; i <= ASC_MAX_TID; i++) { 340 sc->cur_dvc_qng[i] = 0; 341 sc->max_dvc_qng[i] = ASC_MAX_SCSI1_QNG; 342 sc->max_tag_qng[i] = ASC_MAX_INRAM_TAG_QNG; 343 } 344 } 345 346 347 /* 348 * This function initialize some ASC_SOFTC fields with values read from 349 * on-board EEProm. 350 */ 351 u_int16_t 352 AscInitFromEEP(sc) 353 ASC_SOFTC *sc; 354 { 355 bus_space_tag_t iot = sc->sc_iot; 356 bus_space_handle_t ioh = sc->sc_ioh; 357 ASCEEP_CONFIG eep_config_buf; 358 ASCEEP_CONFIG *eep_config; 359 u_int16_t chksum; 360 u_int16_t warn_code; 361 u_int16_t cfg_msw, cfg_lsw; 362 int i; 363 int write_eep = 0; 364 365 366 warn_code = 0; 367 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0x00FE); 368 AscStopQueueExe(iot, ioh); 369 if ((AscStopChip(iot, ioh) == FALSE) || 370 (AscGetChipScsiCtrl(iot, ioh) != 0)) { 371 AscResetChipAndScsiBus(iot, ioh); 372 DvcSleepMilliSecond(sc->scsi_reset_wait * 1000); 373 } 374 if (AscIsChipHalted(iot, ioh) == FALSE) 375 return (-1); 376 377 ASC_SET_PC_ADDR(iot, ioh, ASC_MCODE_START_ADDR); 378 if (ASC_GET_PC_ADDR(iot, ioh) != ASC_MCODE_START_ADDR) 379 return (-2); 380 381 eep_config = &eep_config_buf; 382 cfg_msw = ASC_GET_CHIP_CFG_MSW(iot, ioh); 383 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh); 384 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) { 385 cfg_msw &= (~(ASC_CFG_MSW_CLR_MASK)); 386 warn_code |= ASC_WARN_CFG_MSW_RECOVER; 387 ASC_SET_CHIP_CFG_MSW(iot, ioh, cfg_msw); 388 } 389 chksum = AscGetEEPConfig(iot, ioh, eep_config, sc->bus_type); 390 #ifdef ASC_DEBUG 391 AscPrintEEPConfig(eep_config, chksum); 392 #endif 393 if (chksum == 0) 394 chksum = 0xAA55; 395 396 if (ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_AUTO_CONFIG) { 397 warn_code |= ASC_WARN_AUTO_CONFIG; 398 if (sc->chip_version == 3) { 399 if (eep_config->cfg_lsw != cfg_lsw) { 400 warn_code |= ASC_WARN_EEPROM_RECOVER; 401 eep_config->cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh); 402 } 403 if (eep_config->cfg_msw != cfg_msw) { 404 warn_code |= ASC_WARN_EEPROM_RECOVER; 405 eep_config->cfg_msw = ASC_GET_CHIP_CFG_MSW(iot, ioh); 406 } 407 } 408 } 409 eep_config->cfg_msw &= ~ASC_CFG_MSW_CLR_MASK; 410 eep_config->cfg_lsw |= ASC_CFG0_HOST_INT_ON; 411 412 if (chksum != eep_config->chksum) { 413 if (AscGetChipVersion(iot, ioh, sc->bus_type) == 414 ASC_CHIP_VER_PCI_ULTRA_3050) { 415 eep_config->init_sdtr = 0xFF; 416 eep_config->disc_enable = 0xFF; 417 eep_config->start_motor = 0xFF; 418 eep_config->use_cmd_qng = 0; 419 eep_config->max_total_qng = 0xF0; 420 eep_config->max_tag_qng = 0x20; 421 eep_config->cntl = 0xBFFF; 422 eep_config->chip_scsi_id = 7; 423 eep_config->no_scam = 0; 424 eep_config->adapter_info[0] = 0; 425 eep_config->adapter_info[1] = 0; 426 eep_config->adapter_info[2] = 0; 427 eep_config->adapter_info[3] = 0; 428 #if BYTE_ORDER == BIG_ENDIAN 429 eep_config->adapter_info[5] = 0; 430 /* Indicate EEPROM-less board. */ 431 eep_config->adapter_info[4] = 0xBB; 432 #else 433 eep_config->adapter_info[4] = 0; 434 /* Indicate EEPROM-less board. */ 435 eep_config->adapter_info[5] = 0xBB; 436 #endif 437 } else { 438 write_eep = 1; 439 warn_code |= ASC_WARN_EEPROM_CHKSUM; 440 } 441 } 442 sc->sdtr_enable = eep_config->init_sdtr; 443 sc->disc_enable = eep_config->disc_enable; 444 sc->cmd_qng_enabled = eep_config->use_cmd_qng; 445 sc->isa_dma_speed = eep_config->isa_dma_speed; 446 sc->start_motor = eep_config->start_motor; 447 sc->dvc_cntl = eep_config->cntl; 448 #if BYTE_ORDER == BIG_ENDIAN 449 sc->adapter_info[0] = eep_config->adapter_info[1]; 450 sc->adapter_info[1] = eep_config->adapter_info[0]; 451 sc->adapter_info[2] = eep_config->adapter_info[3]; 452 sc->adapter_info[3] = eep_config->adapter_info[2]; 453 sc->adapter_info[4] = eep_config->adapter_info[5]; 454 sc->adapter_info[5] = eep_config->adapter_info[4]; 455 #else 456 sc->adapter_info[0] = eep_config->adapter_info[0]; 457 sc->adapter_info[1] = eep_config->adapter_info[1]; 458 sc->adapter_info[2] = eep_config->adapter_info[2]; 459 sc->adapter_info[3] = eep_config->adapter_info[3]; 460 sc->adapter_info[4] = eep_config->adapter_info[4]; 461 sc->adapter_info[5] = eep_config->adapter_info[5]; 462 #endif 463 464 if (!AscTestExternalLram(iot, ioh)) { 465 if (((sc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA)) { 466 eep_config->max_total_qng = ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG; 467 eep_config->max_tag_qng = ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG; 468 } else { 469 eep_config->cfg_msw |= 0x0800; 470 cfg_msw |= 0x0800; 471 ASC_SET_CHIP_CFG_MSW(iot, ioh, cfg_msw); 472 eep_config->max_total_qng = ASC_MAX_PCI_INRAM_TOTAL_QNG; 473 eep_config->max_tag_qng = ASC_MAX_INRAM_TAG_QNG; 474 } 475 } 476 if (eep_config->max_total_qng < ASC_MIN_TOTAL_QNG) 477 eep_config->max_total_qng = ASC_MIN_TOTAL_QNG; 478 479 if (eep_config->max_total_qng > ASC_MAX_TOTAL_QNG) 480 eep_config->max_total_qng = ASC_MAX_TOTAL_QNG; 481 482 if (eep_config->max_tag_qng > eep_config->max_total_qng) 483 eep_config->max_tag_qng = eep_config->max_total_qng; 484 485 if (eep_config->max_tag_qng < ASC_MIN_TAG_Q_PER_DVC) 486 eep_config->max_tag_qng = ASC_MIN_TAG_Q_PER_DVC; 487 488 sc->max_total_qng = eep_config->max_total_qng; 489 if ((eep_config->use_cmd_qng & eep_config->disc_enable) != 490 eep_config->use_cmd_qng) { 491 eep_config->disc_enable = eep_config->use_cmd_qng; 492 warn_code |= ASC_WARN_CMD_QNG_CONFLICT; 493 } 494 if (sc->bus_type & (ASC_IS_ISA | ASC_IS_VL | ASC_IS_EISA)) 495 sc->irq_no = AscGetChipIRQ(iot, ioh, sc->bus_type); 496 497 eep_config->chip_scsi_id &= ASC_MAX_TID; 498 sc->chip_scsi_id = eep_config->chip_scsi_id; 499 if (((sc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) && 500 !(sc->dvc_cntl & ASC_CNTL_SDTR_ENABLE_ULTRA)) { 501 sc->host_init_sdtr_index = ASC_SDTR_ULTRA_PCI_10MB_INDEX; 502 } 503 for (i = 0; i <= ASC_MAX_TID; i++) { 504 sc->max_tag_qng[i] = eep_config->max_tag_qng; 505 sc->sdtr_period_offset[i] = ASC_DEF_SDTR_OFFSET | 506 (sc->host_init_sdtr_index << 4); 507 } 508 509 eep_config->cfg_msw = ASC_GET_CHIP_CFG_MSW(iot, ioh); 510 if (write_eep) { 511 AscSetEEPConfig(iot, ioh, eep_config, sc->bus_type); 512 #ifdef ASC_DEBUG 513 AscPrintEEPConfig(eep_config, 0); 514 #endif 515 } 516 517 return (warn_code); 518 } 519 520 521 u_int16_t 522 AscInitFromASC_SOFTC(sc) 523 ASC_SOFTC *sc; 524 { 525 bus_space_tag_t iot = sc->sc_iot; 526 bus_space_handle_t ioh = sc->sc_ioh; 527 u_int16_t cfg_msw; 528 u_int16_t warn_code; 529 u_int16_t pci_device_id = sc->pci_device_id; 530 531 532 warn_code = 0; 533 cfg_msw = ASC_GET_CHIP_CFG_MSW(iot, ioh); 534 535 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) { 536 cfg_msw &= (~(ASC_CFG_MSW_CLR_MASK)); 537 warn_code |= ASC_WARN_CFG_MSW_RECOVER; 538 ASC_SET_CHIP_CFG_MSW(iot, ioh, cfg_msw); 539 } 540 if ((sc->cmd_qng_enabled & sc->disc_enable) != sc->cmd_qng_enabled) { 541 sc->disc_enable = sc->cmd_qng_enabled; 542 warn_code |= ASC_WARN_CMD_QNG_CONFLICT; 543 } 544 if (ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_AUTO_CONFIG) { 545 warn_code |= ASC_WARN_AUTO_CONFIG; 546 } 547 if ((sc->bus_type & (ASC_IS_ISA | ASC_IS_VL)) != 0) { 548 AscSetChipIRQ(iot, ioh, sc->irq_no, sc->bus_type); 549 } 550 if (sc->bus_type & ASC_IS_PCI) { 551 cfg_msw &= 0xFFC0; 552 ASC_SET_CHIP_CFG_MSW(iot, ioh, cfg_msw); 553 554 if ((sc->bus_type & ASC_IS_PCI_ULTRA) != ASC_IS_PCI_ULTRA) { 555 if ((pci_device_id == ASC_PCI_DEVICE_ID_REV_A) || 556 (pci_device_id == ASC_PCI_DEVICE_ID_REV_B)) { 557 sc->bug_fix_cntl |= ASC_BUG_FIX_IF_NOT_DWB; 558 sc->bug_fix_cntl |= ASC_BUG_FIX_ASYN_USE_SYN; 559 } 560 } 561 } else if (sc->bus_type == ASC_IS_ISAPNP) { 562 if (AscGetChipVersion(iot, ioh, sc->bus_type) == 563 ASC_CHIP_VER_ASYN_BUG) { 564 sc->bug_fix_cntl |= ASC_BUG_FIX_ASYN_USE_SYN; 565 } 566 } 567 AscSetChipScsiID(iot, ioh, sc->chip_scsi_id); 568 569 if (sc->bus_type & ASC_IS_ISA) { 570 AscSetIsaDmaChannel(iot, ioh, sc->isa_dma_channel); 571 AscSetIsaDmaSpeed(iot, ioh, sc->isa_dma_speed); 572 } 573 return (warn_code); 574 } 575 576 577 /* 578 * - Initialize RISC chip 579 * - Intialize Lram 580 * - Load uCode into Lram 581 * - Enable Interrupts 582 */ 583 int 584 AscInitDriver(sc) 585 ASC_SOFTC *sc; 586 { 587 bus_space_tag_t iot = sc->sc_iot; 588 bus_space_handle_t ioh = sc->sc_ioh; 589 u_int32_t chksum; 590 591 592 if (!AscFindSignature(iot, ioh)) 593 return (1); 594 595 AscDisableInterrupt(iot, ioh); 596 597 AscInitLram(sc); 598 chksum = AscLoadMicroCode(iot, ioh, 0, (u_int16_t *) asc_mcode, 599 asc_mcode_size); 600 if (chksum != asc_mcode_chksum) 601 return (2); 602 603 if (AscInitMicroCodeVar(sc) == 0) 604 return (3); 605 606 AscEnableInterrupt(iot, ioh); 607 608 return (0); 609 } 610 611 612 int 613 AscFindSignature(iot, ioh) 614 bus_space_tag_t iot; 615 bus_space_handle_t ioh; 616 { 617 u_int16_t sig_word; 618 619 if (ASC_GET_CHIP_SIGNATURE_BYTE(iot, ioh) == ASC_1000_ID1B) { 620 sig_word = ASC_GET_CHIP_SIGNATURE_WORD(iot, ioh); 621 if (sig_word == ASC_1000_ID0W || 622 sig_word == ASC_1000_ID0W_FIX) 623 return (1); 624 } 625 return (0); 626 } 627 628 629 static void 630 AscInitLram(sc) 631 ASC_SOFTC *sc; 632 { 633 bus_space_tag_t iot = sc->sc_iot; 634 bus_space_handle_t ioh = sc->sc_ioh; 635 u_int8_t i; 636 u_int16_t s_addr; 637 638 639 AscMemWordSetLram(iot, ioh, ASC_QADR_BEG, 0, 640 (((sc->max_total_qng + 2 + 1) * 64) >> 1)); 641 642 i = ASC_MIN_ACTIVE_QNO; 643 s_addr = ASC_QADR_BEG + ASC_QBLK_SIZE; 644 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_FWD, i + 1); 645 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_BWD, sc->max_total_qng); 646 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_QNO, i); 647 i++; 648 s_addr += ASC_QBLK_SIZE; 649 for (; i < sc->max_total_qng; i++, s_addr += ASC_QBLK_SIZE) { 650 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_FWD, i + 1); 651 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_BWD, i - 1); 652 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_QNO, i); 653 } 654 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_FWD, ASC_QLINK_END); 655 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_BWD, sc->max_total_qng - 1); 656 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_QNO, sc->max_total_qng); 657 i++; 658 s_addr += ASC_QBLK_SIZE; 659 for (; i <= (u_int8_t) (sc->max_total_qng + 3); i++, s_addr += ASC_QBLK_SIZE) { 660 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_FWD, i); 661 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_BWD, i); 662 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_QNO, i); 663 } 664 } 665 666 667 void 668 AscReInitLram(sc) 669 ASC_SOFTC *sc; 670 { 671 672 AscInitLram(sc); 673 AscInitQLinkVar(sc); 674 } 675 676 677 static void 678 AscInitQLinkVar(sc) 679 ASC_SOFTC *sc; 680 { 681 bus_space_tag_t iot = sc->sc_iot; 682 bus_space_handle_t ioh = sc->sc_ioh; 683 u_int8_t i; 684 u_int16_t lram_addr; 685 686 687 ASC_PUT_RISC_VAR_FREE_QHEAD(iot, ioh, 1); 688 ASC_PUT_RISC_VAR_DONE_QTAIL(iot, ioh, sc->max_total_qng); 689 ASC_PUT_VAR_FREE_QHEAD(iot, ioh, 1); 690 ASC_PUT_VAR_DONE_QTAIL(iot, ioh, sc->max_total_qng); 691 AscWriteLramByte(iot, ioh, ASCV_BUSY_QHEAD_B, sc->max_total_qng + 1); 692 AscWriteLramByte(iot, ioh, ASCV_DISC1_QHEAD_B, sc->max_total_qng + 2); 693 AscWriteLramByte(iot, ioh, ASCV_TOTAL_READY_Q_B, sc->max_total_qng); 694 AscWriteLramWord(iot, ioh, ASCV_ASCDVC_ERR_CODE_W, 0); 695 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 696 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, 0); 697 AscWriteLramByte(iot, ioh, ASCV_SCSIBUSY_B, 0); 698 AscWriteLramByte(iot, ioh, ASCV_WTM_FLAG_B, 0); 699 ASC_PUT_QDONE_IN_PROGRESS(iot, ioh, 0); 700 lram_addr = ASC_QADR_BEG; 701 for (i = 0; i < 32; i++, lram_addr += 2) 702 AscWriteLramWord(iot, ioh, lram_addr, 0); 703 } 704 705 706 static int 707 AscResetChipAndScsiBus(bus_space_tag_t iot, 708 bus_space_handle_t ioh) 709 { 710 while (ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_SCSI_RESET_ACTIVE); 711 712 AscStopChip(iot, ioh); 713 ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_CHIP_RESET | ASC_CC_SCSI_RESET | ASC_CC_HALT); 714 715 DvcDelayNanoSecond(60000); 716 717 AscSetChipIH(iot, ioh, ASC_INS_RFLAG_WTM); 718 AscSetChipIH(iot, ioh, ASC_INS_HALT); 719 ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_CHIP_RESET | ASC_CC_HALT); 720 ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_HALT); 721 722 DvcSleepMilliSecond(200); 723 724 ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_CLR_SCSI_RESET_INT); 725 AscStartChip(iot, ioh); 726 727 DvcSleepMilliSecond(200); 728 729 return (AscIsChipHalted(iot, ioh)); 730 } 731 732 733 static u_int16_t 734 AscGetChipBusType(iot, ioh) 735 bus_space_tag_t iot; 736 bus_space_handle_t ioh; 737 { 738 u_int16_t chip_ver; 739 740 chip_ver = ASC_GET_CHIP_VER_NO(iot, ioh); 741 if ((chip_ver >= ASC_CHIP_MIN_VER_VL) && 742 (chip_ver <= ASC_CHIP_MAX_VER_VL)) { 743 /* 744 * if(((iop_base & 0x0C30) == 0x0C30) || ((iop_base & 0x0C50) 745 * == 0x0C50)) return (ASC_IS_EISA); 746 */ 747 return (ASC_IS_VL); 748 } 749 if ((chip_ver >= ASC_CHIP_MIN_VER_ISA) && 750 (chip_ver <= ASC_CHIP_MAX_VER_ISA)) { 751 if (chip_ver >= ASC_CHIP_MIN_VER_ISA_PNP) 752 return (ASC_IS_ISAPNP); 753 754 return (ASC_IS_ISA); 755 } else if ((chip_ver >= ASC_CHIP_MIN_VER_PCI) && 756 (chip_ver <= ASC_CHIP_MAX_VER_PCI)) 757 return (ASC_IS_PCI); 758 759 return (0); 760 } 761 762 763 /******************************************************************************/ 764 /* Chip register routines */ 765 /******************************************************************************/ 766 767 768 static void 769 AscSetBank(iot, ioh, bank) 770 bus_space_tag_t iot; 771 bus_space_handle_t ioh; 772 u_int8_t bank; 773 { 774 u_int8_t val; 775 776 val = ASC_GET_CHIP_CONTROL(iot, ioh) & 777 (~(ASC_CC_SINGLE_STEP | ASC_CC_TEST | 778 ASC_CC_DIAG | ASC_CC_SCSI_RESET | 779 ASC_CC_CHIP_RESET)); 780 781 switch (bank) { 782 case 1: 783 val |= ASC_CC_BANK_ONE; 784 break; 785 786 case 2: 787 val |= ASC_CC_DIAG | ASC_CC_BANK_ONE; 788 break; 789 790 default: 791 val &= ~ASC_CC_BANK_ONE; 792 } 793 794 ASC_SET_CHIP_CONTROL(iot, ioh, val); 795 return; 796 } 797 798 799 /******************************************************************************/ 800 /* Chip routines */ 801 /******************************************************************************/ 802 803 804 static int 805 AscStartChip(iot, ioh) 806 bus_space_tag_t iot; 807 bus_space_handle_t ioh; 808 { 809 ASC_SET_CHIP_CONTROL(iot, ioh, 0); 810 if ((ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_HALTED) != 0) 811 return (0); 812 813 return (1); 814 } 815 816 817 static int 818 AscStopChip(iot, ioh) 819 bus_space_tag_t iot; 820 bus_space_handle_t ioh; 821 { 822 u_int8_t cc_val; 823 824 cc_val = ASC_GET_CHIP_CONTROL(iot, ioh) & 825 (~(ASC_CC_SINGLE_STEP | ASC_CC_TEST | ASC_CC_DIAG)); 826 ASC_SET_CHIP_CONTROL(iot, ioh, cc_val | ASC_CC_HALT); 827 AscSetChipIH(iot, ioh, ASC_INS_HALT); 828 AscSetChipIH(iot, ioh, ASC_INS_RFLAG_WTM); 829 if ((ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_HALTED) == 0) 830 return (0); 831 832 return (1); 833 } 834 835 836 static u_int8_t 837 AscGetChipVersion(iot, ioh, bus_type) 838 bus_space_tag_t iot; 839 bus_space_handle_t ioh; 840 u_int16_t bus_type; 841 { 842 if (bus_type & ASC_IS_EISA) { 843 /* 844 * u_int16_t eisa_iop; u_int8_t revision; 845 * 846 * eisa_iop = ASC_GET_EISA_SLOT(iop_base) | 847 * ASC_EISA_REV_IOP_MASK; revision = inp(eisa_iop); 848 * return((ASC_CHIP_MIN_VER_EISA - 1) + revision); 849 */ 850 } 851 return (ASC_GET_CHIP_VER_NO(iot, ioh)); 852 } 853 854 855 static u_int8_t 856 AscSetChipScsiID(iot, ioh, new_id) 857 bus_space_tag_t iot; 858 bus_space_handle_t ioh; 859 u_int8_t new_id; 860 { 861 u_int16_t cfg_lsw; 862 863 if (ASC_GET_CHIP_SCSI_ID(iot, ioh) == new_id) 864 return (new_id); 865 866 cfg_lsw = ASC_GET_CHIP_SCSI_ID(iot, ioh); 867 cfg_lsw &= 0xF8FF; 868 cfg_lsw |= (new_id & ASC_MAX_TID) << 8; 869 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg_lsw); 870 return (ASC_GET_CHIP_SCSI_ID(iot, ioh)); 871 } 872 873 874 static u_int8_t 875 AscGetChipScsiCtrl(iot, ioh) 876 bus_space_tag_t iot; 877 bus_space_handle_t ioh; 878 { 879 u_int8_t scsi_ctrl; 880 881 AscSetBank(iot, ioh, 1); 882 scsi_ctrl = bus_space_read_1(iot, ioh, ASC_IOP_REG_SC); 883 AscSetBank(iot, ioh, 0); 884 return (scsi_ctrl); 885 } 886 887 888 static int 889 AscSetRunChipSynRegAtID(iot, ioh, tid_no, sdtr_data) 890 bus_space_tag_t iot; 891 bus_space_handle_t ioh; 892 u_int8_t tid_no; 893 u_int8_t sdtr_data; 894 { 895 int retval = FALSE; 896 897 if (AscHostReqRiscHalt(iot, ioh)) { 898 retval = AscSetChipSynRegAtID(iot, ioh, tid_no, sdtr_data); 899 AscStartChip(iot, ioh); 900 } 901 return (retval); 902 } 903 904 905 static int 906 AscSetChipSynRegAtID(iot, ioh, id, sdtr_data) 907 bus_space_tag_t iot; 908 bus_space_handle_t ioh; 909 u_int8_t id; 910 u_int8_t sdtr_data; 911 { 912 ASC_SCSI_BIT_ID_TYPE org_id; 913 int i; 914 int sta = TRUE; 915 916 AscSetBank(iot, ioh, 1); 917 org_id = ASC_READ_CHIP_DVC_ID(iot, ioh); 918 for (i = 0; i <= ASC_MAX_TID; i++) 919 if (org_id == (0x01 << i)) 920 break; 921 922 org_id = i; 923 ASC_WRITE_CHIP_DVC_ID(iot, ioh, id); 924 if (ASC_READ_CHIP_DVC_ID(iot, ioh) == (0x01 << id)) { 925 AscSetBank(iot, ioh, 0); 926 ASC_SET_CHIP_SYN(iot, ioh, sdtr_data); 927 if (ASC_GET_CHIP_SYN(iot, ioh) != sdtr_data) 928 sta = FALSE; 929 } else 930 sta = FALSE; 931 932 AscSetBank(iot, ioh, 1); 933 ASC_WRITE_CHIP_DVC_ID(iot, ioh, org_id); 934 AscSetBank(iot, ioh, 0); 935 return (sta); 936 } 937 938 939 static int 940 AscHostReqRiscHalt(iot, ioh) 941 bus_space_tag_t iot; 942 bus_space_handle_t ioh; 943 { 944 int count = 0; 945 int retval = 0; 946 u_int8_t saved_stop_code; 947 948 949 if (AscIsChipHalted(iot, ioh)) 950 return (1); 951 saved_stop_code = AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B); 952 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, 953 ASC_STOP_HOST_REQ_RISC_HALT | ASC_STOP_REQ_RISC_STOP); 954 955 do { 956 if (AscIsChipHalted(iot, ioh)) { 957 retval = 1; 958 break; 959 } 960 DvcSleepMilliSecond(100); 961 } while (count++ < 20); 962 963 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, saved_stop_code); 964 965 return (retval); 966 } 967 968 969 static int 970 AscIsChipHalted(iot, ioh) 971 bus_space_tag_t iot; 972 bus_space_handle_t ioh; 973 { 974 if ((ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_HALTED) != 0) 975 if ((ASC_GET_CHIP_CONTROL(iot, ioh) & ASC_CC_HALT) != 0) 976 return (1); 977 978 return (0); 979 } 980 981 982 static void 983 AscSetChipIH(iot, ioh, ins_code) 984 bus_space_tag_t iot; 985 bus_space_handle_t ioh; 986 u_int16_t ins_code; 987 { 988 AscSetBank(iot, ioh, 1); 989 ASC_WRITE_CHIP_IH(iot, ioh, ins_code); 990 AscSetBank(iot, ioh, 0); 991 992 return; 993 } 994 995 996 /******************************************************************************/ 997 /* Lram routines */ 998 /******************************************************************************/ 999 1000 1001 static u_int8_t 1002 AscReadLramByte(iot, ioh, addr) 1003 bus_space_tag_t iot; 1004 bus_space_handle_t ioh; 1005 u_int16_t addr; 1006 { 1007 u_int8_t byte_data; 1008 u_int16_t word_data; 1009 1010 1011 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr & 0xFFFE); 1012 word_data = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 1013 1014 if (addr & 1) { 1015 /* odd address */ 1016 byte_data = (u_int8_t) ((word_data >> 8) & 0xFF); 1017 } else { 1018 /* even address */ 1019 byte_data = (u_int8_t) (word_data & 0xFF); 1020 } 1021 1022 return (byte_data); 1023 } 1024 1025 1026 static void 1027 AscWriteLramByte(iot, ioh, addr, data) 1028 bus_space_tag_t iot; 1029 bus_space_handle_t ioh; 1030 u_int16_t addr; 1031 u_int8_t data; 1032 { 1033 u_int16_t word_data; 1034 1035 1036 word_data = AscReadLramWord(iot, ioh, addr & 0xFFFE); 1037 1038 if (addr & 1) { 1039 /* odd address */ 1040 word_data &= 0x00FF; 1041 word_data |= (((u_int16_t) data) << 8) & 0xFF00; 1042 } else { 1043 /* even address */ 1044 word_data &= 0xFF00; 1045 word_data |= ((u_int16_t) data) & 0x00FF; 1046 } 1047 1048 AscWriteLramWord(iot, ioh, addr, word_data); 1049 } 1050 1051 1052 static u_int16_t 1053 AscReadLramWord(iot, ioh, addr) 1054 bus_space_tag_t iot; 1055 bus_space_handle_t ioh; 1056 u_int16_t addr; 1057 { 1058 1059 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr); 1060 return (ASC_GET_CHIP_LRAM_DATA(iot, ioh)); 1061 } 1062 1063 1064 static void 1065 AscWriteLramWord(iot, ioh, addr, data) 1066 bus_space_tag_t iot; 1067 bus_space_handle_t ioh; 1068 u_int16_t addr; 1069 u_int16_t data; 1070 { 1071 1072 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr); 1073 ASC_SET_CHIP_LRAM_DATA(iot, ioh, data); 1074 } 1075 1076 1077 static u_int32_t 1078 AscReadLramDWord(iot, ioh, addr) 1079 bus_space_tag_t iot; 1080 bus_space_handle_t ioh; 1081 u_int16_t addr; 1082 { 1083 u_int16_t low_word, hi_word; 1084 1085 1086 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr); 1087 low_word = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 1088 hi_word = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 1089 1090 return ((((u_int32_t) hi_word) << 16) | (u_int32_t) low_word); 1091 } 1092 1093 1094 static void 1095 AscWriteLramDWord(iot, ioh, addr, data) 1096 bus_space_tag_t iot; 1097 bus_space_handle_t ioh; 1098 u_int16_t addr; 1099 u_int32_t data; 1100 { 1101 1102 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr); 1103 ASC_SET_CHIP_LRAM_DATA(iot, ioh, (u_int16_t) (data & 0x0000FFFF)); 1104 ASC_SET_CHIP_LRAM_DATA(iot, ioh, (u_int16_t) (data >> 16)); 1105 } 1106 1107 1108 static void 1109 AscMemWordSetLram(iot, ioh, s_addr, s_words, count) 1110 bus_space_tag_t iot; 1111 bus_space_handle_t ioh; 1112 u_int16_t s_addr; 1113 u_int16_t s_words; 1114 int count; 1115 { 1116 int i; 1117 1118 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, s_addr); 1119 for (i = 0; i < count; i++) 1120 ASC_SET_CHIP_LRAM_DATA(iot, ioh, s_words); 1121 } 1122 1123 1124 static void 1125 AscMemWordCopyToLram(iot, ioh, s_addr, s_buffer, words) 1126 bus_space_tag_t iot; 1127 bus_space_handle_t ioh; 1128 u_int16_t s_addr; 1129 u_int16_t *s_buffer; 1130 int words; 1131 { 1132 int i; 1133 1134 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, s_addr); 1135 for (i = 0; i < words; i++, s_buffer++) 1136 ASC_SET_CHIP_LRAM_DATA_NO_SWAP(iot, ioh, *s_buffer); 1137 } 1138 1139 1140 static void 1141 AscMemWordCopyFromLram(iot, ioh, s_addr, s_buffer, words) 1142 bus_space_tag_t iot; 1143 bus_space_handle_t ioh; 1144 u_int16_t s_addr; 1145 u_int16_t *s_buffer; 1146 int words; 1147 { 1148 int i; 1149 1150 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, s_addr); 1151 for (i = 0; i < words; i++, s_buffer++) 1152 *s_buffer = ASC_GET_CHIP_LRAM_DATA_NO_SWAP(iot, ioh); 1153 } 1154 1155 1156 static void 1157 AscMemDWordCopyToLram(iot, ioh, s_addr, s_buffer, dwords) 1158 bus_space_tag_t iot; 1159 bus_space_handle_t ioh; 1160 u_int16_t s_addr; 1161 u_int32_t *s_buffer; 1162 int dwords; 1163 { 1164 int i; 1165 u_int32_t *pw; 1166 1167 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, s_addr); 1168 1169 pw = s_buffer; 1170 for (i = 0; i < dwords; i++, pw++) { 1171 ASC_SET_CHIP_LRAM_DATA(iot, ioh, LO_WORD(*pw)); 1172 DELAY(1); 1173 ASC_SET_CHIP_LRAM_DATA(iot, ioh, HI_WORD(*pw)); 1174 } 1175 } 1176 1177 1178 static u_int32_t 1179 AscMemSumLramWord(iot, ioh, s_addr, words) 1180 bus_space_tag_t iot; 1181 bus_space_handle_t ioh; 1182 u_int16_t s_addr; 1183 int words; 1184 { 1185 u_int32_t sum = 0L; 1186 u_int16_t i; 1187 1188 1189 for (i = 0; i < words; i++, s_addr += 2) 1190 sum += AscReadLramWord(iot, ioh, s_addr); 1191 1192 return (sum); 1193 } 1194 1195 1196 static int 1197 AscTestExternalLram(iot, ioh) 1198 bus_space_tag_t iot; 1199 bus_space_handle_t ioh; 1200 { 1201 u_int16_t q_addr; 1202 u_int16_t saved_word; 1203 int retval; 1204 1205 1206 retval = 0; 1207 q_addr = ASC_QNO_TO_QADDR(241); 1208 saved_word = AscReadLramWord(iot, ioh, q_addr); 1209 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, q_addr); 1210 ASC_SET_CHIP_LRAM_DATA(iot, ioh, 0x55AA); 1211 DvcSleepMilliSecond(10); 1212 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, q_addr); 1213 1214 if (ASC_GET_CHIP_LRAM_DATA(iot, ioh) == 0x55AA) { 1215 retval = 1; 1216 AscWriteLramWord(iot, ioh, q_addr, saved_word); 1217 } 1218 return (retval); 1219 } 1220 1221 1222 /******************************************************************************/ 1223 /* MicroCode routines */ 1224 /******************************************************************************/ 1225 1226 1227 static u_int16_t 1228 AscInitMicroCodeVar(sc) 1229 ASC_SOFTC *sc; 1230 { 1231 bus_space_tag_t iot = sc->sc_iot; 1232 bus_space_handle_t ioh = sc->sc_ioh; 1233 u_int32_t phy_addr; 1234 int i; 1235 1236 1237 for (i = 0; i <= ASC_MAX_TID; i++) 1238 ASC_PUT_MCODE_INIT_SDTR_AT_ID(iot, ioh, i, 1239 sc->sdtr_period_offset[i]); 1240 1241 AscInitQLinkVar(sc); 1242 AscWriteLramByte(iot, ioh, ASCV_DISC_ENABLE_B, sc->disc_enable); 1243 AscWriteLramByte(iot, ioh, ASCV_HOSTSCSI_ID_B, 1244 ASC_TID_TO_TARGET_ID(sc->chip_scsi_id)); 1245 1246 if ((phy_addr = AscGetOnePhyAddr(sc, sc->overrun_buf, 1247 ASC_OVERRUN_BSIZE)) == 0L) { 1248 return (0); 1249 } else { 1250 phy_addr = (phy_addr & 0xFFFFFFF8ul) + 8; 1251 AscWriteLramDWord(iot, ioh, ASCV_OVERRUN_PADDR_D, phy_addr); 1252 AscWriteLramDWord(iot, ioh, ASCV_OVERRUN_BSIZE_D, 1253 ASC_OVERRUN_BSIZE - 8); 1254 } 1255 1256 sc->mcode_date = AscReadLramWord(iot, ioh, ASCV_MC_DATE_W); 1257 sc->mcode_version = AscReadLramWord(iot, ioh, ASCV_MC_VER_W); 1258 ASC_SET_PC_ADDR(iot, ioh, ASC_MCODE_START_ADDR); 1259 1260 if (ASC_GET_PC_ADDR(iot, ioh) != ASC_MCODE_START_ADDR) { 1261 return (0); 1262 } 1263 if (AscStartChip(iot, ioh) != 1) { 1264 return (0); 1265 } 1266 return (1); 1267 } 1268 1269 1270 static u_int32_t 1271 AscLoadMicroCode(iot, ioh, s_addr, mcode_buf, mcode_size) 1272 bus_space_tag_t iot; 1273 bus_space_handle_t ioh; 1274 u_int16_t s_addr; 1275 u_int16_t *mcode_buf; 1276 u_int16_t mcode_size; 1277 { 1278 u_int32_t chksum; 1279 u_int16_t mcode_word_size; 1280 u_int16_t mcode_chksum; 1281 1282 mcode_word_size = mcode_size >> 1; 1283 /* clear board memory */ 1284 AscMemWordSetLram(iot, ioh, s_addr, 0, mcode_word_size); 1285 /* copy uCode to board memory */ 1286 AscMemWordCopyToLram(iot, ioh, s_addr, mcode_buf, mcode_word_size); 1287 chksum = AscMemSumLramWord(iot, ioh, s_addr, mcode_word_size); 1288 mcode_chksum = AscMemSumLramWord(iot, ioh, ASC_CODE_SEC_BEG, 1289 ((mcode_size - s_addr - ASC_CODE_SEC_BEG) >> 1)); 1290 AscWriteLramWord(iot, ioh, ASCV_MCODE_CHKSUM_W, mcode_chksum); 1291 AscWriteLramWord(iot, ioh, ASCV_MCODE_SIZE_W, mcode_size); 1292 1293 return (chksum); 1294 } 1295 1296 1297 static u_int32_t 1298 AscGetOnePhyAddr(sc, buf_addr, buf_size) 1299 ASC_SOFTC *sc; 1300 u_int8_t *buf_addr; 1301 u_int32_t buf_size; 1302 { 1303 ASC_MIN_SG_HEAD sg_head; 1304 1305 sg_head.entry_cnt = ASC_MIN_SG_LIST; 1306 if (AscGetSGList(sc, buf_addr, buf_size, (ASC_SG_HEAD *) & sg_head) != 1307 buf_size) { 1308 return (0L); 1309 } 1310 if (sg_head.entry_cnt > 1) { 1311 return (0L); 1312 } 1313 return (sg_head.sg_list[0].addr); 1314 } 1315 1316 1317 static u_int32_t 1318 AscGetSGList(sc, buf_addr, buf_len, asc_sg_head_ptr) 1319 ASC_SOFTC *sc; 1320 u_int8_t *buf_addr; 1321 u_int32_t buf_len; 1322 ASC_SG_HEAD *asc_sg_head_ptr; 1323 { 1324 u_int32_t buf_size; 1325 1326 buf_size = buf_len; 1327 asc_sg_head_ptr->entry_cnt = 1; 1328 asc_sg_head_ptr->sg_list[0].addr = (u_int32_t) buf_addr; 1329 asc_sg_head_ptr->sg_list[0].bytes = buf_size; 1330 1331 return (buf_size); 1332 } 1333 1334 1335 /******************************************************************************/ 1336 /* EEProm routines */ 1337 /******************************************************************************/ 1338 1339 1340 static int 1341 AscWriteEEPCmdReg(iot, ioh, cmd_reg) 1342 bus_space_tag_t iot; 1343 bus_space_handle_t ioh; 1344 u_int8_t cmd_reg; 1345 { 1346 u_int8_t read_back; 1347 int retry; 1348 1349 retry = 0; 1350 1351 while (TRUE) { 1352 ASC_SET_CHIP_EEP_CMD(iot, ioh, cmd_reg); 1353 DvcSleepMilliSecond(1); 1354 read_back = ASC_GET_CHIP_EEP_CMD(iot, ioh); 1355 if (read_back == cmd_reg) 1356 return (1); 1357 1358 if (retry++ > ASC_EEP_MAX_RETRY) 1359 return (0); 1360 } 1361 } 1362 1363 1364 static int 1365 AscWriteEEPDataReg(iot, ioh, data_reg) 1366 bus_space_tag_t iot; 1367 bus_space_handle_t ioh; 1368 u_int16_t data_reg; 1369 { 1370 u_int16_t read_back; 1371 int retry; 1372 1373 retry = 0; 1374 while (TRUE) { 1375 ASC_SET_CHIP_EEP_DATA(iot, ioh, data_reg); 1376 DvcSleepMilliSecond(1); 1377 read_back = ASC_GET_CHIP_EEP_DATA(iot, ioh); 1378 if (read_back == data_reg) 1379 return (1); 1380 1381 if (retry++ > ASC_EEP_MAX_RETRY) 1382 return (0); 1383 } 1384 } 1385 1386 1387 static void 1388 AscWaitEEPRead(void) 1389 { 1390 1391 DvcSleepMilliSecond(1); 1392 } 1393 1394 1395 static void 1396 AscWaitEEPWrite(void) 1397 { 1398 1399 DvcSleepMilliSecond(1); 1400 } 1401 1402 1403 static u_int16_t 1404 AscReadEEPWord(iot, ioh, addr) 1405 bus_space_tag_t iot; 1406 bus_space_handle_t ioh; 1407 u_int8_t addr; 1408 { 1409 u_int16_t read_wval; 1410 u_int8_t cmd_reg; 1411 1412 AscWriteEEPCmdReg(iot, ioh, ASC_EEP_CMD_WRITE_DISABLE); 1413 AscWaitEEPRead(); 1414 cmd_reg = addr | ASC_EEP_CMD_READ; 1415 AscWriteEEPCmdReg(iot, ioh, cmd_reg); 1416 AscWaitEEPRead(); 1417 read_wval = ASC_GET_CHIP_EEP_DATA(iot, ioh); 1418 AscWaitEEPRead(); 1419 1420 return (read_wval); 1421 } 1422 1423 1424 static u_int16_t 1425 AscWriteEEPWord(iot, ioh, addr, word_val) 1426 bus_space_tag_t iot; 1427 bus_space_handle_t ioh; 1428 u_int8_t addr; 1429 u_int16_t word_val; 1430 { 1431 u_int16_t read_wval; 1432 1433 read_wval = AscReadEEPWord(iot, ioh, addr); 1434 if (read_wval != word_val) { 1435 AscWriteEEPCmdReg(iot, ioh, ASC_EEP_CMD_WRITE_ABLE); 1436 AscWaitEEPRead(); 1437 AscWriteEEPDataReg(iot, ioh, word_val); 1438 AscWaitEEPRead(); 1439 AscWriteEEPCmdReg(iot, ioh, ASC_EEP_CMD_WRITE | addr); 1440 AscWaitEEPWrite(); 1441 AscWriteEEPCmdReg(iot, ioh, ASC_EEP_CMD_WRITE_DISABLE); 1442 AscWaitEEPRead(); 1443 return (AscReadEEPWord(iot, ioh, addr)); 1444 } 1445 return (read_wval); 1446 } 1447 1448 1449 static u_int16_t 1450 AscGetEEPConfig(iot, ioh, cfg_buf, bus_type) 1451 bus_space_tag_t iot; 1452 bus_space_handle_t ioh; 1453 ASCEEP_CONFIG *cfg_buf; 1454 u_int16_t bus_type; 1455 { 1456 u_int16_t wval; 1457 u_int16_t sum; 1458 u_int16_t *wbuf; 1459 int cfg_beg; 1460 int cfg_end; 1461 int s_addr; 1462 int isa_pnp_wsize; 1463 1464 1465 wbuf = (u_int16_t *) cfg_buf; 1466 sum = 0; 1467 isa_pnp_wsize = 0; 1468 1469 for (s_addr = 0; s_addr < (2 + isa_pnp_wsize); s_addr++, wbuf++) { 1470 wval = AscReadEEPWord(iot, ioh, s_addr); 1471 sum += wval; 1472 *wbuf = wval; 1473 } 1474 1475 if (bus_type & ASC_IS_VL) { 1476 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL; 1477 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL; 1478 } else { 1479 cfg_beg = ASC_EEP_DVC_CFG_BEG; 1480 cfg_end = ASC_EEP_MAX_DVC_ADDR; 1481 } 1482 1483 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) { 1484 wval = AscReadEEPWord(iot, ioh, s_addr); 1485 sum += wval; 1486 *wbuf = wval; 1487 } 1488 1489 *wbuf = AscReadEEPWord(iot, ioh, s_addr); 1490 1491 return (sum); 1492 } 1493 1494 1495 static int 1496 AscSetEEPConfig(iot, ioh, cfg_buf, bus_type) 1497 bus_space_tag_t iot; 1498 bus_space_handle_t ioh; 1499 ASCEEP_CONFIG *cfg_buf; 1500 u_int16_t bus_type; 1501 { 1502 int retry; 1503 int n_error; 1504 1505 retry = 0; 1506 while (TRUE) { 1507 if ((n_error = AscSetEEPConfigOnce(iot, ioh, cfg_buf, bus_type)) == 0) 1508 break; 1509 1510 if (++retry > ASC_EEP_MAX_RETRY) 1511 break; 1512 } 1513 1514 return (n_error); 1515 } 1516 1517 1518 static int 1519 AscSetEEPConfigOnce(iot, ioh, cfg_buf, bus_type) 1520 bus_space_tag_t iot; 1521 bus_space_handle_t ioh; 1522 ASCEEP_CONFIG *cfg_buf; 1523 u_int16_t bus_type; 1524 { 1525 int n_error; 1526 u_int16_t *wbuf; 1527 u_int16_t sum; 1528 int s_addr; 1529 int cfg_beg; 1530 int cfg_end; 1531 1532 wbuf = (u_int16_t *) cfg_buf; 1533 n_error = 0; 1534 sum = 0; 1535 1536 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) { 1537 sum += *wbuf; 1538 if (*wbuf != AscWriteEEPWord(iot, ioh, s_addr, *wbuf)) 1539 n_error++; 1540 } 1541 1542 if (bus_type & ASC_IS_VL) { 1543 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL; 1544 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL; 1545 } else { 1546 cfg_beg = ASC_EEP_DVC_CFG_BEG; 1547 cfg_end = ASC_EEP_MAX_DVC_ADDR; 1548 } 1549 1550 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) { 1551 sum += *wbuf; 1552 if (*wbuf != AscWriteEEPWord(iot, ioh, s_addr, *wbuf)) 1553 n_error++; 1554 } 1555 1556 *wbuf = sum; 1557 if (sum != AscWriteEEPWord(iot, ioh, s_addr, sum)) 1558 n_error++; 1559 1560 wbuf = (u_int16_t *) cfg_buf; 1561 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) { 1562 if (*wbuf != AscReadEEPWord(iot, ioh, s_addr)) 1563 n_error++; 1564 } 1565 1566 for (s_addr = cfg_beg; s_addr <= cfg_end; s_addr++, wbuf++) { 1567 if (*wbuf != AscReadEEPWord(iot, ioh, s_addr)) 1568 n_error++; 1569 } 1570 1571 return (n_error); 1572 } 1573 1574 1575 #ifdef ASC_DEBUG 1576 static void 1577 AscPrintEEPConfig(eep_config, chksum) 1578 ASCEEP_CONFIG *eep_config; 1579 u_int16_t chksum; 1580 { 1581 printf("---- ASC EEprom settings ----\n"); 1582 printf("cfg_lsw = 0x%x\n", eep_config->cfg_lsw); 1583 printf("cfg_msw = 0x%x\n", eep_config->cfg_msw); 1584 printf("init_sdtr = 0x%x\n", eep_config->init_sdtr); 1585 printf("disc_enable = 0x%x\n", eep_config->disc_enable); 1586 printf("use_cmd_qng = %d\n", eep_config->use_cmd_qng); 1587 printf("start_motor = 0x%x\n", eep_config->start_motor); 1588 printf("max_total_qng = 0x%x\n", eep_config->max_total_qng); 1589 printf("max_tag_qng = 0x%x\n", eep_config->max_tag_qng); 1590 printf("bios_scan = 0x%x\n", eep_config->bios_scan); 1591 printf("power_up_wait = 0x%x\n", eep_config->power_up_wait); 1592 printf("no_scam = %d\n", eep_config->no_scam); 1593 printf("chip_scsi_id = %d\n", eep_config->chip_scsi_id); 1594 printf("isa_dma_speed = %d\n", eep_config->isa_dma_speed); 1595 printf("cntl = 0x%x\n", eep_config->cntl); 1596 #if BYTE_ORDER == BIG_ENDIAN 1597 printf("adapter_info[0] = 0x%x\n", eep_config->adapter_info[1]); 1598 printf("adapter_info[1] = 0x%x\n", eep_config->adapter_info[0]); 1599 printf("adapter_info[2] = 0x%x\n", eep_config->adapter_info[3]); 1600 printf("adapter_info[3] = 0x%x\n", eep_config->adapter_info[2]); 1601 printf("adapter_info[4] = 0x%x\n", eep_config->adapter_info[5]); 1602 printf("adapter_info[5] = 0x%x\n", eep_config->adapter_info[4]); 1603 #else 1604 printf("adapter_info[0] = 0x%x\n", eep_config->adapter_info[0]); 1605 printf("adapter_info[1] = 0x%x\n", eep_config->adapter_info[1]); 1606 printf("adapter_info[2] = 0x%x\n", eep_config->adapter_info[2]); 1607 printf("adapter_info[3] = 0x%x\n", eep_config->adapter_info[3]); 1608 printf("adapter_info[4] = 0x%x\n", eep_config->adapter_info[4]); 1609 printf("adapter_info[5] = 0x%x\n", eep_config->adapter_info[5]); 1610 #endif 1611 printf("checksum = 0x%x\n", eep_config->chksum); 1612 printf("calculated checksum = 0x%x\n", chksum); 1613 printf("-----------------------------\n"); 1614 } 1615 #endif 1616 1617 1618 /******************************************************************************/ 1619 /* Interrupt routines */ 1620 /******************************************************************************/ 1621 1622 1623 int 1624 AscISR(sc) 1625 ASC_SOFTC *sc; 1626 { 1627 bus_space_tag_t iot = sc->sc_iot; 1628 bus_space_handle_t ioh = sc->sc_ioh; 1629 u_int16_t chipstat; 1630 u_int16_t saved_ram_addr; 1631 u_int8_t ctrl_reg; 1632 u_int8_t saved_ctrl_reg; 1633 int int_pending; 1634 int status; 1635 u_int8_t host_flag; 1636 1637 1638 int_pending = FALSE; 1639 1640 ctrl_reg = ASC_GET_CHIP_CONTROL(iot, ioh); 1641 saved_ctrl_reg = ctrl_reg & (~(ASC_CC_SCSI_RESET | ASC_CC_CHIP_RESET | 1642 ASC_CC_SINGLE_STEP | ASC_CC_DIAG | ASC_CC_TEST)); 1643 chipstat = ASC_GET_CHIP_STATUS(iot, ioh); 1644 if (chipstat & ASC_CSW_SCSI_RESET_LATCH) { 1645 if (!(sc->bus_type & (ASC_IS_VL | ASC_IS_EISA))) { 1646 int_pending = TRUE; 1647 sc->sdtr_done = 0; 1648 saved_ctrl_reg &= (u_int8_t) (~ASC_CC_HALT); 1649 1650 while (ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_SCSI_RESET_ACTIVE); 1651 1652 ASC_SET_CHIP_CONTROL(iot, ioh, (ASC_CC_CHIP_RESET | ASC_CC_HALT)); 1653 ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_HALT); 1654 ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_CLR_SCSI_RESET_INT); 1655 ASC_SET_CHIP_STATUS(iot, ioh, 0); 1656 chipstat = ASC_GET_CHIP_STATUS(iot, ioh); 1657 } 1658 } 1659 saved_ram_addr = ASC_GET_CHIP_LRAM_ADDR(iot, ioh); 1660 host_flag = AscReadLramByte(iot, ioh, ASCV_HOST_FLAG_B) & 1661 (u_int8_t) (~ASC_HOST_FLAG_IN_ISR); 1662 AscWriteLramByte(iot, ioh, ASCV_HOST_FLAG_B, 1663 (host_flag | ASC_HOST_FLAG_IN_ISR)); 1664 1665 if ((chipstat & ASC_CSW_INT_PENDING) || (int_pending)) { 1666 AscAckInterrupt(iot, ioh); 1667 int_pending = TRUE; 1668 1669 if ((chipstat & ASC_CSW_HALTED) && 1670 (ctrl_reg & ASC_CC_SINGLE_STEP)) { 1671 AscIsrChipHalted(sc); 1672 saved_ctrl_reg &= ~ASC_CC_HALT; 1673 } else { 1674 if (sc->dvc_cntl & ASC_CNTL_INT_MULTI_Q) { 1675 while (((status = AscIsrQDone(sc)) & 0x01) != 0); 1676 } else { 1677 do { 1678 if ((status = AscIsrQDone(sc)) == 1) 1679 break; 1680 } while (status == 0x11); 1681 } 1682 1683 if (status & 0x80) 1684 int_pending = -1; 1685 } 1686 } 1687 AscWriteLramByte(iot, ioh, ASCV_HOST_FLAG_B, host_flag); 1688 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, saved_ram_addr); 1689 ASC_SET_CHIP_CONTROL(iot, ioh, saved_ctrl_reg); 1690 1691 return (1); 1692 /* return(int_pending); */ 1693 } 1694 1695 1696 static int 1697 AscIsrQDone(sc) 1698 ASC_SOFTC *sc; 1699 { 1700 u_int8_t next_qp; 1701 u_int8_t n_q_used; 1702 u_int8_t sg_list_qp; 1703 u_int8_t sg_queue_cnt; 1704 u_int8_t q_cnt; 1705 u_int8_t done_q_tail; 1706 u_int8_t tid_no; 1707 ASC_SCSI_BIT_ID_TYPE scsi_busy; 1708 ASC_SCSI_BIT_ID_TYPE target_id; 1709 bus_space_tag_t iot = sc->sc_iot; 1710 bus_space_handle_t ioh = sc->sc_ioh; 1711 u_int16_t q_addr; 1712 u_int16_t sg_q_addr; 1713 u_int8_t cur_target_qng; 1714 ASC_QDONE_INFO scsiq_buf; 1715 ASC_QDONE_INFO *scsiq; 1716 ASC_ISR_CALLBACK asc_isr_callback; 1717 1718 1719 asc_isr_callback = (ASC_ISR_CALLBACK) sc->isr_callback; 1720 n_q_used = 1; 1721 scsiq = (ASC_QDONE_INFO *) & scsiq_buf; 1722 done_q_tail = ASC_GET_VAR_DONE_QTAIL(iot, ioh); 1723 q_addr = ASC_QNO_TO_QADDR(done_q_tail); 1724 next_qp = AscReadLramByte(iot, ioh, (q_addr + ASC_SCSIQ_B_FWD)); 1725 1726 if (next_qp != ASC_QLINK_END) { 1727 ASC_PUT_VAR_DONE_QTAIL(iot, ioh, next_qp); 1728 q_addr = ASC_QNO_TO_QADDR(next_qp); 1729 sg_queue_cnt = _AscCopyLramScsiDoneQ(iot, ioh, q_addr, scsiq, 1730 sc->max_dma_count); 1731 AscWriteLramByte(iot, ioh, (q_addr + ASC_SCSIQ_B_STATUS), 1732 (scsiq->q_status & ~(ASC_QS_READY | ASC_QS_ABORTED))); 1733 tid_no = ASC_TIX_TO_TID(scsiq->d2.target_ix); 1734 target_id = ASC_TIX_TO_TARGET_ID(scsiq->d2.target_ix); 1735 if ((scsiq->cntl & ASC_QC_SG_HEAD) != 0) { 1736 sg_q_addr = q_addr; 1737 sg_list_qp = next_qp; 1738 for (q_cnt = 0; q_cnt < sg_queue_cnt; q_cnt++) { 1739 sg_list_qp = AscReadLramByte(iot, ioh, 1740 sg_q_addr + ASC_SCSIQ_B_FWD); 1741 sg_q_addr = ASC_QNO_TO_QADDR(sg_list_qp); 1742 if (sg_list_qp == ASC_QLINK_END) { 1743 AscSetLibErrorCode(sc, ASCQ_ERR_SG_Q_LINKS); 1744 scsiq->d3.done_stat = ASC_QD_WITH_ERROR; 1745 scsiq->d3.host_stat = ASC_QHSTA_D_QDONE_SG_LIST_CORRUPTED; 1746 panic("AscIsrQDone: Corrupted SG list encountered"); 1747 } 1748 AscWriteLramByte(iot, ioh, 1749 sg_q_addr + ASC_SCSIQ_B_STATUS, ASC_QS_FREE); 1750 } 1751 n_q_used = sg_queue_cnt + 1; 1752 ASC_PUT_VAR_DONE_QTAIL(iot, ioh, sg_list_qp); 1753 } 1754 if (sc->queue_full_or_busy & target_id) { 1755 cur_target_qng = AscReadLramByte(iot, ioh, 1756 ASC_QADR_BEG + scsiq->d2.target_ix); 1757 1758 if (cur_target_qng < sc->max_dvc_qng[tid_no]) { 1759 scsi_busy = AscReadLramByte(iot, ioh, ASCV_SCSIBUSY_B); 1760 scsi_busy &= ~target_id; 1761 AscWriteLramByte(iot, ioh, ASCV_SCSIBUSY_B, scsi_busy); 1762 sc->queue_full_or_busy &= ~target_id; 1763 } 1764 } 1765 if (sc->cur_total_qng >= n_q_used) { 1766 sc->cur_total_qng -= n_q_used; 1767 if (sc->cur_dvc_qng[tid_no] != 0) { 1768 sc->cur_dvc_qng[tid_no]--; 1769 } 1770 } else { 1771 AscSetLibErrorCode(sc, ASCQ_ERR_CUR_QNG); 1772 scsiq->d3.done_stat = ASC_QD_WITH_ERROR; 1773 panic("AscIsrQDone: Attempting to free more queues than are active"); 1774 } 1775 1776 if ((scsiq->d2.ccb_ptr == 0UL) || ((scsiq->q_status & ASC_QS_ABORTED) != 0)) { 1777 return (0x11); 1778 } else if (scsiq->q_status == ASC_QS_DONE) { 1779 scsiq->remain_bytes += scsiq->extra_bytes; 1780 1781 if (scsiq->d3.done_stat == ASC_QD_WITH_ERROR) { 1782 if (scsiq->d3.host_stat == ASC_QHSTA_M_DATA_OVER_RUN) { 1783 if ((scsiq->cntl & (ASC_QC_DATA_IN | ASC_QC_DATA_OUT)) == 0) { 1784 scsiq->d3.done_stat = ASC_QD_NO_ERROR; 1785 scsiq->d3.host_stat = ASC_QHSTA_NO_ERROR; 1786 } 1787 } else if (scsiq->d3.host_stat == ASC_QHSTA_M_HUNG_REQ_SCSI_BUS_RESET) { 1788 AscStopChip(iot, ioh); 1789 ASC_SET_CHIP_CONTROL(iot, ioh, (ASC_CC_SCSI_RESET | ASC_CC_HALT)); 1790 DvcDelayNanoSecond(60000); 1791 ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_HALT); 1792 ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_CLR_SCSI_RESET_INT); 1793 ASC_SET_CHIP_STATUS(iot, ioh, 0); 1794 ASC_SET_CHIP_CONTROL(iot, ioh, 0); 1795 } 1796 } 1797 (*asc_isr_callback) (sc, scsiq); 1798 1799 return (1); 1800 } else { 1801 AscSetLibErrorCode(sc, ASCQ_ERR_Q_STATUS); 1802 panic("AscIsrQDone: completed scsiq with unknown status"); 1803 1804 return (0x80); 1805 } 1806 } 1807 return (0); 1808 } 1809 1810 1811 /* 1812 * handle all the conditions that may halt the board 1813 * waiting us to intervene 1814 */ 1815 static void 1816 AscIsrChipHalted(sc) 1817 ASC_SOFTC *sc; 1818 { 1819 bus_space_tag_t iot = sc->sc_iot; 1820 bus_space_handle_t ioh = sc->sc_ioh; 1821 EXT_MSG out_msg; 1822 u_int16_t int_halt_code; 1823 u_int16_t halt_q_addr; 1824 u_int8_t halt_qp; 1825 u_int8_t target_ix; 1826 u_int8_t tag_code; 1827 u_int8_t q_status; 1828 u_int8_t q_cntl; 1829 u_int8_t tid_no; 1830 u_int8_t cur_dvc_qng; 1831 u_int8_t asyn_sdtr; 1832 u_int8_t scsi_status; 1833 u_int8_t sdtr_data; 1834 ASC_SCSI_BIT_ID_TYPE scsi_busy; 1835 ASC_SCSI_BIT_ID_TYPE target_id; 1836 1837 1838 int_halt_code = AscReadLramWord(iot, ioh, ASCV_HALTCODE_W); 1839 1840 halt_qp = AscReadLramByte(iot, ioh, ASCV_CURCDB_B); 1841 halt_q_addr = ASC_QNO_TO_QADDR(halt_qp); 1842 target_ix = AscReadLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_TARGET_IX); 1843 q_cntl = AscReadLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_CNTL); 1844 tid_no = ASC_TIX_TO_TID(target_ix); 1845 target_id = ASC_TID_TO_TARGET_ID(tid_no); 1846 1847 if (sc->pci_fix_asyn_xfer & target_id) { 1848 asyn_sdtr = ASYN_SDTR_DATA_FIX_PCI_REV_AB; 1849 } else { 1850 asyn_sdtr = 0; 1851 } 1852 1853 if (int_halt_code == ASC_HALT_DISABLE_ASYN_USE_SYN_FIX) { 1854 if (sc->pci_fix_asyn_xfer & target_id) { 1855 AscSetChipSDTR(iot, ioh, 0, tid_no); 1856 sc->sdtr_data[tid_no] = 0; 1857 } 1858 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 1859 } else if (int_halt_code == ASC_HALT_ENABLE_ASYN_USE_SYN_FIX) { 1860 if (sc->pci_fix_asyn_xfer & target_id) { 1861 AscSetChipSDTR(iot, ioh, asyn_sdtr, tid_no); 1862 sc->sdtr_data[tid_no] = asyn_sdtr; 1863 } 1864 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 1865 } else if (int_halt_code == ASC_HALT_EXTMSG_IN) { 1866 AscHandleExtMsgIn(sc, halt_q_addr, q_cntl, target_id, 1867 tid_no, asyn_sdtr); 1868 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 1869 } else if (int_halt_code == ASC_HALT_CHK_CONDITION) { 1870 q_cntl |= ASC_QC_REQ_SENSE; 1871 1872 if (sc->init_sdtr & target_id) { 1873 sc->sdtr_done &= ~target_id; 1874 1875 sdtr_data = ASC_GET_MCODE_INIT_SDTR_AT_ID(iot, ioh, tid_no); 1876 q_cntl |= ASC_QC_MSG_OUT; 1877 AscMsgOutSDTR(sc, sc->sdtr_period_tbl[(sdtr_data >> 4) & 1878 (sc->max_sdtr_index - 1)], 1879 (sdtr_data & ASC_SYN_MAX_OFFSET)); 1880 } 1881 AscWriteLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_CNTL, q_cntl); 1882 1883 tag_code = AscReadLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_TAG_CODE); 1884 tag_code &= 0xDC; 1885 1886 if ((sc->pci_fix_asyn_xfer & target_id) && 1887 !(sc->pci_fix_asyn_xfer_always & target_id)) { 1888 tag_code |= (ASC_TAG_FLAG_DISABLE_DISCONNECT | 1889 ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX); 1890 } 1891 AscWriteLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_TAG_CODE, tag_code); 1892 1893 q_status = AscReadLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_STATUS); 1894 q_status |= ASC_QS_READY | ASC_QS_BUSY; 1895 1896 AscWriteLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_STATUS, q_status); 1897 1898 scsi_busy = AscReadLramByte(iot, ioh, ASCV_SCSIBUSY_B); 1899 scsi_busy &= ~target_id; 1900 AscWriteLramByte(iot, ioh, ASCV_SCSIBUSY_B, scsi_busy); 1901 1902 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 1903 } else if (int_halt_code == ASC_HALT_SDTR_REJECTED) { 1904 AscMemWordCopyFromLram(iot, ioh, ASCV_MSGOUT_BEG, 1905 (u_int16_t *) & out_msg, sizeof(EXT_MSG) >> 1); 1906 1907 if ((out_msg.msg_type == MS_EXTEND) && 1908 (out_msg.msg_len == MS_SDTR_LEN) && 1909 (out_msg.msg_req == MS_SDTR_CODE)) { 1910 sc->init_sdtr &= ~target_id; 1911 sc->sdtr_done &= ~target_id; 1912 AscSetChipSDTR(iot, ioh, asyn_sdtr, tid_no); 1913 sc->sdtr_data[tid_no] = asyn_sdtr; 1914 } 1915 q_cntl &= ~ASC_QC_MSG_OUT; 1916 AscWriteLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_CNTL, q_cntl); 1917 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 1918 } else if (int_halt_code == ASC_HALT_SS_QUEUE_FULL) { 1919 scsi_status = AscReadLramByte(iot, ioh, 1920 halt_q_addr + ASC_SCSIQ_SCSI_STATUS); 1921 cur_dvc_qng = AscReadLramByte(iot, ioh, target_ix + ASC_QADR_BEG); 1922 1923 if ((cur_dvc_qng > 0) && (sc->cur_dvc_qng[tid_no] > 0)) { 1924 scsi_busy = AscReadLramByte(iot, ioh, ASCV_SCSIBUSY_B); 1925 scsi_busy |= target_id; 1926 AscWriteLramByte(iot, ioh, ASCV_SCSIBUSY_B, scsi_busy); 1927 sc->queue_full_or_busy |= target_id; 1928 1929 if (scsi_status == SS_QUEUE_FULL) { 1930 if (cur_dvc_qng > ASC_MIN_TAGGED_CMD) { 1931 cur_dvc_qng -= 1; 1932 sc->max_dvc_qng[tid_no] = cur_dvc_qng; 1933 1934 AscWriteLramByte(iot, ioh, 1935 tid_no + ASCV_MAX_DVC_QNG_BEG, cur_dvc_qng); 1936 1937 #if ASC_QUEUE_FLOW_CONTROL 1938 if ((sc->device[tid_no] != NULL) && 1939 (sc->device[tid_no]->queue_curr_depth > cur_dvc_qng)) { 1940 sc->device[tid_no]->queue_curr_depth = cur_dvc_qng; 1941 } 1942 #endif /* ASC_QUEUE_FLOW_CONTROL */ 1943 } 1944 } 1945 } 1946 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 1947 } 1948 return; 1949 } 1950 1951 1952 static int 1953 AscWaitTixISRDone(sc, target_ix) 1954 ASC_SOFTC *sc; 1955 u_int8_t target_ix; 1956 { 1957 u_int8_t cur_req; 1958 u_int8_t tid_no; 1959 int i = 0; 1960 1961 tid_no = ASC_TIX_TO_TID(target_ix); 1962 while (i++ < 10) { 1963 if ((cur_req = sc->cur_dvc_qng[tid_no]) == 0) 1964 break; 1965 1966 DvcSleepMilliSecond(1000L); 1967 if (sc->cur_dvc_qng[tid_no] == cur_req) 1968 break; 1969 } 1970 return (1); 1971 } 1972 1973 static int 1974 AscWaitISRDone(sc) 1975 ASC_SOFTC *sc; 1976 { 1977 int tid; 1978 1979 for (tid = 0; tid <= ASC_MAX_TID; tid++) 1980 AscWaitTixISRDone(sc, ASC_TID_TO_TIX(tid)); 1981 1982 return (1); 1983 } 1984 1985 1986 static u_int8_t 1987 _AscCopyLramScsiDoneQ(iot, ioh, q_addr, scsiq, max_dma_count) 1988 bus_space_tag_t iot; 1989 bus_space_handle_t ioh; 1990 u_int16_t q_addr; 1991 ASC_QDONE_INFO *scsiq; 1992 u_int32_t max_dma_count; 1993 { 1994 u_int16_t _val; 1995 u_int8_t sg_queue_cnt; 1996 1997 AscGetQDoneInfo(iot, ioh, q_addr + ASC_SCSIQ_DONE_INFO_BEG, scsiq); 1998 1999 _val = AscReadLramWord(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS); 2000 scsiq->q_status = LO_BYTE(_val); 2001 scsiq->q_no = HI_BYTE(_val); 2002 _val = AscReadLramWord(iot, ioh, q_addr + ASC_SCSIQ_B_CNTL); 2003 scsiq->cntl = LO_BYTE(_val); 2004 sg_queue_cnt = HI_BYTE(_val); 2005 _val = AscReadLramWord(iot, ioh, q_addr + ASC_SCSIQ_B_SENSE_LEN); 2006 scsiq->sense_len = LO_BYTE(_val); 2007 scsiq->extra_bytes = HI_BYTE(_val); 2008 scsiq->remain_bytes = AscReadLramWord(iot, ioh, 2009 q_addr + ASC_SCSIQ_DW_REMAIN_XFER_CNT); 2010 scsiq->remain_bytes &= max_dma_count; 2011 2012 return (sg_queue_cnt); 2013 } 2014 2015 2016 static void 2017 AscGetQDoneInfo(iot, ioh, addr, scsiq) 2018 bus_space_tag_t iot; 2019 bus_space_handle_t ioh; 2020 u_int16_t addr; 2021 ASC_QDONE_INFO *scsiq; 2022 { 2023 u_int16_t val; 2024 2025 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr); 2026 2027 val = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 2028 scsiq->d2.ccb_ptr = MAKELONG(val, ASC_GET_CHIP_LRAM_DATA(iot, ioh)); 2029 val = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 2030 scsiq->d2.target_ix = LO_BYTE(val); 2031 scsiq->d2.flag = HI_BYTE(val); 2032 val = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 2033 scsiq->d2.cdb_len = LO_BYTE(val); 2034 scsiq->d2.tag_code = HI_BYTE(val); 2035 scsiq->d2.vm_id = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 2036 2037 val = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 2038 scsiq->d3.done_stat = LO_BYTE(val); 2039 scsiq->d3.host_stat = HI_BYTE(val); 2040 val = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 2041 scsiq->d3.scsi_stat = LO_BYTE(val); 2042 scsiq->d3.scsi_msg = HI_BYTE(val); 2043 } 2044 2045 2046 static void 2047 AscToggleIRQAct(iot, ioh) 2048 bus_space_tag_t iot; 2049 bus_space_handle_t ioh; 2050 { 2051 2052 ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_IRQ_ACT); 2053 ASC_SET_CHIP_STATUS(iot, ioh, 0); 2054 } 2055 2056 2057 static void 2058 AscDisableInterrupt(iot, ioh) 2059 bus_space_tag_t iot; 2060 bus_space_handle_t ioh; 2061 { 2062 u_int16_t cfg; 2063 2064 cfg = ASC_GET_CHIP_CFG_LSW(iot, ioh); 2065 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg & (~ASC_CFG0_HOST_INT_ON)); 2066 } 2067 2068 2069 static void 2070 AscEnableInterrupt(iot, ioh) 2071 bus_space_tag_t iot; 2072 bus_space_handle_t ioh; 2073 { 2074 u_int16_t cfg; 2075 2076 cfg = ASC_GET_CHIP_CFG_LSW(iot, ioh); 2077 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg | ASC_CFG0_HOST_INT_ON); 2078 } 2079 2080 2081 static u_int8_t 2082 AscGetChipIRQ(iot, ioh, bus_type) 2083 bus_space_tag_t iot; 2084 bus_space_handle_t ioh; 2085 u_int16_t bus_type; 2086 { 2087 u_int16_t cfg_lsw; 2088 u_int8_t chip_irq; 2089 2090 2091 if (bus_type & ASC_IS_EISA) { 2092 /* 2093 * cfg_lsw = AscGetEisaChipCfg(iot, ioh); chip_irq = 2094 * ((cfg_lsw >> 8) & 0x07) + 10; if((chip_irq == 13) || 2095 * (chip_irq > 15)) return (0); return(chip_irq); 2096 */ 2097 } 2098 if ((bus_type & ASC_IS_VL) != 0) { 2099 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh); 2100 chip_irq = (cfg_lsw >> 2) & 0x07; 2101 if ((chip_irq == 0) || 2102 (chip_irq == 4) || 2103 (chip_irq == 7)) { 2104 return (0); 2105 } 2106 return (chip_irq + (ASC_MIN_IRQ_NO - 1)); 2107 } 2108 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh); 2109 chip_irq = (cfg_lsw >> 2) & 0x03; 2110 if (chip_irq == 3) 2111 chip_irq += 2; 2112 return (chip_irq + ASC_MIN_IRQ_NO); 2113 } 2114 2115 2116 static u_int8_t 2117 AscSetChipIRQ(iot, ioh, irq_no, bus_type) 2118 bus_space_tag_t iot; 2119 bus_space_handle_t ioh; 2120 u_int8_t irq_no; 2121 u_int16_t bus_type; 2122 { 2123 u_int16_t cfg_lsw; 2124 2125 2126 if (bus_type & ASC_IS_VL) { 2127 if (irq_no) { 2128 if ((irq_no < ASC_MIN_IRQ_NO) || (irq_no > ASC_MAX_IRQ_NO)) 2129 irq_no = 0; 2130 else 2131 irq_no -= ASC_MIN_IRQ_NO - 1; 2132 } 2133 2134 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0xFFE3; 2135 cfg_lsw |= 0x0010; 2136 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg_lsw); 2137 AscToggleIRQAct(iot, ioh); 2138 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0xFFE0; 2139 cfg_lsw |= (irq_no & 0x07) << 2; 2140 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg_lsw); 2141 AscToggleIRQAct(iot, ioh); 2142 2143 return (AscGetChipIRQ(iot, ioh, bus_type)); 2144 } 2145 if (bus_type & ASC_IS_ISA) { 2146 if (irq_no == 15) 2147 irq_no -= 2; 2148 irq_no -= ASC_MIN_IRQ_NO; 2149 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0xFFF3; 2150 cfg_lsw |= (irq_no & 0x03) << 2; 2151 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg_lsw); 2152 2153 return (AscGetChipIRQ(iot, ioh, bus_type)); 2154 } 2155 return (0); 2156 } 2157 2158 2159 static void 2160 AscAckInterrupt(iot, ioh) 2161 bus_space_tag_t iot; 2162 bus_space_handle_t ioh; 2163 { 2164 u_int8_t host_flag; 2165 u_int8_t risc_flag; 2166 u_int16_t loop; 2167 2168 2169 loop = 0; 2170 do { 2171 risc_flag = AscReadLramByte(iot, ioh, ASCV_RISC_FLAG_B); 2172 if (loop++ > 0x7FFF) 2173 break; 2174 } while ((risc_flag & ASC_RISC_FLAG_GEN_INT) != 0); 2175 2176 host_flag = AscReadLramByte(iot, ioh, ASCV_HOST_FLAG_B) & 2177 (~ASC_HOST_FLAG_ACK_INT); 2178 AscWriteLramByte(iot, ioh, ASCV_HOST_FLAG_B, 2179 host_flag | ASC_HOST_FLAG_ACK_INT); 2180 ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_INT_ACK); 2181 2182 loop = 0; 2183 while (ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_INT_PENDING) { 2184 ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_INT_ACK); 2185 if (loop++ > 3) 2186 break; 2187 } 2188 2189 AscWriteLramByte(iot, ioh, ASCV_HOST_FLAG_B, host_flag); 2190 } 2191 2192 2193 static u_int32_t 2194 AscGetMaxDmaCount(bus_type) 2195 u_int16_t bus_type; 2196 { 2197 if (bus_type & ASC_IS_ISA) 2198 return (ASC_MAX_ISA_DMA_COUNT); 2199 else if (bus_type & (ASC_IS_EISA | ASC_IS_VL)) 2200 return (ASC_MAX_VL_DMA_COUNT); 2201 return (ASC_MAX_PCI_DMA_COUNT); 2202 } 2203 2204 2205 static u_int16_t 2206 AscGetIsaDmaChannel(iot, ioh) 2207 bus_space_tag_t iot; 2208 bus_space_handle_t ioh; 2209 { 2210 u_int16_t channel; 2211 2212 channel = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0x0003; 2213 if (channel == 0x03) 2214 return (0); 2215 else if (channel == 0x00) 2216 return (7); 2217 return (channel + 4); 2218 } 2219 2220 2221 static u_int16_t 2222 AscSetIsaDmaChannel(iot, ioh, dma_channel) 2223 bus_space_tag_t iot; 2224 bus_space_handle_t ioh; 2225 u_int16_t dma_channel; 2226 { 2227 u_int16_t cfg_lsw; 2228 u_int8_t value; 2229 2230 if ((dma_channel >= 5) && (dma_channel <= 7)) { 2231 if (dma_channel == 7) 2232 value = 0x00; 2233 else 2234 value = dma_channel - 4; 2235 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0xFFFC; 2236 cfg_lsw |= value; 2237 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg_lsw); 2238 return (AscGetIsaDmaChannel(iot, ioh)); 2239 } 2240 return (0); 2241 } 2242 2243 2244 static u_int8_t 2245 AscGetIsaDmaSpeed(iot, ioh) 2246 bus_space_tag_t iot; 2247 bus_space_handle_t ioh; 2248 { 2249 u_int8_t speed_value; 2250 2251 AscSetBank(iot, ioh, 1); 2252 speed_value = ASC_READ_CHIP_DMA_SPEED(iot, ioh); 2253 speed_value &= 0x07; 2254 AscSetBank(iot, ioh, 0); 2255 return (speed_value); 2256 } 2257 2258 2259 static u_int8_t 2260 AscSetIsaDmaSpeed(iot, ioh, speed_value) 2261 bus_space_tag_t iot; 2262 bus_space_handle_t ioh; 2263 u_int8_t speed_value; 2264 { 2265 speed_value &= 0x07; 2266 AscSetBank(iot, ioh, 1); 2267 ASC_WRITE_CHIP_DMA_SPEED(iot, ioh, speed_value); 2268 AscSetBank(iot, ioh, 0); 2269 return (AscGetIsaDmaSpeed(iot, ioh)); 2270 } 2271 2272 2273 /******************************************************************************/ 2274 /* Messages routines */ 2275 /******************************************************************************/ 2276 2277 2278 static void 2279 AscHandleExtMsgIn(sc, halt_q_addr, q_cntl, target_id, tid_no, asyn_sdtr) 2280 ASC_SOFTC *sc; 2281 u_int16_t halt_q_addr; 2282 u_int8_t q_cntl; 2283 ASC_SCSI_BIT_ID_TYPE target_id; 2284 int tid_no; 2285 u_int8_t asyn_sdtr; 2286 { 2287 bus_space_tag_t iot = sc->sc_iot; 2288 bus_space_handle_t ioh = sc->sc_ioh; 2289 EXT_MSG ext_msg; 2290 u_int8_t sdtr_data; 2291 int sdtr_accept; 2292 2293 2294 AscMemWordCopyFromLram(iot, ioh, ASCV_MSGIN_BEG, 2295 (u_int16_t *) & ext_msg, sizeof(EXT_MSG) >> 1); 2296 2297 if (ext_msg.msg_type == MS_EXTEND && 2298 ext_msg.msg_req == MS_SDTR_CODE && 2299 ext_msg.msg_len == MS_SDTR_LEN) { 2300 sdtr_accept = TRUE; 2301 2302 if (ext_msg.req_ack_offset > ASC_SYN_MAX_OFFSET) { 2303 sdtr_accept = FALSE; 2304 ext_msg.req_ack_offset = ASC_SYN_MAX_OFFSET; 2305 } 2306 if ((ext_msg.xfer_period < 2307 sc->sdtr_period_tbl[sc->host_init_sdtr_index]) || 2308 (ext_msg.xfer_period > 2309 sc->sdtr_period_tbl[sc->max_sdtr_index])) { 2310 sdtr_accept = FALSE; 2311 ext_msg.xfer_period = sc->sdtr_period_tbl[sc->host_init_sdtr_index]; 2312 } 2313 if (sdtr_accept) { 2314 sdtr_data = AscCalSDTRData(sc, ext_msg.xfer_period, 2315 ext_msg.req_ack_offset); 2316 if (sdtr_data == 0xFF) { 2317 q_cntl |= ASC_QC_MSG_OUT; 2318 sc->init_sdtr &= ~target_id; 2319 sc->sdtr_done &= ~target_id; 2320 AscSetChipSDTR(iot, ioh, asyn_sdtr, tid_no); 2321 sc->sdtr_data[tid_no] = asyn_sdtr; 2322 } 2323 } 2324 if (ext_msg.req_ack_offset == 0) { 2325 q_cntl &= ~ASC_QC_MSG_OUT; 2326 sc->init_sdtr &= ~target_id; 2327 sc->sdtr_done &= ~target_id; 2328 AscSetChipSDTR(iot, ioh, asyn_sdtr, tid_no); 2329 } else { 2330 if (sdtr_accept && (q_cntl & ASC_QC_MSG_OUT)) { 2331 q_cntl &= ~ASC_QC_MSG_OUT; 2332 sc->sdtr_done |= target_id; 2333 sc->init_sdtr |= target_id; 2334 sc->pci_fix_asyn_xfer &= ~target_id; 2335 sdtr_data = AscCalSDTRData(sc, ext_msg.xfer_period, 2336 ext_msg.req_ack_offset); 2337 AscSetChipSDTR(iot, ioh, sdtr_data, tid_no); 2338 sc->sdtr_data[tid_no] = sdtr_data; 2339 } else { 2340 q_cntl |= ASC_QC_MSG_OUT; 2341 AscMsgOutSDTR(sc, ext_msg.xfer_period, 2342 ext_msg.req_ack_offset); 2343 sc->pci_fix_asyn_xfer &= ~target_id; 2344 sdtr_data = AscCalSDTRData(sc, ext_msg.xfer_period, 2345 ext_msg.req_ack_offset); 2346 AscSetChipSDTR(iot, ioh, sdtr_data, tid_no); 2347 sc->sdtr_data[tid_no] = sdtr_data; 2348 sc->sdtr_done |= target_id; 2349 sc->init_sdtr |= target_id; 2350 } 2351 } 2352 } else if (ext_msg.msg_type == MS_EXTEND && 2353 ext_msg.msg_req == MS_WDTR_CODE && 2354 ext_msg.msg_len == MS_WDTR_LEN) { 2355 ext_msg.wdtr_width = 0; 2356 AscMemWordCopyToLram(iot, ioh, ASCV_MSGOUT_BEG, 2357 (u_int16_t *) & ext_msg, sizeof(EXT_MSG) >> 1); 2358 q_cntl |= ASC_QC_MSG_OUT; 2359 } else { 2360 ext_msg.msg_type = M1_MSG_REJECT; 2361 AscMemWordCopyToLram(iot, ioh, ASCV_MSGOUT_BEG, 2362 (u_int16_t *) & ext_msg, sizeof(EXT_MSG) >> 1); 2363 q_cntl |= ASC_QC_MSG_OUT; 2364 } 2365 2366 AscWriteLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_CNTL, q_cntl); 2367 } 2368 2369 2370 static u_int8_t 2371 AscMsgOutSDTR(sc, sdtr_period, sdtr_offset) 2372 ASC_SOFTC *sc; 2373 u_int8_t sdtr_period; 2374 u_int8_t sdtr_offset; 2375 { 2376 bus_space_tag_t iot = sc->sc_iot; 2377 bus_space_handle_t ioh = sc->sc_ioh; 2378 EXT_MSG sdtr_buf; 2379 u_int8_t sdtr_period_index; 2380 2381 2382 sdtr_buf.msg_type = MS_EXTEND; 2383 sdtr_buf.msg_len = MS_SDTR_LEN; 2384 sdtr_buf.msg_req = MS_SDTR_CODE; 2385 sdtr_buf.xfer_period = sdtr_period; 2386 sdtr_offset &= ASC_SYN_MAX_OFFSET; 2387 sdtr_buf.req_ack_offset = sdtr_offset; 2388 if ((sdtr_period_index = AscGetSynPeriodIndex(sc, sdtr_period)) <= 2389 sc->max_sdtr_index) { 2390 AscMemWordCopyToLram(iot, ioh, ASCV_MSGOUT_BEG, 2391 (u_int16_t *) & sdtr_buf, sizeof(EXT_MSG) >> 1); 2392 return ((sdtr_period_index << 4) | sdtr_offset); 2393 } else { 2394 sdtr_buf.req_ack_offset = 0; 2395 AscMemWordCopyToLram(iot, ioh, ASCV_MSGOUT_BEG, 2396 (u_int16_t *) & sdtr_buf, sizeof(EXT_MSG) >> 1); 2397 return (0); 2398 } 2399 } 2400 2401 2402 /******************************************************************************/ 2403 /* SDTR routines */ 2404 /******************************************************************************/ 2405 2406 2407 static void 2408 AscSetChipSDTR(iot, ioh, sdtr_data, tid_no) 2409 bus_space_tag_t iot; 2410 bus_space_handle_t ioh; 2411 u_int8_t sdtr_data; 2412 u_int8_t tid_no; 2413 { 2414 AscSetChipSynRegAtID(iot, ioh, tid_no, sdtr_data); 2415 AscWriteLramByte(iot, ioh, tid_no + ASCV_SDTR_DONE_BEG, sdtr_data); 2416 } 2417 2418 2419 static u_int8_t 2420 AscCalSDTRData(sc, sdtr_period, syn_offset) 2421 ASC_SOFTC *sc; 2422 u_int8_t sdtr_period; 2423 u_int8_t syn_offset; 2424 { 2425 u_int8_t byte; 2426 u_int8_t sdtr_period_ix; 2427 2428 sdtr_period_ix = AscGetSynPeriodIndex(sc, sdtr_period); 2429 if (sdtr_period_ix > sc->max_sdtr_index) 2430 return (0xFF); 2431 2432 byte = (sdtr_period_ix << 4) | (syn_offset & ASC_SYN_MAX_OFFSET); 2433 return (byte); 2434 } 2435 2436 2437 static u_int8_t 2438 AscGetSynPeriodIndex(sc, syn_time) 2439 ASC_SOFTC *sc; 2440 u_int8_t syn_time; 2441 { 2442 u_int8_t *period_table; 2443 int max_index; 2444 int min_index; 2445 int i; 2446 2447 period_table = sc->sdtr_period_tbl; 2448 max_index = sc->max_sdtr_index; 2449 min_index = sc->host_init_sdtr_index; 2450 if ((syn_time <= period_table[max_index])) { 2451 for (i = min_index; i < (max_index - 1); i++) { 2452 if (syn_time <= period_table[i]) 2453 return (i); 2454 } 2455 2456 return (max_index); 2457 } else 2458 return (max_index + 1); 2459 } 2460 2461 2462 /******************************************************************************/ 2463 /* Queue routines */ 2464 /******************************************************************************/ 2465 2466 /* 2467 * Send a command to the board 2468 */ 2469 int 2470 AscExeScsiQueue(sc, scsiq) 2471 ASC_SOFTC *sc; 2472 ASC_SCSI_Q *scsiq; 2473 { 2474 bus_space_tag_t iot = sc->sc_iot; 2475 bus_space_handle_t ioh = sc->sc_ioh; 2476 ASC_SG_HEAD *sg_head = scsiq->sg_head; 2477 int retval; 2478 int n_q_required; 2479 int disable_syn_offset_one_fix; 2480 int i; 2481 u_int32_t addr; 2482 u_int16_t sg_entry_cnt = 0; 2483 u_int16_t sg_entry_cnt_minus_one = 0; 2484 u_int8_t target_ix; 2485 u_int8_t tid_no; 2486 u_int8_t sdtr_data; 2487 u_int8_t extra_bytes; 2488 u_int8_t scsi_cmd; 2489 u_int32_t data_cnt; 2490 2491 2492 scsiq->q1.q_no = 0; 2493 if ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0) 2494 scsiq->q1.extra_bytes = 0; 2495 2496 retval = ASC_BUSY; 2497 target_ix = scsiq->q2.target_ix; 2498 tid_no = ASC_TIX_TO_TID(target_ix); 2499 n_q_required = 1; 2500 2501 if (scsiq->cdbptr[0] == SCSICMD_RequestSense) 2502 if ((sc->init_sdtr & scsiq->q1.target_id) != 0) { 2503 sc->sdtr_done &= ~scsiq->q1.target_id; 2504 sdtr_data = ASC_GET_MCODE_INIT_SDTR_AT_ID(iot, ioh, tid_no); 2505 AscMsgOutSDTR(sc, sc->sdtr_period_tbl[(sdtr_data >> 4) & 2506 (sc->max_sdtr_index - 1)], 2507 sdtr_data & ASC_SYN_MAX_OFFSET); 2508 scsiq->q1.cntl |= (ASC_QC_MSG_OUT | ASC_QC_URGENT); 2509 } 2510 /* 2511 * if there is just one segment into S/G list then 2512 * map it as it was a single request, filling 2513 * data_addr and data_cnt of ASC_SCSIQ structure. 2514 */ 2515 if ((scsiq->q1.cntl & ASC_QC_SG_HEAD) != 0) { 2516 sg_entry_cnt = sg_head->entry_cnt; 2517 2518 if (sg_entry_cnt < 1) 2519 panic("AscExeScsiQueue: Queue with QC_SG_HEAD set but %d segs.", 2520 sg_entry_cnt); 2521 2522 if (sg_entry_cnt > ASC_MAX_SG_LIST) 2523 panic("AscExeScsiQueue: Queue with too many segs."); 2524 2525 if (sg_entry_cnt == 1) { 2526 scsiq->q1.data_addr = sg_head->sg_list[0].addr; 2527 scsiq->q1.data_cnt = sg_head->sg_list[0].bytes; 2528 scsiq->q1.cntl &= ~(ASC_QC_SG_HEAD | ASC_QC_SG_SWAP_QUEUE); 2529 } 2530 sg_entry_cnt_minus_one = sg_entry_cnt - 1; 2531 } 2532 scsi_cmd = scsiq->cdbptr[0]; 2533 disable_syn_offset_one_fix = FALSE; 2534 if ((sc->pci_fix_asyn_xfer & scsiq->q1.target_id) && 2535 !(sc->pci_fix_asyn_xfer_always & scsiq->q1.target_id)) { 2536 if (scsiq->q1.cntl & ASC_QC_SG_HEAD) { 2537 data_cnt = 0; 2538 for (i = 0; i < sg_entry_cnt; i++) 2539 data_cnt += sg_head->sg_list[i].bytes; 2540 } else { 2541 data_cnt = scsiq->q1.data_cnt; 2542 } 2543 2544 if (data_cnt != 0ul) { 2545 if (data_cnt < 512ul) { 2546 disable_syn_offset_one_fix = TRUE; 2547 } else { 2548 if (scsi_cmd == SCSICMD_Inquiry || 2549 scsi_cmd == SCSICMD_RequestSense || 2550 scsi_cmd == SCSICMD_ReadCapacity || 2551 scsi_cmd == SCSICMD_ReadTOC || 2552 scsi_cmd == SCSICMD_ModeSelect6 || 2553 scsi_cmd == SCSICMD_ModeSense6 || 2554 scsi_cmd == SCSICMD_ModeSelect10 || 2555 scsi_cmd == SCSICMD_ModeSense10) { 2556 disable_syn_offset_one_fix = TRUE; 2557 } 2558 } 2559 } 2560 } 2561 if (disable_syn_offset_one_fix) { 2562 scsiq->q2.tag_code &= ~M2_QTAG_MSG_SIMPLE; 2563 scsiq->q2.tag_code |= (ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX | 2564 ASC_TAG_FLAG_DISABLE_DISCONNECT); 2565 } else { 2566 scsiq->q2.tag_code &= 0x23; 2567 } 2568 2569 if ((scsiq->q1.cntl & ASC_QC_SG_HEAD) != 0) { 2570 if (sc->bug_fix_cntl) { 2571 if (sc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) { 2572 if ((scsi_cmd == SCSICMD_Read6) || (scsi_cmd == SCSICMD_Read10)) { 2573 addr = sg_head->sg_list[sg_entry_cnt_minus_one].addr + 2574 sg_head->sg_list[sg_entry_cnt_minus_one].bytes; 2575 extra_bytes = addr & 0x0003; 2576 if ((extra_bytes != 0) && 2577 ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0)) { 2578 scsiq->q2.tag_code |= ASC_TAG_FLAG_EXTRA_BYTES; 2579 scsiq->q1.extra_bytes = extra_bytes; 2580 sg_head->sg_list[sg_entry_cnt_minus_one].bytes -= 2581 extra_bytes; 2582 } 2583 } 2584 } 2585 } 2586 sg_head->entry_to_copy = sg_head->entry_cnt; 2587 n_q_required = AscSgListToQueue(sg_entry_cnt); 2588 if ((AscGetNumOfFreeQueue(sc, target_ix, n_q_required) >= n_q_required) 2589 || ((scsiq->q1.cntl & ASC_QC_URGENT) != 0)) { 2590 retval = AscSendScsiQueue(sc, scsiq, n_q_required); 2591 } 2592 } else { 2593 if (sc->bug_fix_cntl) { 2594 if (sc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) { 2595 if ((scsi_cmd == SCSICMD_Read6) || (scsi_cmd == SCSICMD_Read10)) { 2596 addr = scsiq->q1.data_addr + scsiq->q1.data_cnt; 2597 extra_bytes = addr & 0x0003; 2598 if ((extra_bytes != 0) && 2599 ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0)) { 2600 if ((scsiq->q1.data_cnt & 0x01FF) == 0) { 2601 scsiq->q2.tag_code |= ASC_TAG_FLAG_EXTRA_BYTES; 2602 scsiq->q1.data_cnt -= extra_bytes; 2603 scsiq->q1.extra_bytes = extra_bytes; 2604 } 2605 } 2606 } 2607 } 2608 } 2609 n_q_required = 1; 2610 if ((AscGetNumOfFreeQueue(sc, target_ix, 1) >= 1) || 2611 ((scsiq->q1.cntl & ASC_QC_URGENT) != 0)) { 2612 retval = AscSendScsiQueue(sc, scsiq, n_q_required); 2613 } 2614 } 2615 2616 return (retval); 2617 } 2618 2619 2620 static int 2621 AscSendScsiQueue(sc, scsiq, n_q_required) 2622 ASC_SOFTC *sc; 2623 ASC_SCSI_Q *scsiq; 2624 u_int8_t n_q_required; 2625 { 2626 bus_space_tag_t iot = sc->sc_iot; 2627 bus_space_handle_t ioh = sc->sc_ioh; 2628 u_int8_t free_q_head; 2629 u_int8_t next_qp; 2630 u_int8_t tid_no; 2631 u_int8_t target_ix; 2632 int retval; 2633 2634 2635 target_ix = scsiq->q2.target_ix; 2636 tid_no = ASC_TIX_TO_TID(target_ix); 2637 retval = ASC_BUSY; 2638 free_q_head = ASC_GET_VAR_FREE_QHEAD(iot, ioh); 2639 2640 if ((next_qp = AscAllocMultipleFreeQueue(iot, ioh, free_q_head, n_q_required)) 2641 != ASC_QLINK_END) { 2642 if (n_q_required > 1) { 2643 sc->last_q_shortage = 0; 2644 scsiq->sg_head->queue_cnt = n_q_required - 1; 2645 } 2646 scsiq->q1.q_no = free_q_head; 2647 2648 if ((retval = AscPutReadySgListQueue(sc, scsiq, free_q_head)) == ASC_NOERROR) { 2649 ASC_PUT_VAR_FREE_QHEAD(iot, ioh, next_qp); 2650 sc->cur_total_qng += n_q_required; 2651 sc->cur_dvc_qng[tid_no]++; 2652 } 2653 } 2654 return (retval); 2655 } 2656 2657 2658 static int 2659 AscPutReadySgListQueue(sc, scsiq, q_no) 2660 ASC_SOFTC *sc; 2661 ASC_SCSI_Q *scsiq; 2662 u_int8_t q_no; 2663 { 2664 bus_space_tag_t iot = sc->sc_iot; 2665 bus_space_handle_t ioh = sc->sc_ioh; 2666 int retval; 2667 int i; 2668 ASC_SG_HEAD *sg_head; 2669 ASC_SG_LIST_Q scsi_sg_q; 2670 u_int32_t saved_data_addr; 2671 u_int32_t saved_data_cnt; 2672 u_int16_t sg_list_dwords; 2673 u_int16_t sg_index; 2674 u_int16_t sg_entry_cnt; 2675 u_int16_t q_addr; 2676 u_int8_t next_qp; 2677 2678 2679 saved_data_addr = scsiq->q1.data_addr; 2680 saved_data_cnt = scsiq->q1.data_cnt; 2681 2682 if ((sg_head = scsiq->sg_head) != 0) { 2683 scsiq->q1.data_addr = sg_head->sg_list[0].addr; 2684 scsiq->q1.data_cnt = sg_head->sg_list[0].bytes; 2685 sg_entry_cnt = sg_head->entry_cnt - 1; 2686 if (sg_entry_cnt != 0) { 2687 q_addr = ASC_QNO_TO_QADDR(q_no); 2688 sg_index = 1; 2689 scsiq->q1.sg_queue_cnt = sg_head->queue_cnt; 2690 scsi_sg_q.sg_head_qp = q_no; 2691 scsi_sg_q.cntl = ASC_QCSG_SG_XFER_LIST; 2692 2693 for (i = 0; i < sg_head->queue_cnt; i++) { 2694 scsi_sg_q.seq_no = i + 1; 2695 if (sg_entry_cnt > ASC_SG_LIST_PER_Q) { 2696 sg_list_dwords = ASC_SG_LIST_PER_Q * 2; 2697 sg_entry_cnt -= ASC_SG_LIST_PER_Q; 2698 if (i == 0) { 2699 scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q; 2700 scsi_sg_q.sg_cur_list_cnt = ASC_SG_LIST_PER_Q; 2701 } else { 2702 scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q - 1; 2703 scsi_sg_q.sg_cur_list_cnt = ASC_SG_LIST_PER_Q - 1; 2704 } 2705 } else { 2706 scsi_sg_q.cntl |= ASC_QCSG_SG_XFER_END; 2707 sg_list_dwords = sg_entry_cnt << 1; 2708 if (i == 0) { 2709 scsi_sg_q.sg_list_cnt = sg_entry_cnt; 2710 scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt; 2711 } else { 2712 scsi_sg_q.sg_list_cnt = sg_entry_cnt - 1; 2713 scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt - 1; 2714 } 2715 2716 sg_entry_cnt = 0; 2717 } 2718 2719 next_qp = AscReadLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_FWD); 2720 scsi_sg_q.q_no = next_qp; 2721 q_addr = ASC_QNO_TO_QADDR(next_qp); 2722 2723 /* 2724 * Tell the board how many entries are in the S/G list 2725 */ 2726 AscMemWordCopyToLram(iot, ioh, q_addr + ASC_SCSIQ_SGHD_CPY_BEG, 2727 (u_int16_t *) & scsi_sg_q, 2728 sizeof(ASC_SG_LIST_Q) >> 1); 2729 /* 2730 * Tell the board the addresses of the S/G list segments 2731 */ 2732 AscMemDWordCopyToLram(iot, ioh, q_addr + ASC_SGQ_LIST_BEG, 2733 (u_int32_t *) & sg_head->sg_list[sg_index], 2734 sg_list_dwords); 2735 sg_index += ASC_SG_LIST_PER_Q; 2736 } 2737 } 2738 } 2739 retval = AscPutReadyQueue(sc, scsiq, q_no); 2740 scsiq->q1.data_addr = saved_data_addr; 2741 scsiq->q1.data_cnt = saved_data_cnt; 2742 return (retval); 2743 } 2744 2745 2746 static int 2747 AscPutReadyQueue(sc, scsiq, q_no) 2748 ASC_SOFTC *sc; 2749 ASC_SCSI_Q *scsiq; 2750 u_int8_t q_no; 2751 { 2752 bus_space_tag_t iot = sc->sc_iot; 2753 bus_space_handle_t ioh = sc->sc_ioh; 2754 u_int16_t q_addr; 2755 u_int8_t tid_no; 2756 u_int8_t sdtr_data; 2757 u_int8_t syn_period_ix; 2758 u_int8_t syn_offset; 2759 2760 2761 if (((sc->init_sdtr & scsiq->q1.target_id) != 0) && 2762 ((sc->sdtr_done & scsiq->q1.target_id) == 0)) { 2763 tid_no = ASC_TIX_TO_TID(scsiq->q2.target_ix); 2764 sdtr_data = ASC_GET_MCODE_INIT_SDTR_AT_ID(iot, ioh, tid_no); 2765 syn_period_ix = (sdtr_data >> 4) & (sc->max_sdtr_index - 1); 2766 syn_offset = sdtr_data & ASC_SYN_MAX_OFFSET; 2767 AscMsgOutSDTR(sc, sc->sdtr_period_tbl[syn_period_ix], syn_offset); 2768 scsiq->q1.cntl |= ASC_QC_MSG_OUT; 2769 } 2770 q_addr = ASC_QNO_TO_QADDR(q_no); 2771 2772 if ((scsiq->q1.target_id & sc->use_tagged_qng) == 0) { 2773 scsiq->q2.tag_code &= ~M2_QTAG_MSG_SIMPLE; 2774 } 2775 scsiq->q1.status = ASC_QS_FREE; 2776 AscMemWordCopyToLram(iot, ioh, q_addr + ASC_SCSIQ_CDB_BEG, 2777 (u_int16_t *) scsiq->cdbptr, scsiq->q2.cdb_len >> 1); 2778 2779 AscPutSCSIQ(iot, ioh, q_addr + ASC_SCSIQ_CPY_BEG, scsiq); 2780 2781 /* 2782 * Let's start the command 2783 */ 2784 AscWriteLramWord(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS, 2785 (scsiq->q1.q_no << 8) | ASC_QS_READY); 2786 2787 return (ASC_NOERROR); 2788 } 2789 2790 2791 static void 2792 AscPutSCSIQ(iot, ioh, addr, scsiq) 2793 bus_space_tag_t iot; 2794 bus_space_handle_t ioh; 2795 u_int16_t addr; 2796 ASC_SCSI_Q *scsiq; 2797 { 2798 u_int16_t val; 2799 2800 2801 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr); 2802 2803 /* ASC_SCSIQ_1 */ 2804 val = MAKEWORD(scsiq->q1.cntl, scsiq->q1.sg_queue_cnt); 2805 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2806 val = MAKEWORD(scsiq->q1.target_id, scsiq->q1.target_lun); 2807 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2808 val = LO_WORD(scsiq->q1.data_addr); 2809 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2810 val = HI_WORD(scsiq->q1.data_addr); 2811 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2812 val = LO_WORD(scsiq->q1.data_cnt); 2813 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2814 val = HI_WORD(scsiq->q1.data_cnt); 2815 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2816 val = LO_WORD(scsiq->q1.sense_addr); 2817 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2818 val = HI_WORD(scsiq->q1.sense_addr); 2819 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2820 val = MAKEWORD(scsiq->q1.sense_len, scsiq->q1.extra_bytes); 2821 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2822 2823 /* ASC_SCSIQ_2 */ 2824 val = LO_WORD(scsiq->q2.ccb_ptr); 2825 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2826 val = HI_WORD(scsiq->q2.ccb_ptr); 2827 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2828 val = MAKEWORD(scsiq->q2.target_ix, scsiq->q2.flag); 2829 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2830 val = MAKEWORD(scsiq->q2.cdb_len, scsiq->q2.tag_code); 2831 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2832 ASC_SET_CHIP_LRAM_DATA(iot, ioh, scsiq->q2.vm_id); 2833 } 2834 2835 2836 static int 2837 AscSgListToQueue(sg_list) 2838 int sg_list; 2839 { 2840 int n_sg_list_qs; 2841 2842 n_sg_list_qs = ((sg_list - 1) / ASC_SG_LIST_PER_Q); 2843 if (((sg_list - 1) % ASC_SG_LIST_PER_Q) != 0) 2844 n_sg_list_qs++; 2845 2846 return (n_sg_list_qs + 1); 2847 } 2848 2849 2850 static u_int 2851 AscGetNumOfFreeQueue(sc, target_ix, n_qs) 2852 ASC_SOFTC *sc; 2853 u_int8_t target_ix; 2854 u_int8_t n_qs; 2855 { 2856 u_int cur_used_qs; 2857 u_int cur_free_qs; 2858 2859 2860 if (n_qs == 1) { 2861 cur_used_qs = sc->cur_total_qng + 2862 sc->last_q_shortage + 2863 ASC_MIN_FREE_Q; 2864 } else { 2865 cur_used_qs = sc->cur_total_qng + ASC_MIN_FREE_Q; 2866 } 2867 2868 if ((cur_used_qs + n_qs) <= sc->max_total_qng) { 2869 cur_free_qs = sc->max_total_qng - cur_used_qs; 2870 return (cur_free_qs); 2871 } 2872 if (n_qs > 1) 2873 if ((n_qs > sc->last_q_shortage) && 2874 (n_qs <= (sc->max_total_qng - ASC_MIN_FREE_Q))) { 2875 sc->last_q_shortage = n_qs; 2876 } 2877 return (0); 2878 } 2879 2880 2881 static u_int8_t 2882 AscAllocFreeQueue(iot, ioh, free_q_head) 2883 bus_space_tag_t iot; 2884 bus_space_handle_t ioh; 2885 u_int8_t free_q_head; 2886 { 2887 u_int16_t q_addr; 2888 u_int8_t next_qp; 2889 u_int8_t q_status; 2890 2891 2892 q_addr = ASC_QNO_TO_QADDR(free_q_head); 2893 q_status = AscReadLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS); 2894 next_qp = AscReadLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_FWD); 2895 if (((q_status & ASC_QS_READY) == 0) && (next_qp != ASC_QLINK_END)) 2896 return (next_qp); 2897 2898 return (ASC_QLINK_END); 2899 } 2900 2901 2902 static u_int8_t 2903 AscAllocMultipleFreeQueue(iot, ioh, free_q_head, n_free_q) 2904 bus_space_tag_t iot; 2905 bus_space_handle_t ioh; 2906 u_int8_t free_q_head; 2907 u_int8_t n_free_q; 2908 { 2909 u_int8_t i; 2910 2911 for (i = 0; i < n_free_q; i++) { 2912 free_q_head = AscAllocFreeQueue(iot, ioh, free_q_head); 2913 if (free_q_head == ASC_QLINK_END) 2914 break; 2915 } 2916 2917 return (free_q_head); 2918 } 2919 2920 2921 static int 2922 AscStopQueueExe(iot, ioh) 2923 bus_space_tag_t iot; 2924 bus_space_handle_t ioh; 2925 { 2926 int count = 0; 2927 2928 if (AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B) == 0) { 2929 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, ASC_STOP_REQ_RISC_STOP); 2930 do { 2931 if (AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B) & 2932 ASC_STOP_ACK_RISC_STOP) 2933 return (1); 2934 2935 DvcSleepMilliSecond(100); 2936 } while (count++ < 20); 2937 } 2938 return (0); 2939 } 2940 2941 2942 static void 2943 AscStartQueueExe(iot, ioh) 2944 bus_space_tag_t iot; 2945 bus_space_handle_t ioh; 2946 { 2947 2948 if (AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B) != 0) 2949 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, 0); 2950 } 2951 2952 2953 static void 2954 AscCleanUpBusyQueue(iot, ioh) 2955 bus_space_tag_t iot; 2956 bus_space_handle_t ioh; 2957 { 2958 int count = 0; 2959 u_int8_t stop_code; 2960 2961 2962 if (AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B) != 0) { 2963 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, ASC_STOP_CLEAN_UP_BUSY_Q); 2964 do { 2965 stop_code = AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B); 2966 if ((stop_code & ASC_STOP_CLEAN_UP_BUSY_Q) == 0) 2967 break; 2968 2969 DvcSleepMilliSecond(100); 2970 } while (count++ < 20); 2971 } 2972 } 2973 2974 2975 static int 2976 _AscWaitQDone(iot, ioh, scsiq) 2977 bus_space_tag_t iot; 2978 bus_space_handle_t ioh; 2979 ASC_SCSI_Q *scsiq; 2980 { 2981 u_int16_t q_addr; 2982 u_int8_t q_status; 2983 int count = 0; 2984 2985 while (scsiq->q1.q_no == 0); 2986 2987 q_addr = ASC_QNO_TO_QADDR(scsiq->q1.q_no); 2988 do { 2989 q_status = AscReadLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS); 2990 DvcSleepMilliSecond(100L); 2991 if (count++ > 30) 2992 return (0); 2993 2994 } while ((q_status & ASC_QS_READY) != 0); 2995 2996 return (1); 2997 } 2998 2999 3000 static int 3001 AscCleanUpDiscQueue(iot, ioh) 3002 bus_space_tag_t iot; 3003 bus_space_handle_t ioh; 3004 { 3005 int count; 3006 u_int8_t stop_code; 3007 3008 count = 0; 3009 if (AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B) != 0) { 3010 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, ASC_STOP_CLEAN_UP_DISC_Q); 3011 do { 3012 stop_code = AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B); 3013 if ((stop_code & ASC_STOP_CLEAN_UP_DISC_Q) == 0) 3014 break; 3015 3016 DvcSleepMilliSecond(100); 3017 } while (count++ < 20); 3018 } 3019 return (1); 3020 } 3021 3022 3023 /******************************************************************************/ 3024 /* Abort and Reset CCB routines */ 3025 /******************************************************************************/ 3026 3027 3028 int 3029 AscAbortCCB(sc, ccb) 3030 ASC_SOFTC *sc; 3031 u_int32_t ccb; 3032 { 3033 bus_space_tag_t iot = sc->sc_iot; 3034 bus_space_handle_t ioh = sc->sc_ioh; 3035 int retval; 3036 ASC_SCSI_BIT_ID_TYPE saved_unit_not_ready; 3037 3038 3039 retval = -1; 3040 saved_unit_not_ready = sc->unit_not_ready; 3041 sc->unit_not_ready = 0xFF; 3042 AscWaitISRDone(sc); 3043 if (AscStopQueueExe(iot, ioh) == 1) { 3044 if (AscRiscHaltedAbortCCB(sc, ccb) == 1) { 3045 retval = 1; 3046 AscCleanUpBusyQueue(iot, ioh); 3047 AscStartQueueExe(iot, ioh); 3048 } else { 3049 retval = 0; 3050 AscStartQueueExe(iot, ioh); 3051 } 3052 } 3053 sc->unit_not_ready = saved_unit_not_ready; 3054 3055 return (retval); 3056 } 3057 3058 3059 static int 3060 AscRiscHaltedAbortCCB(sc, ccb) 3061 ASC_SOFTC *sc; 3062 u_int32_t ccb; 3063 { 3064 bus_space_tag_t iot = sc->sc_iot; 3065 bus_space_handle_t ioh = sc->sc_ioh; 3066 u_int16_t q_addr; 3067 u_int8_t q_no; 3068 ASC_QDONE_INFO scsiq_buf; 3069 ASC_QDONE_INFO *scsiq; 3070 ASC_ISR_CALLBACK asc_isr_callback; 3071 int last_int_level; 3072 3073 3074 asc_isr_callback = (ASC_ISR_CALLBACK) sc->isr_callback; 3075 last_int_level = DvcEnterCritical(); 3076 scsiq = (ASC_QDONE_INFO *) & scsiq_buf; 3077 3078 for (q_no = ASC_MIN_ACTIVE_QNO; q_no <= sc->max_total_qng; q_no++) { 3079 q_addr = ASC_QNO_TO_QADDR(q_no); 3080 scsiq->d2.ccb_ptr = AscReadLramDWord(iot, ioh, 3081 q_addr + ASC_SCSIQ_D_CCBPTR); 3082 if (scsiq->d2.ccb_ptr == ccb) { 3083 _AscCopyLramScsiDoneQ(iot, ioh, q_addr, scsiq, sc->max_dma_count); 3084 if (((scsiq->q_status & ASC_QS_READY) != 0) 3085 && ((scsiq->q_status & ASC_QS_ABORTED) == 0) 3086 && ((scsiq->cntl & ASC_QCSG_SG_XFER_LIST) == 0)) { 3087 scsiq->q_status |= ASC_QS_ABORTED; 3088 scsiq->d3.done_stat = ASC_QD_ABORTED_BY_HOST; 3089 AscWriteLramDWord(iot, ioh, q_addr + ASC_SCSIQ_D_CCBPTR, 0L); 3090 AscWriteLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS, 3091 scsiq->q_status); 3092 (*asc_isr_callback) (sc, scsiq); 3093 DvcLeaveCritical(last_int_level); 3094 return (1); 3095 } 3096 } 3097 } 3098 3099 DvcLeaveCritical(last_int_level); 3100 return (0); 3101 } 3102 3103 3104 static int 3105 AscRiscHaltedAbortTIX(sc, target_ix) 3106 ASC_SOFTC *sc; 3107 u_int8_t target_ix; 3108 { 3109 bus_space_tag_t iot = sc->sc_iot; 3110 bus_space_handle_t ioh = sc->sc_ioh; 3111 u_int16_t q_addr; 3112 u_int8_t q_no; 3113 ASC_QDONE_INFO scsiq_buf; 3114 ASC_QDONE_INFO *scsiq; 3115 ASC_ISR_CALLBACK asc_isr_callback; 3116 int last_int_level; 3117 3118 3119 asc_isr_callback = (ASC_ISR_CALLBACK) sc->isr_callback; 3120 last_int_level = DvcEnterCritical(); 3121 scsiq = (ASC_QDONE_INFO *) & scsiq_buf; 3122 for (q_no = ASC_MIN_ACTIVE_QNO; q_no <= sc->max_total_qng; q_no++) { 3123 q_addr = ASC_QNO_TO_QADDR(q_no); 3124 _AscCopyLramScsiDoneQ(iot, ioh, q_addr, scsiq, sc->max_dma_count); 3125 if (((scsiq->q_status & ASC_QS_READY) != 0) && 3126 ((scsiq->q_status & ASC_QS_ABORTED) == 0) && 3127 ((scsiq->cntl & ASC_QCSG_SG_XFER_LIST) == 0)) { 3128 if (scsiq->d2.target_ix == target_ix) { 3129 scsiq->q_status |= ASC_QS_ABORTED; 3130 scsiq->d3.done_stat = ASC_QD_ABORTED_BY_HOST; 3131 AscWriteLramDWord(iot, ioh, q_addr + ASC_SCSIQ_D_CCBPTR, 0L); 3132 AscWriteLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS, 3133 scsiq->q_status); 3134 (*asc_isr_callback) (sc, scsiq); 3135 } 3136 } 3137 } 3138 DvcLeaveCritical(last_int_level); 3139 return (1); 3140 } 3141 3142 3143 /* 3144 * AscResetDevice calls _AscWaitQDone which requires interrupt enabled, 3145 * so we cannot use this function with the actual NetBSD SCSI layer 3146 * because at boot time interrupts are disabled. 3147 */ 3148 int 3149 AscResetDevice(sc, target_ix) 3150 ASC_SOFTC *sc; 3151 u_char target_ix; 3152 { 3153 bus_space_tag_t iot = sc->sc_iot; 3154 bus_space_handle_t ioh = sc->sc_ioh; 3155 int retval; 3156 u_int8_t tid_no; 3157 ASC_SCSI_BIT_ID_TYPE target_id; 3158 int i; 3159 ASC_SCSI_REQ_Q scsiq_buf; 3160 ASC_SCSI_REQ_Q *scsiq; 3161 u_int8_t *buf; 3162 ASC_SCSI_BIT_ID_TYPE saved_unit_not_ready; 3163 3164 3165 tid_no = ASC_TIX_TO_TID(target_ix); 3166 target_id = ASC_TID_TO_TARGET_ID(tid_no); 3167 saved_unit_not_ready = sc->unit_not_ready; 3168 sc->unit_not_ready = target_id; 3169 retval = ASC_ERROR; 3170 3171 AscWaitTixISRDone(sc, target_ix); 3172 3173 if (AscStopQueueExe(iot, ioh) == 1) { 3174 if (AscRiscHaltedAbortTIX(sc, target_ix) == 1) { 3175 AscCleanUpBusyQueue(iot, ioh); 3176 AscStartQueueExe(iot, ioh); 3177 AscWaitTixISRDone(sc, target_ix); 3178 retval = ASC_NOERROR; 3179 scsiq = (ASC_SCSI_REQ_Q *) & scsiq_buf; 3180 buf = (u_char *) & scsiq_buf; 3181 for (i = 0; i < sizeof(ASC_SCSI_REQ_Q); i++) 3182 *buf++ = 0x00; 3183 scsiq->q1.status = (u_char) ASC_QS_READY; 3184 scsiq->q2.cdb_len = 6; 3185 scsiq->q2.tag_code = M2_QTAG_MSG_SIMPLE; 3186 scsiq->q1.target_id = target_id; 3187 scsiq->q2.target_ix = ASC_TIDLUN_TO_IX(tid_no, 0); 3188 scsiq->cdbptr = (u_int8_t *) scsiq->cdb; 3189 scsiq->q1.cntl = ASC_QC_NO_CALLBACK | ASC_QC_MSG_OUT | ASC_QC_URGENT; 3190 AscWriteLramByte(iot, ioh, ASCV_MSGOUT_BEG, M1_BUS_DVC_RESET); 3191 sc->unit_not_ready &= ~target_id; 3192 sc->sdtr_done |= target_id; 3193 if (AscExeScsiQueue(sc, (ASC_SCSI_Q *) scsiq) == ASC_NOERROR) { 3194 sc->unit_not_ready = target_id; 3195 DvcSleepMilliSecond(1000); 3196 _AscWaitQDone(iot, ioh, (ASC_SCSI_Q *) scsiq); 3197 if (AscStopQueueExe(iot, ioh) == ASC_NOERROR) { 3198 AscCleanUpDiscQueue(iot, ioh); 3199 AscStartQueueExe(iot, ioh); 3200 if (sc->pci_fix_asyn_xfer & target_id) 3201 AscSetRunChipSynRegAtID(iot, ioh, tid_no, 3202 ASYN_SDTR_DATA_FIX_PCI_REV_AB); 3203 AscWaitTixISRDone(sc, target_ix); 3204 } 3205 } else 3206 retval = ASC_BUSY; 3207 sc->sdtr_done &= ~target_id; 3208 } else { 3209 retval = ASC_ERROR; 3210 AscStartQueueExe(iot, ioh); 3211 } 3212 } 3213 sc->unit_not_ready = saved_unit_not_ready; 3214 return (retval); 3215 } 3216 3217 3218 int 3219 AscResetBus(sc) 3220 ASC_SOFTC *sc; 3221 { 3222 bus_space_tag_t iot = sc->sc_iot; 3223 bus_space_handle_t ioh = sc->sc_ioh; 3224 int retval; 3225 int i; 3226 3227 3228 sc->unit_not_ready = 0xFF; 3229 retval = ASC_NOERROR; 3230 3231 AscWaitISRDone(sc); 3232 AscStopQueueExe(iot, ioh); 3233 sc->sdtr_done = 0; 3234 AscResetChipAndScsiBus(iot, ioh); 3235 DvcSleepMilliSecond((u_long) ((u_int16_t) sc->scsi_reset_wait * 1000)); 3236 AscReInitLram(sc); 3237 for (i = 0; i <= ASC_MAX_TID; i++) { 3238 sc->cur_dvc_qng[i] = 0; 3239 if (sc->pci_fix_asyn_xfer & (ASC_SCSI_BIT_ID_TYPE) (0x01 << i)) 3240 AscSetChipSynRegAtID(iot, ioh, i, ASYN_SDTR_DATA_FIX_PCI_REV_AB); 3241 } 3242 3243 ASC_SET_PC_ADDR(iot, ioh, ASC_MCODE_START_ADDR); 3244 if (ASC_GET_PC_ADDR(iot, ioh) != ASC_MCODE_START_ADDR) 3245 retval = ASC_ERROR; 3246 3247 if (AscStartChip(iot, ioh) == 0) 3248 retval = ASC_ERROR; 3249 3250 AscStartQueueExe(iot, ioh); 3251 sc->unit_not_ready = 0; 3252 sc->queue_full_or_busy = 0; 3253 return (retval); 3254 } 3255 3256 3257 /******************************************************************************/ 3258 /* Error Handling routines */ 3259 /******************************************************************************/ 3260 3261 3262 static int 3263 AscSetLibErrorCode(sc, err_code) 3264 ASC_SOFTC *sc; 3265 u_int16_t err_code; 3266 { 3267 /* 3268 * if(sc->err_code == 0) { sc->err_code = err_code; 3269 */ AscWriteLramWord(sc->sc_iot, sc->sc_ioh, ASCV_ASCDVC_ERR_CODE_W, 3270 err_code); 3271 /* 3272 * } 3273 */ 3274 return (err_code); 3275 } 3276 3277 3278 /******************************************************************************/ 3279 /* Handle bugged borads routines */ 3280 /******************************************************************************/ 3281 3282 3283 void 3284 AscInquiryHandling(sc, tid_no, inq) 3285 ASC_SOFTC *sc; 3286 u_int8_t tid_no; 3287 ASC_SCSI_INQUIRY *inq; 3288 { 3289 bus_space_tag_t iot = sc->sc_iot; 3290 bus_space_handle_t ioh = sc->sc_ioh; 3291 ASC_SCSI_BIT_ID_TYPE tid_bit = ASC_TIX_TO_TARGET_ID(tid_no); 3292 ASC_SCSI_BIT_ID_TYPE orig_init_sdtr, orig_use_tagged_qng; 3293 3294 3295 orig_init_sdtr = sc->init_sdtr; 3296 orig_use_tagged_qng = sc->use_tagged_qng; 3297 3298 sc->init_sdtr &= ~tid_bit; 3299 sc->can_tagged_qng &= ~tid_bit; 3300 sc->use_tagged_qng &= ~tid_bit; 3301 3302 if (inq->byte3.rsp_data_fmt >= 2 || inq->byte2.ansi_apr_ver >= 2) { 3303 if ((sc->sdtr_enable & tid_bit) && inq->byte7.Sync) 3304 sc->init_sdtr |= tid_bit; 3305 3306 if ((sc->cmd_qng_enabled & tid_bit) && inq->byte7.CmdQue) 3307 if (AscTagQueuingSafe(inq)) { 3308 sc->use_tagged_qng |= tid_bit; 3309 sc->can_tagged_qng |= tid_bit; 3310 } 3311 } 3312 if (orig_use_tagged_qng != sc->use_tagged_qng) { 3313 AscWriteLramByte(iot, ioh, ASCV_DISC_ENABLE_B, 3314 sc->disc_enable); 3315 AscWriteLramByte(iot, ioh, ASCV_USE_TAGGED_QNG_B, 3316 sc->use_tagged_qng); 3317 AscWriteLramByte(iot, ioh, ASCV_CAN_TAGGED_QNG_B, 3318 sc->can_tagged_qng); 3319 3320 sc->max_dvc_qng[tid_no] = 3321 sc->max_tag_qng[tid_no]; 3322 AscWriteLramByte(iot, ioh, ASCV_MAX_DVC_QNG_BEG + tid_no, 3323 sc->max_dvc_qng[tid_no]); 3324 } 3325 if (orig_init_sdtr != sc->init_sdtr) 3326 AscAsyncFix(sc, tid_no, inq); 3327 } 3328 3329 3330 static int 3331 AscTagQueuingSafe(inq) 3332 ASC_SCSI_INQUIRY *inq; 3333 { 3334 if ((inq->add_len >= 32) && 3335 (AscCompareString(inq->vendor_id, "QUANTUM XP34301", 15) == 0) && 3336 (AscCompareString(inq->product_rev_level, "1071", 4) == 0)) { 3337 return 0; 3338 } 3339 return 1; 3340 } 3341 3342 3343 static void 3344 AscAsyncFix(sc, tid_no, inq) 3345 ASC_SOFTC *sc; 3346 u_int8_t tid_no; 3347 ASC_SCSI_INQUIRY *inq; 3348 { 3349 u_int8_t dvc_type; 3350 ASC_SCSI_BIT_ID_TYPE tid_bits; 3351 3352 3353 dvc_type = inq->byte0.peri_dvc_type; 3354 tid_bits = ASC_TIX_TO_TARGET_ID(tid_no); 3355 3356 if (sc->bug_fix_cntl & ASC_BUG_FIX_ASYN_USE_SYN) { 3357 if (!(sc->init_sdtr & tid_bits)) { 3358 if ((dvc_type == SCSI_TYPE_CDROM) && 3359 (AscCompareString(inq->vendor_id, "HP ", 3) == 0)) { 3360 sc->pci_fix_asyn_xfer_always |= tid_bits; 3361 } 3362 sc->pci_fix_asyn_xfer |= tid_bits; 3363 if ((dvc_type == SCSI_TYPE_PROC) || 3364 (dvc_type == SCSI_TYPE_SCANNER)) { 3365 sc->pci_fix_asyn_xfer &= ~tid_bits; 3366 } 3367 if ((dvc_type == SCSI_TYPE_SASD) && 3368 (AscCompareString(inq->vendor_id, "TANDBERG", 8) == 0) && 3369 (AscCompareString(inq->product_id, " TDC 36", 7) == 0)) { 3370 sc->pci_fix_asyn_xfer &= ~tid_bits; 3371 } 3372 if ((dvc_type == SCSI_TYPE_SASD) && 3373 (AscCompareString(inq->vendor_id, "WANGTEK ", 8) == 0)) { 3374 sc->pci_fix_asyn_xfer &= ~tid_bits; 3375 } 3376 if ((dvc_type == SCSI_TYPE_CDROM) && 3377 (AscCompareString(inq->vendor_id, "NEC ", 8) == 0) && 3378 (AscCompareString(inq->product_id, "CD-ROM DRIVE ", 16) == 0)) { 3379 sc->pci_fix_asyn_xfer &= ~tid_bits; 3380 } 3381 if ((dvc_type == SCSI_TYPE_CDROM) && 3382 (AscCompareString(inq->vendor_id, "YAMAHA", 6) == 0) && 3383 (AscCompareString(inq->product_id, "CDR400", 6) == 0)) { 3384 sc->pci_fix_asyn_xfer &= ~tid_bits; 3385 } 3386 if (sc->pci_fix_asyn_xfer & tid_bits) { 3387 AscSetRunChipSynRegAtID(sc->sc_iot, sc->sc_ioh, tid_no, 3388 ASYN_SDTR_DATA_FIX_PCI_REV_AB); 3389 } 3390 } 3391 } 3392 } 3393 3394 3395 /******************************************************************************/ 3396 /* Miscellaneous routines */ 3397 /******************************************************************************/ 3398 3399 3400 static int 3401 AscCompareString(str1, str2, len) 3402 u_char *str1; 3403 u_char *str2; 3404 int len; 3405 { 3406 int i; 3407 int diff; 3408 3409 for (i = 0; i < len; i++) { 3410 diff = (int) (str1[i] - str2[i]); 3411 if (diff != 0) 3412 return (diff); 3413 } 3414 3415 return (0); 3416 } 3417 3418 3419 /******************************************************************************/ 3420 /* Device oriented routines */ 3421 /******************************************************************************/ 3422 3423 3424 static int 3425 DvcEnterCritical(void) 3426 { 3427 int s; 3428 3429 s = splbio(); 3430 return (s); 3431 } 3432 3433 3434 static void 3435 DvcLeaveCritical(s) 3436 int s; 3437 { 3438 3439 splx(s); 3440 } 3441 3442 3443 static void 3444 DvcSleepMilliSecond(n) 3445 u_int32_t n; 3446 { 3447 3448 DELAY(n * 1000); 3449 } 3450 3451 #ifdef UNUSED 3452 static void 3453 DvcDelayMicroSecond(n) 3454 u_int32_t n; 3455 { 3456 3457 DELAY(n); 3458 } 3459 #endif 3460 3461 static void 3462 DvcDelayNanoSecond(n) 3463 u_int32_t n; 3464 { 3465 3466 DELAY((n + 999) / 1000); 3467 } 3468