1 /* $OpenBSD: advlib.c,v 1.13 2008/06/26 05:42:15 ray Exp $ */ 2 /* $NetBSD: advlib.c,v 1.7 1998/10/28 20:39:46 dante Exp $ */ 3 4 /* 5 * Low level routines for the Advanced Systems Inc. SCSI controllers chips 6 * 7 * Copyright (c) 1998 The NetBSD Foundation, Inc. 8 * All rights reserved. 9 * 10 * Author: Baldassare Dante Profeta <dante@mclink.it> 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 /* 34 * Ported from: 35 */ 36 /* 37 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters 38 * 39 * Copyright (c) 1995-1998 Advanced System Products, Inc. 40 * All Rights Reserved. 41 * 42 * Redistribution and use in source and binary forms, with or without 43 * modification, are permitted provided that redistributions of source 44 * code retain the above copyright notice and this comment without 45 * modification. 46 * 47 */ 48 49 #include <sys/types.h> 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/malloc.h> 53 #include <sys/kernel.h> 54 #include <sys/queue.h> 55 #include <sys/device.h> 56 57 #include <machine/bus.h> 58 #include <machine/intr.h> 59 60 #include <scsi/scsi_all.h> 61 #include <scsi/scsiconf.h> 62 63 #include <uvm/uvm_extern.h> 64 65 #include <dev/ic/adv.h> 66 #include <dev/ic/advlib.h> 67 68 #include <dev/microcode/adw/advmcode.h> 69 70 71 /* #define ASC_DEBUG */ 72 73 /******************************************************************************/ 74 /* Static functions */ 75 /******************************************************************************/ 76 77 /* Initialization routines */ 78 static u_int32_t AscLoadMicroCode(bus_space_tag_t, bus_space_handle_t, 79 u_int16_t, u_int16_t *, u_int16_t); 80 static void AscInitLram(ASC_SOFTC *); 81 static void AscInitQLinkVar(ASC_SOFTC *); 82 static int AscResetChipAndScsiBus(bus_space_tag_t, bus_space_handle_t); 83 static u_int16_t AscGetChipBusType(bus_space_tag_t, bus_space_handle_t); 84 85 /* Chip register routines */ 86 static void AscSetBank(bus_space_tag_t, bus_space_handle_t, u_int8_t); 87 88 /* RISC Chip routines */ 89 static int AscStartChip(bus_space_tag_t, bus_space_handle_t); 90 static int AscStopChip(bus_space_tag_t, bus_space_handle_t); 91 static u_int8_t AscSetChipScsiID(bus_space_tag_t, bus_space_handle_t, 92 u_int8_t); 93 static u_int8_t AscGetChipScsiCtrl(bus_space_tag_t, bus_space_handle_t); 94 static u_int8_t AscGetChipVersion(bus_space_tag_t, bus_space_handle_t, 95 u_int16_t); 96 static int AscSetRunChipSynRegAtID(bus_space_tag_t, bus_space_handle_t, 97 u_int8_t, u_int8_t); 98 static int AscSetChipSynRegAtID(bus_space_tag_t, bus_space_handle_t, 99 u_int8_t, u_int8_t); 100 static int AscHostReqRiscHalt(bus_space_tag_t, bus_space_handle_t); 101 static int AscIsChipHalted(bus_space_tag_t, bus_space_handle_t); 102 static void AscSetChipIH(bus_space_tag_t, bus_space_handle_t, u_int16_t); 103 104 /* Lram routines */ 105 static u_int8_t AscReadLramByte(bus_space_tag_t, bus_space_handle_t, 106 u_int16_t); 107 static void AscWriteLramByte(bus_space_tag_t, bus_space_handle_t, 108 u_int16_t, u_int8_t); 109 static u_int16_t AscReadLramWord(bus_space_tag_t, bus_space_handle_t, 110 u_int16_t); 111 static void AscWriteLramWord(bus_space_tag_t, bus_space_handle_t, 112 u_int16_t, u_int16_t); 113 static u_int32_t AscReadLramDWord(bus_space_tag_t, bus_space_handle_t, 114 u_int16_t); 115 static void AscWriteLramDWord(bus_space_tag_t, bus_space_handle_t, 116 u_int16_t, u_int32_t); 117 static void AscMemWordSetLram(bus_space_tag_t, bus_space_handle_t, 118 u_int16_t, u_int16_t, int); 119 static void AscMemWordCopyToLram(bus_space_tag_t, bus_space_handle_t, 120 u_int16_t, u_int16_t *, int); 121 static void AscMemWordCopyFromLram(bus_space_tag_t, bus_space_handle_t, 122 u_int16_t, u_int16_t *, int); 123 static void AscMemDWordCopyToLram(bus_space_tag_t, bus_space_handle_t, 124 u_int16_t, u_int32_t *, int); 125 static u_int32_t AscMemSumLramWord(bus_space_tag_t, bus_space_handle_t, 126 u_int16_t, int); 127 static int AscTestExternalLram(bus_space_tag_t, bus_space_handle_t); 128 129 /* MicroCode routines */ 130 static u_int16_t AscInitMicroCodeVar(ASC_SOFTC *); 131 static u_int32_t AscGetOnePhyAddr(ASC_SOFTC *, u_int8_t *, u_int32_t); 132 static u_int32_t AscGetSGList(ASC_SOFTC *, u_int8_t *, u_int32_t, 133 ASC_SG_HEAD *); 134 135 /* EEProm routines */ 136 static int AscWriteEEPCmdReg(bus_space_tag_t, bus_space_handle_t, 137 u_int8_t); 138 static int AscWriteEEPDataReg(bus_space_tag_t, bus_space_handle_t, 139 u_int16_t); 140 static void AscWaitEEPRead(void); 141 static void AscWaitEEPWrite(void); 142 static u_int16_t AscReadEEPWord(bus_space_tag_t, bus_space_handle_t, 143 u_int8_t); 144 static u_int16_t AscWriteEEPWord(bus_space_tag_t, bus_space_handle_t, 145 u_int8_t, u_int16_t); 146 static u_int16_t AscGetEEPConfig(bus_space_tag_t, bus_space_handle_t, 147 ASCEEP_CONFIG *, u_int16_t); 148 static int AscSetEEPConfig(bus_space_tag_t, bus_space_handle_t, 149 ASCEEP_CONFIG *, u_int16_t); 150 static int AscSetEEPConfigOnce(bus_space_tag_t, bus_space_handle_t, 151 ASCEEP_CONFIG *, u_int16_t); 152 #ifdef ASC_DEBUG 153 static void AscPrintEEPConfig(ASCEEP_CONFIG *, u_int16_t); 154 #endif 155 156 /* Interrupt routines */ 157 static void AscIsrChipHalted(ASC_SOFTC *); 158 static int AscIsrQDone(ASC_SOFTC *); 159 static int AscWaitTixISRDone(ASC_SOFTC *, u_int8_t); 160 static int AscWaitISRDone(ASC_SOFTC *); 161 static u_int8_t _AscCopyLramScsiDoneQ(bus_space_tag_t, bus_space_handle_t, 162 u_int16_t, ASC_QDONE_INFO *, 163 u_int32_t); 164 static void AscGetQDoneInfo(bus_space_tag_t, bus_space_handle_t, u_int16_t, 165 ASC_QDONE_INFO *); 166 static void AscToggleIRQAct(bus_space_tag_t, bus_space_handle_t); 167 static void AscDisableInterrupt(bus_space_tag_t, bus_space_handle_t); 168 static void AscEnableInterrupt(bus_space_tag_t, bus_space_handle_t); 169 static u_int8_t AscGetChipIRQ(bus_space_tag_t, bus_space_handle_t, 170 u_int16_t); 171 static u_int8_t AscSetChipIRQ(bus_space_tag_t, bus_space_handle_t, 172 u_int8_t, u_int16_t); 173 static void AscAckInterrupt(bus_space_tag_t, bus_space_handle_t); 174 static u_int32_t AscGetMaxDmaCount(u_int16_t); 175 static u_int16_t AscGetIsaDmaChannel(bus_space_tag_t, bus_space_handle_t); 176 static u_int16_t AscSetIsaDmaChannel(bus_space_tag_t, bus_space_handle_t, 177 u_int16_t); 178 static u_int8_t AscGetIsaDmaSpeed(bus_space_tag_t, bus_space_handle_t); 179 static u_int8_t AscSetIsaDmaSpeed(bus_space_tag_t, bus_space_handle_t, 180 u_int8_t); 181 182 /* Messages routines */ 183 static void AscHandleExtMsgIn(ASC_SOFTC *, u_int16_t, u_int8_t, 184 ASC_SCSI_BIT_ID_TYPE, int, u_int8_t); 185 static u_int8_t AscMsgOutSDTR(ASC_SOFTC *, u_int8_t, u_int8_t); 186 187 /* SDTR routines */ 188 static void AscSetChipSDTR(bus_space_tag_t, bus_space_handle_t, 189 u_int8_t, u_int8_t); 190 static u_int8_t AscCalSDTRData(ASC_SOFTC *, u_int8_t, u_int8_t); 191 static u_int8_t AscGetSynPeriodIndex(ASC_SOFTC *, u_int8_t); 192 193 /* Queue routines */ 194 static int AscSendScsiQueue(ASC_SOFTC *, ASC_SCSI_Q *, u_int8_t); 195 static int AscSgListToQueue(int); 196 static u_int AscGetNumOfFreeQueue(ASC_SOFTC *, u_int8_t, u_int8_t); 197 static int AscPutReadyQueue(ASC_SOFTC *, ASC_SCSI_Q *, u_int8_t); 198 static void AscPutSCSIQ(bus_space_tag_t, bus_space_handle_t, 199 u_int16_t, ASC_SCSI_Q *); 200 static int AscPutReadySgListQueue(ASC_SOFTC *, ASC_SCSI_Q *, u_int8_t); 201 static u_int8_t AscAllocFreeQueue(bus_space_tag_t, bus_space_handle_t, 202 u_int8_t); 203 static u_int8_t AscAllocMultipleFreeQueue(bus_space_tag_t, 204 bus_space_handle_t, 205 u_int8_t, u_int8_t); 206 static int AscStopQueueExe(bus_space_tag_t, bus_space_handle_t); 207 static void AscStartQueueExe(bus_space_tag_t, bus_space_handle_t); 208 static void AscCleanUpBusyQueue(bus_space_tag_t, bus_space_handle_t); 209 static int _AscWaitQDone(bus_space_tag_t, bus_space_handle_t, 210 ASC_SCSI_Q *); 211 static int AscCleanUpDiscQueue(bus_space_tag_t, bus_space_handle_t); 212 213 /* Abort and Reset CCB routines */ 214 static int AscRiscHaltedAbortCCB(ASC_SOFTC *, u_int32_t); 215 static int AscRiscHaltedAbortTIX(ASC_SOFTC *, u_int8_t); 216 217 /* Error Handling routines */ 218 static int AscSetLibErrorCode(ASC_SOFTC *, u_int16_t); 219 220 /* Handle bugged borads routines */ 221 static int AscTagQueuingSafe(ASC_SCSI_INQUIRY *); 222 static void AscAsyncFix(ASC_SOFTC *, u_int8_t, ASC_SCSI_INQUIRY *); 223 224 /* Miscellaneous routines */ 225 static int AscCompareString(u_char *, u_char *, int); 226 227 /* Device oriented routines */ 228 static int DvcEnterCritical(void); 229 static void DvcLeaveCritical(int); 230 static void DvcSleepMilliSecond(u_int32_t); 231 //static void DvcDelayMicroSecond(u_int32_t); 232 static void DvcDelayNanoSecond(u_int32_t); 233 234 235 /******************************************************************************/ 236 /* Initialization routines */ 237 /******************************************************************************/ 238 239 /* 240 * This function perform the following steps: 241 * - initialize ASC_SOFTC structure with defaults values. 242 * - inquire board registers to know what kind of board it is. 243 * - keep track of bugged borads. 244 */ 245 void 246 AscInitASC_SOFTC(sc) 247 ASC_SOFTC *sc; 248 { 249 bus_space_tag_t iot = sc->sc_iot; 250 bus_space_handle_t ioh = sc->sc_ioh; 251 int i; 252 u_int8_t chip_version; 253 254 255 ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_HALT); 256 ASC_SET_CHIP_STATUS(iot, ioh, 0); 257 258 sc->bug_fix_cntl = 0; 259 sc->pci_fix_asyn_xfer = 0; 260 sc->pci_fix_asyn_xfer_always = 0; 261 sc->sdtr_done = 0; 262 sc->cur_total_qng = 0; 263 sc->last_q_shortage = 0; 264 sc->use_tagged_qng = 0; 265 sc->unit_not_ready = 0; 266 sc->queue_full_or_busy = 0; 267 sc->host_init_sdtr_index = 0; 268 sc->can_tagged_qng = 0; 269 sc->cmd_qng_enabled = 0; 270 sc->dvc_cntl = ASC_DEF_DVC_CNTL; 271 sc->init_sdtr = 0; 272 sc->max_total_qng = ASC_DEF_MAX_TOTAL_QNG; 273 sc->scsi_reset_wait = 3; 274 sc->start_motor = ASC_SCSI_WIDTH_BIT_SET; 275 sc->max_dma_count = AscGetMaxDmaCount(sc->bus_type); 276 sc->sdtr_enable = ASC_SCSI_WIDTH_BIT_SET; 277 sc->disc_enable = ASC_SCSI_WIDTH_BIT_SET; 278 sc->chip_scsi_id = ASC_DEF_CHIP_SCSI_ID; 279 sc->lib_serial_no = ASC_LIB_SERIAL_NUMBER; 280 sc->lib_version = (ASC_LIB_VERSION_MAJOR << 8) | ASC_LIB_VERSION_MINOR; 281 chip_version = AscGetChipVersion(iot, ioh, sc->bus_type); 282 sc->chip_version = chip_version; 283 if ((sc->bus_type & ASC_IS_PCI) && 284 (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3150)) { 285 sc->bus_type = ASC_IS_PCI_ULTRA; 286 sc->sdtr_period_tbl[0] = SYN_ULTRA_XFER_NS_0; 287 sc->sdtr_period_tbl[1] = SYN_ULTRA_XFER_NS_1; 288 sc->sdtr_period_tbl[2] = SYN_ULTRA_XFER_NS_2; 289 sc->sdtr_period_tbl[3] = SYN_ULTRA_XFER_NS_3; 290 sc->sdtr_period_tbl[4] = SYN_ULTRA_XFER_NS_4; 291 sc->sdtr_period_tbl[5] = SYN_ULTRA_XFER_NS_5; 292 sc->sdtr_period_tbl[6] = SYN_ULTRA_XFER_NS_6; 293 sc->sdtr_period_tbl[7] = SYN_ULTRA_XFER_NS_7; 294 sc->sdtr_period_tbl[8] = SYN_ULTRA_XFER_NS_8; 295 sc->sdtr_period_tbl[9] = SYN_ULTRA_XFER_NS_9; 296 sc->sdtr_period_tbl[10] = SYN_ULTRA_XFER_NS_10; 297 sc->sdtr_period_tbl[11] = SYN_ULTRA_XFER_NS_11; 298 sc->sdtr_period_tbl[12] = SYN_ULTRA_XFER_NS_12; 299 sc->sdtr_period_tbl[13] = SYN_ULTRA_XFER_NS_13; 300 sc->sdtr_period_tbl[14] = SYN_ULTRA_XFER_NS_14; 301 sc->sdtr_period_tbl[15] = SYN_ULTRA_XFER_NS_15; 302 sc->max_sdtr_index = 15; 303 if (chip_version == ASC_CHIP_VER_PCI_ULTRA_3150) 304 ASC_SET_EXTRA_CONTROL(iot, ioh, 305 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE)); 306 else if (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3050) 307 ASC_SET_EXTRA_CONTROL(iot, ioh, 308 (SEC_ACTIVE_NEGATE | SEC_ENABLE_FILTER)); 309 } else { 310 sc->sdtr_period_tbl[0] = SYN_XFER_NS_0; 311 sc->sdtr_period_tbl[1] = SYN_XFER_NS_1; 312 sc->sdtr_period_tbl[2] = SYN_XFER_NS_2; 313 sc->sdtr_period_tbl[3] = SYN_XFER_NS_3; 314 sc->sdtr_period_tbl[4] = SYN_XFER_NS_4; 315 sc->sdtr_period_tbl[5] = SYN_XFER_NS_5; 316 sc->sdtr_period_tbl[6] = SYN_XFER_NS_6; 317 sc->sdtr_period_tbl[7] = SYN_XFER_NS_7; 318 sc->max_sdtr_index = 7; 319 } 320 321 if (sc->bus_type == ASC_IS_PCI) 322 ASC_SET_EXTRA_CONTROL(iot, ioh, 323 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE)); 324 325 sc->isa_dma_speed = ASC_DEF_ISA_DMA_SPEED; 326 if (AscGetChipBusType(iot, ioh) == ASC_IS_ISAPNP) { 327 ASC_SET_CHIP_IFC(iot, ioh, ASC_IFC_INIT_DEFAULT); 328 sc->bus_type = ASC_IS_ISAPNP; 329 } 330 if ((sc->bus_type & ASC_IS_ISA) != 0) 331 sc->isa_dma_channel = AscGetIsaDmaChannel(iot, ioh); 332 333 for (i = 0; i <= ASC_MAX_TID; i++) { 334 sc->cur_dvc_qng[i] = 0; 335 sc->max_dvc_qng[i] = ASC_MAX_SCSI1_QNG; 336 sc->max_tag_qng[i] = ASC_MAX_INRAM_TAG_QNG; 337 } 338 } 339 340 341 /* 342 * This function initialize some ASC_SOFTC fields with values read from 343 * on-board EEProm. 344 */ 345 u_int16_t 346 AscInitFromEEP(sc) 347 ASC_SOFTC *sc; 348 { 349 bus_space_tag_t iot = sc->sc_iot; 350 bus_space_handle_t ioh = sc->sc_ioh; 351 ASCEEP_CONFIG eep_config_buf; 352 ASCEEP_CONFIG *eep_config; 353 u_int16_t chksum; 354 u_int16_t warn_code; 355 u_int16_t cfg_msw, cfg_lsw; 356 int i; 357 int write_eep = 0; 358 359 360 warn_code = 0; 361 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0x00FE); 362 AscStopQueueExe(iot, ioh); 363 if ((AscStopChip(iot, ioh) == FALSE) || 364 (AscGetChipScsiCtrl(iot, ioh) != 0)) { 365 AscResetChipAndScsiBus(iot, ioh); 366 DvcSleepMilliSecond(sc->scsi_reset_wait * 1000); 367 } 368 if (AscIsChipHalted(iot, ioh) == FALSE) 369 return (-1); 370 371 ASC_SET_PC_ADDR(iot, ioh, ASC_MCODE_START_ADDR); 372 if (ASC_GET_PC_ADDR(iot, ioh) != ASC_MCODE_START_ADDR) 373 return (-2); 374 375 eep_config = &eep_config_buf; 376 cfg_msw = ASC_GET_CHIP_CFG_MSW(iot, ioh); 377 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh); 378 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) { 379 cfg_msw &= (~(ASC_CFG_MSW_CLR_MASK)); 380 warn_code |= ASC_WARN_CFG_MSW_RECOVER; 381 ASC_SET_CHIP_CFG_MSW(iot, ioh, cfg_msw); 382 } 383 chksum = AscGetEEPConfig(iot, ioh, eep_config, sc->bus_type); 384 #ifdef ASC_DEBUG 385 AscPrintEEPConfig(eep_config, chksum); 386 #endif 387 if (chksum == 0) 388 chksum = 0xAA55; 389 390 if (ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_AUTO_CONFIG) { 391 warn_code |= ASC_WARN_AUTO_CONFIG; 392 if (sc->chip_version == 3) { 393 if (eep_config->cfg_lsw != cfg_lsw) { 394 warn_code |= ASC_WARN_EEPROM_RECOVER; 395 eep_config->cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh); 396 } 397 if (eep_config->cfg_msw != cfg_msw) { 398 warn_code |= ASC_WARN_EEPROM_RECOVER; 399 eep_config->cfg_msw = ASC_GET_CHIP_CFG_MSW(iot, ioh); 400 } 401 } 402 } 403 eep_config->cfg_msw &= ~ASC_CFG_MSW_CLR_MASK; 404 eep_config->cfg_lsw |= ASC_CFG0_HOST_INT_ON; 405 406 if (chksum != eep_config->chksum) { 407 if (AscGetChipVersion(iot, ioh, sc->bus_type) == 408 ASC_CHIP_VER_PCI_ULTRA_3050) { 409 eep_config->init_sdtr = 0xFF; 410 eep_config->disc_enable = 0xFF; 411 eep_config->start_motor = 0xFF; 412 eep_config->use_cmd_qng = 0; 413 eep_config->max_total_qng = 0xF0; 414 eep_config->max_tag_qng = 0x20; 415 eep_config->cntl = 0xBFFF; 416 eep_config->chip_scsi_id = 7; 417 eep_config->no_scam = 0; 418 eep_config->adapter_info[0] = 0; 419 eep_config->adapter_info[1] = 0; 420 eep_config->adapter_info[2] = 0; 421 eep_config->adapter_info[3] = 0; 422 #if BYTE_ORDER == BIG_ENDIAN 423 eep_config->adapter_info[5] = 0; 424 /* Indicate EEPROM-less board. */ 425 eep_config->adapter_info[4] = 0xBB; 426 #else 427 eep_config->adapter_info[4] = 0; 428 /* Indicate EEPROM-less board. */ 429 eep_config->adapter_info[5] = 0xBB; 430 #endif 431 } else { 432 write_eep = 1; 433 warn_code |= ASC_WARN_EEPROM_CHKSUM; 434 } 435 } 436 sc->sdtr_enable = eep_config->init_sdtr; 437 sc->disc_enable = eep_config->disc_enable; 438 sc->cmd_qng_enabled = eep_config->use_cmd_qng; 439 sc->isa_dma_speed = eep_config->isa_dma_speed; 440 sc->start_motor = eep_config->start_motor; 441 sc->dvc_cntl = eep_config->cntl; 442 #if BYTE_ORDER == BIG_ENDIAN 443 sc->adapter_info[0] = eep_config->adapter_info[1]; 444 sc->adapter_info[1] = eep_config->adapter_info[0]; 445 sc->adapter_info[2] = eep_config->adapter_info[3]; 446 sc->adapter_info[3] = eep_config->adapter_info[2]; 447 sc->adapter_info[4] = eep_config->adapter_info[5]; 448 sc->adapter_info[5] = eep_config->adapter_info[4]; 449 #else 450 sc->adapter_info[0] = eep_config->adapter_info[0]; 451 sc->adapter_info[1] = eep_config->adapter_info[1]; 452 sc->adapter_info[2] = eep_config->adapter_info[2]; 453 sc->adapter_info[3] = eep_config->adapter_info[3]; 454 sc->adapter_info[4] = eep_config->adapter_info[4]; 455 sc->adapter_info[5] = eep_config->adapter_info[5]; 456 #endif 457 458 if (!AscTestExternalLram(iot, ioh)) { 459 if (((sc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA)) { 460 eep_config->max_total_qng = ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG; 461 eep_config->max_tag_qng = ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG; 462 } else { 463 eep_config->cfg_msw |= 0x0800; 464 cfg_msw |= 0x0800; 465 ASC_SET_CHIP_CFG_MSW(iot, ioh, cfg_msw); 466 eep_config->max_total_qng = ASC_MAX_PCI_INRAM_TOTAL_QNG; 467 eep_config->max_tag_qng = ASC_MAX_INRAM_TAG_QNG; 468 } 469 } 470 if (eep_config->max_total_qng < ASC_MIN_TOTAL_QNG) 471 eep_config->max_total_qng = ASC_MIN_TOTAL_QNG; 472 473 if (eep_config->max_total_qng > ASC_MAX_TOTAL_QNG) 474 eep_config->max_total_qng = ASC_MAX_TOTAL_QNG; 475 476 if (eep_config->max_tag_qng > eep_config->max_total_qng) 477 eep_config->max_tag_qng = eep_config->max_total_qng; 478 479 if (eep_config->max_tag_qng < ASC_MIN_TAG_Q_PER_DVC) 480 eep_config->max_tag_qng = ASC_MIN_TAG_Q_PER_DVC; 481 482 sc->max_total_qng = eep_config->max_total_qng; 483 if ((eep_config->use_cmd_qng & eep_config->disc_enable) != 484 eep_config->use_cmd_qng) { 485 eep_config->disc_enable = eep_config->use_cmd_qng; 486 warn_code |= ASC_WARN_CMD_QNG_CONFLICT; 487 } 488 if (sc->bus_type & (ASC_IS_ISA | ASC_IS_VL | ASC_IS_EISA)) 489 sc->irq_no = AscGetChipIRQ(iot, ioh, sc->bus_type); 490 491 eep_config->chip_scsi_id &= ASC_MAX_TID; 492 sc->chip_scsi_id = eep_config->chip_scsi_id; 493 if (((sc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) && 494 !(sc->dvc_cntl & ASC_CNTL_SDTR_ENABLE_ULTRA)) { 495 sc->host_init_sdtr_index = ASC_SDTR_ULTRA_PCI_10MB_INDEX; 496 } 497 for (i = 0; i <= ASC_MAX_TID; i++) { 498 sc->max_tag_qng[i] = eep_config->max_tag_qng; 499 sc->sdtr_period_offset[i] = ASC_DEF_SDTR_OFFSET | 500 (sc->host_init_sdtr_index << 4); 501 } 502 503 eep_config->cfg_msw = ASC_GET_CHIP_CFG_MSW(iot, ioh); 504 if (write_eep) { 505 AscSetEEPConfig(iot, ioh, eep_config, sc->bus_type); 506 #ifdef ASC_DEBUG 507 AscPrintEEPConfig(eep_config, 0); 508 #endif 509 } 510 511 return (warn_code); 512 } 513 514 515 u_int16_t 516 AscInitFromASC_SOFTC(sc) 517 ASC_SOFTC *sc; 518 { 519 bus_space_tag_t iot = sc->sc_iot; 520 bus_space_handle_t ioh = sc->sc_ioh; 521 u_int16_t cfg_msw; 522 u_int16_t warn_code; 523 u_int16_t pci_device_id = sc->pci_device_id; 524 525 526 warn_code = 0; 527 cfg_msw = ASC_GET_CHIP_CFG_MSW(iot, ioh); 528 529 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) { 530 cfg_msw &= (~(ASC_CFG_MSW_CLR_MASK)); 531 warn_code |= ASC_WARN_CFG_MSW_RECOVER; 532 ASC_SET_CHIP_CFG_MSW(iot, ioh, cfg_msw); 533 } 534 if ((sc->cmd_qng_enabled & sc->disc_enable) != sc->cmd_qng_enabled) { 535 sc->disc_enable = sc->cmd_qng_enabled; 536 warn_code |= ASC_WARN_CMD_QNG_CONFLICT; 537 } 538 if (ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_AUTO_CONFIG) { 539 warn_code |= ASC_WARN_AUTO_CONFIG; 540 } 541 if ((sc->bus_type & (ASC_IS_ISA | ASC_IS_VL)) != 0) { 542 AscSetChipIRQ(iot, ioh, sc->irq_no, sc->bus_type); 543 } 544 if (sc->bus_type & ASC_IS_PCI) { 545 cfg_msw &= 0xFFC0; 546 ASC_SET_CHIP_CFG_MSW(iot, ioh, cfg_msw); 547 548 if ((sc->bus_type & ASC_IS_PCI_ULTRA) != ASC_IS_PCI_ULTRA) { 549 if ((pci_device_id == ASC_PCI_DEVICE_ID_REV_A) || 550 (pci_device_id == ASC_PCI_DEVICE_ID_REV_B)) { 551 sc->bug_fix_cntl |= ASC_BUG_FIX_IF_NOT_DWB; 552 sc->bug_fix_cntl |= ASC_BUG_FIX_ASYN_USE_SYN; 553 } 554 } 555 } else if (sc->bus_type == ASC_IS_ISAPNP) { 556 if (AscGetChipVersion(iot, ioh, sc->bus_type) == 557 ASC_CHIP_VER_ASYN_BUG) { 558 sc->bug_fix_cntl |= ASC_BUG_FIX_ASYN_USE_SYN; 559 } 560 } 561 AscSetChipScsiID(iot, ioh, sc->chip_scsi_id); 562 563 if (sc->bus_type & ASC_IS_ISA) { 564 AscSetIsaDmaChannel(iot, ioh, sc->isa_dma_channel); 565 AscSetIsaDmaSpeed(iot, ioh, sc->isa_dma_speed); 566 } 567 return (warn_code); 568 } 569 570 571 /* 572 * - Initialize RISC chip 573 * - Initialize Lram 574 * - Load uCode into Lram 575 * - Enable Interrupts 576 */ 577 int 578 AscInitDriver(sc) 579 ASC_SOFTC *sc; 580 { 581 bus_space_tag_t iot = sc->sc_iot; 582 bus_space_handle_t ioh = sc->sc_ioh; 583 u_int32_t chksum; 584 585 586 if (!AscFindSignature(iot, ioh)) 587 return (1); 588 589 AscDisableInterrupt(iot, ioh); 590 591 AscInitLram(sc); 592 chksum = AscLoadMicroCode(iot, ioh, 0, (u_int16_t *) asc_mcode, 593 asc_mcode_size); 594 if (chksum != asc_mcode_chksum) 595 return (2); 596 597 if (AscInitMicroCodeVar(sc) == 0) 598 return (3); 599 600 AscEnableInterrupt(iot, ioh); 601 602 return (0); 603 } 604 605 606 int 607 AscFindSignature(iot, ioh) 608 bus_space_tag_t iot; 609 bus_space_handle_t ioh; 610 { 611 u_int16_t sig_word; 612 613 if (ASC_GET_CHIP_SIGNATURE_BYTE(iot, ioh) == ASC_1000_ID1B) { 614 sig_word = ASC_GET_CHIP_SIGNATURE_WORD(iot, ioh); 615 if (sig_word == ASC_1000_ID0W || 616 sig_word == ASC_1000_ID0W_FIX) 617 return (1); 618 } 619 return (0); 620 } 621 622 623 static void 624 AscInitLram(sc) 625 ASC_SOFTC *sc; 626 { 627 bus_space_tag_t iot = sc->sc_iot; 628 bus_space_handle_t ioh = sc->sc_ioh; 629 u_int8_t i; 630 u_int16_t s_addr; 631 632 633 AscMemWordSetLram(iot, ioh, ASC_QADR_BEG, 0, 634 (((sc->max_total_qng + 2 + 1) * 64) >> 1)); 635 636 i = ASC_MIN_ACTIVE_QNO; 637 s_addr = ASC_QADR_BEG + ASC_QBLK_SIZE; 638 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_FWD, i + 1); 639 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_BWD, sc->max_total_qng); 640 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_QNO, i); 641 i++; 642 s_addr += ASC_QBLK_SIZE; 643 for (; i < sc->max_total_qng; i++, s_addr += ASC_QBLK_SIZE) { 644 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_FWD, i + 1); 645 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_BWD, i - 1); 646 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_QNO, i); 647 } 648 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_FWD, ASC_QLINK_END); 649 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_BWD, sc->max_total_qng - 1); 650 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_QNO, sc->max_total_qng); 651 i++; 652 s_addr += ASC_QBLK_SIZE; 653 for (; i <= (u_int8_t) (sc->max_total_qng + 3); i++, s_addr += ASC_QBLK_SIZE) { 654 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_FWD, i); 655 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_BWD, i); 656 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_QNO, i); 657 } 658 } 659 660 661 void 662 AscReInitLram(sc) 663 ASC_SOFTC *sc; 664 { 665 666 AscInitLram(sc); 667 AscInitQLinkVar(sc); 668 } 669 670 671 static void 672 AscInitQLinkVar(sc) 673 ASC_SOFTC *sc; 674 { 675 bus_space_tag_t iot = sc->sc_iot; 676 bus_space_handle_t ioh = sc->sc_ioh; 677 u_int8_t i; 678 u_int16_t lram_addr; 679 680 681 ASC_PUT_RISC_VAR_FREE_QHEAD(iot, ioh, 1); 682 ASC_PUT_RISC_VAR_DONE_QTAIL(iot, ioh, sc->max_total_qng); 683 ASC_PUT_VAR_FREE_QHEAD(iot, ioh, 1); 684 ASC_PUT_VAR_DONE_QTAIL(iot, ioh, sc->max_total_qng); 685 AscWriteLramByte(iot, ioh, ASCV_BUSY_QHEAD_B, sc->max_total_qng + 1); 686 AscWriteLramByte(iot, ioh, ASCV_DISC1_QHEAD_B, sc->max_total_qng + 2); 687 AscWriteLramByte(iot, ioh, ASCV_TOTAL_READY_Q_B, sc->max_total_qng); 688 AscWriteLramWord(iot, ioh, ASCV_ASCDVC_ERR_CODE_W, 0); 689 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 690 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, 0); 691 AscWriteLramByte(iot, ioh, ASCV_SCSIBUSY_B, 0); 692 AscWriteLramByte(iot, ioh, ASCV_WTM_FLAG_B, 0); 693 ASC_PUT_QDONE_IN_PROGRESS(iot, ioh, 0); 694 lram_addr = ASC_QADR_BEG; 695 for (i = 0; i < 32; i++, lram_addr += 2) 696 AscWriteLramWord(iot, ioh, lram_addr, 0); 697 } 698 699 700 static int 701 AscResetChipAndScsiBus(bus_space_tag_t iot, 702 bus_space_handle_t ioh) 703 { 704 while (ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_SCSI_RESET_ACTIVE); 705 706 AscStopChip(iot, ioh); 707 ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_CHIP_RESET | ASC_CC_SCSI_RESET | ASC_CC_HALT); 708 709 DvcDelayNanoSecond(60000); 710 711 AscSetChipIH(iot, ioh, ASC_INS_RFLAG_WTM); 712 AscSetChipIH(iot, ioh, ASC_INS_HALT); 713 ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_CHIP_RESET | ASC_CC_HALT); 714 ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_HALT); 715 716 DvcSleepMilliSecond(200); 717 718 ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_CLR_SCSI_RESET_INT); 719 AscStartChip(iot, ioh); 720 721 DvcSleepMilliSecond(200); 722 723 return (AscIsChipHalted(iot, ioh)); 724 } 725 726 727 static u_int16_t 728 AscGetChipBusType(iot, ioh) 729 bus_space_tag_t iot; 730 bus_space_handle_t ioh; 731 { 732 u_int16_t chip_ver; 733 734 chip_ver = ASC_GET_CHIP_VER_NO(iot, ioh); 735 if ((chip_ver >= ASC_CHIP_MIN_VER_VL) && 736 (chip_ver <= ASC_CHIP_MAX_VER_VL)) { 737 /* 738 * if(((iop_base & 0x0C30) == 0x0C30) || ((iop_base & 0x0C50) 739 * == 0x0C50)) return (ASC_IS_EISA); 740 */ 741 return (ASC_IS_VL); 742 } 743 if ((chip_ver >= ASC_CHIP_MIN_VER_ISA) && 744 (chip_ver <= ASC_CHIP_MAX_VER_ISA)) { 745 if (chip_ver >= ASC_CHIP_MIN_VER_ISA_PNP) 746 return (ASC_IS_ISAPNP); 747 748 return (ASC_IS_ISA); 749 } else if ((chip_ver >= ASC_CHIP_MIN_VER_PCI) && 750 (chip_ver <= ASC_CHIP_MAX_VER_PCI)) 751 return (ASC_IS_PCI); 752 753 return (0); 754 } 755 756 757 /******************************************************************************/ 758 /* Chip register routines */ 759 /******************************************************************************/ 760 761 762 static void 763 AscSetBank(iot, ioh, bank) 764 bus_space_tag_t iot; 765 bus_space_handle_t ioh; 766 u_int8_t bank; 767 { 768 u_int8_t val; 769 770 val = ASC_GET_CHIP_CONTROL(iot, ioh) & 771 (~(ASC_CC_SINGLE_STEP | ASC_CC_TEST | 772 ASC_CC_DIAG | ASC_CC_SCSI_RESET | 773 ASC_CC_CHIP_RESET)); 774 775 switch (bank) { 776 case 1: 777 val |= ASC_CC_BANK_ONE; 778 break; 779 780 case 2: 781 val |= ASC_CC_DIAG | ASC_CC_BANK_ONE; 782 break; 783 784 default: 785 val &= ~ASC_CC_BANK_ONE; 786 } 787 788 ASC_SET_CHIP_CONTROL(iot, ioh, val); 789 return; 790 } 791 792 793 /******************************************************************************/ 794 /* Chip routines */ 795 /******************************************************************************/ 796 797 798 static int 799 AscStartChip(iot, ioh) 800 bus_space_tag_t iot; 801 bus_space_handle_t ioh; 802 { 803 ASC_SET_CHIP_CONTROL(iot, ioh, 0); 804 if ((ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_HALTED) != 0) 805 return (0); 806 807 return (1); 808 } 809 810 811 static int 812 AscStopChip(iot, ioh) 813 bus_space_tag_t iot; 814 bus_space_handle_t ioh; 815 { 816 u_int8_t cc_val; 817 818 cc_val = ASC_GET_CHIP_CONTROL(iot, ioh) & 819 (~(ASC_CC_SINGLE_STEP | ASC_CC_TEST | ASC_CC_DIAG)); 820 ASC_SET_CHIP_CONTROL(iot, ioh, cc_val | ASC_CC_HALT); 821 AscSetChipIH(iot, ioh, ASC_INS_HALT); 822 AscSetChipIH(iot, ioh, ASC_INS_RFLAG_WTM); 823 if ((ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_HALTED) == 0) 824 return (0); 825 826 return (1); 827 } 828 829 830 static u_int8_t 831 AscGetChipVersion(iot, ioh, bus_type) 832 bus_space_tag_t iot; 833 bus_space_handle_t ioh; 834 u_int16_t bus_type; 835 { 836 if (bus_type & ASC_IS_EISA) { 837 /* 838 * u_int16_t eisa_iop; u_int8_t revision; 839 * 840 * eisa_iop = ASC_GET_EISA_SLOT(iop_base) | 841 * ASC_EISA_REV_IOP_MASK; revision = inp(eisa_iop); 842 * return((ASC_CHIP_MIN_VER_EISA - 1) + revision); 843 */ 844 } 845 return (ASC_GET_CHIP_VER_NO(iot, ioh)); 846 } 847 848 849 static u_int8_t 850 AscSetChipScsiID(iot, ioh, new_id) 851 bus_space_tag_t iot; 852 bus_space_handle_t ioh; 853 u_int8_t new_id; 854 { 855 u_int16_t cfg_lsw; 856 857 if (ASC_GET_CHIP_SCSI_ID(iot, ioh) == new_id) 858 return (new_id); 859 860 cfg_lsw = ASC_GET_CHIP_SCSI_ID(iot, ioh); 861 cfg_lsw &= 0xF8FF; 862 cfg_lsw |= (new_id & ASC_MAX_TID) << 8; 863 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg_lsw); 864 return (ASC_GET_CHIP_SCSI_ID(iot, ioh)); 865 } 866 867 868 static u_int8_t 869 AscGetChipScsiCtrl(iot, ioh) 870 bus_space_tag_t iot; 871 bus_space_handle_t ioh; 872 { 873 u_int8_t scsi_ctrl; 874 875 AscSetBank(iot, ioh, 1); 876 scsi_ctrl = bus_space_read_1(iot, ioh, ASC_IOP_REG_SC); 877 AscSetBank(iot, ioh, 0); 878 return (scsi_ctrl); 879 } 880 881 882 static int 883 AscSetRunChipSynRegAtID(iot, ioh, tid_no, sdtr_data) 884 bus_space_tag_t iot; 885 bus_space_handle_t ioh; 886 u_int8_t tid_no; 887 u_int8_t sdtr_data; 888 { 889 int retval = FALSE; 890 891 if (AscHostReqRiscHalt(iot, ioh)) { 892 retval = AscSetChipSynRegAtID(iot, ioh, tid_no, sdtr_data); 893 AscStartChip(iot, ioh); 894 } 895 return (retval); 896 } 897 898 899 static int 900 AscSetChipSynRegAtID(iot, ioh, id, sdtr_data) 901 bus_space_tag_t iot; 902 bus_space_handle_t ioh; 903 u_int8_t id; 904 u_int8_t sdtr_data; 905 { 906 ASC_SCSI_BIT_ID_TYPE org_id; 907 int i; 908 int sta = TRUE; 909 910 AscSetBank(iot, ioh, 1); 911 org_id = ASC_READ_CHIP_DVC_ID(iot, ioh); 912 for (i = 0; i <= ASC_MAX_TID; i++) 913 if (org_id == (0x01 << i)) 914 break; 915 916 org_id = i; 917 ASC_WRITE_CHIP_DVC_ID(iot, ioh, id); 918 if (ASC_READ_CHIP_DVC_ID(iot, ioh) == (0x01 << id)) { 919 AscSetBank(iot, ioh, 0); 920 ASC_SET_CHIP_SYN(iot, ioh, sdtr_data); 921 if (ASC_GET_CHIP_SYN(iot, ioh) != sdtr_data) 922 sta = FALSE; 923 } else 924 sta = FALSE; 925 926 AscSetBank(iot, ioh, 1); 927 ASC_WRITE_CHIP_DVC_ID(iot, ioh, org_id); 928 AscSetBank(iot, ioh, 0); 929 return (sta); 930 } 931 932 933 static int 934 AscHostReqRiscHalt(iot, ioh) 935 bus_space_tag_t iot; 936 bus_space_handle_t ioh; 937 { 938 int count = 0; 939 int retval = 0; 940 u_int8_t saved_stop_code; 941 942 943 if (AscIsChipHalted(iot, ioh)) 944 return (1); 945 saved_stop_code = AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B); 946 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, 947 ASC_STOP_HOST_REQ_RISC_HALT | ASC_STOP_REQ_RISC_STOP); 948 949 do { 950 if (AscIsChipHalted(iot, ioh)) { 951 retval = 1; 952 break; 953 } 954 DvcSleepMilliSecond(100); 955 } while (count++ < 20); 956 957 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, saved_stop_code); 958 959 return (retval); 960 } 961 962 963 static int 964 AscIsChipHalted(iot, ioh) 965 bus_space_tag_t iot; 966 bus_space_handle_t ioh; 967 { 968 if ((ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_HALTED) != 0) 969 if ((ASC_GET_CHIP_CONTROL(iot, ioh) & ASC_CC_HALT) != 0) 970 return (1); 971 972 return (0); 973 } 974 975 976 static void 977 AscSetChipIH(iot, ioh, ins_code) 978 bus_space_tag_t iot; 979 bus_space_handle_t ioh; 980 u_int16_t ins_code; 981 { 982 AscSetBank(iot, ioh, 1); 983 ASC_WRITE_CHIP_IH(iot, ioh, ins_code); 984 AscSetBank(iot, ioh, 0); 985 986 return; 987 } 988 989 990 /******************************************************************************/ 991 /* Lram routines */ 992 /******************************************************************************/ 993 994 995 static u_int8_t 996 AscReadLramByte(iot, ioh, addr) 997 bus_space_tag_t iot; 998 bus_space_handle_t ioh; 999 u_int16_t addr; 1000 { 1001 u_int8_t byte_data; 1002 u_int16_t word_data; 1003 1004 1005 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr & 0xFFFE); 1006 word_data = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 1007 1008 if (addr & 1) { 1009 /* odd address */ 1010 byte_data = (u_int8_t) ((word_data >> 8) & 0xFF); 1011 } else { 1012 /* even address */ 1013 byte_data = (u_int8_t) (word_data & 0xFF); 1014 } 1015 1016 return (byte_data); 1017 } 1018 1019 1020 static void 1021 AscWriteLramByte(iot, ioh, addr, data) 1022 bus_space_tag_t iot; 1023 bus_space_handle_t ioh; 1024 u_int16_t addr; 1025 u_int8_t data; 1026 { 1027 u_int16_t word_data; 1028 1029 1030 word_data = AscReadLramWord(iot, ioh, addr & 0xFFFE); 1031 1032 if (addr & 1) { 1033 /* odd address */ 1034 word_data &= 0x00FF; 1035 word_data |= (((u_int16_t) data) << 8) & 0xFF00; 1036 } else { 1037 /* even address */ 1038 word_data &= 0xFF00; 1039 word_data |= ((u_int16_t) data) & 0x00FF; 1040 } 1041 1042 AscWriteLramWord(iot, ioh, addr, word_data); 1043 } 1044 1045 1046 static u_int16_t 1047 AscReadLramWord(iot, ioh, addr) 1048 bus_space_tag_t iot; 1049 bus_space_handle_t ioh; 1050 u_int16_t addr; 1051 { 1052 1053 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr); 1054 return (ASC_GET_CHIP_LRAM_DATA(iot, ioh)); 1055 } 1056 1057 1058 static void 1059 AscWriteLramWord(iot, ioh, addr, data) 1060 bus_space_tag_t iot; 1061 bus_space_handle_t ioh; 1062 u_int16_t addr; 1063 u_int16_t data; 1064 { 1065 1066 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr); 1067 ASC_SET_CHIP_LRAM_DATA(iot, ioh, data); 1068 } 1069 1070 1071 static u_int32_t 1072 AscReadLramDWord(iot, ioh, addr) 1073 bus_space_tag_t iot; 1074 bus_space_handle_t ioh; 1075 u_int16_t addr; 1076 { 1077 u_int16_t low_word, hi_word; 1078 1079 1080 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr); 1081 low_word = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 1082 hi_word = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 1083 1084 return ((((u_int32_t) hi_word) << 16) | (u_int32_t) low_word); 1085 } 1086 1087 1088 static void 1089 AscWriteLramDWord(iot, ioh, addr, data) 1090 bus_space_tag_t iot; 1091 bus_space_handle_t ioh; 1092 u_int16_t addr; 1093 u_int32_t data; 1094 { 1095 1096 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr); 1097 ASC_SET_CHIP_LRAM_DATA(iot, ioh, (u_int16_t) (data & 0x0000FFFF)); 1098 ASC_SET_CHIP_LRAM_DATA(iot, ioh, (u_int16_t) (data >> 16)); 1099 } 1100 1101 1102 static void 1103 AscMemWordSetLram(iot, ioh, s_addr, s_words, count) 1104 bus_space_tag_t iot; 1105 bus_space_handle_t ioh; 1106 u_int16_t s_addr; 1107 u_int16_t s_words; 1108 int count; 1109 { 1110 int i; 1111 1112 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, s_addr); 1113 for (i = 0; i < count; i++) 1114 ASC_SET_CHIP_LRAM_DATA(iot, ioh, s_words); 1115 } 1116 1117 1118 static void 1119 AscMemWordCopyToLram(iot, ioh, s_addr, s_buffer, words) 1120 bus_space_tag_t iot; 1121 bus_space_handle_t ioh; 1122 u_int16_t s_addr; 1123 u_int16_t *s_buffer; 1124 int words; 1125 { 1126 int i; 1127 1128 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, s_addr); 1129 for (i = 0; i < words; i++, s_buffer++) 1130 ASC_SET_CHIP_LRAM_DATA_NO_SWAP(iot, ioh, *s_buffer); 1131 } 1132 1133 1134 static void 1135 AscMemWordCopyFromLram(iot, ioh, s_addr, s_buffer, words) 1136 bus_space_tag_t iot; 1137 bus_space_handle_t ioh; 1138 u_int16_t s_addr; 1139 u_int16_t *s_buffer; 1140 int words; 1141 { 1142 int i; 1143 1144 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, s_addr); 1145 for (i = 0; i < words; i++, s_buffer++) 1146 *s_buffer = ASC_GET_CHIP_LRAM_DATA_NO_SWAP(iot, ioh); 1147 } 1148 1149 1150 static void 1151 AscMemDWordCopyToLram(iot, ioh, s_addr, s_buffer, dwords) 1152 bus_space_tag_t iot; 1153 bus_space_handle_t ioh; 1154 u_int16_t s_addr; 1155 u_int32_t *s_buffer; 1156 int dwords; 1157 { 1158 int i; 1159 u_int32_t *pw; 1160 1161 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, s_addr); 1162 1163 pw = s_buffer; 1164 for (i = 0; i < dwords; i++, pw++) { 1165 ASC_SET_CHIP_LRAM_DATA(iot, ioh, LO_WORD(*pw)); 1166 DELAY(1); 1167 ASC_SET_CHIP_LRAM_DATA(iot, ioh, HI_WORD(*pw)); 1168 } 1169 } 1170 1171 1172 static u_int32_t 1173 AscMemSumLramWord(iot, ioh, s_addr, words) 1174 bus_space_tag_t iot; 1175 bus_space_handle_t ioh; 1176 u_int16_t s_addr; 1177 int words; 1178 { 1179 u_int32_t sum = 0L; 1180 u_int16_t i; 1181 1182 1183 for (i = 0; i < words; i++, s_addr += 2) 1184 sum += AscReadLramWord(iot, ioh, s_addr); 1185 1186 return (sum); 1187 } 1188 1189 1190 static int 1191 AscTestExternalLram(iot, ioh) 1192 bus_space_tag_t iot; 1193 bus_space_handle_t ioh; 1194 { 1195 u_int16_t q_addr; 1196 u_int16_t saved_word; 1197 int retval; 1198 1199 1200 retval = 0; 1201 q_addr = ASC_QNO_TO_QADDR(241); 1202 saved_word = AscReadLramWord(iot, ioh, q_addr); 1203 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, q_addr); 1204 ASC_SET_CHIP_LRAM_DATA(iot, ioh, 0x55AA); 1205 DvcSleepMilliSecond(10); 1206 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, q_addr); 1207 1208 if (ASC_GET_CHIP_LRAM_DATA(iot, ioh) == 0x55AA) { 1209 retval = 1; 1210 AscWriteLramWord(iot, ioh, q_addr, saved_word); 1211 } 1212 return (retval); 1213 } 1214 1215 1216 /******************************************************************************/ 1217 /* MicroCode routines */ 1218 /******************************************************************************/ 1219 1220 1221 static u_int16_t 1222 AscInitMicroCodeVar(sc) 1223 ASC_SOFTC *sc; 1224 { 1225 bus_space_tag_t iot = sc->sc_iot; 1226 bus_space_handle_t ioh = sc->sc_ioh; 1227 u_int32_t phy_addr; 1228 int i; 1229 1230 1231 for (i = 0; i <= ASC_MAX_TID; i++) 1232 ASC_PUT_MCODE_INIT_SDTR_AT_ID(iot, ioh, i, 1233 sc->sdtr_period_offset[i]); 1234 1235 AscInitQLinkVar(sc); 1236 AscWriteLramByte(iot, ioh, ASCV_DISC_ENABLE_B, sc->disc_enable); 1237 AscWriteLramByte(iot, ioh, ASCV_HOSTSCSI_ID_B, 1238 ASC_TID_TO_TARGET_ID(sc->chip_scsi_id)); 1239 1240 if ((phy_addr = AscGetOnePhyAddr(sc, sc->overrun_buf, 1241 ASC_OVERRUN_BSIZE)) == 0L) { 1242 return (0); 1243 } else { 1244 phy_addr = (phy_addr & 0xFFFFFFF8ul) + 8; 1245 AscWriteLramDWord(iot, ioh, ASCV_OVERRUN_PADDR_D, phy_addr); 1246 AscWriteLramDWord(iot, ioh, ASCV_OVERRUN_BSIZE_D, 1247 ASC_OVERRUN_BSIZE - 8); 1248 } 1249 1250 sc->mcode_date = AscReadLramWord(iot, ioh, ASCV_MC_DATE_W); 1251 sc->mcode_version = AscReadLramWord(iot, ioh, ASCV_MC_VER_W); 1252 ASC_SET_PC_ADDR(iot, ioh, ASC_MCODE_START_ADDR); 1253 1254 if (ASC_GET_PC_ADDR(iot, ioh) != ASC_MCODE_START_ADDR) { 1255 return (0); 1256 } 1257 if (AscStartChip(iot, ioh) != 1) { 1258 return (0); 1259 } 1260 return (1); 1261 } 1262 1263 1264 static u_int32_t 1265 AscLoadMicroCode(iot, ioh, s_addr, mcode_buf, mcode_size) 1266 bus_space_tag_t iot; 1267 bus_space_handle_t ioh; 1268 u_int16_t s_addr; 1269 u_int16_t *mcode_buf; 1270 u_int16_t mcode_size; 1271 { 1272 u_int32_t chksum; 1273 u_int16_t mcode_word_size; 1274 u_int16_t mcode_chksum; 1275 1276 mcode_word_size = mcode_size >> 1; 1277 /* clear board memory */ 1278 AscMemWordSetLram(iot, ioh, s_addr, 0, mcode_word_size); 1279 /* copy uCode to board memory */ 1280 AscMemWordCopyToLram(iot, ioh, s_addr, mcode_buf, mcode_word_size); 1281 chksum = AscMemSumLramWord(iot, ioh, s_addr, mcode_word_size); 1282 mcode_chksum = AscMemSumLramWord(iot, ioh, ASC_CODE_SEC_BEG, 1283 ((mcode_size - s_addr - ASC_CODE_SEC_BEG) >> 1)); 1284 AscWriteLramWord(iot, ioh, ASCV_MCODE_CHKSUM_W, mcode_chksum); 1285 AscWriteLramWord(iot, ioh, ASCV_MCODE_SIZE_W, mcode_size); 1286 1287 return (chksum); 1288 } 1289 1290 1291 static u_int32_t 1292 AscGetOnePhyAddr(sc, buf_addr, buf_size) 1293 ASC_SOFTC *sc; 1294 u_int8_t *buf_addr; 1295 u_int32_t buf_size; 1296 { 1297 ASC_MIN_SG_HEAD sg_head; 1298 1299 sg_head.entry_cnt = ASC_MIN_SG_LIST; 1300 if (AscGetSGList(sc, buf_addr, buf_size, (ASC_SG_HEAD *) & sg_head) != 1301 buf_size) { 1302 return (0L); 1303 } 1304 if (sg_head.entry_cnt > 1) { 1305 return (0L); 1306 } 1307 return (sg_head.sg_list[0].addr); 1308 } 1309 1310 1311 static u_int32_t 1312 AscGetSGList(sc, buf_addr, buf_len, asc_sg_head_ptr) 1313 ASC_SOFTC *sc; 1314 u_int8_t *buf_addr; 1315 u_int32_t buf_len; 1316 ASC_SG_HEAD *asc_sg_head_ptr; 1317 { 1318 u_int32_t buf_size; 1319 1320 buf_size = buf_len; 1321 asc_sg_head_ptr->entry_cnt = 1; 1322 asc_sg_head_ptr->sg_list[0].addr = (u_int32_t) buf_addr; 1323 asc_sg_head_ptr->sg_list[0].bytes = buf_size; 1324 1325 return (buf_size); 1326 } 1327 1328 1329 /******************************************************************************/ 1330 /* EEProm routines */ 1331 /******************************************************************************/ 1332 1333 1334 static int 1335 AscWriteEEPCmdReg(iot, ioh, cmd_reg) 1336 bus_space_tag_t iot; 1337 bus_space_handle_t ioh; 1338 u_int8_t cmd_reg; 1339 { 1340 u_int8_t read_back; 1341 int retry; 1342 1343 retry = 0; 1344 1345 while (TRUE) { 1346 ASC_SET_CHIP_EEP_CMD(iot, ioh, cmd_reg); 1347 DvcSleepMilliSecond(1); 1348 read_back = ASC_GET_CHIP_EEP_CMD(iot, ioh); 1349 if (read_back == cmd_reg) 1350 return (1); 1351 1352 if (retry++ > ASC_EEP_MAX_RETRY) 1353 return (0); 1354 } 1355 } 1356 1357 1358 static int 1359 AscWriteEEPDataReg(iot, ioh, data_reg) 1360 bus_space_tag_t iot; 1361 bus_space_handle_t ioh; 1362 u_int16_t data_reg; 1363 { 1364 u_int16_t read_back; 1365 int retry; 1366 1367 retry = 0; 1368 while (TRUE) { 1369 ASC_SET_CHIP_EEP_DATA(iot, ioh, data_reg); 1370 DvcSleepMilliSecond(1); 1371 read_back = ASC_GET_CHIP_EEP_DATA(iot, ioh); 1372 if (read_back == data_reg) 1373 return (1); 1374 1375 if (retry++ > ASC_EEP_MAX_RETRY) 1376 return (0); 1377 } 1378 } 1379 1380 1381 static void 1382 AscWaitEEPRead(void) 1383 { 1384 1385 DvcSleepMilliSecond(1); 1386 } 1387 1388 1389 static void 1390 AscWaitEEPWrite(void) 1391 { 1392 1393 DvcSleepMilliSecond(1); 1394 } 1395 1396 1397 static u_int16_t 1398 AscReadEEPWord(iot, ioh, addr) 1399 bus_space_tag_t iot; 1400 bus_space_handle_t ioh; 1401 u_int8_t addr; 1402 { 1403 u_int16_t read_wval; 1404 u_int8_t cmd_reg; 1405 1406 AscWriteEEPCmdReg(iot, ioh, ASC_EEP_CMD_WRITE_DISABLE); 1407 AscWaitEEPRead(); 1408 cmd_reg = addr | ASC_EEP_CMD_READ; 1409 AscWriteEEPCmdReg(iot, ioh, cmd_reg); 1410 AscWaitEEPRead(); 1411 read_wval = ASC_GET_CHIP_EEP_DATA(iot, ioh); 1412 AscWaitEEPRead(); 1413 1414 return (read_wval); 1415 } 1416 1417 1418 static u_int16_t 1419 AscWriteEEPWord(iot, ioh, addr, word_val) 1420 bus_space_tag_t iot; 1421 bus_space_handle_t ioh; 1422 u_int8_t addr; 1423 u_int16_t word_val; 1424 { 1425 u_int16_t read_wval; 1426 1427 read_wval = AscReadEEPWord(iot, ioh, addr); 1428 if (read_wval != word_val) { 1429 AscWriteEEPCmdReg(iot, ioh, ASC_EEP_CMD_WRITE_ABLE); 1430 AscWaitEEPRead(); 1431 AscWriteEEPDataReg(iot, ioh, word_val); 1432 AscWaitEEPRead(); 1433 AscWriteEEPCmdReg(iot, ioh, ASC_EEP_CMD_WRITE | addr); 1434 AscWaitEEPWrite(); 1435 AscWriteEEPCmdReg(iot, ioh, ASC_EEP_CMD_WRITE_DISABLE); 1436 AscWaitEEPRead(); 1437 return (AscReadEEPWord(iot, ioh, addr)); 1438 } 1439 return (read_wval); 1440 } 1441 1442 1443 static u_int16_t 1444 AscGetEEPConfig(iot, ioh, cfg_buf, bus_type) 1445 bus_space_tag_t iot; 1446 bus_space_handle_t ioh; 1447 ASCEEP_CONFIG *cfg_buf; 1448 u_int16_t bus_type; 1449 { 1450 u_int16_t wval; 1451 u_int16_t sum; 1452 u_int16_t *wbuf; 1453 int cfg_beg; 1454 int cfg_end; 1455 int s_addr; 1456 int isa_pnp_wsize; 1457 1458 1459 wbuf = (u_int16_t *) cfg_buf; 1460 sum = 0; 1461 isa_pnp_wsize = 0; 1462 1463 for (s_addr = 0; s_addr < (2 + isa_pnp_wsize); s_addr++, wbuf++) { 1464 wval = AscReadEEPWord(iot, ioh, s_addr); 1465 sum += wval; 1466 *wbuf = wval; 1467 } 1468 1469 if (bus_type & ASC_IS_VL) { 1470 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL; 1471 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL; 1472 } else { 1473 cfg_beg = ASC_EEP_DVC_CFG_BEG; 1474 cfg_end = ASC_EEP_MAX_DVC_ADDR; 1475 } 1476 1477 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) { 1478 wval = AscReadEEPWord(iot, ioh, s_addr); 1479 sum += wval; 1480 *wbuf = wval; 1481 } 1482 1483 *wbuf = AscReadEEPWord(iot, ioh, s_addr); 1484 1485 return (sum); 1486 } 1487 1488 1489 static int 1490 AscSetEEPConfig(iot, ioh, cfg_buf, bus_type) 1491 bus_space_tag_t iot; 1492 bus_space_handle_t ioh; 1493 ASCEEP_CONFIG *cfg_buf; 1494 u_int16_t bus_type; 1495 { 1496 int retry; 1497 int n_error; 1498 1499 retry = 0; 1500 while (TRUE) { 1501 if ((n_error = AscSetEEPConfigOnce(iot, ioh, cfg_buf, bus_type)) == 0) 1502 break; 1503 1504 if (++retry > ASC_EEP_MAX_RETRY) 1505 break; 1506 } 1507 1508 return (n_error); 1509 } 1510 1511 1512 static int 1513 AscSetEEPConfigOnce(iot, ioh, cfg_buf, bus_type) 1514 bus_space_tag_t iot; 1515 bus_space_handle_t ioh; 1516 ASCEEP_CONFIG *cfg_buf; 1517 u_int16_t bus_type; 1518 { 1519 int n_error; 1520 u_int16_t *wbuf; 1521 u_int16_t sum; 1522 int s_addr; 1523 int cfg_beg; 1524 int cfg_end; 1525 1526 wbuf = (u_int16_t *) cfg_buf; 1527 n_error = 0; 1528 sum = 0; 1529 1530 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) { 1531 sum += *wbuf; 1532 if (*wbuf != AscWriteEEPWord(iot, ioh, s_addr, *wbuf)) 1533 n_error++; 1534 } 1535 1536 if (bus_type & ASC_IS_VL) { 1537 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL; 1538 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL; 1539 } else { 1540 cfg_beg = ASC_EEP_DVC_CFG_BEG; 1541 cfg_end = ASC_EEP_MAX_DVC_ADDR; 1542 } 1543 1544 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) { 1545 sum += *wbuf; 1546 if (*wbuf != AscWriteEEPWord(iot, ioh, s_addr, *wbuf)) 1547 n_error++; 1548 } 1549 1550 *wbuf = sum; 1551 if (sum != AscWriteEEPWord(iot, ioh, s_addr, sum)) 1552 n_error++; 1553 1554 wbuf = (u_int16_t *) cfg_buf; 1555 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) { 1556 if (*wbuf != AscReadEEPWord(iot, ioh, s_addr)) 1557 n_error++; 1558 } 1559 1560 for (s_addr = cfg_beg; s_addr <= cfg_end; s_addr++, wbuf++) { 1561 if (*wbuf != AscReadEEPWord(iot, ioh, s_addr)) 1562 n_error++; 1563 } 1564 1565 return (n_error); 1566 } 1567 1568 1569 #ifdef ASC_DEBUG 1570 static void 1571 AscPrintEEPConfig(eep_config, chksum) 1572 ASCEEP_CONFIG *eep_config; 1573 u_int16_t chksum; 1574 { 1575 printf("---- ASC EEprom settings ----\n"); 1576 printf("cfg_lsw = 0x%x\n", eep_config->cfg_lsw); 1577 printf("cfg_msw = 0x%x\n", eep_config->cfg_msw); 1578 printf("init_sdtr = 0x%x\n", eep_config->init_sdtr); 1579 printf("disc_enable = 0x%x\n", eep_config->disc_enable); 1580 printf("use_cmd_qng = %d\n", eep_config->use_cmd_qng); 1581 printf("start_motor = 0x%x\n", eep_config->start_motor); 1582 printf("max_total_qng = 0x%x\n", eep_config->max_total_qng); 1583 printf("max_tag_qng = 0x%x\n", eep_config->max_tag_qng); 1584 printf("bios_scan = 0x%x\n", eep_config->bios_scan); 1585 printf("power_up_wait = 0x%x\n", eep_config->power_up_wait); 1586 printf("no_scam = %d\n", eep_config->no_scam); 1587 printf("chip_scsi_id = %d\n", eep_config->chip_scsi_id); 1588 printf("isa_dma_speed = %d\n", eep_config->isa_dma_speed); 1589 printf("cntl = 0x%x\n", eep_config->cntl); 1590 #if BYTE_ORDER == BIG_ENDIAN 1591 printf("adapter_info[0] = 0x%x\n", eep_config->adapter_info[1]); 1592 printf("adapter_info[1] = 0x%x\n", eep_config->adapter_info[0]); 1593 printf("adapter_info[2] = 0x%x\n", eep_config->adapter_info[3]); 1594 printf("adapter_info[3] = 0x%x\n", eep_config->adapter_info[2]); 1595 printf("adapter_info[4] = 0x%x\n", eep_config->adapter_info[5]); 1596 printf("adapter_info[5] = 0x%x\n", eep_config->adapter_info[4]); 1597 #else 1598 printf("adapter_info[0] = 0x%x\n", eep_config->adapter_info[0]); 1599 printf("adapter_info[1] = 0x%x\n", eep_config->adapter_info[1]); 1600 printf("adapter_info[2] = 0x%x\n", eep_config->adapter_info[2]); 1601 printf("adapter_info[3] = 0x%x\n", eep_config->adapter_info[3]); 1602 printf("adapter_info[4] = 0x%x\n", eep_config->adapter_info[4]); 1603 printf("adapter_info[5] = 0x%x\n", eep_config->adapter_info[5]); 1604 #endif 1605 printf("checksum = 0x%x\n", eep_config->chksum); 1606 printf("calculated checksum = 0x%x\n", chksum); 1607 printf("-----------------------------\n"); 1608 } 1609 #endif 1610 1611 1612 /******************************************************************************/ 1613 /* Interrupt routines */ 1614 /******************************************************************************/ 1615 1616 1617 int 1618 AscISR(sc) 1619 ASC_SOFTC *sc; 1620 { 1621 bus_space_tag_t iot = sc->sc_iot; 1622 bus_space_handle_t ioh = sc->sc_ioh; 1623 u_int16_t chipstat; 1624 u_int16_t saved_ram_addr; 1625 u_int8_t ctrl_reg; 1626 u_int8_t saved_ctrl_reg; 1627 int int_pending; 1628 int status; 1629 u_int8_t host_flag; 1630 1631 1632 int_pending = FALSE; 1633 1634 ctrl_reg = ASC_GET_CHIP_CONTROL(iot, ioh); 1635 saved_ctrl_reg = ctrl_reg & (~(ASC_CC_SCSI_RESET | ASC_CC_CHIP_RESET | 1636 ASC_CC_SINGLE_STEP | ASC_CC_DIAG | ASC_CC_TEST)); 1637 chipstat = ASC_GET_CHIP_STATUS(iot, ioh); 1638 if (chipstat & ASC_CSW_SCSI_RESET_LATCH) { 1639 if (!(sc->bus_type & (ASC_IS_VL | ASC_IS_EISA))) { 1640 int_pending = TRUE; 1641 sc->sdtr_done = 0; 1642 saved_ctrl_reg &= (u_int8_t) (~ASC_CC_HALT); 1643 1644 while (ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_SCSI_RESET_ACTIVE); 1645 1646 ASC_SET_CHIP_CONTROL(iot, ioh, (ASC_CC_CHIP_RESET | ASC_CC_HALT)); 1647 ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_HALT); 1648 ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_CLR_SCSI_RESET_INT); 1649 ASC_SET_CHIP_STATUS(iot, ioh, 0); 1650 chipstat = ASC_GET_CHIP_STATUS(iot, ioh); 1651 } 1652 } 1653 saved_ram_addr = ASC_GET_CHIP_LRAM_ADDR(iot, ioh); 1654 host_flag = AscReadLramByte(iot, ioh, ASCV_HOST_FLAG_B) & 1655 (u_int8_t) (~ASC_HOST_FLAG_IN_ISR); 1656 AscWriteLramByte(iot, ioh, ASCV_HOST_FLAG_B, 1657 (host_flag | ASC_HOST_FLAG_IN_ISR)); 1658 1659 if ((chipstat & ASC_CSW_INT_PENDING) || (int_pending)) { 1660 AscAckInterrupt(iot, ioh); 1661 int_pending = TRUE; 1662 1663 if ((chipstat & ASC_CSW_HALTED) && 1664 (ctrl_reg & ASC_CC_SINGLE_STEP)) { 1665 AscIsrChipHalted(sc); 1666 saved_ctrl_reg &= ~ASC_CC_HALT; 1667 } else { 1668 if (sc->dvc_cntl & ASC_CNTL_INT_MULTI_Q) { 1669 while (((status = AscIsrQDone(sc)) & 0x01) != 0); 1670 } else { 1671 do { 1672 if ((status = AscIsrQDone(sc)) == 1) 1673 break; 1674 } while (status == 0x11); 1675 } 1676 1677 if (status & 0x80) 1678 int_pending = -1; 1679 } 1680 } 1681 AscWriteLramByte(iot, ioh, ASCV_HOST_FLAG_B, host_flag); 1682 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, saved_ram_addr); 1683 ASC_SET_CHIP_CONTROL(iot, ioh, saved_ctrl_reg); 1684 1685 return (1); 1686 /* return(int_pending); */ 1687 } 1688 1689 1690 static int 1691 AscIsrQDone(sc) 1692 ASC_SOFTC *sc; 1693 { 1694 u_int8_t next_qp; 1695 u_int8_t n_q_used; 1696 u_int8_t sg_list_qp; 1697 u_int8_t sg_queue_cnt; 1698 u_int8_t q_cnt; 1699 u_int8_t done_q_tail; 1700 u_int8_t tid_no; 1701 ASC_SCSI_BIT_ID_TYPE scsi_busy; 1702 ASC_SCSI_BIT_ID_TYPE target_id; 1703 bus_space_tag_t iot = sc->sc_iot; 1704 bus_space_handle_t ioh = sc->sc_ioh; 1705 u_int16_t q_addr; 1706 u_int16_t sg_q_addr; 1707 u_int8_t cur_target_qng; 1708 ASC_QDONE_INFO scsiq_buf; 1709 ASC_QDONE_INFO *scsiq; 1710 ASC_ISR_CALLBACK asc_isr_callback; 1711 1712 1713 asc_isr_callback = (ASC_ISR_CALLBACK) sc->isr_callback; 1714 n_q_used = 1; 1715 scsiq = (ASC_QDONE_INFO *) & scsiq_buf; 1716 done_q_tail = ASC_GET_VAR_DONE_QTAIL(iot, ioh); 1717 q_addr = ASC_QNO_TO_QADDR(done_q_tail); 1718 next_qp = AscReadLramByte(iot, ioh, (q_addr + ASC_SCSIQ_B_FWD)); 1719 1720 if (next_qp != ASC_QLINK_END) { 1721 ASC_PUT_VAR_DONE_QTAIL(iot, ioh, next_qp); 1722 q_addr = ASC_QNO_TO_QADDR(next_qp); 1723 sg_queue_cnt = _AscCopyLramScsiDoneQ(iot, ioh, q_addr, scsiq, 1724 sc->max_dma_count); 1725 AscWriteLramByte(iot, ioh, (q_addr + ASC_SCSIQ_B_STATUS), 1726 (scsiq->q_status & ~(ASC_QS_READY | ASC_QS_ABORTED))); 1727 tid_no = ASC_TIX_TO_TID(scsiq->d2.target_ix); 1728 target_id = ASC_TIX_TO_TARGET_ID(scsiq->d2.target_ix); 1729 if ((scsiq->cntl & ASC_QC_SG_HEAD) != 0) { 1730 sg_q_addr = q_addr; 1731 sg_list_qp = next_qp; 1732 for (q_cnt = 0; q_cnt < sg_queue_cnt; q_cnt++) { 1733 sg_list_qp = AscReadLramByte(iot, ioh, 1734 sg_q_addr + ASC_SCSIQ_B_FWD); 1735 sg_q_addr = ASC_QNO_TO_QADDR(sg_list_qp); 1736 if (sg_list_qp == ASC_QLINK_END) { 1737 AscSetLibErrorCode(sc, ASCQ_ERR_SG_Q_LINKS); 1738 scsiq->d3.done_stat = ASC_QD_WITH_ERROR; 1739 scsiq->d3.host_stat = ASC_QHSTA_D_QDONE_SG_LIST_CORRUPTED; 1740 panic("AscIsrQDone: Corrupted SG list encountered"); 1741 } 1742 AscWriteLramByte(iot, ioh, 1743 sg_q_addr + ASC_SCSIQ_B_STATUS, ASC_QS_FREE); 1744 } 1745 n_q_used = sg_queue_cnt + 1; 1746 ASC_PUT_VAR_DONE_QTAIL(iot, ioh, sg_list_qp); 1747 } 1748 if (sc->queue_full_or_busy & target_id) { 1749 cur_target_qng = AscReadLramByte(iot, ioh, 1750 ASC_QADR_BEG + scsiq->d2.target_ix); 1751 1752 if (cur_target_qng < sc->max_dvc_qng[tid_no]) { 1753 scsi_busy = AscReadLramByte(iot, ioh, ASCV_SCSIBUSY_B); 1754 scsi_busy &= ~target_id; 1755 AscWriteLramByte(iot, ioh, ASCV_SCSIBUSY_B, scsi_busy); 1756 sc->queue_full_or_busy &= ~target_id; 1757 } 1758 } 1759 if (sc->cur_total_qng >= n_q_used) { 1760 sc->cur_total_qng -= n_q_used; 1761 if (sc->cur_dvc_qng[tid_no] != 0) { 1762 sc->cur_dvc_qng[tid_no]--; 1763 } 1764 } else { 1765 AscSetLibErrorCode(sc, ASCQ_ERR_CUR_QNG); 1766 scsiq->d3.done_stat = ASC_QD_WITH_ERROR; 1767 panic("AscIsrQDone: Attempting to free more queues than are active"); 1768 } 1769 1770 if ((scsiq->d2.ccb_ptr == 0UL) || ((scsiq->q_status & ASC_QS_ABORTED) != 0)) { 1771 return (0x11); 1772 } else if (scsiq->q_status == ASC_QS_DONE) { 1773 scsiq->remain_bytes += scsiq->extra_bytes; 1774 1775 if (scsiq->d3.done_stat == ASC_QD_WITH_ERROR) { 1776 if (scsiq->d3.host_stat == ASC_QHSTA_M_DATA_OVER_RUN) { 1777 if ((scsiq->cntl & (ASC_QC_DATA_IN | ASC_QC_DATA_OUT)) == 0) { 1778 scsiq->d3.done_stat = ASC_QD_NO_ERROR; 1779 scsiq->d3.host_stat = ASC_QHSTA_NO_ERROR; 1780 } 1781 } else if (scsiq->d3.host_stat == ASC_QHSTA_M_HUNG_REQ_SCSI_BUS_RESET) { 1782 AscStopChip(iot, ioh); 1783 ASC_SET_CHIP_CONTROL(iot, ioh, (ASC_CC_SCSI_RESET | ASC_CC_HALT)); 1784 DvcDelayNanoSecond(60000); 1785 ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_HALT); 1786 ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_CLR_SCSI_RESET_INT); 1787 ASC_SET_CHIP_STATUS(iot, ioh, 0); 1788 ASC_SET_CHIP_CONTROL(iot, ioh, 0); 1789 } 1790 } 1791 (*asc_isr_callback) (sc, scsiq); 1792 1793 return (1); 1794 } else { 1795 AscSetLibErrorCode(sc, ASCQ_ERR_Q_STATUS); 1796 panic("AscIsrQDone: completed scsiq with unknown status"); 1797 1798 return (0x80); 1799 } 1800 } 1801 return (0); 1802 } 1803 1804 1805 /* 1806 * handle all the conditions that may halt the board 1807 * waiting us to intervene 1808 */ 1809 static void 1810 AscIsrChipHalted(sc) 1811 ASC_SOFTC *sc; 1812 { 1813 bus_space_tag_t iot = sc->sc_iot; 1814 bus_space_handle_t ioh = sc->sc_ioh; 1815 EXT_MSG out_msg; 1816 u_int16_t int_halt_code; 1817 u_int16_t halt_q_addr; 1818 u_int8_t halt_qp; 1819 u_int8_t target_ix; 1820 u_int8_t tag_code; 1821 u_int8_t q_status; 1822 u_int8_t q_cntl; 1823 u_int8_t tid_no; 1824 u_int8_t cur_dvc_qng; 1825 u_int8_t asyn_sdtr; 1826 u_int8_t scsi_status; 1827 u_int8_t sdtr_data; 1828 ASC_SCSI_BIT_ID_TYPE scsi_busy; 1829 ASC_SCSI_BIT_ID_TYPE target_id; 1830 1831 1832 int_halt_code = AscReadLramWord(iot, ioh, ASCV_HALTCODE_W); 1833 1834 halt_qp = AscReadLramByte(iot, ioh, ASCV_CURCDB_B); 1835 halt_q_addr = ASC_QNO_TO_QADDR(halt_qp); 1836 target_ix = AscReadLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_TARGET_IX); 1837 q_cntl = AscReadLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_CNTL); 1838 tid_no = ASC_TIX_TO_TID(target_ix); 1839 target_id = ASC_TID_TO_TARGET_ID(tid_no); 1840 1841 if (sc->pci_fix_asyn_xfer & target_id) { 1842 asyn_sdtr = ASYN_SDTR_DATA_FIX_PCI_REV_AB; 1843 } else { 1844 asyn_sdtr = 0; 1845 } 1846 1847 if (int_halt_code == ASC_HALT_DISABLE_ASYN_USE_SYN_FIX) { 1848 if (sc->pci_fix_asyn_xfer & target_id) { 1849 AscSetChipSDTR(iot, ioh, 0, tid_no); 1850 sc->sdtr_data[tid_no] = 0; 1851 } 1852 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 1853 } else if (int_halt_code == ASC_HALT_ENABLE_ASYN_USE_SYN_FIX) { 1854 if (sc->pci_fix_asyn_xfer & target_id) { 1855 AscSetChipSDTR(iot, ioh, asyn_sdtr, tid_no); 1856 sc->sdtr_data[tid_no] = asyn_sdtr; 1857 } 1858 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 1859 } else if (int_halt_code == ASC_HALT_EXTMSG_IN) { 1860 AscHandleExtMsgIn(sc, halt_q_addr, q_cntl, target_id, 1861 tid_no, asyn_sdtr); 1862 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 1863 } else if (int_halt_code == ASC_HALT_CHK_CONDITION) { 1864 q_cntl |= ASC_QC_REQ_SENSE; 1865 1866 if (sc->init_sdtr & target_id) { 1867 sc->sdtr_done &= ~target_id; 1868 1869 sdtr_data = ASC_GET_MCODE_INIT_SDTR_AT_ID(iot, ioh, tid_no); 1870 q_cntl |= ASC_QC_MSG_OUT; 1871 AscMsgOutSDTR(sc, sc->sdtr_period_tbl[(sdtr_data >> 4) & 1872 (sc->max_sdtr_index - 1)], 1873 (sdtr_data & ASC_SYN_MAX_OFFSET)); 1874 } 1875 AscWriteLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_CNTL, q_cntl); 1876 1877 tag_code = AscReadLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_TAG_CODE); 1878 tag_code &= 0xDC; 1879 1880 if ((sc->pci_fix_asyn_xfer & target_id) && 1881 !(sc->pci_fix_asyn_xfer_always & target_id)) { 1882 tag_code |= (ASC_TAG_FLAG_DISABLE_DISCONNECT | 1883 ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX); 1884 } 1885 AscWriteLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_TAG_CODE, tag_code); 1886 1887 q_status = AscReadLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_STATUS); 1888 q_status |= ASC_QS_READY | ASC_QS_BUSY; 1889 1890 AscWriteLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_STATUS, q_status); 1891 1892 scsi_busy = AscReadLramByte(iot, ioh, ASCV_SCSIBUSY_B); 1893 scsi_busy &= ~target_id; 1894 AscWriteLramByte(iot, ioh, ASCV_SCSIBUSY_B, scsi_busy); 1895 1896 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 1897 } else if (int_halt_code == ASC_HALT_SDTR_REJECTED) { 1898 AscMemWordCopyFromLram(iot, ioh, ASCV_MSGOUT_BEG, 1899 (u_int16_t *) & out_msg, sizeof(EXT_MSG) >> 1); 1900 1901 if ((out_msg.msg_type == MS_EXTEND) && 1902 (out_msg.msg_len == MS_SDTR_LEN) && 1903 (out_msg.msg_req == MS_SDTR_CODE)) { 1904 sc->init_sdtr &= ~target_id; 1905 sc->sdtr_done &= ~target_id; 1906 AscSetChipSDTR(iot, ioh, asyn_sdtr, tid_no); 1907 sc->sdtr_data[tid_no] = asyn_sdtr; 1908 } 1909 q_cntl &= ~ASC_QC_MSG_OUT; 1910 AscWriteLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_CNTL, q_cntl); 1911 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 1912 } else if (int_halt_code == ASC_HALT_SS_QUEUE_FULL) { 1913 scsi_status = AscReadLramByte(iot, ioh, 1914 halt_q_addr + ASC_SCSIQ_SCSI_STATUS); 1915 cur_dvc_qng = AscReadLramByte(iot, ioh, target_ix + ASC_QADR_BEG); 1916 1917 if ((cur_dvc_qng > 0) && (sc->cur_dvc_qng[tid_no] > 0)) { 1918 scsi_busy = AscReadLramByte(iot, ioh, ASCV_SCSIBUSY_B); 1919 scsi_busy |= target_id; 1920 AscWriteLramByte(iot, ioh, ASCV_SCSIBUSY_B, scsi_busy); 1921 sc->queue_full_or_busy |= target_id; 1922 1923 if (scsi_status == SS_QUEUE_FULL) { 1924 if (cur_dvc_qng > ASC_MIN_TAGGED_CMD) { 1925 cur_dvc_qng -= 1; 1926 sc->max_dvc_qng[tid_no] = cur_dvc_qng; 1927 1928 AscWriteLramByte(iot, ioh, 1929 tid_no + ASCV_MAX_DVC_QNG_BEG, cur_dvc_qng); 1930 1931 #if ASC_QUEUE_FLOW_CONTROL 1932 if ((sc->device[tid_no] != NULL) && 1933 (sc->device[tid_no]->queue_curr_depth > cur_dvc_qng)) { 1934 sc->device[tid_no]->queue_curr_depth = cur_dvc_qng; 1935 } 1936 #endif /* ASC_QUEUE_FLOW_CONTROL */ 1937 } 1938 } 1939 } 1940 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 1941 } 1942 return; 1943 } 1944 1945 1946 static int 1947 AscWaitTixISRDone(sc, target_ix) 1948 ASC_SOFTC *sc; 1949 u_int8_t target_ix; 1950 { 1951 u_int8_t cur_req; 1952 u_int8_t tid_no; 1953 int i = 0; 1954 1955 tid_no = ASC_TIX_TO_TID(target_ix); 1956 while (i++ < 10) { 1957 if ((cur_req = sc->cur_dvc_qng[tid_no]) == 0) 1958 break; 1959 1960 DvcSleepMilliSecond(1000L); 1961 if (sc->cur_dvc_qng[tid_no] == cur_req) 1962 break; 1963 } 1964 return (1); 1965 } 1966 1967 static int 1968 AscWaitISRDone(sc) 1969 ASC_SOFTC *sc; 1970 { 1971 int tid; 1972 1973 for (tid = 0; tid <= ASC_MAX_TID; tid++) 1974 AscWaitTixISRDone(sc, ASC_TID_TO_TIX(tid)); 1975 1976 return (1); 1977 } 1978 1979 1980 static u_int8_t 1981 _AscCopyLramScsiDoneQ(iot, ioh, q_addr, scsiq, max_dma_count) 1982 bus_space_tag_t iot; 1983 bus_space_handle_t ioh; 1984 u_int16_t q_addr; 1985 ASC_QDONE_INFO *scsiq; 1986 u_int32_t max_dma_count; 1987 { 1988 u_int16_t _val; 1989 u_int8_t sg_queue_cnt; 1990 1991 AscGetQDoneInfo(iot, ioh, q_addr + ASC_SCSIQ_DONE_INFO_BEG, scsiq); 1992 1993 _val = AscReadLramWord(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS); 1994 scsiq->q_status = LO_BYTE(_val); 1995 scsiq->q_no = HI_BYTE(_val); 1996 _val = AscReadLramWord(iot, ioh, q_addr + ASC_SCSIQ_B_CNTL); 1997 scsiq->cntl = LO_BYTE(_val); 1998 sg_queue_cnt = HI_BYTE(_val); 1999 _val = AscReadLramWord(iot, ioh, q_addr + ASC_SCSIQ_B_SENSE_LEN); 2000 scsiq->sense_len = LO_BYTE(_val); 2001 scsiq->extra_bytes = HI_BYTE(_val); 2002 scsiq->remain_bytes = AscReadLramWord(iot, ioh, 2003 q_addr + ASC_SCSIQ_DW_REMAIN_XFER_CNT); 2004 scsiq->remain_bytes &= max_dma_count; 2005 2006 return (sg_queue_cnt); 2007 } 2008 2009 2010 static void 2011 AscGetQDoneInfo(iot, ioh, addr, scsiq) 2012 bus_space_tag_t iot; 2013 bus_space_handle_t ioh; 2014 u_int16_t addr; 2015 ASC_QDONE_INFO *scsiq; 2016 { 2017 u_int16_t val; 2018 2019 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr); 2020 2021 val = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 2022 scsiq->d2.ccb_ptr = MAKELONG(val, ASC_GET_CHIP_LRAM_DATA(iot, ioh)); 2023 val = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 2024 scsiq->d2.target_ix = LO_BYTE(val); 2025 scsiq->d2.flag = HI_BYTE(val); 2026 val = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 2027 scsiq->d2.cdb_len = LO_BYTE(val); 2028 scsiq->d2.tag_code = HI_BYTE(val); 2029 scsiq->d2.vm_id = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 2030 2031 val = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 2032 scsiq->d3.done_stat = LO_BYTE(val); 2033 scsiq->d3.host_stat = HI_BYTE(val); 2034 val = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 2035 scsiq->d3.scsi_stat = LO_BYTE(val); 2036 scsiq->d3.scsi_msg = HI_BYTE(val); 2037 } 2038 2039 2040 static void 2041 AscToggleIRQAct(iot, ioh) 2042 bus_space_tag_t iot; 2043 bus_space_handle_t ioh; 2044 { 2045 2046 ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_IRQ_ACT); 2047 ASC_SET_CHIP_STATUS(iot, ioh, 0); 2048 } 2049 2050 2051 static void 2052 AscDisableInterrupt(iot, ioh) 2053 bus_space_tag_t iot; 2054 bus_space_handle_t ioh; 2055 { 2056 u_int16_t cfg; 2057 2058 cfg = ASC_GET_CHIP_CFG_LSW(iot, ioh); 2059 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg & (~ASC_CFG0_HOST_INT_ON)); 2060 } 2061 2062 2063 static void 2064 AscEnableInterrupt(iot, ioh) 2065 bus_space_tag_t iot; 2066 bus_space_handle_t ioh; 2067 { 2068 u_int16_t cfg; 2069 2070 cfg = ASC_GET_CHIP_CFG_LSW(iot, ioh); 2071 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg | ASC_CFG0_HOST_INT_ON); 2072 } 2073 2074 2075 static u_int8_t 2076 AscGetChipIRQ(iot, ioh, bus_type) 2077 bus_space_tag_t iot; 2078 bus_space_handle_t ioh; 2079 u_int16_t bus_type; 2080 { 2081 u_int16_t cfg_lsw; 2082 u_int8_t chip_irq; 2083 2084 2085 if (bus_type & ASC_IS_EISA) { 2086 /* 2087 * cfg_lsw = AscGetEisaChipCfg(iot, ioh); chip_irq = 2088 * ((cfg_lsw >> 8) & 0x07) + 10; if((chip_irq == 13) || 2089 * (chip_irq > 15)) return (0); return(chip_irq); 2090 */ 2091 } 2092 if ((bus_type & ASC_IS_VL) != 0) { 2093 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh); 2094 chip_irq = (cfg_lsw >> 2) & 0x07; 2095 if ((chip_irq == 0) || 2096 (chip_irq == 4) || 2097 (chip_irq == 7)) { 2098 return (0); 2099 } 2100 return (chip_irq + (ASC_MIN_IRQ_NO - 1)); 2101 } 2102 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh); 2103 chip_irq = (cfg_lsw >> 2) & 0x03; 2104 if (chip_irq == 3) 2105 chip_irq += 2; 2106 return (chip_irq + ASC_MIN_IRQ_NO); 2107 } 2108 2109 2110 static u_int8_t 2111 AscSetChipIRQ(iot, ioh, irq_no, bus_type) 2112 bus_space_tag_t iot; 2113 bus_space_handle_t ioh; 2114 u_int8_t irq_no; 2115 u_int16_t bus_type; 2116 { 2117 u_int16_t cfg_lsw; 2118 2119 2120 if (bus_type & ASC_IS_VL) { 2121 if (irq_no) { 2122 if ((irq_no < ASC_MIN_IRQ_NO) || (irq_no > ASC_MAX_IRQ_NO)) 2123 irq_no = 0; 2124 else 2125 irq_no -= ASC_MIN_IRQ_NO - 1; 2126 } 2127 2128 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0xFFE3; 2129 cfg_lsw |= 0x0010; 2130 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg_lsw); 2131 AscToggleIRQAct(iot, ioh); 2132 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0xFFE0; 2133 cfg_lsw |= (irq_no & 0x07) << 2; 2134 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg_lsw); 2135 AscToggleIRQAct(iot, ioh); 2136 2137 return (AscGetChipIRQ(iot, ioh, bus_type)); 2138 } 2139 if (bus_type & ASC_IS_ISA) { 2140 if (irq_no == 15) 2141 irq_no -= 2; 2142 irq_no -= ASC_MIN_IRQ_NO; 2143 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0xFFF3; 2144 cfg_lsw |= (irq_no & 0x03) << 2; 2145 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg_lsw); 2146 2147 return (AscGetChipIRQ(iot, ioh, bus_type)); 2148 } 2149 return (0); 2150 } 2151 2152 2153 static void 2154 AscAckInterrupt(iot, ioh) 2155 bus_space_tag_t iot; 2156 bus_space_handle_t ioh; 2157 { 2158 u_int8_t host_flag; 2159 u_int8_t risc_flag; 2160 u_int16_t loop; 2161 2162 2163 loop = 0; 2164 do { 2165 risc_flag = AscReadLramByte(iot, ioh, ASCV_RISC_FLAG_B); 2166 if (loop++ > 0x7FFF) 2167 break; 2168 } while ((risc_flag & ASC_RISC_FLAG_GEN_INT) != 0); 2169 2170 host_flag = AscReadLramByte(iot, ioh, ASCV_HOST_FLAG_B) & 2171 (~ASC_HOST_FLAG_ACK_INT); 2172 AscWriteLramByte(iot, ioh, ASCV_HOST_FLAG_B, 2173 host_flag | ASC_HOST_FLAG_ACK_INT); 2174 ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_INT_ACK); 2175 2176 loop = 0; 2177 while (ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_INT_PENDING) { 2178 ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_INT_ACK); 2179 if (loop++ > 3) 2180 break; 2181 } 2182 2183 AscWriteLramByte(iot, ioh, ASCV_HOST_FLAG_B, host_flag); 2184 } 2185 2186 2187 static u_int32_t 2188 AscGetMaxDmaCount(bus_type) 2189 u_int16_t bus_type; 2190 { 2191 if (bus_type & ASC_IS_ISA) 2192 return (ASC_MAX_ISA_DMA_COUNT); 2193 else if (bus_type & (ASC_IS_EISA | ASC_IS_VL)) 2194 return (ASC_MAX_VL_DMA_COUNT); 2195 return (ASC_MAX_PCI_DMA_COUNT); 2196 } 2197 2198 2199 static u_int16_t 2200 AscGetIsaDmaChannel(iot, ioh) 2201 bus_space_tag_t iot; 2202 bus_space_handle_t ioh; 2203 { 2204 u_int16_t channel; 2205 2206 channel = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0x0003; 2207 if (channel == 0x03) 2208 return (0); 2209 else if (channel == 0x00) 2210 return (7); 2211 return (channel + 4); 2212 } 2213 2214 2215 static u_int16_t 2216 AscSetIsaDmaChannel(iot, ioh, dma_channel) 2217 bus_space_tag_t iot; 2218 bus_space_handle_t ioh; 2219 u_int16_t dma_channel; 2220 { 2221 u_int16_t cfg_lsw; 2222 u_int8_t value; 2223 2224 if ((dma_channel >= 5) && (dma_channel <= 7)) { 2225 if (dma_channel == 7) 2226 value = 0x00; 2227 else 2228 value = dma_channel - 4; 2229 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0xFFFC; 2230 cfg_lsw |= value; 2231 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg_lsw); 2232 return (AscGetIsaDmaChannel(iot, ioh)); 2233 } 2234 return (0); 2235 } 2236 2237 2238 static u_int8_t 2239 AscGetIsaDmaSpeed(iot, ioh) 2240 bus_space_tag_t iot; 2241 bus_space_handle_t ioh; 2242 { 2243 u_int8_t speed_value; 2244 2245 AscSetBank(iot, ioh, 1); 2246 speed_value = ASC_READ_CHIP_DMA_SPEED(iot, ioh); 2247 speed_value &= 0x07; 2248 AscSetBank(iot, ioh, 0); 2249 return (speed_value); 2250 } 2251 2252 2253 static u_int8_t 2254 AscSetIsaDmaSpeed(iot, ioh, speed_value) 2255 bus_space_tag_t iot; 2256 bus_space_handle_t ioh; 2257 u_int8_t speed_value; 2258 { 2259 speed_value &= 0x07; 2260 AscSetBank(iot, ioh, 1); 2261 ASC_WRITE_CHIP_DMA_SPEED(iot, ioh, speed_value); 2262 AscSetBank(iot, ioh, 0); 2263 return (AscGetIsaDmaSpeed(iot, ioh)); 2264 } 2265 2266 2267 /******************************************************************************/ 2268 /* Messages routines */ 2269 /******************************************************************************/ 2270 2271 2272 static void 2273 AscHandleExtMsgIn(sc, halt_q_addr, q_cntl, target_id, tid_no, asyn_sdtr) 2274 ASC_SOFTC *sc; 2275 u_int16_t halt_q_addr; 2276 u_int8_t q_cntl; 2277 ASC_SCSI_BIT_ID_TYPE target_id; 2278 int tid_no; 2279 u_int8_t asyn_sdtr; 2280 { 2281 bus_space_tag_t iot = sc->sc_iot; 2282 bus_space_handle_t ioh = sc->sc_ioh; 2283 EXT_MSG ext_msg; 2284 u_int8_t sdtr_data; 2285 int sdtr_accept; 2286 2287 2288 AscMemWordCopyFromLram(iot, ioh, ASCV_MSGIN_BEG, 2289 (u_int16_t *) & ext_msg, sizeof(EXT_MSG) >> 1); 2290 2291 if (ext_msg.msg_type == MS_EXTEND && 2292 ext_msg.msg_req == MS_SDTR_CODE && 2293 ext_msg.msg_len == MS_SDTR_LEN) { 2294 sdtr_accept = TRUE; 2295 2296 if (ext_msg.req_ack_offset > ASC_SYN_MAX_OFFSET) { 2297 sdtr_accept = FALSE; 2298 ext_msg.req_ack_offset = ASC_SYN_MAX_OFFSET; 2299 } 2300 if ((ext_msg.xfer_period < 2301 sc->sdtr_period_tbl[sc->host_init_sdtr_index]) || 2302 (ext_msg.xfer_period > 2303 sc->sdtr_period_tbl[sc->max_sdtr_index])) { 2304 sdtr_accept = FALSE; 2305 ext_msg.xfer_period = sc->sdtr_period_tbl[sc->host_init_sdtr_index]; 2306 } 2307 if (sdtr_accept) { 2308 sdtr_data = AscCalSDTRData(sc, ext_msg.xfer_period, 2309 ext_msg.req_ack_offset); 2310 if (sdtr_data == 0xFF) { 2311 q_cntl |= ASC_QC_MSG_OUT; 2312 sc->init_sdtr &= ~target_id; 2313 sc->sdtr_done &= ~target_id; 2314 AscSetChipSDTR(iot, ioh, asyn_sdtr, tid_no); 2315 sc->sdtr_data[tid_no] = asyn_sdtr; 2316 } 2317 } 2318 if (ext_msg.req_ack_offset == 0) { 2319 q_cntl &= ~ASC_QC_MSG_OUT; 2320 sc->init_sdtr &= ~target_id; 2321 sc->sdtr_done &= ~target_id; 2322 AscSetChipSDTR(iot, ioh, asyn_sdtr, tid_no); 2323 } else { 2324 if (sdtr_accept && (q_cntl & ASC_QC_MSG_OUT)) { 2325 q_cntl &= ~ASC_QC_MSG_OUT; 2326 sc->sdtr_done |= target_id; 2327 sc->init_sdtr |= target_id; 2328 sc->pci_fix_asyn_xfer &= ~target_id; 2329 sdtr_data = AscCalSDTRData(sc, ext_msg.xfer_period, 2330 ext_msg.req_ack_offset); 2331 AscSetChipSDTR(iot, ioh, sdtr_data, tid_no); 2332 sc->sdtr_data[tid_no] = sdtr_data; 2333 } else { 2334 q_cntl |= ASC_QC_MSG_OUT; 2335 AscMsgOutSDTR(sc, ext_msg.xfer_period, 2336 ext_msg.req_ack_offset); 2337 sc->pci_fix_asyn_xfer &= ~target_id; 2338 sdtr_data = AscCalSDTRData(sc, ext_msg.xfer_period, 2339 ext_msg.req_ack_offset); 2340 AscSetChipSDTR(iot, ioh, sdtr_data, tid_no); 2341 sc->sdtr_data[tid_no] = sdtr_data; 2342 sc->sdtr_done |= target_id; 2343 sc->init_sdtr |= target_id; 2344 } 2345 } 2346 } else if (ext_msg.msg_type == MS_EXTEND && 2347 ext_msg.msg_req == MS_WDTR_CODE && 2348 ext_msg.msg_len == MS_WDTR_LEN) { 2349 ext_msg.wdtr_width = 0; 2350 AscMemWordCopyToLram(iot, ioh, ASCV_MSGOUT_BEG, 2351 (u_int16_t *) & ext_msg, sizeof(EXT_MSG) >> 1); 2352 q_cntl |= ASC_QC_MSG_OUT; 2353 } else { 2354 ext_msg.msg_type = M1_MSG_REJECT; 2355 AscMemWordCopyToLram(iot, ioh, ASCV_MSGOUT_BEG, 2356 (u_int16_t *) & ext_msg, sizeof(EXT_MSG) >> 1); 2357 q_cntl |= ASC_QC_MSG_OUT; 2358 } 2359 2360 AscWriteLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_CNTL, q_cntl); 2361 } 2362 2363 2364 static u_int8_t 2365 AscMsgOutSDTR(sc, sdtr_period, sdtr_offset) 2366 ASC_SOFTC *sc; 2367 u_int8_t sdtr_period; 2368 u_int8_t sdtr_offset; 2369 { 2370 bus_space_tag_t iot = sc->sc_iot; 2371 bus_space_handle_t ioh = sc->sc_ioh; 2372 EXT_MSG sdtr_buf; 2373 u_int8_t sdtr_period_index; 2374 2375 2376 sdtr_buf.msg_type = MS_EXTEND; 2377 sdtr_buf.msg_len = MS_SDTR_LEN; 2378 sdtr_buf.msg_req = MS_SDTR_CODE; 2379 sdtr_buf.xfer_period = sdtr_period; 2380 sdtr_offset &= ASC_SYN_MAX_OFFSET; 2381 sdtr_buf.req_ack_offset = sdtr_offset; 2382 if ((sdtr_period_index = AscGetSynPeriodIndex(sc, sdtr_period)) <= 2383 sc->max_sdtr_index) { 2384 AscMemWordCopyToLram(iot, ioh, ASCV_MSGOUT_BEG, 2385 (u_int16_t *) & sdtr_buf, sizeof(EXT_MSG) >> 1); 2386 return ((sdtr_period_index << 4) | sdtr_offset); 2387 } else { 2388 sdtr_buf.req_ack_offset = 0; 2389 AscMemWordCopyToLram(iot, ioh, ASCV_MSGOUT_BEG, 2390 (u_int16_t *) & sdtr_buf, sizeof(EXT_MSG) >> 1); 2391 return (0); 2392 } 2393 } 2394 2395 2396 /******************************************************************************/ 2397 /* SDTR routines */ 2398 /******************************************************************************/ 2399 2400 2401 static void 2402 AscSetChipSDTR(iot, ioh, sdtr_data, tid_no) 2403 bus_space_tag_t iot; 2404 bus_space_handle_t ioh; 2405 u_int8_t sdtr_data; 2406 u_int8_t tid_no; 2407 { 2408 AscSetChipSynRegAtID(iot, ioh, tid_no, sdtr_data); 2409 AscWriteLramByte(iot, ioh, tid_no + ASCV_SDTR_DONE_BEG, sdtr_data); 2410 } 2411 2412 2413 static u_int8_t 2414 AscCalSDTRData(sc, sdtr_period, syn_offset) 2415 ASC_SOFTC *sc; 2416 u_int8_t sdtr_period; 2417 u_int8_t syn_offset; 2418 { 2419 u_int8_t byte; 2420 u_int8_t sdtr_period_ix; 2421 2422 sdtr_period_ix = AscGetSynPeriodIndex(sc, sdtr_period); 2423 if (sdtr_period_ix > sc->max_sdtr_index) 2424 return (0xFF); 2425 2426 byte = (sdtr_period_ix << 4) | (syn_offset & ASC_SYN_MAX_OFFSET); 2427 return (byte); 2428 } 2429 2430 2431 static u_int8_t 2432 AscGetSynPeriodIndex(sc, syn_time) 2433 ASC_SOFTC *sc; 2434 u_int8_t syn_time; 2435 { 2436 u_int8_t *period_table; 2437 int max_index; 2438 int min_index; 2439 int i; 2440 2441 period_table = sc->sdtr_period_tbl; 2442 max_index = sc->max_sdtr_index; 2443 min_index = sc->host_init_sdtr_index; 2444 if ((syn_time <= period_table[max_index])) { 2445 for (i = min_index; i < (max_index - 1); i++) { 2446 if (syn_time <= period_table[i]) 2447 return (i); 2448 } 2449 2450 return (max_index); 2451 } else 2452 return (max_index + 1); 2453 } 2454 2455 2456 /******************************************************************************/ 2457 /* Queue routines */ 2458 /******************************************************************************/ 2459 2460 /* 2461 * Send a command to the board 2462 */ 2463 int 2464 AscExeScsiQueue(sc, scsiq) 2465 ASC_SOFTC *sc; 2466 ASC_SCSI_Q *scsiq; 2467 { 2468 bus_space_tag_t iot = sc->sc_iot; 2469 bus_space_handle_t ioh = sc->sc_ioh; 2470 ASC_SG_HEAD *sg_head = scsiq->sg_head; 2471 int retval; 2472 int n_q_required; 2473 int disable_syn_offset_one_fix; 2474 int i; 2475 u_int32_t addr; 2476 u_int16_t sg_entry_cnt = 0; 2477 u_int16_t sg_entry_cnt_minus_one = 0; 2478 u_int8_t target_ix; 2479 u_int8_t tid_no; 2480 u_int8_t sdtr_data; 2481 u_int8_t extra_bytes; 2482 u_int8_t scsi_cmd; 2483 u_int32_t data_cnt; 2484 2485 2486 scsiq->q1.q_no = 0; 2487 if ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0) 2488 scsiq->q1.extra_bytes = 0; 2489 2490 retval = ASC_BUSY; 2491 target_ix = scsiq->q2.target_ix; 2492 tid_no = ASC_TIX_TO_TID(target_ix); 2493 n_q_required = 1; 2494 2495 if (scsiq->cdbptr[0] == SCSICMD_RequestSense) 2496 if ((sc->init_sdtr & scsiq->q1.target_id) != 0) { 2497 sc->sdtr_done &= ~scsiq->q1.target_id; 2498 sdtr_data = ASC_GET_MCODE_INIT_SDTR_AT_ID(iot, ioh, tid_no); 2499 AscMsgOutSDTR(sc, sc->sdtr_period_tbl[(sdtr_data >> 4) & 2500 (sc->max_sdtr_index - 1)], 2501 sdtr_data & ASC_SYN_MAX_OFFSET); 2502 scsiq->q1.cntl |= (ASC_QC_MSG_OUT | ASC_QC_URGENT); 2503 } 2504 /* 2505 * if there is just one segment into S/G list then 2506 * map it as it was a single request, filling 2507 * data_addr and data_cnt of ASC_SCSIQ structure. 2508 */ 2509 if ((scsiq->q1.cntl & ASC_QC_SG_HEAD) != 0) { 2510 sg_entry_cnt = sg_head->entry_cnt; 2511 2512 if (sg_entry_cnt < 1) 2513 panic("AscExeScsiQueue: Queue with QC_SG_HEAD set but %d segs.", 2514 sg_entry_cnt); 2515 2516 if (sg_entry_cnt > ASC_MAX_SG_LIST) 2517 panic("AscExeScsiQueue: Queue with too many segs."); 2518 2519 if (sg_entry_cnt == 1) { 2520 scsiq->q1.data_addr = sg_head->sg_list[0].addr; 2521 scsiq->q1.data_cnt = sg_head->sg_list[0].bytes; 2522 scsiq->q1.cntl &= ~(ASC_QC_SG_HEAD | ASC_QC_SG_SWAP_QUEUE); 2523 } 2524 sg_entry_cnt_minus_one = sg_entry_cnt - 1; 2525 } 2526 scsi_cmd = scsiq->cdbptr[0]; 2527 disable_syn_offset_one_fix = FALSE; 2528 if ((sc->pci_fix_asyn_xfer & scsiq->q1.target_id) && 2529 !(sc->pci_fix_asyn_xfer_always & scsiq->q1.target_id)) { 2530 if (scsiq->q1.cntl & ASC_QC_SG_HEAD) { 2531 data_cnt = 0; 2532 for (i = 0; i < sg_entry_cnt; i++) 2533 data_cnt += sg_head->sg_list[i].bytes; 2534 } else { 2535 data_cnt = scsiq->q1.data_cnt; 2536 } 2537 2538 if (data_cnt != 0ul) { 2539 if (data_cnt < 512ul) { 2540 disable_syn_offset_one_fix = TRUE; 2541 } else { 2542 if (scsi_cmd == SCSICMD_Inquiry || 2543 scsi_cmd == SCSICMD_RequestSense || 2544 scsi_cmd == SCSICMD_ReadCapacity || 2545 scsi_cmd == SCSICMD_ReadTOC || 2546 scsi_cmd == SCSICMD_ModeSelect6 || 2547 scsi_cmd == SCSICMD_ModeSense6 || 2548 scsi_cmd == SCSICMD_ModeSelect10 || 2549 scsi_cmd == SCSICMD_ModeSense10) { 2550 disable_syn_offset_one_fix = TRUE; 2551 } 2552 } 2553 } 2554 } 2555 if (disable_syn_offset_one_fix) { 2556 scsiq->q2.tag_code &= ~M2_QTAG_MSG_SIMPLE; 2557 scsiq->q2.tag_code |= (ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX | 2558 ASC_TAG_FLAG_DISABLE_DISCONNECT); 2559 } else { 2560 scsiq->q2.tag_code &= 0x23; 2561 } 2562 2563 if ((scsiq->q1.cntl & ASC_QC_SG_HEAD) != 0) { 2564 if (sc->bug_fix_cntl) { 2565 if (sc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) { 2566 if ((scsi_cmd == SCSICMD_Read6) || (scsi_cmd == SCSICMD_Read10)) { 2567 addr = sg_head->sg_list[sg_entry_cnt_minus_one].addr + 2568 sg_head->sg_list[sg_entry_cnt_minus_one].bytes; 2569 extra_bytes = addr & 0x0003; 2570 if ((extra_bytes != 0) && 2571 ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0)) { 2572 scsiq->q2.tag_code |= ASC_TAG_FLAG_EXTRA_BYTES; 2573 scsiq->q1.extra_bytes = extra_bytes; 2574 sg_head->sg_list[sg_entry_cnt_minus_one].bytes -= 2575 extra_bytes; 2576 } 2577 } 2578 } 2579 } 2580 sg_head->entry_to_copy = sg_head->entry_cnt; 2581 n_q_required = AscSgListToQueue(sg_entry_cnt); 2582 if ((AscGetNumOfFreeQueue(sc, target_ix, n_q_required) >= n_q_required) 2583 || ((scsiq->q1.cntl & ASC_QC_URGENT) != 0)) { 2584 retval = AscSendScsiQueue(sc, scsiq, n_q_required); 2585 } 2586 } else { 2587 if (sc->bug_fix_cntl) { 2588 if (sc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) { 2589 if ((scsi_cmd == SCSICMD_Read6) || (scsi_cmd == SCSICMD_Read10)) { 2590 addr = scsiq->q1.data_addr + scsiq->q1.data_cnt; 2591 extra_bytes = addr & 0x0003; 2592 if ((extra_bytes != 0) && 2593 ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0)) { 2594 if ((scsiq->q1.data_cnt & 0x01FF) == 0) { 2595 scsiq->q2.tag_code |= ASC_TAG_FLAG_EXTRA_BYTES; 2596 scsiq->q1.data_cnt -= extra_bytes; 2597 scsiq->q1.extra_bytes = extra_bytes; 2598 } 2599 } 2600 } 2601 } 2602 } 2603 n_q_required = 1; 2604 if ((AscGetNumOfFreeQueue(sc, target_ix, 1) >= 1) || 2605 ((scsiq->q1.cntl & ASC_QC_URGENT) != 0)) { 2606 retval = AscSendScsiQueue(sc, scsiq, n_q_required); 2607 } 2608 } 2609 2610 return (retval); 2611 } 2612 2613 2614 static int 2615 AscSendScsiQueue(sc, scsiq, n_q_required) 2616 ASC_SOFTC *sc; 2617 ASC_SCSI_Q *scsiq; 2618 u_int8_t n_q_required; 2619 { 2620 bus_space_tag_t iot = sc->sc_iot; 2621 bus_space_handle_t ioh = sc->sc_ioh; 2622 u_int8_t free_q_head; 2623 u_int8_t next_qp; 2624 u_int8_t tid_no; 2625 u_int8_t target_ix; 2626 int retval; 2627 2628 2629 target_ix = scsiq->q2.target_ix; 2630 tid_no = ASC_TIX_TO_TID(target_ix); 2631 retval = ASC_BUSY; 2632 free_q_head = ASC_GET_VAR_FREE_QHEAD(iot, ioh); 2633 2634 if ((next_qp = AscAllocMultipleFreeQueue(iot, ioh, free_q_head, n_q_required)) 2635 != ASC_QLINK_END) { 2636 if (n_q_required > 1) { 2637 sc->last_q_shortage = 0; 2638 scsiq->sg_head->queue_cnt = n_q_required - 1; 2639 } 2640 scsiq->q1.q_no = free_q_head; 2641 2642 if ((retval = AscPutReadySgListQueue(sc, scsiq, free_q_head)) == ASC_NOERROR) { 2643 ASC_PUT_VAR_FREE_QHEAD(iot, ioh, next_qp); 2644 sc->cur_total_qng += n_q_required; 2645 sc->cur_dvc_qng[tid_no]++; 2646 } 2647 } 2648 return (retval); 2649 } 2650 2651 2652 static int 2653 AscPutReadySgListQueue(sc, scsiq, q_no) 2654 ASC_SOFTC *sc; 2655 ASC_SCSI_Q *scsiq; 2656 u_int8_t q_no; 2657 { 2658 bus_space_tag_t iot = sc->sc_iot; 2659 bus_space_handle_t ioh = sc->sc_ioh; 2660 int retval; 2661 int i; 2662 ASC_SG_HEAD *sg_head; 2663 ASC_SG_LIST_Q scsi_sg_q; 2664 u_int32_t saved_data_addr; 2665 u_int32_t saved_data_cnt; 2666 u_int16_t sg_list_dwords; 2667 u_int16_t sg_index; 2668 u_int16_t sg_entry_cnt; 2669 u_int16_t q_addr; 2670 u_int8_t next_qp; 2671 2672 2673 saved_data_addr = scsiq->q1.data_addr; 2674 saved_data_cnt = scsiq->q1.data_cnt; 2675 2676 if ((sg_head = scsiq->sg_head) != 0) { 2677 scsiq->q1.data_addr = sg_head->sg_list[0].addr; 2678 scsiq->q1.data_cnt = sg_head->sg_list[0].bytes; 2679 sg_entry_cnt = sg_head->entry_cnt - 1; 2680 if (sg_entry_cnt != 0) { 2681 q_addr = ASC_QNO_TO_QADDR(q_no); 2682 sg_index = 1; 2683 scsiq->q1.sg_queue_cnt = sg_head->queue_cnt; 2684 scsi_sg_q.sg_head_qp = q_no; 2685 scsi_sg_q.cntl = ASC_QCSG_SG_XFER_LIST; 2686 2687 for (i = 0; i < sg_head->queue_cnt; i++) { 2688 scsi_sg_q.seq_no = i + 1; 2689 if (sg_entry_cnt > ASC_SG_LIST_PER_Q) { 2690 sg_list_dwords = ASC_SG_LIST_PER_Q * 2; 2691 sg_entry_cnt -= ASC_SG_LIST_PER_Q; 2692 if (i == 0) { 2693 scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q; 2694 scsi_sg_q.sg_cur_list_cnt = ASC_SG_LIST_PER_Q; 2695 } else { 2696 scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q - 1; 2697 scsi_sg_q.sg_cur_list_cnt = ASC_SG_LIST_PER_Q - 1; 2698 } 2699 } else { 2700 scsi_sg_q.cntl |= ASC_QCSG_SG_XFER_END; 2701 sg_list_dwords = sg_entry_cnt << 1; 2702 if (i == 0) { 2703 scsi_sg_q.sg_list_cnt = sg_entry_cnt; 2704 scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt; 2705 } else { 2706 scsi_sg_q.sg_list_cnt = sg_entry_cnt - 1; 2707 scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt - 1; 2708 } 2709 2710 sg_entry_cnt = 0; 2711 } 2712 2713 next_qp = AscReadLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_FWD); 2714 scsi_sg_q.q_no = next_qp; 2715 q_addr = ASC_QNO_TO_QADDR(next_qp); 2716 2717 /* 2718 * Tell the board how many entries are in the S/G list 2719 */ 2720 AscMemWordCopyToLram(iot, ioh, q_addr + ASC_SCSIQ_SGHD_CPY_BEG, 2721 (u_int16_t *) & scsi_sg_q, 2722 sizeof(ASC_SG_LIST_Q) >> 1); 2723 /* 2724 * Tell the board the addresses of the S/G list segments 2725 */ 2726 AscMemDWordCopyToLram(iot, ioh, q_addr + ASC_SGQ_LIST_BEG, 2727 (u_int32_t *) & sg_head->sg_list[sg_index], 2728 sg_list_dwords); 2729 sg_index += ASC_SG_LIST_PER_Q; 2730 } 2731 } 2732 } 2733 retval = AscPutReadyQueue(sc, scsiq, q_no); 2734 scsiq->q1.data_addr = saved_data_addr; 2735 scsiq->q1.data_cnt = saved_data_cnt; 2736 return (retval); 2737 } 2738 2739 2740 static int 2741 AscPutReadyQueue(sc, scsiq, q_no) 2742 ASC_SOFTC *sc; 2743 ASC_SCSI_Q *scsiq; 2744 u_int8_t q_no; 2745 { 2746 bus_space_tag_t iot = sc->sc_iot; 2747 bus_space_handle_t ioh = sc->sc_ioh; 2748 u_int16_t q_addr; 2749 u_int8_t tid_no; 2750 u_int8_t sdtr_data; 2751 u_int8_t syn_period_ix; 2752 u_int8_t syn_offset; 2753 2754 2755 if (((sc->init_sdtr & scsiq->q1.target_id) != 0) && 2756 ((sc->sdtr_done & scsiq->q1.target_id) == 0)) { 2757 tid_no = ASC_TIX_TO_TID(scsiq->q2.target_ix); 2758 sdtr_data = ASC_GET_MCODE_INIT_SDTR_AT_ID(iot, ioh, tid_no); 2759 syn_period_ix = (sdtr_data >> 4) & (sc->max_sdtr_index - 1); 2760 syn_offset = sdtr_data & ASC_SYN_MAX_OFFSET; 2761 AscMsgOutSDTR(sc, sc->sdtr_period_tbl[syn_period_ix], syn_offset); 2762 scsiq->q1.cntl |= ASC_QC_MSG_OUT; 2763 } 2764 q_addr = ASC_QNO_TO_QADDR(q_no); 2765 2766 if ((scsiq->q1.target_id & sc->use_tagged_qng) == 0) { 2767 scsiq->q2.tag_code &= ~M2_QTAG_MSG_SIMPLE; 2768 } 2769 scsiq->q1.status = ASC_QS_FREE; 2770 AscMemWordCopyToLram(iot, ioh, q_addr + ASC_SCSIQ_CDB_BEG, 2771 (u_int16_t *) scsiq->cdbptr, scsiq->q2.cdb_len >> 1); 2772 2773 AscPutSCSIQ(iot, ioh, q_addr + ASC_SCSIQ_CPY_BEG, scsiq); 2774 2775 /* 2776 * Let's start the command 2777 */ 2778 AscWriteLramWord(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS, 2779 (scsiq->q1.q_no << 8) | ASC_QS_READY); 2780 2781 return (ASC_NOERROR); 2782 } 2783 2784 2785 static void 2786 AscPutSCSIQ(iot, ioh, addr, scsiq) 2787 bus_space_tag_t iot; 2788 bus_space_handle_t ioh; 2789 u_int16_t addr; 2790 ASC_SCSI_Q *scsiq; 2791 { 2792 u_int16_t val; 2793 2794 2795 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr); 2796 2797 /* ASC_SCSIQ_1 */ 2798 val = MAKEWORD(scsiq->q1.cntl, scsiq->q1.sg_queue_cnt); 2799 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2800 val = MAKEWORD(scsiq->q1.target_id, scsiq->q1.target_lun); 2801 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2802 val = LO_WORD(scsiq->q1.data_addr); 2803 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2804 val = HI_WORD(scsiq->q1.data_addr); 2805 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2806 val = LO_WORD(scsiq->q1.data_cnt); 2807 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2808 val = HI_WORD(scsiq->q1.data_cnt); 2809 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2810 val = LO_WORD(scsiq->q1.sense_addr); 2811 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2812 val = HI_WORD(scsiq->q1.sense_addr); 2813 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2814 val = MAKEWORD(scsiq->q1.sense_len, scsiq->q1.extra_bytes); 2815 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2816 2817 /* ASC_SCSIQ_2 */ 2818 val = LO_WORD(scsiq->q2.ccb_ptr); 2819 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2820 val = HI_WORD(scsiq->q2.ccb_ptr); 2821 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2822 val = MAKEWORD(scsiq->q2.target_ix, scsiq->q2.flag); 2823 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2824 val = MAKEWORD(scsiq->q2.cdb_len, scsiq->q2.tag_code); 2825 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2826 ASC_SET_CHIP_LRAM_DATA(iot, ioh, scsiq->q2.vm_id); 2827 } 2828 2829 2830 static int 2831 AscSgListToQueue(sg_list) 2832 int sg_list; 2833 { 2834 int n_sg_list_qs; 2835 2836 n_sg_list_qs = ((sg_list - 1) / ASC_SG_LIST_PER_Q); 2837 if (((sg_list - 1) % ASC_SG_LIST_PER_Q) != 0) 2838 n_sg_list_qs++; 2839 2840 return (n_sg_list_qs + 1); 2841 } 2842 2843 2844 static u_int 2845 AscGetNumOfFreeQueue(sc, target_ix, n_qs) 2846 ASC_SOFTC *sc; 2847 u_int8_t target_ix; 2848 u_int8_t n_qs; 2849 { 2850 u_int cur_used_qs; 2851 u_int cur_free_qs; 2852 2853 2854 if (n_qs == 1) { 2855 cur_used_qs = sc->cur_total_qng + 2856 sc->last_q_shortage + 2857 ASC_MIN_FREE_Q; 2858 } else { 2859 cur_used_qs = sc->cur_total_qng + ASC_MIN_FREE_Q; 2860 } 2861 2862 if ((cur_used_qs + n_qs) <= sc->max_total_qng) { 2863 cur_free_qs = sc->max_total_qng - cur_used_qs; 2864 return (cur_free_qs); 2865 } 2866 if (n_qs > 1) 2867 if ((n_qs > sc->last_q_shortage) && 2868 (n_qs <= (sc->max_total_qng - ASC_MIN_FREE_Q))) { 2869 sc->last_q_shortage = n_qs; 2870 } 2871 return (0); 2872 } 2873 2874 2875 static u_int8_t 2876 AscAllocFreeQueue(iot, ioh, free_q_head) 2877 bus_space_tag_t iot; 2878 bus_space_handle_t ioh; 2879 u_int8_t free_q_head; 2880 { 2881 u_int16_t q_addr; 2882 u_int8_t next_qp; 2883 u_int8_t q_status; 2884 2885 2886 q_addr = ASC_QNO_TO_QADDR(free_q_head); 2887 q_status = AscReadLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS); 2888 next_qp = AscReadLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_FWD); 2889 if (((q_status & ASC_QS_READY) == 0) && (next_qp != ASC_QLINK_END)) 2890 return (next_qp); 2891 2892 return (ASC_QLINK_END); 2893 } 2894 2895 2896 static u_int8_t 2897 AscAllocMultipleFreeQueue(iot, ioh, free_q_head, n_free_q) 2898 bus_space_tag_t iot; 2899 bus_space_handle_t ioh; 2900 u_int8_t free_q_head; 2901 u_int8_t n_free_q; 2902 { 2903 u_int8_t i; 2904 2905 for (i = 0; i < n_free_q; i++) { 2906 free_q_head = AscAllocFreeQueue(iot, ioh, free_q_head); 2907 if (free_q_head == ASC_QLINK_END) 2908 break; 2909 } 2910 2911 return (free_q_head); 2912 } 2913 2914 2915 static int 2916 AscStopQueueExe(iot, ioh) 2917 bus_space_tag_t iot; 2918 bus_space_handle_t ioh; 2919 { 2920 int count = 0; 2921 2922 if (AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B) == 0) { 2923 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, ASC_STOP_REQ_RISC_STOP); 2924 do { 2925 if (AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B) & 2926 ASC_STOP_ACK_RISC_STOP) 2927 return (1); 2928 2929 DvcSleepMilliSecond(100); 2930 } while (count++ < 20); 2931 } 2932 return (0); 2933 } 2934 2935 2936 static void 2937 AscStartQueueExe(iot, ioh) 2938 bus_space_tag_t iot; 2939 bus_space_handle_t ioh; 2940 { 2941 2942 if (AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B) != 0) 2943 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, 0); 2944 } 2945 2946 2947 static void 2948 AscCleanUpBusyQueue(iot, ioh) 2949 bus_space_tag_t iot; 2950 bus_space_handle_t ioh; 2951 { 2952 int count = 0; 2953 u_int8_t stop_code; 2954 2955 2956 if (AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B) != 0) { 2957 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, ASC_STOP_CLEAN_UP_BUSY_Q); 2958 do { 2959 stop_code = AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B); 2960 if ((stop_code & ASC_STOP_CLEAN_UP_BUSY_Q) == 0) 2961 break; 2962 2963 DvcSleepMilliSecond(100); 2964 } while (count++ < 20); 2965 } 2966 } 2967 2968 2969 static int 2970 _AscWaitQDone(iot, ioh, scsiq) 2971 bus_space_tag_t iot; 2972 bus_space_handle_t ioh; 2973 ASC_SCSI_Q *scsiq; 2974 { 2975 u_int16_t q_addr; 2976 u_int8_t q_status; 2977 int count = 0; 2978 2979 while (scsiq->q1.q_no == 0); 2980 2981 q_addr = ASC_QNO_TO_QADDR(scsiq->q1.q_no); 2982 do { 2983 q_status = AscReadLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS); 2984 DvcSleepMilliSecond(100L); 2985 if (count++ > 30) 2986 return (0); 2987 2988 } while ((q_status & ASC_QS_READY) != 0); 2989 2990 return (1); 2991 } 2992 2993 2994 static int 2995 AscCleanUpDiscQueue(iot, ioh) 2996 bus_space_tag_t iot; 2997 bus_space_handle_t ioh; 2998 { 2999 int count; 3000 u_int8_t stop_code; 3001 3002 count = 0; 3003 if (AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B) != 0) { 3004 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, ASC_STOP_CLEAN_UP_DISC_Q); 3005 do { 3006 stop_code = AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B); 3007 if ((stop_code & ASC_STOP_CLEAN_UP_DISC_Q) == 0) 3008 break; 3009 3010 DvcSleepMilliSecond(100); 3011 } while (count++ < 20); 3012 } 3013 return (1); 3014 } 3015 3016 3017 /******************************************************************************/ 3018 /* Abort and Reset CCB routines */ 3019 /******************************************************************************/ 3020 3021 3022 int 3023 AscAbortCCB(sc, ccb) 3024 ASC_SOFTC *sc; 3025 u_int32_t ccb; 3026 { 3027 bus_space_tag_t iot = sc->sc_iot; 3028 bus_space_handle_t ioh = sc->sc_ioh; 3029 int retval; 3030 ASC_SCSI_BIT_ID_TYPE saved_unit_not_ready; 3031 3032 3033 retval = -1; 3034 saved_unit_not_ready = sc->unit_not_ready; 3035 sc->unit_not_ready = 0xFF; 3036 AscWaitISRDone(sc); 3037 if (AscStopQueueExe(iot, ioh) == 1) { 3038 if (AscRiscHaltedAbortCCB(sc, ccb) == 1) { 3039 retval = 1; 3040 AscCleanUpBusyQueue(iot, ioh); 3041 AscStartQueueExe(iot, ioh); 3042 } else { 3043 retval = 0; 3044 AscStartQueueExe(iot, ioh); 3045 } 3046 } 3047 sc->unit_not_ready = saved_unit_not_ready; 3048 3049 return (retval); 3050 } 3051 3052 3053 static int 3054 AscRiscHaltedAbortCCB(sc, ccb) 3055 ASC_SOFTC *sc; 3056 u_int32_t ccb; 3057 { 3058 bus_space_tag_t iot = sc->sc_iot; 3059 bus_space_handle_t ioh = sc->sc_ioh; 3060 u_int16_t q_addr; 3061 u_int8_t q_no; 3062 ASC_QDONE_INFO scsiq_buf; 3063 ASC_QDONE_INFO *scsiq; 3064 ASC_ISR_CALLBACK asc_isr_callback; 3065 int last_int_level; 3066 3067 3068 asc_isr_callback = (ASC_ISR_CALLBACK) sc->isr_callback; 3069 last_int_level = DvcEnterCritical(); 3070 scsiq = (ASC_QDONE_INFO *) & scsiq_buf; 3071 3072 for (q_no = ASC_MIN_ACTIVE_QNO; q_no <= sc->max_total_qng; q_no++) { 3073 q_addr = ASC_QNO_TO_QADDR(q_no); 3074 scsiq->d2.ccb_ptr = AscReadLramDWord(iot, ioh, 3075 q_addr + ASC_SCSIQ_D_CCBPTR); 3076 if (scsiq->d2.ccb_ptr == ccb) { 3077 _AscCopyLramScsiDoneQ(iot, ioh, q_addr, scsiq, sc->max_dma_count); 3078 if (((scsiq->q_status & ASC_QS_READY) != 0) 3079 && ((scsiq->q_status & ASC_QS_ABORTED) == 0) 3080 && ((scsiq->cntl & ASC_QCSG_SG_XFER_LIST) == 0)) { 3081 scsiq->q_status |= ASC_QS_ABORTED; 3082 scsiq->d3.done_stat = ASC_QD_ABORTED_BY_HOST; 3083 AscWriteLramDWord(iot, ioh, q_addr + ASC_SCSIQ_D_CCBPTR, 0L); 3084 AscWriteLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS, 3085 scsiq->q_status); 3086 (*asc_isr_callback) (sc, scsiq); 3087 DvcLeaveCritical(last_int_level); 3088 return (1); 3089 } 3090 } 3091 } 3092 3093 DvcLeaveCritical(last_int_level); 3094 return (0); 3095 } 3096 3097 3098 static int 3099 AscRiscHaltedAbortTIX(sc, target_ix) 3100 ASC_SOFTC *sc; 3101 u_int8_t target_ix; 3102 { 3103 bus_space_tag_t iot = sc->sc_iot; 3104 bus_space_handle_t ioh = sc->sc_ioh; 3105 u_int16_t q_addr; 3106 u_int8_t q_no; 3107 ASC_QDONE_INFO scsiq_buf; 3108 ASC_QDONE_INFO *scsiq; 3109 ASC_ISR_CALLBACK asc_isr_callback; 3110 int last_int_level; 3111 3112 3113 asc_isr_callback = (ASC_ISR_CALLBACK) sc->isr_callback; 3114 last_int_level = DvcEnterCritical(); 3115 scsiq = (ASC_QDONE_INFO *) & scsiq_buf; 3116 for (q_no = ASC_MIN_ACTIVE_QNO; q_no <= sc->max_total_qng; q_no++) { 3117 q_addr = ASC_QNO_TO_QADDR(q_no); 3118 _AscCopyLramScsiDoneQ(iot, ioh, q_addr, scsiq, sc->max_dma_count); 3119 if (((scsiq->q_status & ASC_QS_READY) != 0) && 3120 ((scsiq->q_status & ASC_QS_ABORTED) == 0) && 3121 ((scsiq->cntl & ASC_QCSG_SG_XFER_LIST) == 0)) { 3122 if (scsiq->d2.target_ix == target_ix) { 3123 scsiq->q_status |= ASC_QS_ABORTED; 3124 scsiq->d3.done_stat = ASC_QD_ABORTED_BY_HOST; 3125 AscWriteLramDWord(iot, ioh, q_addr + ASC_SCSIQ_D_CCBPTR, 0L); 3126 AscWriteLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS, 3127 scsiq->q_status); 3128 (*asc_isr_callback) (sc, scsiq); 3129 } 3130 } 3131 } 3132 DvcLeaveCritical(last_int_level); 3133 return (1); 3134 } 3135 3136 3137 /* 3138 * AscResetDevice calls _AscWaitQDone which requires interrupt enabled, 3139 * so we cannot use this function with the actual NetBSD SCSI layer 3140 * because at boot time interrupts are disabled. 3141 */ 3142 int 3143 AscResetDevice(sc, target_ix) 3144 ASC_SOFTC *sc; 3145 u_char target_ix; 3146 { 3147 bus_space_tag_t iot = sc->sc_iot; 3148 bus_space_handle_t ioh = sc->sc_ioh; 3149 int retval; 3150 u_int8_t tid_no; 3151 ASC_SCSI_BIT_ID_TYPE target_id; 3152 int i; 3153 ASC_SCSI_REQ_Q scsiq_buf; 3154 ASC_SCSI_REQ_Q *scsiq; 3155 u_int8_t *buf; 3156 ASC_SCSI_BIT_ID_TYPE saved_unit_not_ready; 3157 3158 3159 tid_no = ASC_TIX_TO_TID(target_ix); 3160 target_id = ASC_TID_TO_TARGET_ID(tid_no); 3161 saved_unit_not_ready = sc->unit_not_ready; 3162 sc->unit_not_ready = target_id; 3163 retval = ASC_ERROR; 3164 3165 AscWaitTixISRDone(sc, target_ix); 3166 3167 if (AscStopQueueExe(iot, ioh) == 1) { 3168 if (AscRiscHaltedAbortTIX(sc, target_ix) == 1) { 3169 AscCleanUpBusyQueue(iot, ioh); 3170 AscStartQueueExe(iot, ioh); 3171 AscWaitTixISRDone(sc, target_ix); 3172 retval = ASC_NOERROR; 3173 scsiq = (ASC_SCSI_REQ_Q *) & scsiq_buf; 3174 buf = (u_char *) & scsiq_buf; 3175 for (i = 0; i < sizeof(ASC_SCSI_REQ_Q); i++) 3176 *buf++ = 0x00; 3177 scsiq->q1.status = (u_char) ASC_QS_READY; 3178 scsiq->q2.cdb_len = 6; 3179 scsiq->q2.tag_code = M2_QTAG_MSG_SIMPLE; 3180 scsiq->q1.target_id = target_id; 3181 scsiq->q2.target_ix = ASC_TIDLUN_TO_IX(tid_no, 0); 3182 scsiq->cdbptr = (u_int8_t *) scsiq->cdb; 3183 scsiq->q1.cntl = ASC_QC_NO_CALLBACK | ASC_QC_MSG_OUT | ASC_QC_URGENT; 3184 AscWriteLramByte(iot, ioh, ASCV_MSGOUT_BEG, M1_BUS_DVC_RESET); 3185 sc->unit_not_ready &= ~target_id; 3186 sc->sdtr_done |= target_id; 3187 if (AscExeScsiQueue(sc, (ASC_SCSI_Q *) scsiq) == ASC_NOERROR) { 3188 sc->unit_not_ready = target_id; 3189 DvcSleepMilliSecond(1000); 3190 _AscWaitQDone(iot, ioh, (ASC_SCSI_Q *) scsiq); 3191 if (AscStopQueueExe(iot, ioh) == ASC_NOERROR) { 3192 AscCleanUpDiscQueue(iot, ioh); 3193 AscStartQueueExe(iot, ioh); 3194 if (sc->pci_fix_asyn_xfer & target_id) 3195 AscSetRunChipSynRegAtID(iot, ioh, tid_no, 3196 ASYN_SDTR_DATA_FIX_PCI_REV_AB); 3197 AscWaitTixISRDone(sc, target_ix); 3198 } 3199 } else 3200 retval = ASC_BUSY; 3201 sc->sdtr_done &= ~target_id; 3202 } else { 3203 retval = ASC_ERROR; 3204 AscStartQueueExe(iot, ioh); 3205 } 3206 } 3207 sc->unit_not_ready = saved_unit_not_ready; 3208 return (retval); 3209 } 3210 3211 3212 int 3213 AscResetBus(sc) 3214 ASC_SOFTC *sc; 3215 { 3216 bus_space_tag_t iot = sc->sc_iot; 3217 bus_space_handle_t ioh = sc->sc_ioh; 3218 int retval; 3219 int i; 3220 3221 3222 sc->unit_not_ready = 0xFF; 3223 retval = ASC_NOERROR; 3224 3225 AscWaitISRDone(sc); 3226 AscStopQueueExe(iot, ioh); 3227 sc->sdtr_done = 0; 3228 AscResetChipAndScsiBus(iot, ioh); 3229 DvcSleepMilliSecond((u_long) ((u_int16_t) sc->scsi_reset_wait * 1000)); 3230 AscReInitLram(sc); 3231 for (i = 0; i <= ASC_MAX_TID; i++) { 3232 sc->cur_dvc_qng[i] = 0; 3233 if (sc->pci_fix_asyn_xfer & (ASC_SCSI_BIT_ID_TYPE) (0x01 << i)) 3234 AscSetChipSynRegAtID(iot, ioh, i, ASYN_SDTR_DATA_FIX_PCI_REV_AB); 3235 } 3236 3237 ASC_SET_PC_ADDR(iot, ioh, ASC_MCODE_START_ADDR); 3238 if (ASC_GET_PC_ADDR(iot, ioh) != ASC_MCODE_START_ADDR) 3239 retval = ASC_ERROR; 3240 3241 if (AscStartChip(iot, ioh) == 0) 3242 retval = ASC_ERROR; 3243 3244 AscStartQueueExe(iot, ioh); 3245 sc->unit_not_ready = 0; 3246 sc->queue_full_or_busy = 0; 3247 return (retval); 3248 } 3249 3250 3251 /******************************************************************************/ 3252 /* Error Handling routines */ 3253 /******************************************************************************/ 3254 3255 3256 static int 3257 AscSetLibErrorCode(sc, err_code) 3258 ASC_SOFTC *sc; 3259 u_int16_t err_code; 3260 { 3261 /* 3262 * if(sc->err_code == 0) { sc->err_code = err_code; 3263 */ AscWriteLramWord(sc->sc_iot, sc->sc_ioh, ASCV_ASCDVC_ERR_CODE_W, 3264 err_code); 3265 /* 3266 * } 3267 */ 3268 return (err_code); 3269 } 3270 3271 3272 /******************************************************************************/ 3273 /* Handle bugged borads routines */ 3274 /******************************************************************************/ 3275 3276 3277 void 3278 AscInquiryHandling(sc, tid_no, inq) 3279 ASC_SOFTC *sc; 3280 u_int8_t tid_no; 3281 ASC_SCSI_INQUIRY *inq; 3282 { 3283 bus_space_tag_t iot = sc->sc_iot; 3284 bus_space_handle_t ioh = sc->sc_ioh; 3285 ASC_SCSI_BIT_ID_TYPE tid_bit = ASC_TIX_TO_TARGET_ID(tid_no); 3286 ASC_SCSI_BIT_ID_TYPE orig_init_sdtr, orig_use_tagged_qng; 3287 3288 3289 orig_init_sdtr = sc->init_sdtr; 3290 orig_use_tagged_qng = sc->use_tagged_qng; 3291 3292 sc->init_sdtr &= ~tid_bit; 3293 sc->can_tagged_qng &= ~tid_bit; 3294 sc->use_tagged_qng &= ~tid_bit; 3295 3296 if (inq->byte3.rsp_data_fmt >= 2 || inq->byte2.ansi_apr_ver >= 2) { 3297 if ((sc->sdtr_enable & tid_bit) && inq->byte7.Sync) 3298 sc->init_sdtr |= tid_bit; 3299 3300 if ((sc->cmd_qng_enabled & tid_bit) && inq->byte7.CmdQue) 3301 if (AscTagQueuingSafe(inq)) { 3302 sc->use_tagged_qng |= tid_bit; 3303 sc->can_tagged_qng |= tid_bit; 3304 } 3305 } 3306 if (orig_use_tagged_qng != sc->use_tagged_qng) { 3307 AscWriteLramByte(iot, ioh, ASCV_DISC_ENABLE_B, 3308 sc->disc_enable); 3309 AscWriteLramByte(iot, ioh, ASCV_USE_TAGGED_QNG_B, 3310 sc->use_tagged_qng); 3311 AscWriteLramByte(iot, ioh, ASCV_CAN_TAGGED_QNG_B, 3312 sc->can_tagged_qng); 3313 3314 sc->max_dvc_qng[tid_no] = 3315 sc->max_tag_qng[tid_no]; 3316 AscWriteLramByte(iot, ioh, ASCV_MAX_DVC_QNG_BEG + tid_no, 3317 sc->max_dvc_qng[tid_no]); 3318 } 3319 if (orig_init_sdtr != sc->init_sdtr) 3320 AscAsyncFix(sc, tid_no, inq); 3321 } 3322 3323 3324 static int 3325 AscTagQueuingSafe(inq) 3326 ASC_SCSI_INQUIRY *inq; 3327 { 3328 if ((inq->add_len >= 32) && 3329 (AscCompareString(inq->vendor_id, "QUANTUM XP34301", 15) == 0) && 3330 (AscCompareString(inq->product_rev_level, "1071", 4) == 0)) { 3331 return 0; 3332 } 3333 return 1; 3334 } 3335 3336 3337 static void 3338 AscAsyncFix(sc, tid_no, inq) 3339 ASC_SOFTC *sc; 3340 u_int8_t tid_no; 3341 ASC_SCSI_INQUIRY *inq; 3342 { 3343 u_int8_t dvc_type; 3344 ASC_SCSI_BIT_ID_TYPE tid_bits; 3345 3346 3347 dvc_type = inq->byte0.peri_dvc_type; 3348 tid_bits = ASC_TIX_TO_TARGET_ID(tid_no); 3349 3350 if (sc->bug_fix_cntl & ASC_BUG_FIX_ASYN_USE_SYN) { 3351 if (!(sc->init_sdtr & tid_bits)) { 3352 if ((dvc_type == SCSI_TYPE_CDROM) && 3353 (AscCompareString(inq->vendor_id, "HP ", 3) == 0)) { 3354 sc->pci_fix_asyn_xfer_always |= tid_bits; 3355 } 3356 sc->pci_fix_asyn_xfer |= tid_bits; 3357 if ((dvc_type == SCSI_TYPE_PROC) || 3358 (dvc_type == SCSI_TYPE_SCANNER)) { 3359 sc->pci_fix_asyn_xfer &= ~tid_bits; 3360 } 3361 if ((dvc_type == SCSI_TYPE_SASD) && 3362 (AscCompareString(inq->vendor_id, "TANDBERG", 8) == 0) && 3363 (AscCompareString(inq->product_id, " TDC 36", 7) == 0)) { 3364 sc->pci_fix_asyn_xfer &= ~tid_bits; 3365 } 3366 if ((dvc_type == SCSI_TYPE_SASD) && 3367 (AscCompareString(inq->vendor_id, "WANGTEK ", 8) == 0)) { 3368 sc->pci_fix_asyn_xfer &= ~tid_bits; 3369 } 3370 if ((dvc_type == SCSI_TYPE_CDROM) && 3371 (AscCompareString(inq->vendor_id, "NEC ", 8) == 0) && 3372 (AscCompareString(inq->product_id, "CD-ROM DRIVE ", 16) == 0)) { 3373 sc->pci_fix_asyn_xfer &= ~tid_bits; 3374 } 3375 if ((dvc_type == SCSI_TYPE_CDROM) && 3376 (AscCompareString(inq->vendor_id, "YAMAHA", 6) == 0) && 3377 (AscCompareString(inq->product_id, "CDR400", 6) == 0)) { 3378 sc->pci_fix_asyn_xfer &= ~tid_bits; 3379 } 3380 if (sc->pci_fix_asyn_xfer & tid_bits) { 3381 AscSetRunChipSynRegAtID(sc->sc_iot, sc->sc_ioh, tid_no, 3382 ASYN_SDTR_DATA_FIX_PCI_REV_AB); 3383 } 3384 } 3385 } 3386 } 3387 3388 3389 /******************************************************************************/ 3390 /* Miscellaneous routines */ 3391 /******************************************************************************/ 3392 3393 3394 static int 3395 AscCompareString(str1, str2, len) 3396 u_char *str1; 3397 u_char *str2; 3398 int len; 3399 { 3400 int i; 3401 int diff; 3402 3403 for (i = 0; i < len; i++) { 3404 diff = (int) (str1[i] - str2[i]); 3405 if (diff != 0) 3406 return (diff); 3407 } 3408 3409 return (0); 3410 } 3411 3412 3413 /******************************************************************************/ 3414 /* Device oriented routines */ 3415 /******************************************************************************/ 3416 3417 3418 static int 3419 DvcEnterCritical(void) 3420 { 3421 int s; 3422 3423 s = splbio(); 3424 return (s); 3425 } 3426 3427 3428 static void 3429 DvcLeaveCritical(s) 3430 int s; 3431 { 3432 3433 splx(s); 3434 } 3435 3436 3437 static void 3438 DvcSleepMilliSecond(n) 3439 u_int32_t n; 3440 { 3441 3442 DELAY(n * 1000); 3443 } 3444 3445 #ifdef UNUSED 3446 static void 3447 DvcDelayMicroSecond(n) 3448 u_int32_t n; 3449 { 3450 3451 DELAY(n); 3452 } 3453 #endif 3454 3455 static void 3456 DvcDelayNanoSecond(n) 3457 u_int32_t n; 3458 { 3459 3460 DELAY((n + 999) / 1000); 3461 } 3462