1 /* $OpenBSD: sxitwi.c,v 1.7 2018/01/06 11:23:14 kettenis Exp $ */ 2 /* $NetBSD: gttwsi_core.c,v 1.2 2014/11/23 13:37:27 jmcneill Exp $ */ 3 /* 4 * Copyright (c) 2008 Eiji Kawauchi. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed for the NetBSD Project by 18 * Eiji Kawauchi. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 /* 34 * Copyright (c) 2005 Brocade Communcations, inc. 35 * All rights reserved. 36 * 37 * Written by Matt Thomas for Brocade Communcations, Inc. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. The name of Brocade Communications, Inc. may not be used to endorse 48 * or promote products derived from this software without specific prior 49 * written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY BROCADE COMMUNICATIONS, INC. ``AS IS'' AND 52 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 53 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 54 * ARE DISCLAIMED. IN NO EVENT SHALL EITHER BROCADE COMMUNICATIONS, INC. BE 55 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 56 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 57 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 58 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 59 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 60 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 61 * OF THE POSSIBILITY OF SUCH DAMAGE. 62 */ 63 64 /* 65 * Marvell Two-Wire Serial Interface (aka I2C) master driver 66 */ 67 68 #include <sys/param.h> 69 #include <sys/systm.h> 70 #include <sys/device.h> 71 #include <sys/kernel.h> 72 #include <sys/rwlock.h> 73 74 #define _I2C_PRIVATE 75 #include <dev/i2c/i2cvar.h> 76 77 #include <machine/bus.h> 78 #include <machine/fdt.h> 79 80 #include <dev/ofw/openfirm.h> 81 #include <dev/ofw/ofw_clock.h> 82 #include <dev/ofw/ofw_pinctrl.h> 83 #include <dev/ofw/fdt.h> 84 85 #define TWI_CCR_REG 0x14 86 #define TWI_CCR_CLK_M (0x0f << 3) 87 #define TWI_CCR_CLK_N (0x07 << 0) 88 89 #define TWSI_SLAVEADDR 0x00 90 #define TWSI_EXTEND_SLAVEADDR 0x04 91 #define TWSI_DATA 0x08 92 #define TWSI_CONTROL 0x0c 93 #define TWSI_STATUS 0x10 94 #define TWSI_BAUDRATE 0x14 95 #define TWSI_SOFTRESET 0x18 96 97 #define SLAVEADDR_GCE_MASK 0x01 98 #define SLAVEADDR_SADDR_MASK 0xfe 99 100 #define EXTEND_SLAVEADDR_MASK 0xff 101 102 #define DATA_MASK 0xff 103 104 #define CONTROL_ACK (1 << 2) 105 #define CONTROL_IFLG (1 << 3) 106 #define CONTROL_STOP (1 << 4) 107 #define CONTROL_START (1 << 5) 108 #define CONTROL_TWSIEN (1 << 6) 109 #define CONTROL_INTEN (1 << 7) 110 111 #define STAT_BE 0x00 /* Bus Error */ 112 #define STAT_SCT 0x08 /* Start condition transmitted */ 113 #define STAT_RSCT 0x10 /* Repeated start condition transmitted */ 114 #define STAT_AWBT_AR 0x18 /* Address + write bit transd, ack recvd */ 115 #define STAT_AWBT_ANR 0x20 /* Address + write bit transd, ack not recvd */ 116 #define STAT_MTDB_AR 0x28 /* Master transd data byte, ack recvd */ 117 #define STAT_MTDB_ANR 0x30 /* Master transd data byte, ack not recvd */ 118 #define STAT_MLADADT 0x38 /* Master lost arbitr during addr or data tx */ 119 #define STAT_ARBT_AR 0x40 /* Address + read bit transd, ack recvd */ 120 #define STAT_ARBT_ANR 0x48 /* Address + read bit transd, ack not recvd */ 121 #define STAT_MRRD_AT 0x50 /* Master received read data, ack transd */ 122 #define STAT_MRRD_ANT 0x58 /* Master received read data, ack not transd */ 123 #define STAT_SAWBT_AR 0xd0 /* Second addr + write bit transd, ack recvd */ 124 #define STAT_SAWBT_ANR 0xd8 /* S addr + write bit transd, ack not recvd */ 125 #define STAT_SARBT_AR 0xe0 /* Second addr + read bit transd, ack recvd */ 126 #define STAT_SARBT_ANR 0xe8 /* S addr + read bit transd, ack not recvd */ 127 #define STAT_NRS 0xf8 /* No relevant status */ 128 129 #define SOFTRESET_VAL 0 /* reset value */ 130 131 struct sxitwi_softc { 132 struct device sc_dev; 133 bus_space_tag_t sc_iot; 134 bus_space_handle_t sc_ioh; 135 int sc_node; 136 u_int sc_started; 137 u_int sc_twsien_iflg; 138 struct i2c_controller sc_ic; 139 struct rwlock sc_buslock; 140 void *sc_ih; 141 }; 142 143 void sxitwi_attach(struct device *, struct device *, void *); 144 int sxitwi_match(struct device *, void *, void *); 145 void sxitwi_bus_scan(struct device *, struct i2cbus_attach_args *, void *); 146 147 int sxitwi_intr(void *); 148 int sxitwi_acquire_bus(void *, int); 149 void sxitwi_release_bus(void *, int); 150 int sxitwi_send_start(void *, int); 151 int sxitwi_send_stop(void *, int); 152 int sxitwi_initiate_xfer(void *, i2c_addr_t, int); 153 int sxitwi_read_byte(void *, uint8_t *, int); 154 int sxitwi_write_byte(void *, uint8_t, int); 155 int sxitwi_wait(struct sxitwi_softc *, u_int, u_int, int); 156 static inline u_int sxitwi_read_4(struct sxitwi_softc *, u_int); 157 static inline void sxitwi_write_4(struct sxitwi_softc *, u_int, u_int); 158 159 struct cfdriver sxitwi_cd = { 160 NULL, "sxitwi", DV_DULL 161 }; 162 163 struct cfattach sxitwi_ca = { 164 sizeof(struct sxitwi_softc), sxitwi_match, sxitwi_attach 165 }; 166 167 int 168 sxitwi_match(struct device *parent, void *match, void *aux) 169 { 170 struct fdt_attach_args *faa = aux; 171 172 return (OF_is_compatible(faa->fa_node, "allwinner,sun4i-a10-i2c") || 173 OF_is_compatible(faa->fa_node, "allwinner,sun6i-a31-i2c") || 174 OF_is_compatible(faa->fa_node, "allwinner,sun7i-a20-i2c")); 175 } 176 177 void 178 sxitwi_attach(struct device *parent, struct device *self, void *aux) 179 { 180 struct sxitwi_softc *sc = (struct sxitwi_softc *)self; 181 struct fdt_attach_args *faa = aux; 182 struct i2cbus_attach_args iba; 183 uint32_t freq, parent_freq; 184 uint32_t m, n; 185 186 if (faa->fa_nreg < 1) { 187 printf(": no registers\n"); 188 return; 189 } 190 191 /* 192 * Calculate clock dividers up front such that we can bail out 193 * early if the desired clock rate can't be obtained. Make 194 * sure the bus clock rate is never above the desired rate. 195 */ 196 parent_freq = clock_get_frequency(faa->fa_node, NULL); 197 freq = OF_getpropint(faa->fa_node, "clock-frequency", 100000); 198 if (parent_freq == 0) { 199 printf(": unknown clock frequency\n"); 200 return; 201 } 202 n = 0, m = 0; 203 while ((freq * (1 << n) * 16 * 10) < parent_freq) 204 n++; 205 while ((freq * (1 << n) * (m + 1) * 10) < parent_freq) 206 m++; 207 if (n > 8 || m > 16) { 208 printf(": clock frequency too high\n"); 209 return; 210 } 211 212 sc->sc_node = faa->fa_node; 213 sc->sc_iot = faa->fa_iot; 214 215 if (bus_space_map(sc->sc_iot, faa->fa_reg[0].addr, 216 faa->fa_reg[0].size, 0, &sc->sc_ioh)) { 217 printf(": can't map registers\n"); 218 return; 219 } 220 221 rw_init(&sc->sc_buslock, sc->sc_dev.dv_xname); 222 223 /* 224 * On the Allwinner A31 we need to write 1 to clear a pending 225 * interrupt. 226 */ 227 sc->sc_twsien_iflg = CONTROL_TWSIEN; 228 if (OF_is_compatible(sc->sc_node, "allwinner,sun6i-a31-i2c")) 229 sc->sc_twsien_iflg |= CONTROL_IFLG; 230 231 sc->sc_started = 0; 232 sc->sc_ic.ic_cookie = sc; 233 sc->sc_ic.ic_acquire_bus = sxitwi_acquire_bus; 234 sc->sc_ic.ic_release_bus = sxitwi_release_bus; 235 sc->sc_ic.ic_exec = NULL; 236 sc->sc_ic.ic_send_start = sxitwi_send_start; 237 sc->sc_ic.ic_send_stop = sxitwi_send_stop; 238 sc->sc_ic.ic_initiate_xfer = sxitwi_initiate_xfer; 239 sc->sc_ic.ic_read_byte = sxitwi_read_byte; 240 sc->sc_ic.ic_write_byte = sxitwi_write_byte; 241 242 pinctrl_byname(faa->fa_node, "default"); 243 244 /* Enable clock */ 245 clock_enable(faa->fa_node, NULL); 246 reset_deassert_all(faa->fa_node); 247 248 /* Set clock rate. */ 249 sxitwi_write_4(sc, TWI_CCR_REG, (m << 3) | (n << 0)); 250 251 /* Put the controller into Soft Reset. */ 252 sxitwi_write_4(sc, TWSI_SOFTRESET, SOFTRESET_VAL); 253 254 /* Establish interrupt */ 255 sc->sc_ih = arm_intr_establish_fdt(faa->fa_node, IPL_BIO, 256 sxitwi_intr, sc, sc->sc_dev.dv_xname); 257 if (sc->sc_ih == NULL) { 258 printf(": can't to establish interrupt\n"); 259 return; 260 } 261 262 printf("\n"); 263 264 /* Configure its children */ 265 memset(&iba, 0, sizeof(iba)); 266 iba.iba_name = "iic"; 267 iba.iba_tag = &sc->sc_ic; 268 iba.iba_bus_scan = sxitwi_bus_scan; 269 iba.iba_bus_scan_arg = &sc->sc_node; 270 271 config_found(&sc->sc_dev, &iba, iicbus_print); 272 } 273 274 void 275 sxitwi_bus_scan(struct device *self, struct i2cbus_attach_args *iba, void *arg) 276 { 277 int iba_node = *(int *)arg; 278 struct i2c_attach_args ia; 279 char name[32]; 280 uint32_t reg[1]; 281 int node; 282 283 for (node = OF_child(iba_node); node; node = OF_peer(node)) { 284 memset(name, 0, sizeof(name)); 285 memset(reg, 0, sizeof(reg)); 286 287 if (OF_getprop(node, "compatible", name, sizeof(name)) == -1) 288 continue; 289 if (name[0] == '\0') 290 continue; 291 292 if (OF_getprop(node, "reg", ®, sizeof(reg)) != sizeof(reg)) 293 continue; 294 295 memset(&ia, 0, sizeof(ia)); 296 ia.ia_tag = iba->iba_tag; 297 ia.ia_addr = bemtoh32(®[0]); 298 ia.ia_name = name; 299 ia.ia_cookie = &node; 300 config_found(self, &ia, iic_print); 301 } 302 } 303 304 u_int 305 sxitwi_read_4(struct sxitwi_softc *sc, u_int reg) 306 { 307 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, reg); 308 } 309 310 void 311 sxitwi_write_4(struct sxitwi_softc *sc, u_int reg, u_int val) 312 { 313 bus_space_write_4(sc->sc_iot, sc->sc_ioh, reg, val); 314 } 315 316 int 317 sxitwi_intr(void *arg) 318 { 319 struct sxitwi_softc *sc = arg; 320 u_int val; 321 322 val = sxitwi_read_4(sc, TWSI_CONTROL); 323 if (val & CONTROL_IFLG) { 324 sxitwi_write_4(sc, TWSI_CONTROL, val & ~CONTROL_INTEN); 325 return 1; 326 } 327 return 0; 328 } 329 330 int 331 sxitwi_acquire_bus(void *arg, int flags) 332 { 333 struct sxitwi_softc *sc = arg; 334 335 if (flags & I2C_F_POLL) 336 return 0; 337 338 return rw_enter(&sc->sc_buslock, RW_WRITE); 339 } 340 341 void 342 sxitwi_release_bus(void *arg, int flags) 343 { 344 struct sxitwi_softc *sc = arg; 345 346 if (flags & I2C_F_POLL) 347 return; 348 349 rw_exit(&sc->sc_buslock); 350 } 351 352 int 353 sxitwi_send_start(void *v, int flags) 354 { 355 struct sxitwi_softc *sc = v; 356 int expect; 357 358 if (sc->sc_started) 359 expect = STAT_RSCT; 360 else 361 expect = STAT_SCT; 362 sc->sc_started = 1; 363 364 return sxitwi_wait(sc, CONTROL_START, expect, flags); 365 } 366 367 int 368 sxitwi_send_stop(void *v, int flags) 369 { 370 struct sxitwi_softc *sc = v; 371 372 sc->sc_started = 0; 373 374 /* 375 * No need to wait; the controller doesn't transmit the next 376 * START condition until the bus is free. 377 */ 378 sxitwi_write_4(sc, TWSI_CONTROL, CONTROL_STOP | sc->sc_twsien_iflg); 379 return 0; 380 } 381 382 int 383 sxitwi_initiate_xfer(void *v, i2c_addr_t addr, int flags) 384 { 385 struct sxitwi_softc *sc = v; 386 u_int data, expect; 387 int error, read; 388 389 sxitwi_send_start(v, flags); 390 391 read = (flags & I2C_F_READ) != 0; 392 if (read) 393 expect = STAT_ARBT_AR; 394 else 395 expect = STAT_AWBT_AR; 396 397 /* 398 * First byte contains whether this xfer is a read or write. 399 */ 400 data = read; 401 if (addr > 0x7f) { 402 /* 403 * If this is a 10bit request, the first address byte is 404 * 0b11110<b9><b8><r/w>. 405 */ 406 data |= 0xf0 | ((addr & 0x300) >> 7); 407 sxitwi_write_4(sc, TWSI_DATA, data); 408 error = sxitwi_wait(sc, 0, expect, flags); 409 if (error) 410 return error; 411 /* 412 * The first address byte has been sent, now to send 413 * the second one. 414 */ 415 if (read) 416 expect = STAT_SARBT_AR; 417 else 418 expect = STAT_SAWBT_AR; 419 data = (uint8_t)addr; 420 } else 421 data |= (addr << 1); 422 423 sxitwi_write_4(sc, TWSI_DATA, data); 424 return sxitwi_wait(sc, 0, expect, flags); 425 } 426 427 int 428 sxitwi_read_byte(void *v, uint8_t *valp, int flags) 429 { 430 struct sxitwi_softc *sc = v; 431 int error; 432 433 if (flags & I2C_F_LAST) 434 error = sxitwi_wait(sc, 0, STAT_MRRD_ANT, flags); 435 else 436 error = sxitwi_wait(sc, CONTROL_ACK, STAT_MRRD_AT, flags); 437 if (!error) 438 *valp = sxitwi_read_4(sc, TWSI_DATA); 439 if ((flags & (I2C_F_LAST | I2C_F_STOP)) == (I2C_F_LAST | I2C_F_STOP)) 440 error = sxitwi_send_stop(sc, flags); 441 return error; 442 } 443 444 int 445 sxitwi_write_byte(void *v, uint8_t val, int flags) 446 { 447 struct sxitwi_softc *sc = v; 448 int error; 449 450 sxitwi_write_4(sc, TWSI_DATA, val); 451 error = sxitwi_wait(sc, 0, STAT_MTDB_AR, flags); 452 if (flags & I2C_F_STOP) 453 sxitwi_send_stop(sc, flags); 454 return error; 455 } 456 457 int 458 sxitwi_wait(struct sxitwi_softc *sc, u_int control, u_int expect, int flags) 459 { 460 u_int status; 461 int timo; 462 463 sxitwi_write_4(sc, TWSI_CONTROL, control | sc->sc_twsien_iflg); 464 465 for (timo = 10000; timo > 0; timo--) { 466 control = sxitwi_read_4(sc, TWSI_CONTROL); 467 if (control & CONTROL_IFLG) 468 break; 469 delay(1); 470 } 471 if (timo == 0) 472 return ETIMEDOUT; 473 474 status = sxitwi_read_4(sc, TWSI_STATUS); 475 if (status != expect) 476 return EIO; 477 return 0; 478 } 479