1 /* $OpenBSD: sxitwi.c,v 1.12 2020/10/08 20:57:52 patrick Exp $ */ 2 /* $NetBSD: gttwsi_core.c,v 1.2 2014/11/23 13:37:27 jmcneill Exp $ */ 3 /* 4 * Copyright (c) 2008 Eiji Kawauchi. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed for the NetBSD Project by 18 * Eiji Kawauchi. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 /* 34 * Copyright (c) 2005 Brocade Communcations, inc. 35 * All rights reserved. 36 * 37 * Written by Matt Thomas for Brocade Communcations, Inc. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. The name of Brocade Communications, Inc. may not be used to endorse 48 * or promote products derived from this software without specific prior 49 * written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY BROCADE COMMUNICATIONS, INC. ``AS IS'' AND 52 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 53 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 54 * ARE DISCLAIMED. IN NO EVENT SHALL EITHER BROCADE COMMUNICATIONS, INC. BE 55 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 56 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 57 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 58 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 59 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 60 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 61 * OF THE POSSIBILITY OF SUCH DAMAGE. 62 */ 63 64 /* 65 * Marvell Two-Wire Serial Interface (aka I2C) master driver 66 */ 67 68 #include <sys/param.h> 69 #include <sys/systm.h> 70 #include <sys/device.h> 71 #include <sys/kernel.h> 72 #include <sys/rwlock.h> 73 74 #define _I2C_PRIVATE 75 #include <dev/i2c/i2cvar.h> 76 77 #include <machine/bus.h> 78 #include <machine/fdt.h> 79 80 #include <dev/ofw/openfirm.h> 81 #include <dev/ofw/ofw_clock.h> 82 #include <dev/ofw/ofw_pinctrl.h> 83 #include <dev/ofw/ofw_misc.h> 84 #include <dev/ofw/fdt.h> 85 86 #define TWSI_SLAVEADDR 0 87 #define TWSI_EXTEND_SLAVEADDR 1 88 #define TWSI_DATA 2 89 #define TWSI_CONTROL 3 90 #define TWSI_STATUS 4 91 #define TWSI_CLOCK 5 92 #define TWSI_SOFTRESET 6 93 #define TWSI_NREG 7 94 95 #define SLAVEADDR_GCE_MASK 0x01 96 #define SLAVEADDR_SADDR_MASK 0xfe 97 98 #define EXTEND_SLAVEADDR_MASK 0xff 99 100 #define DATA_MASK 0xff 101 102 #define CONTROL_ACK (1 << 2) 103 #define CONTROL_IFLG (1 << 3) 104 #define CONTROL_STOP (1 << 4) 105 #define CONTROL_START (1 << 5) 106 #define CONTROL_TWSIEN (1 << 6) 107 #define CONTROL_INTEN (1 << 7) 108 109 #define STAT_BE 0x00 /* Bus Error */ 110 #define STAT_SCT 0x08 /* Start condition transmitted */ 111 #define STAT_RSCT 0x10 /* Repeated start condition transmitted */ 112 #define STAT_AWBT_AR 0x18 /* Address + write bit transd, ack recvd */ 113 #define STAT_AWBT_ANR 0x20 /* Address + write bit transd, ack not recvd */ 114 #define STAT_MTDB_AR 0x28 /* Master transd data byte, ack recvd */ 115 #define STAT_MTDB_ANR 0x30 /* Master transd data byte, ack not recvd */ 116 #define STAT_MLADADT 0x38 /* Master lost arbitr during addr or data tx */ 117 #define STAT_ARBT_AR 0x40 /* Address + read bit transd, ack recvd */ 118 #define STAT_ARBT_ANR 0x48 /* Address + read bit transd, ack not recvd */ 119 #define STAT_MRRD_AT 0x50 /* Master received read data, ack transd */ 120 #define STAT_MRRD_ANT 0x58 /* Master received read data, ack not transd */ 121 #define STAT_SAWBT_AR 0xd0 /* Second addr + write bit transd, ack recvd */ 122 #define STAT_SAWBT_ANR 0xd8 /* S addr + write bit transd, ack not recvd */ 123 #define STAT_SARBT_AR 0xe0 /* Second addr + read bit transd, ack recvd */ 124 #define STAT_SARBT_ANR 0xe8 /* S addr + read bit transd, ack not recvd */ 125 #define STAT_NRS 0xf8 /* No relevant status */ 126 127 #define SOFTRESET_VAL 0 /* reset value */ 128 129 struct sxitwi_softc { 130 struct device sc_dev; 131 bus_space_tag_t sc_iot; 132 bus_space_handle_t sc_ioh; 133 int sc_node; 134 u_int sc_started; 135 u_int sc_twsien_iflg; 136 struct i2c_controller sc_ic; 137 struct i2c_bus sc_ib; 138 struct rwlock sc_buslock; 139 void *sc_ih; 140 uint8_t sc_regs[TWSI_NREG]; 141 int sc_delay; 142 }; 143 144 void sxitwi_attach(struct device *, struct device *, void *); 145 int sxitwi_match(struct device *, void *, void *); 146 void sxitwi_bus_scan(struct device *, struct i2cbus_attach_args *, void *); 147 148 int sxitwi_intr(void *); 149 int sxitwi_acquire_bus(void *, int); 150 void sxitwi_release_bus(void *, int); 151 int sxitwi_send_start(void *, int); 152 int sxitwi_send_stop(void *, int); 153 int sxitwi_initiate_xfer(void *, i2c_addr_t, int); 154 int sxitwi_read_byte(void *, uint8_t *, int); 155 int sxitwi_write_byte(void *, uint8_t, int); 156 int sxitwi_wait(struct sxitwi_softc *, u_int, u_int, int); 157 static inline u_int sxitwi_read_4(struct sxitwi_softc *, u_int); 158 static inline void sxitwi_write_4(struct sxitwi_softc *, u_int, u_int); 159 160 struct cfdriver sxitwi_cd = { 161 NULL, "sxitwi", DV_DULL 162 }; 163 164 struct cfattach sxitwi_ca = { 165 sizeof(struct sxitwi_softc), sxitwi_match, sxitwi_attach 166 }; 167 168 int 169 sxitwi_match(struct device *parent, void *match, void *aux) 170 { 171 struct fdt_attach_args *faa = aux; 172 173 return (OF_is_compatible(faa->fa_node, "allwinner,sun4i-a10-i2c") || 174 OF_is_compatible(faa->fa_node, "allwinner,sun6i-a31-i2c") || 175 OF_is_compatible(faa->fa_node, "allwinner,sun7i-a20-i2c") || 176 OF_is_compatible(faa->fa_node, "marvell,mv78230-i2c") || 177 OF_is_compatible(faa->fa_node, "marvell,mv78230-a0-i2c")); 178 } 179 180 void 181 sxitwi_attach(struct device *parent, struct device *self, void *aux) 182 { 183 struct sxitwi_softc *sc = (struct sxitwi_softc *)self; 184 struct fdt_attach_args *faa = aux; 185 struct i2cbus_attach_args iba; 186 uint32_t freq, parent_freq; 187 uint32_t m, n, nbase; 188 189 if (faa->fa_nreg < 1) { 190 printf(": no registers\n"); 191 return; 192 } 193 194 nbase = 1; 195 sc->sc_regs[TWSI_SLAVEADDR] = 0x00; 196 sc->sc_regs[TWSI_EXTEND_SLAVEADDR] = 0x04; 197 sc->sc_regs[TWSI_DATA] = 0x08; 198 sc->sc_regs[TWSI_CONTROL] = 0x0c; 199 sc->sc_regs[TWSI_STATUS] = 0x10; 200 sc->sc_regs[TWSI_CLOCK] = 0x14; 201 sc->sc_regs[TWSI_SOFTRESET] = 0x18; 202 203 if (OF_is_compatible(faa->fa_node, "marvell,mv78230-i2c") || 204 OF_is_compatible(faa->fa_node, "marvell,mv78230-a0-i2c")) { 205 nbase = 2; 206 sc->sc_delay = 1; 207 sc->sc_regs[TWSI_SLAVEADDR] = 0x00; 208 sc->sc_regs[TWSI_EXTEND_SLAVEADDR] = 0x10; 209 sc->sc_regs[TWSI_DATA] = 0x04; 210 sc->sc_regs[TWSI_CONTROL] = 0x08; 211 sc->sc_regs[TWSI_STATUS] = 0x0c; 212 sc->sc_regs[TWSI_CLOCK] = 0x0c; 213 sc->sc_regs[TWSI_SOFTRESET] = 0x1c; 214 } 215 216 /* 217 * Calculate clock dividers up front such that we can bail out 218 * early if the desired clock rate can't be obtained. Make 219 * sure the bus clock rate is never above the desired rate. 220 */ 221 parent_freq = clock_get_frequency(faa->fa_node, NULL); 222 freq = OF_getpropint(faa->fa_node, "clock-frequency", 100000); 223 if (parent_freq == 0) { 224 printf(": unknown clock frequency\n"); 225 return; 226 } 227 n = 0, m = 0; 228 while ((freq * (nbase << n) * 16 * 10) < parent_freq) 229 n++; 230 while ((freq * (nbase << n) * (m + 1) * 10) < parent_freq) 231 m++; 232 if (n > 8 || m > 16) { 233 printf(": clock frequency too high\n"); 234 return; 235 } 236 237 sc->sc_node = faa->fa_node; 238 sc->sc_iot = faa->fa_iot; 239 240 if (bus_space_map(sc->sc_iot, faa->fa_reg[0].addr, 241 faa->fa_reg[0].size, 0, &sc->sc_ioh)) { 242 printf(": can't map registers\n"); 243 return; 244 } 245 246 rw_init(&sc->sc_buslock, sc->sc_dev.dv_xname); 247 248 /* 249 * On the Allwinner A31 we need to write 1 to clear a pending 250 * interrupt. 251 */ 252 sc->sc_twsien_iflg = CONTROL_TWSIEN; 253 if (OF_is_compatible(sc->sc_node, "allwinner,sun6i-a31-i2c")) 254 sc->sc_twsien_iflg |= CONTROL_IFLG; 255 256 sc->sc_started = 0; 257 sc->sc_ic.ic_cookie = sc; 258 sc->sc_ic.ic_acquire_bus = sxitwi_acquire_bus; 259 sc->sc_ic.ic_release_bus = sxitwi_release_bus; 260 sc->sc_ic.ic_exec = NULL; 261 sc->sc_ic.ic_send_start = sxitwi_send_start; 262 sc->sc_ic.ic_send_stop = sxitwi_send_stop; 263 sc->sc_ic.ic_initiate_xfer = sxitwi_initiate_xfer; 264 sc->sc_ic.ic_read_byte = sxitwi_read_byte; 265 sc->sc_ic.ic_write_byte = sxitwi_write_byte; 266 267 pinctrl_byname(faa->fa_node, "default"); 268 269 /* Enable clock */ 270 clock_enable(faa->fa_node, NULL); 271 reset_deassert_all(faa->fa_node); 272 273 /* Set clock rate. */ 274 sxitwi_write_4(sc, TWSI_CLOCK, (m << 3) | (n << 0)); 275 276 /* Put the controller into Soft Reset. */ 277 sxitwi_write_4(sc, TWSI_SOFTRESET, SOFTRESET_VAL); 278 279 /* Establish interrupt */ 280 sc->sc_ih = fdt_intr_establish(faa->fa_node, IPL_BIO, 281 sxitwi_intr, sc, sc->sc_dev.dv_xname); 282 if (sc->sc_ih == NULL) { 283 printf(": can't establish interrupt\n"); 284 return; 285 } 286 287 printf("\n"); 288 289 /* Configure its children */ 290 memset(&iba, 0, sizeof(iba)); 291 iba.iba_name = "iic"; 292 iba.iba_tag = &sc->sc_ic; 293 iba.iba_bus_scan = sxitwi_bus_scan; 294 iba.iba_bus_scan_arg = &sc->sc_node; 295 config_found(&sc->sc_dev, &iba, iicbus_print); 296 297 sc->sc_ib.ib_node = sc->sc_node; 298 sc->sc_ib.ib_ic = &sc->sc_ic; 299 i2c_register(&sc->sc_ib); 300 } 301 302 void 303 sxitwi_bus_scan(struct device *self, struct i2cbus_attach_args *iba, void *arg) 304 { 305 int iba_node = *(int *)arg; 306 struct i2c_attach_args ia; 307 char name[32]; 308 uint32_t reg[1]; 309 int node; 310 311 for (node = OF_child(iba_node); node; node = OF_peer(node)) { 312 memset(name, 0, sizeof(name)); 313 memset(reg, 0, sizeof(reg)); 314 315 if (OF_getprop(node, "compatible", name, sizeof(name)) == -1) 316 continue; 317 if (name[0] == '\0') 318 continue; 319 320 if (OF_getprop(node, "reg", ®, sizeof(reg)) != sizeof(reg)) 321 continue; 322 323 memset(&ia, 0, sizeof(ia)); 324 ia.ia_tag = iba->iba_tag; 325 ia.ia_addr = bemtoh32(®[0]); 326 ia.ia_name = name; 327 ia.ia_cookie = &node; 328 config_found(self, &ia, iic_print); 329 } 330 } 331 332 u_int 333 sxitwi_read_4(struct sxitwi_softc *sc, u_int reg) 334 { 335 KASSERT(reg < TWSI_NREG); 336 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, sc->sc_regs[reg]); 337 } 338 339 void 340 sxitwi_write_4(struct sxitwi_softc *sc, u_int reg, u_int val) 341 { 342 KASSERT(reg < TWSI_NREG); 343 bus_space_write_4(sc->sc_iot, sc->sc_ioh, sc->sc_regs[reg], val); 344 } 345 346 int 347 sxitwi_intr(void *arg) 348 { 349 struct sxitwi_softc *sc = arg; 350 u_int val; 351 352 val = sxitwi_read_4(sc, TWSI_CONTROL); 353 if (val & CONTROL_IFLG) { 354 sxitwi_write_4(sc, TWSI_CONTROL, val & ~CONTROL_INTEN); 355 return 1; 356 } 357 return 0; 358 } 359 360 int 361 sxitwi_acquire_bus(void *arg, int flags) 362 { 363 struct sxitwi_softc *sc = arg; 364 365 if (flags & I2C_F_POLL) 366 return 0; 367 368 return rw_enter(&sc->sc_buslock, RW_WRITE); 369 } 370 371 void 372 sxitwi_release_bus(void *arg, int flags) 373 { 374 struct sxitwi_softc *sc = arg; 375 376 if (flags & I2C_F_POLL) 377 return; 378 379 rw_exit(&sc->sc_buslock); 380 } 381 382 int 383 sxitwi_send_start(void *v, int flags) 384 { 385 struct sxitwi_softc *sc = v; 386 int expect; 387 388 if (sc->sc_started) 389 expect = STAT_RSCT; 390 else 391 expect = STAT_SCT; 392 sc->sc_started = 1; 393 394 return sxitwi_wait(sc, CONTROL_START, expect, flags); 395 } 396 397 int 398 sxitwi_send_stop(void *v, int flags) 399 { 400 struct sxitwi_softc *sc = v; 401 402 sc->sc_started = 0; 403 404 /* 405 * No need to wait; the controller doesn't transmit the next 406 * START condition until the bus is free. 407 */ 408 sxitwi_write_4(sc, TWSI_CONTROL, CONTROL_STOP | sc->sc_twsien_iflg); 409 if (sc->sc_delay) 410 delay(5); 411 return 0; 412 } 413 414 int 415 sxitwi_initiate_xfer(void *v, i2c_addr_t addr, int flags) 416 { 417 struct sxitwi_softc *sc = v; 418 u_int data, expect; 419 int error, read; 420 421 sxitwi_send_start(v, flags); 422 423 read = (flags & I2C_F_READ) != 0; 424 if (read) 425 expect = STAT_ARBT_AR; 426 else 427 expect = STAT_AWBT_AR; 428 429 /* 430 * First byte contains whether this xfer is a read or write. 431 */ 432 data = read; 433 if (addr > 0x7f) { 434 /* 435 * If this is a 10bit request, the first address byte is 436 * 0b11110<b9><b8><r/w>. 437 */ 438 data |= 0xf0 | ((addr & 0x300) >> 7); 439 sxitwi_write_4(sc, TWSI_DATA, data); 440 error = sxitwi_wait(sc, 0, expect, flags); 441 if (error) 442 return error; 443 /* 444 * The first address byte has been sent, now to send 445 * the second one. 446 */ 447 if (read) 448 expect = STAT_SARBT_AR; 449 else 450 expect = STAT_SAWBT_AR; 451 data = (uint8_t)addr; 452 } else 453 data |= (addr << 1); 454 455 sxitwi_write_4(sc, TWSI_DATA, data); 456 return sxitwi_wait(sc, 0, expect, flags); 457 } 458 459 int 460 sxitwi_read_byte(void *v, uint8_t *valp, int flags) 461 { 462 struct sxitwi_softc *sc = v; 463 int error; 464 465 if (flags & I2C_F_LAST) 466 error = sxitwi_wait(sc, 0, STAT_MRRD_ANT, flags); 467 else 468 error = sxitwi_wait(sc, CONTROL_ACK, STAT_MRRD_AT, flags); 469 if (!error) 470 *valp = sxitwi_read_4(sc, TWSI_DATA); 471 if ((flags & (I2C_F_LAST | I2C_F_STOP)) == (I2C_F_LAST | I2C_F_STOP)) 472 error = sxitwi_send_stop(sc, flags); 473 return error; 474 } 475 476 int 477 sxitwi_write_byte(void *v, uint8_t val, int flags) 478 { 479 struct sxitwi_softc *sc = v; 480 int error; 481 482 sxitwi_write_4(sc, TWSI_DATA, val); 483 error = sxitwi_wait(sc, 0, STAT_MTDB_AR, flags); 484 if (flags & I2C_F_STOP) 485 sxitwi_send_stop(sc, flags); 486 return error; 487 } 488 489 int 490 sxitwi_wait(struct sxitwi_softc *sc, u_int control, u_int expect, int flags) 491 { 492 u_int status; 493 int timo; 494 495 sxitwi_write_4(sc, TWSI_CONTROL, control | sc->sc_twsien_iflg); 496 497 for (timo = 10000; timo > 0; timo--) { 498 control = sxitwi_read_4(sc, TWSI_CONTROL); 499 if (control & CONTROL_IFLG) 500 break; 501 delay(1); 502 } 503 if (timo == 0) 504 return ETIMEDOUT; 505 506 if (sc->sc_delay) 507 delay(5); 508 509 status = sxitwi_read_4(sc, TWSI_STATUS); 510 if (status != expect) 511 return EIO; 512 return 0; 513 } 514