1 /* Public Domain */ 2 3 4 /* 5 * Clocks Signals 6 */ 7 8 /* A10/A20 */ 9 10 #define A10_CLK_HOSC 1 11 #define A10_CLK_PLL_CORE 2 12 #define A10_CLK_PLL_PERIPH_BASE 14 13 #define A10_CLK_PLL_PERIPH 15 14 15 #define A10_CLK_CPU 20 16 #define A10_CLK_APB1 25 17 18 #define A10_CLK_AHB_EHCI0 27 19 #define A10_CLK_AHB_EHCI1 29 20 #define A10_CLK_AHB_MMC0 34 21 #define A10_CLK_AHB_MMC1 35 22 #define A10_CLK_AHB_MMC2 36 23 #define A10_CLK_AHB_MMC3 37 24 #define A10_CLK_AHB_EMAC 42 25 #define A10_CLK_AHB_SATA 49 26 #define A10_CLK_AHB_GMAC 66 27 #define A10_CLK_APB0_PIO 74 28 #define A10_CLK_APB1_I2C0 79 29 #define A10_CLK_APB1_I2C1 80 30 #define A10_CLK_APB1_I2C2 81 31 #define A10_CLK_APB1_I2C3 82 32 #define A10_CLK_APB1_I2C4 87 33 #define A10_CLK_APB1_UART0 88 34 #define A10_CLK_APB1_UART1 89 35 #define A10_CLK_APB1_UART2 90 36 #define A10_CLK_APB1_UART3 91 37 #define A10_CLK_APB1_UART4 92 38 #define A10_CLK_APB1_UART5 93 39 #define A10_CLK_APB1_UART6 94 40 #define A10_CLK_APB1_UART7 95 41 42 #define A10_CLK_MMC0 98 43 #define A10_CLK_MMC1 101 44 #define A10_CLK_MMC2 104 45 #define A10_CLK_MMC3 107 46 #define A10_CLK_SATA 122 47 #define A10_CLK_USB_PHY 125 48 49 #define A10_CLK_LOSC 254 50 51 struct sxiccmu_ccu_bit sun4i_a10_gates[] = { 52 [A10_CLK_AHB_EHCI0] = { 0x0060, 1 }, 53 [A10_CLK_AHB_EHCI1] = { 0x0060, 3 }, 54 [A10_CLK_AHB_MMC0] = { 0x0060, 8 }, 55 [A10_CLK_AHB_MMC1] = { 0x0060, 9 }, 56 [A10_CLK_AHB_MMC2] = { 0x0060, 10 }, 57 [A10_CLK_AHB_MMC3] = { 0x0060, 11 }, 58 [A10_CLK_AHB_EMAC] = { 0x0060, 17 }, 59 [A10_CLK_AHB_SATA] = { 0x0060, 25 }, 60 [A10_CLK_AHB_GMAC] = { 0x0064, 17 }, 61 [A10_CLK_APB0_PIO] = { 0x0068, 5 }, 62 [A10_CLK_APB1_I2C0] = { 0x006c, 0, A10_CLK_APB1 }, 63 [A10_CLK_APB1_I2C1] = { 0x006c, 1, A10_CLK_APB1 }, 64 [A10_CLK_APB1_I2C2] = { 0x006c, 2, A10_CLK_APB1 }, 65 [A10_CLK_APB1_I2C3] = { 0x006c, 3, A10_CLK_APB1 }, 66 [A10_CLK_APB1_I2C4] = { 0x006c, 15, A10_CLK_APB1 }, 67 [A10_CLK_APB1_UART0] = { 0x006c, 16, A10_CLK_APB1 }, 68 [A10_CLK_APB1_UART1] = { 0x006c, 17, A10_CLK_APB1 }, 69 [A10_CLK_APB1_UART2] = { 0x006c, 18, A10_CLK_APB1 }, 70 [A10_CLK_APB1_UART3] = { 0x006c, 19, A10_CLK_APB1 }, 71 [A10_CLK_APB1_UART4] = { 0x006c, 20, A10_CLK_APB1 }, 72 [A10_CLK_APB1_UART5] = { 0x006c, 21, A10_CLK_APB1 }, 73 [A10_CLK_APB1_UART6] = { 0x006c, 22, A10_CLK_APB1 }, 74 [A10_CLK_APB1_UART7] = { 0x006c, 23, A10_CLK_APB1 }, 75 [A10_CLK_MMC0] = { 0x0088, 31 }, 76 [A10_CLK_MMC1] = { 0x008c, 31 }, 77 [A10_CLK_MMC2] = { 0x0090, 31 }, 78 [A10_CLK_MMC3] = { 0x0094, 31 }, 79 [A10_CLK_SATA] = { 0x00c8, 31 }, 80 [A10_CLK_USB_PHY] = { 0x00cc, 8 }, 81 }; 82 83 /* A23/A33 */ 84 85 #define A23_CLK_PLL_PERIPH 10 86 87 #define A23_CLK_AXI 19 88 #define A23_CLK_AHB1 20 89 #define A23_CLK_APB1 21 90 #define A23_CLK_APB2 22 91 92 #define A23_CLK_BUS_MMC0 26 93 #define A23_CLK_BUS_MMC1 27 94 #define A23_CLK_BUS_MMC2 28 95 #define A23_CLK_BUS_EHCI 35 96 #define A23_CLK_BUS_OHCI 36 97 #define A23_CLK_BUS_PIO 48 98 #define A23_CLK_BUS_I2C0 51 99 #define A23_CLK_BUS_I2C1 52 100 #define A23_CLK_BUS_I2C2 53 101 #define A23_CLK_BUS_UART0 54 102 #define A23_CLK_BUS_UART1 55 103 #define A23_CLK_BUS_UART2 56 104 #define A23_CLK_BUS_UART3 57 105 #define A23_CLK_BUS_UART4 58 106 107 #define A23_CLK_MMC0 60 108 #define A23_CLK_MMC1 63 109 #define A23_CLK_MMC2 66 110 111 struct sxiccmu_ccu_bit sun8i_a23_gates[] = { 112 [A23_CLK_BUS_MMC0] = { 0x0060, 8 }, 113 [A23_CLK_BUS_MMC1] = { 0x0060, 9 }, 114 [A23_CLK_BUS_MMC2] = { 0x0060, 10 }, 115 [A23_CLK_BUS_EHCI] = { 0x0060, 26 }, 116 [A23_CLK_BUS_OHCI] = { 0x0060, 29 }, 117 [A23_CLK_BUS_PIO] = { 0x0068, 5 }, 118 [A23_CLK_BUS_I2C0] = { 0x006c, 0, A23_CLK_APB2 }, 119 [A23_CLK_BUS_I2C1] = { 0x006c, 1, A23_CLK_APB2 }, 120 [A23_CLK_BUS_I2C2] = { 0x006c, 2, A23_CLK_APB2 }, 121 [A23_CLK_BUS_UART0] = { 0x006c, 16, A23_CLK_APB2 }, 122 [A23_CLK_BUS_UART1] = { 0x006c, 17, A23_CLK_APB2 }, 123 [A23_CLK_BUS_UART2] = { 0x006c, 18, A23_CLK_APB2 }, 124 [A23_CLK_BUS_UART3] = { 0x006c, 19, A23_CLK_APB2 }, 125 [A23_CLK_BUS_UART4] = { 0x006c, 20, A23_CLK_APB2 }, 126 [A23_CLK_MMC0] = { 0x0088, 31 }, 127 [A23_CLK_MMC1] = { 0x008c, 31 }, 128 [A23_CLK_MMC2] = { 0x0090, 31 }, 129 }; 130 131 /* A64 */ 132 133 #define A64_CLK_PLL_PERIPH0 11 134 #define A64_CLK_PLL_PERIPH0_2X 12 135 136 #define A64_CLK_AXI 22 137 #define A64_CLK_APB 23 138 #define A64_CLK_AHB1 24 139 #define A64_CLK_APB1 25 140 #define A64_CLK_APB2 26 141 #define A64_CLK_AHB2 27 142 143 #define A64_CLK_BUS_MMC0 31 144 #define A64_CLK_BUS_MMC1 32 145 #define A64_CLK_BUS_MMC2 33 146 #define A64_CLK_BUS_EMAC 36 147 #define A64_CLK_BUS_EHCI0 42 148 #define A64_CLK_BUS_EHCI1 43 149 #define A64_CLK_BUS_OHCI0 44 150 #define A64_CLK_BUS_OHCI1 45 151 #define A64_CLK_BUS_PIO 58 152 #define A64_CLK_BUS_THS 59 153 #define A64_CLK_BUS_I2C0 63 154 #define A64_CLK_BUS_I2C1 64 155 #define A64_CLK_BUS_I2C2 65 156 #define A64_CLK_BUS_UART0 67 157 #define A64_CLK_BUS_UART1 68 158 #define A64_CLK_BUS_UART2 69 159 #define A64_CLK_BUS_UART3 70 160 #define A64_CLK_BUS_UART4 71 161 162 #define A64_CLK_THS 73 163 #define A64_CLK_MMC0 75 164 #define A64_CLK_MMC1 76 165 #define A64_CLK_MMC2 77 166 #define A64_CLK_USB_OHCI0 91 167 #define A64_CLK_USB_OHCI1 93 168 #define A64_CLK_USB_PHY0 86 169 #define A64_CLK_USB_PHY1 87 170 171 #define A64_CLK_LOSC 254 172 #define A64_CLK_HOSC 253 173 174 struct sxiccmu_ccu_bit sun50i_a64_gates[] = { 175 [A64_CLK_PLL_PERIPH0] = { 0x0028, 31 }, 176 [A64_CLK_BUS_MMC0] = { 0x0060, 8 }, 177 [A64_CLK_BUS_MMC1] = { 0x0060, 9 }, 178 [A64_CLK_BUS_MMC2] = { 0x0060, 10 }, 179 [A64_CLK_BUS_EMAC] = { 0x0060, 17, A64_CLK_AHB2 }, 180 [A64_CLK_BUS_EHCI0] = { 0x0060, 24 }, 181 [A64_CLK_BUS_EHCI1] = { 0x0060, 25 }, 182 [A64_CLK_BUS_OHCI0] = { 0x0060, 28 }, 183 [A64_CLK_BUS_OHCI1] = { 0x0060, 29 }, 184 [A64_CLK_BUS_PIO] = { 0x0068, 5 }, 185 [A64_CLK_BUS_THS] = { 0x0068, 8 }, 186 [A64_CLK_BUS_I2C0] = { 0x006c, 0, A64_CLK_APB2 }, 187 [A64_CLK_BUS_I2C1] = { 0x006c, 1, A64_CLK_APB2 }, 188 [A64_CLK_BUS_I2C2] = { 0x006c, 2, A64_CLK_APB2 }, 189 [A64_CLK_BUS_UART0] = { 0x006c, 16, A64_CLK_APB2 }, 190 [A64_CLK_BUS_UART1] = { 0x006c, 17, A64_CLK_APB2 }, 191 [A64_CLK_BUS_UART2] = { 0x006c, 18, A64_CLK_APB2 }, 192 [A64_CLK_BUS_UART3] = { 0x006c, 19, A64_CLK_APB2 }, 193 [A64_CLK_BUS_UART4] = { 0x006c, 20, A64_CLK_APB2 }, 194 [A64_CLK_THS] = { 0x0074, 31 }, 195 [A64_CLK_MMC0] = { 0x0088, 31 }, 196 [A64_CLK_MMC1] = { 0x008c, 31 }, 197 [A64_CLK_MMC2] = { 0x0090, 31 }, 198 [A64_CLK_USB_OHCI0] = { 0x00cc, 16 }, 199 [A64_CLK_USB_OHCI1] = { 0x00cc, 17 }, 200 [A64_CLK_USB_PHY0] = { 0x00cc, 8 }, 201 [A64_CLK_USB_PHY1] = { 0x00cc, 9 }, 202 }; 203 204 /* A80 */ 205 206 #define A80_CLK_PLL_PERIPH0 3 207 208 #define A80_CLK_APB1 23 209 210 #define A80_CLK_MMC0 33 211 #define A80_CLK_MMC1 36 212 #define A80_CLK_MMC2 39 213 #define A80_CLK_MMC3 42 214 215 #define A80_CLK_BUS_MMC 84 216 #define A80_CLK_BUS_USB 96 217 #define A80_CLK_BUS_PIO 111 218 #define A80_CLK_BUS_UART0 124 219 #define A80_CLK_BUS_UART1 125 220 #define A80_CLK_BUS_UART2 126 221 #define A80_CLK_BUS_UART3 127 222 #define A80_CLK_BUS_UART4 128 223 #define A80_CLK_BUS_UART5 129 224 225 struct sxiccmu_ccu_bit sun9i_a80_gates[] = { 226 [A80_CLK_MMC0] = { 0x0410, 31 }, 227 [A80_CLK_MMC1] = { 0x0414, 31 }, 228 [A80_CLK_MMC2] = { 0x0418, 31 }, 229 [A80_CLK_MMC3] = { 0x041c, 31 }, /* Undocumented */ 230 [A80_CLK_BUS_MMC] = { 0x0580, 8 }, 231 [A80_CLK_BUS_USB] = { 0x0584, 1 }, 232 [A80_CLK_BUS_PIO] = { 0x0590, 5 }, 233 [A80_CLK_BUS_UART0] = { 0x0594, 16, A80_CLK_APB1 }, 234 [A80_CLK_BUS_UART1] = { 0x0594, 17, A80_CLK_APB1 }, 235 [A80_CLK_BUS_UART2] = { 0x0594, 18, A80_CLK_APB1 }, 236 [A80_CLK_BUS_UART3] = { 0x0594, 19, A80_CLK_APB1 }, 237 [A80_CLK_BUS_UART4] = { 0x0594, 20, A80_CLK_APB1 }, 238 [A80_CLK_BUS_UART5] = { 0x0594, 21, A80_CLK_APB1 }, 239 }; 240 241 #define A80_USB_CLK_HCI0 0 242 #define A80_USB_CLK_OHCI0 1 243 #define A80_USB_CLK_HCI1 2 244 #define A80_USB_CLK_HCI2 3 245 #define A80_USB_CLK_OHCI2 4 246 247 #define A80_USB_CLK_HCI0_PHY 5 248 #define A80_USB_CLK_HCI1_HSIC 6 249 #define A80_USB_CLK_HCI1_PHY 7 250 #define A80_USB_CLK_HCI2_HSIC 8 251 #define A80_USB_CLK_HCI2_UTMIPHY 9 252 #define A80_USB_CLK_HCI1_HSIC_12M 10 253 254 struct sxiccmu_ccu_bit sun9i_a80_usb_gates[] = { 255 [A80_USB_CLK_HCI0] = { 0x0000, 1 }, 256 [A80_USB_CLK_OHCI0] = { 0x0000, 2 }, 257 [A80_USB_CLK_HCI1] = { 0x0000, 3 }, 258 [A80_USB_CLK_HCI2] = { 0x0000, 5 }, 259 [A80_USB_CLK_OHCI2] = { 0x0000, 6 }, 260 [A80_USB_CLK_HCI0_PHY] = { 0x0004, 1 }, 261 [A80_USB_CLK_HCI1_HSIC] = { 0x0004, 2 }, 262 [A80_USB_CLK_HCI1_PHY] = { 0x0004, 3 }, /* Undocumented */ 263 [A80_USB_CLK_HCI2_HSIC] = { 0x0004, 4 }, 264 [A80_USB_CLK_HCI2_UTMIPHY] = { 0x0004, 5 }, 265 [A80_USB_CLK_HCI1_HSIC_12M] = { 0x0004, 10 }, 266 }; 267 268 struct sxiccmu_ccu_bit sun9i_a80_mmc_gates[] = { 269 { 0x0000, 16 }, 270 { 0x0004, 16 }, 271 { 0x0008, 16 }, 272 { 0x000c, 16 }, 273 }; 274 275 /* H3/H5 */ 276 277 #define H3_CLK_PLL_CPUX 0 278 #define H3_CLK_PLL_PERIPH0 9 279 280 #define H3_CLK_CPUX 14 281 #define H3_CLK_AXI 15 282 #define H3_CLK_AHB1 16 283 #define H3_CLK_APB1 17 284 #define H3_CLK_APB2 18 285 #define H3_CLK_AHB2 19 286 287 #define H3_CLK_BUS_MMC0 22 288 #define H3_CLK_BUS_MMC1 23 289 #define H3_CLK_BUS_MMC2 24 290 #define H3_CLK_BUS_EMAC 27 291 #define H3_CLK_BUS_EHCI0 33 292 #define H3_CLK_BUS_EHCI1 34 293 #define H3_CLK_BUS_EHCI2 35 294 #define H3_CLK_BUS_EHCI3 36 295 #define H3_CLK_BUS_OHCI0 37 296 #define H3_CLK_BUS_OHCI1 38 297 #define H3_CLK_BUS_OHCI2 39 298 #define H3_CLK_BUS_OHCI3 40 299 #define H3_CLK_BUS_PIO 54 300 #define H3_CLK_BUS_THS 55 301 #define H3_CLK_BUS_I2C0 59 302 #define H3_CLK_BUS_I2C1 60 303 #define H3_CLK_BUS_I2C2 61 304 #define H3_CLK_BUS_UART0 62 305 #define H3_CLK_BUS_UART1 63 306 #define H3_CLK_BUS_UART2 64 307 #define H3_CLK_BUS_UART3 65 308 #define H3_CLK_BUS_EPHY 67 309 310 #define H3_CLK_THS 69 311 #define H3_CLK_MMC0 71 312 #define H3_CLK_MMC1 74 313 #define H3_CLK_MMC2 77 314 #define H3_CLK_USB_PHY0 88 315 #define H3_CLK_USB_PHY1 89 316 #define H3_CLK_USB_PHY2 90 317 #define H3_CLK_USB_PHY3 91 318 319 #define H3_CLK_LOSC 254 320 #define H3_CLK_HOSC 253 321 322 struct sxiccmu_ccu_bit sun8i_h3_gates[] = { 323 [H3_CLK_PLL_PERIPH0] = { 0x0028, 31 }, 324 [H3_CLK_BUS_MMC0] = { 0x0060, 8 }, 325 [H3_CLK_BUS_MMC1] = { 0x0060, 9 }, 326 [H3_CLK_BUS_MMC2] = { 0x0060, 10 }, 327 [H3_CLK_BUS_EMAC] = { 0x0060, 17, H3_CLK_AHB2 }, 328 [H3_CLK_BUS_EHCI0] = { 0x0060, 24 }, 329 [H3_CLK_BUS_EHCI1] = { 0x0060, 25 }, 330 [H3_CLK_BUS_EHCI2] = { 0x0060, 26 }, 331 [H3_CLK_BUS_EHCI3] = { 0x0060, 27 }, 332 [H3_CLK_BUS_OHCI0] = { 0x0060, 28 }, 333 [H3_CLK_BUS_OHCI1] = { 0x0060, 29 }, 334 [H3_CLK_BUS_OHCI2] = { 0x0060, 30 }, 335 [H3_CLK_BUS_OHCI3] = { 0x0060, 31 }, 336 [H3_CLK_BUS_PIO] = { 0x0068, 5 }, 337 [H3_CLK_BUS_THS] = { 0x0068, 8 }, 338 [H3_CLK_BUS_I2C0] = { 0x006c, 0, H3_CLK_APB2 }, 339 [H3_CLK_BUS_I2C1] = { 0x006c, 1, H3_CLK_APB2 }, 340 [H3_CLK_BUS_I2C2] = { 0x006c, 2, H3_CLK_APB2 }, 341 [H3_CLK_BUS_UART0] = { 0x006c, 16, H3_CLK_APB2 }, 342 [H3_CLK_BUS_UART1] = { 0x006c, 17, H3_CLK_APB2 }, 343 [H3_CLK_BUS_UART2] = { 0x006c, 18, H3_CLK_APB2 }, 344 [H3_CLK_BUS_UART3] = { 0x006c, 19, H3_CLK_APB2 }, 345 [H3_CLK_BUS_EPHY] = { 0x0070, 0 }, 346 [H3_CLK_THS] = { 0x0074, 31 }, 347 [H3_CLK_MMC0] = { 0x0088, 31 }, 348 [H3_CLK_MMC1] = { 0x008c, 31 }, 349 [H3_CLK_MMC2] = { 0x0090, 31 }, 350 [H3_CLK_USB_PHY0] = { 0x00cc, 8 }, 351 [H3_CLK_USB_PHY1] = { 0x00cc, 9 }, 352 [H3_CLK_USB_PHY2] = { 0x00cc, 10 }, 353 [H3_CLK_USB_PHY3] = { 0x00cc, 11 }, 354 }; 355 356 #define H3_R_CLK_AHB0 1 357 #define H3_R_CLK_APB0 2 358 359 #define H3_R_CLK_APB0_PIO 3 360 #define H3_R_CLK_APB0_RSB 6 361 #define H3_R_CLK_APB0_I2C 9 362 363 struct sxiccmu_ccu_bit sun8i_h3_r_gates[] = { 364 [H3_R_CLK_APB0_PIO] = { 0x0028, 0 }, 365 [H3_R_CLK_APB0_RSB] = { 0x0028, 3, H3_R_CLK_APB0 }, 366 [H3_R_CLK_APB0_I2C] = { 0x0028, 6, H3_R_CLK_APB0 }, 367 }; 368 369 /* R40 */ 370 371 #define R40_CLK_PLL_PERIPH0 11 372 #define R40_CLK_PLL_PERIPH0_2X 13 373 374 #define R40_CLK_AXI 25 375 #define R40_CLK_AHB1 26 376 #define R40_CLK_APB2 28 377 378 #define R40_CLK_BUS_MMC0 32 379 #define R40_CLK_BUS_MMC1 33 380 #define R40_CLK_BUS_MMC2 34 381 #define R40_CLK_BUS_MMC3 35 382 #define R40_CLK_BUS_SATA 45 383 #define R40_CLK_BUS_EHCI0 47 384 #define R40_CLK_BUS_EHCI1 48 385 #define R40_CLK_BUS_EHCI2 49 386 #define R40_CLK_BUS_OHCI0 50 387 #define R40_CLK_BUS_OHCI1 51 388 #define R40_CLK_BUS_OHCI2 52 389 #define R40_CLK_BUS_GMAC 64 390 #define R40_CLK_BUS_PIO 79 391 #define R40_CLK_BUS_THS 82 392 #define R40_CLK_BUS_I2C0 87 393 #define R40_CLK_BUS_I2C1 88 394 #define R40_CLK_BUS_I2C2 89 395 #define R40_CLK_BUS_I2C3 90 396 #define R40_CLK_BUS_I2C4 95 397 #define R40_CLK_BUS_UART0 96 398 #define R40_CLK_BUS_UART1 97 399 #define R40_CLK_BUS_UART2 98 400 #define R40_CLK_BUS_UART3 99 401 #define R40_CLK_BUS_UART4 100 402 #define R40_CLK_BUS_UART5 101 403 #define R40_CLK_BUS_UART6 102 404 #define R40_CLK_BUS_UART7 103 405 406 #define R40_CLK_THS 105 407 #define R40_CLK_MMC0 107 408 #define R40_CLK_MMC1 108 409 #define R40_CLK_MMC2 109 410 #define R40_CLK_MMC3 110 411 #define R40_CLK_SATA 123 412 #define R40_CLK_USB_PHY0 124 413 #define R40_CLK_USB_PHY1 125 414 #define R40_CLK_USB_PHY2 126 415 416 #define R40_CLK_HOSC 253 417 #define R40_CLK_LOSC 254 418 419 struct sxiccmu_ccu_bit sun8i_r40_gates[] = { 420 [R40_CLK_BUS_MMC0] = { 0x0060, 8 }, 421 [R40_CLK_BUS_MMC1] = { 0x0060, 9 }, 422 [R40_CLK_BUS_MMC2] = { 0x0060, 10 }, 423 [R40_CLK_BUS_MMC3] = { 0x0060, 11 }, 424 [R40_CLK_BUS_SATA] = { 0x0060, 24 }, 425 [R40_CLK_BUS_EHCI0] = { 0x0060, 26 }, 426 [R40_CLK_BUS_EHCI1] = { 0x0060, 27 }, 427 [R40_CLK_BUS_EHCI2] = { 0x0060, 28 }, 428 [R40_CLK_BUS_OHCI0] = { 0x0060, 29 }, 429 [R40_CLK_BUS_OHCI1] = { 0x0060, 30 }, 430 [R40_CLK_BUS_OHCI2] = { 0x0060, 31 }, 431 [R40_CLK_BUS_GMAC] = { 0x0064, 17, R40_CLK_AHB1 }, 432 [R40_CLK_BUS_PIO] = { 0x0068, 5 }, 433 [R40_CLK_BUS_THS] = { 0x0068, 8 }, 434 [R40_CLK_BUS_I2C0] = { 0x006c, 0, R40_CLK_APB2 }, 435 [R40_CLK_BUS_I2C1] = { 0x006c, 1, R40_CLK_APB2 }, 436 [R40_CLK_BUS_I2C2] = { 0x006c, 2, R40_CLK_APB2 }, 437 [R40_CLK_BUS_I2C3] = { 0x006c, 3, R40_CLK_APB2 }, 438 [R40_CLK_BUS_I2C4] = { 0x006c, 15, R40_CLK_APB2 }, 439 [R40_CLK_BUS_UART0] = { 0x006c, 16, R40_CLK_APB2 }, 440 [R40_CLK_BUS_UART1] = { 0x006c, 17, R40_CLK_APB2 }, 441 [R40_CLK_BUS_UART2] = { 0x006c, 18, R40_CLK_APB2 }, 442 [R40_CLK_BUS_UART3] = { 0x006c, 19, R40_CLK_APB2 }, 443 [R40_CLK_BUS_UART4] = { 0x006c, 20, R40_CLK_APB2 }, 444 [R40_CLK_BUS_UART5] = { 0x006c, 21, R40_CLK_APB2 }, 445 [R40_CLK_BUS_UART6] = { 0x006c, 22, R40_CLK_APB2 }, 446 [R40_CLK_BUS_UART7] = { 0x006c, 23, R40_CLK_APB2 }, 447 [R40_CLK_THS] = { 0x0074, 31 }, 448 [R40_CLK_MMC0] = { 0x0088, 31 }, 449 [R40_CLK_MMC1] = { 0x008c, 31 }, 450 [R40_CLK_MMC2] = { 0x0090, 31 }, 451 [R40_CLK_MMC3] = { 0x0094, 31 }, 452 [R40_CLK_SATA] = { 0x00c8, 31 }, 453 [R40_CLK_USB_PHY0] = { 0x00cc, 8 }, 454 [R40_CLK_USB_PHY1] = { 0x00cc, 9 }, 455 [R40_CLK_USB_PHY2] = { 0x00cc, 10 }, 456 }; 457 458 /* 459 * Reset Signals 460 */ 461 462 /* A10 */ 463 464 #define A10_RST_USB_PHY0 1 465 #define A10_RST_USB_PHY1 2 466 #define A10_RST_USB_PHY2 3 467 468 struct sxiccmu_ccu_bit sun4i_a10_resets[] = { 469 [A10_RST_USB_PHY0] = { 0x00cc, 0 }, 470 [A10_RST_USB_PHY1] = { 0x00cc, 1 }, 471 [A10_RST_USB_PHY2] = { 0x00cc, 2 }, 472 }; 473 474 /* A23/A33 */ 475 476 #define A23_RST_USB_PHY0 0 477 #define A23_RST_USB_PHY1 1 478 479 #define A23_RST_BUS_MMC0 7 480 #define A23_RST_BUS_MMC1 8 481 #define A23_RST_BUS_MMC2 9 482 483 #define A23_RST_BUS_EHCI 16 484 #define A23_RST_BUS_OHCI 17 485 486 #define A23_RST_BUS_I2C0 32 487 #define A23_RST_BUS_I2C1 33 488 #define A23_RST_BUS_I2C2 34 489 490 #define A23_CLK_HOSC 253 491 #define A23_CLK_LOSC 254 492 493 struct sxiccmu_ccu_bit sun8i_a23_resets[] = { 494 [A23_RST_USB_PHY0] = { 0x00cc, 0 }, 495 [A23_RST_USB_PHY1] = { 0x00cc, 1 }, 496 [A23_RST_BUS_MMC0] = { 0x02c0, 8 }, 497 [A23_RST_BUS_MMC1] = { 0x02c0, 9 }, 498 [A23_RST_BUS_MMC2] = { 0x02c0, 10 }, 499 [A23_RST_BUS_EHCI] = { 0x02c0, 26 }, 500 [A23_RST_BUS_OHCI] = { 0x02c0, 29 }, 501 [A23_RST_BUS_I2C0] = { 0x02d8, 0 }, 502 [A23_RST_BUS_I2C1] = { 0x02d8, 1 }, 503 [A23_RST_BUS_I2C2] = { 0x02d8, 2 }, 504 }; 505 506 /* A64 */ 507 508 #define A64_RST_USB_PHY0 0 509 #define A64_RST_USB_PHY1 1 510 511 #define A64_RST_BUS_MMC0 8 512 #define A64_RST_BUS_MMC1 9 513 #define A64_RST_BUS_MMC2 10 514 #define A64_RST_BUS_EMAC 13 515 #define A64_RST_BUS_EHCI0 19 516 #define A64_RST_BUS_EHCI1 20 517 #define A64_RST_BUS_OHCI0 21 518 #define A64_RST_BUS_OHCI1 22 519 #define A64_RST_BUS_THS 38 520 #define A64_RST_BUS_I2C0 42 521 #define A64_RST_BUS_I2C1 43 522 #define A64_RST_BUS_I2C2 44 523 524 struct sxiccmu_ccu_bit sun50i_a64_resets[] = { 525 [A64_RST_USB_PHY0] = { 0x00cc, 0 }, 526 [A64_RST_USB_PHY1] = { 0x00cc, 1 }, 527 [A64_RST_BUS_MMC0] = { 0x02c0, 8 }, 528 [A64_RST_BUS_MMC1] = { 0x02c0, 9 }, 529 [A64_RST_BUS_MMC2] = { 0x02c0, 10 }, 530 [A64_RST_BUS_EMAC] = { 0x02c0, 17 }, 531 [A64_RST_BUS_EHCI0] = { 0x02c0, 24 }, 532 [A64_RST_BUS_EHCI1] = { 0x02c0, 25 }, 533 [A64_RST_BUS_OHCI0] = { 0x02c0, 28 }, 534 [A64_RST_BUS_OHCI1] = { 0x02c0, 29 }, 535 [A64_RST_BUS_THS] = { 0x02d0, 8 }, 536 [A64_RST_BUS_I2C0] = { 0x02d8, 0 }, 537 [A64_RST_BUS_I2C1] = { 0x02d8, 1 }, 538 [A64_RST_BUS_I2C2] = { 0x02d8, 2 }, 539 }; 540 541 /* A80 */ 542 543 #define A80_RST_BUS_MMC 4 544 #define A80_RST_BUS_UART0 45 545 #define A80_RST_BUS_UART1 46 546 #define A80_RST_BUS_UART2 47 547 #define A80_RST_BUS_UART3 48 548 #define A80_RST_BUS_UART4 49 549 #define A80_RST_BUS_UART5 50 550 551 struct sxiccmu_ccu_bit sun9i_a80_resets[] = { 552 [A80_RST_BUS_MMC] = { 0x05a0, 8 }, 553 [A80_RST_BUS_UART0] = { 0x05b4, 16 }, 554 [A80_RST_BUS_UART1] = { 0x05b4, 17 }, 555 [A80_RST_BUS_UART2] = { 0x05b4, 18 }, 556 [A80_RST_BUS_UART3] = { 0x05b4, 19 }, 557 [A80_RST_BUS_UART4] = { 0x05b4, 20 }, 558 [A80_RST_BUS_UART5] = { 0x05b4, 21 }, 559 }; 560 561 #define A80_USB_RST_HCI0 0 562 #define A80_USB_RST_HCI1 1 563 #define A80_USB_RST_HCI2 2 564 565 #define A80_USB_RST_HCI0_PHY 3 566 #define A80_USB_RST_HCI1_HSIC 4 567 #define A80_USB_RST_HCI1_PHY 5 568 #define A80_USB_RST_HCI2_HSIC 6 569 #define A80_USB_RST_HCI2_UTMIPHY 7 570 571 struct sxiccmu_ccu_bit sun9i_a80_usb_resets[] = { 572 [A80_USB_RST_HCI0] = { 0x0000, 17 }, 573 [A80_USB_RST_HCI1] = { 0x0000, 18 }, 574 [A80_USB_RST_HCI2] = { 0x0000, 19 }, 575 [A80_USB_RST_HCI0_PHY] = { 0x0004, 17 }, 576 [A80_USB_RST_HCI1_HSIC]= { 0x0004, 18 }, 577 [A80_USB_RST_HCI1_PHY]= { 0x0004, 19 }, /* Undocumented */ 578 [A80_USB_RST_HCI2_HSIC]= { 0x0004, 20 }, /* Undocumented */ 579 [A80_USB_RST_HCI2_UTMIPHY] = { 0x0004, 21 }, 580 }; 581 582 struct sxiccmu_ccu_bit sun9i_a80_mmc_resets[] = { 583 { 0x0000, 18 }, 584 { 0x0004, 18 }, 585 { 0x0008, 18 }, 586 { 0x000c, 18 }, 587 }; 588 589 /* H3/H5 */ 590 591 #define H3_RST_USB_PHY0 0 592 #define H3_RST_USB_PHY1 1 593 #define H3_RST_USB_PHY2 2 594 #define H3_RST_USB_PHY3 3 595 596 #define H3_RST_BUS_MMC0 7 597 #define H3_RST_BUS_MMC1 8 598 #define H3_RST_BUS_MMC2 9 599 600 #define H3_RST_BUS_EMAC 12 601 602 #define H3_RST_BUS_EHCI0 18 603 #define H3_RST_BUS_EHCI1 19 604 #define H3_RST_BUS_EHCI2 20 605 #define H3_RST_BUS_EHCI3 21 606 #define H3_RST_BUS_OHCI0 22 607 #define H3_RST_BUS_OHCI1 23 608 #define H3_RST_BUS_OHCI2 24 609 #define H3_RST_BUS_OHCI3 25 610 #define H3_RST_BUS_EPHY 39 611 #define H3_RST_BUS_THS 42 612 #define H3_RST_BUS_I2C0 46 613 #define H3_RST_BUS_I2C1 47 614 #define H3_RST_BUS_I2C2 48 615 616 struct sxiccmu_ccu_bit sun8i_h3_resets[] = { 617 [H3_RST_USB_PHY0] = { 0x00cc, 0 }, 618 [H3_RST_USB_PHY1] = { 0x00cc, 1 }, 619 [H3_RST_USB_PHY2] = { 0x00cc, 2 }, 620 [H3_RST_USB_PHY3] = { 0x00cc, 3 }, 621 [H3_RST_BUS_MMC0] = { 0x02c0, 8 }, 622 [H3_RST_BUS_MMC1] = { 0x02c0, 9 }, 623 [H3_RST_BUS_MMC2] = { 0x02c0, 10 }, 624 [H3_RST_BUS_EMAC] = { 0x02c0, 17 }, 625 [H3_RST_BUS_EHCI0] = { 0x02c0, 24 }, 626 [H3_RST_BUS_EHCI1] = { 0x02c0, 25 }, 627 [H3_RST_BUS_EHCI2] = { 0x02c0, 26 }, 628 [H3_RST_BUS_EHCI3] = { 0x02c0, 27 }, 629 [H3_RST_BUS_OHCI0] = { 0x02c0, 28 }, 630 [H3_RST_BUS_OHCI1] = { 0x02c0, 29 }, 631 [H3_RST_BUS_OHCI2] = { 0x02c0, 30 }, 632 [H3_RST_BUS_OHCI3] = { 0x02c0, 31 }, 633 [H3_RST_BUS_EPHY] = { 0x02c8, 2 }, 634 [H3_RST_BUS_THS] = { 0x02d0, 8 }, 635 [H3_RST_BUS_I2C0] = { 0x02d8, 0 }, 636 [H3_RST_BUS_I2C1] = { 0x02d8, 1 }, 637 [H3_RST_BUS_I2C2] = { 0x02d8, 2 }, 638 }; 639 640 #define H3_R_RST_APB0_RSB 2 641 #define H3_R_RST_APB0_I2C 5 642 643 struct sxiccmu_ccu_bit sun8i_h3_r_resets[] = { 644 [H3_R_RST_APB0_RSB] = { 0x00b0, 3 }, 645 [H3_R_RST_APB0_I2C] = { 0x00b0, 6 }, 646 }; 647 648 /* R40 */ 649 650 #define R40_RST_USB_PHY0 0 651 #define R40_RST_USB_PHY1 1 652 #define R40_RST_USB_PHY2 2 653 654 #define R40_RST_BUS_MMC0 8 655 #define R40_RST_BUS_MMC1 9 656 #define R40_RST_BUS_MMC2 10 657 #define R40_RST_BUS_MMC3 11 658 #define R40_RST_BUS_SATA 21 659 #define R40_RST_BUS_EHCI0 23 660 #define R40_RST_BUS_EHCI1 24 661 #define R40_RST_BUS_EHCI2 25 662 #define R40_RST_BUS_OHCI0 26 663 #define R40_RST_BUS_OHCI1 27 664 #define R40_RST_BUS_OHCI2 28 665 #define R40_RST_BUS_GMAC 40 666 #define R40_RST_BUS_THS 59 667 #define R40_RST_BUS_I2C0 64 668 #define R40_RST_BUS_I2C1 65 669 #define R40_RST_BUS_I2C2 66 670 #define R40_RST_BUS_I2C3 67 671 #define R40_RST_BUS_I2C4 72 672 #define R40_RST_BUS_UART0 73 673 #define R40_RST_BUS_UART1 74 674 #define R40_RST_BUS_UART2 75 675 #define R40_RST_BUS_UART3 76 676 #define R40_RST_BUS_UART4 77 677 #define R40_RST_BUS_UART5 78 678 #define R40_RST_BUS_UART6 79 679 #define R40_RST_BUS_UART7 80 680 681 struct sxiccmu_ccu_bit sun8i_r40_resets[] = { 682 [R40_RST_USB_PHY0] = { 0x00cc, 0 }, 683 [R40_RST_USB_PHY1] = { 0x00cc, 1 }, 684 [R40_RST_USB_PHY2] = { 0x00cc, 2 }, 685 [R40_RST_BUS_MMC0] = { 0x02c0, 8 }, 686 [R40_RST_BUS_MMC1] = { 0x02c0, 9 }, 687 [R40_RST_BUS_MMC2] = { 0x02c0, 10 }, 688 [R40_RST_BUS_MMC3] = { 0x02c0, 11 }, 689 [R40_RST_BUS_SATA] = { 0x02c0, 24 }, 690 [R40_RST_BUS_EHCI0] = { 0x02c0, 26 }, 691 [R40_RST_BUS_EHCI1] = { 0x02c0, 27 }, 692 [R40_RST_BUS_EHCI2] = { 0x02c0, 28 }, 693 [R40_RST_BUS_OHCI0] = { 0x02c0, 29 }, 694 [R40_RST_BUS_OHCI1] = { 0x02c0, 30 }, 695 [R40_RST_BUS_OHCI2] = { 0x02c0, 31 }, 696 [R40_RST_BUS_GMAC] = { 0x02c4, 17 }, 697 [R40_RST_BUS_THS] = { 0x02d0, 8 }, 698 [R40_RST_BUS_I2C0] = { 0x02d8, 0 }, 699 [R40_RST_BUS_I2C1] = { 0x02d8, 1 }, 700 [R40_RST_BUS_I2C2] = { 0x02d8, 2 }, 701 [R40_RST_BUS_I2C3] = { 0x02d8, 3 }, 702 [R40_RST_BUS_I2C4] = { 0x02d8, 15 }, 703 [R40_RST_BUS_UART0] = { 0x02d8, 16 }, 704 [R40_RST_BUS_UART1] = { 0x02d8, 17 }, 705 [R40_RST_BUS_UART2] = { 0x02d8, 18 }, 706 [R40_RST_BUS_UART3] = { 0x02d8, 19 }, 707 [R40_RST_BUS_UART4] = { 0x02d8, 20 }, 708 [R40_RST_BUS_UART5] = { 0x02d8, 21 }, 709 [R40_RST_BUS_UART6] = { 0x02d8, 22 }, 710 [R40_RST_BUS_UART7] = { 0x02d8, 23 }, 711 }; 712