1 /* Public Domain */ 2 3 4 /* 5 * Clocks Signals 6 */ 7 8 /* A10/A20 */ 9 10 #define A10_CLK_HOSC 1 11 #define A10_CLK_PLL_CORE 2 12 #define A10_CLK_PLL_PERIPH_BASE 14 13 #define A10_CLK_PLL_PERIPH 15 14 15 #define A10_CLK_CPU 20 16 #define A10_CLK_APB1 25 17 18 #define A10_CLK_AHB_EHCI0 27 19 #define A10_CLK_AHB_OHCI0 28 20 #define A10_CLK_AHB_EHCI1 29 21 #define A10_CLK_AHB_OHCI1 30 22 #define A10_CLK_AHB_MMC0 34 23 #define A10_CLK_AHB_MMC1 35 24 #define A10_CLK_AHB_MMC2 36 25 #define A10_CLK_AHB_MMC3 37 26 #define A10_CLK_AHB_EMAC 42 27 #define A10_CLK_AHB_SATA 49 28 #define A10_CLK_AHB_GMAC 66 29 #define A10_CLK_APB0_PIO 74 30 #define A10_CLK_APB1_I2C0 79 31 #define A10_CLK_APB1_I2C1 80 32 #define A10_CLK_APB1_I2C2 81 33 #define A10_CLK_APB1_I2C3 82 34 #define A10_CLK_APB1_I2C4 87 35 #define A10_CLK_APB1_UART0 88 36 #define A10_CLK_APB1_UART1 89 37 #define A10_CLK_APB1_UART2 90 38 #define A10_CLK_APB1_UART3 91 39 #define A10_CLK_APB1_UART4 92 40 #define A10_CLK_APB1_UART5 93 41 #define A10_CLK_APB1_UART6 94 42 #define A10_CLK_APB1_UART7 95 43 44 #define A10_CLK_MMC0 98 45 #define A10_CLK_MMC1 101 46 #define A10_CLK_MMC2 104 47 #define A10_CLK_MMC3 107 48 #define A10_CLK_SATA 122 49 #define A10_CLK_USB_OHCI0 123 50 #define A10_CLK_USB_OHCI1 124 51 #define A10_CLK_USB_PHY 125 52 53 #define A10_CLK_LOSC 254 54 55 struct sxiccmu_ccu_bit sun4i_a10_gates[] = { 56 [A10_CLK_AHB_EHCI0] = { 0x0060, 1 }, 57 [A10_CLK_AHB_OHCI0] = { 0x0060, 2 }, 58 [A10_CLK_AHB_EHCI1] = { 0x0060, 3 }, 59 [A10_CLK_AHB_OHCI1] = { 0x0060, 4 }, 60 [A10_CLK_AHB_MMC0] = { 0x0060, 8 }, 61 [A10_CLK_AHB_MMC1] = { 0x0060, 9 }, 62 [A10_CLK_AHB_MMC2] = { 0x0060, 10 }, 63 [A10_CLK_AHB_MMC3] = { 0x0060, 11 }, 64 [A10_CLK_AHB_EMAC] = { 0x0060, 17 }, 65 [A10_CLK_AHB_SATA] = { 0x0060, 25 }, 66 [A10_CLK_AHB_GMAC] = { 0x0064, 17 }, 67 [A10_CLK_APB0_PIO] = { 0x0068, 5 }, 68 [A10_CLK_APB1_I2C0] = { 0x006c, 0, A10_CLK_APB1 }, 69 [A10_CLK_APB1_I2C1] = { 0x006c, 1, A10_CLK_APB1 }, 70 [A10_CLK_APB1_I2C2] = { 0x006c, 2, A10_CLK_APB1 }, 71 [A10_CLK_APB1_I2C3] = { 0x006c, 3, A10_CLK_APB1 }, 72 [A10_CLK_APB1_I2C4] = { 0x006c, 15, A10_CLK_APB1 }, 73 [A10_CLK_APB1_UART0] = { 0x006c, 16, A10_CLK_APB1 }, 74 [A10_CLK_APB1_UART1] = { 0x006c, 17, A10_CLK_APB1 }, 75 [A10_CLK_APB1_UART2] = { 0x006c, 18, A10_CLK_APB1 }, 76 [A10_CLK_APB1_UART3] = { 0x006c, 19, A10_CLK_APB1 }, 77 [A10_CLK_APB1_UART4] = { 0x006c, 20, A10_CLK_APB1 }, 78 [A10_CLK_APB1_UART5] = { 0x006c, 21, A10_CLK_APB1 }, 79 [A10_CLK_APB1_UART6] = { 0x006c, 22, A10_CLK_APB1 }, 80 [A10_CLK_APB1_UART7] = { 0x006c, 23, A10_CLK_APB1 }, 81 [A10_CLK_MMC0] = { 0x0088, 31 }, 82 [A10_CLK_MMC1] = { 0x008c, 31 }, 83 [A10_CLK_MMC2] = { 0x0090, 31 }, 84 [A10_CLK_MMC3] = { 0x0094, 31 }, 85 [A10_CLK_SATA] = { 0x00c8, 31 }, 86 [A10_CLK_USB_OHCI0] = { 0x00cc, 6 }, 87 [A10_CLK_USB_OHCI1] = { 0x00cc, 7 }, 88 [A10_CLK_USB_PHY] = { 0x00cc, 8 }, 89 }; 90 91 /* A23/A33 */ 92 93 #define A23_CLK_PLL_PERIPH 10 94 95 #define A23_CLK_AXI 19 96 #define A23_CLK_AHB1 20 97 #define A23_CLK_APB1 21 98 #define A23_CLK_APB2 22 99 100 #define A23_CLK_BUS_MMC0 26 101 #define A23_CLK_BUS_MMC1 27 102 #define A23_CLK_BUS_MMC2 28 103 #define A23_CLK_BUS_EHCI 35 104 #define A23_CLK_BUS_OHCI 36 105 #define A23_CLK_BUS_PIO 48 106 #define A23_CLK_BUS_I2C0 51 107 #define A23_CLK_BUS_I2C1 52 108 #define A23_CLK_BUS_I2C2 53 109 #define A23_CLK_BUS_UART0 54 110 #define A23_CLK_BUS_UART1 55 111 #define A23_CLK_BUS_UART2 56 112 #define A23_CLK_BUS_UART3 57 113 #define A23_CLK_BUS_UART4 58 114 115 #define A23_CLK_MMC0 60 116 #define A23_CLK_MMC1 63 117 #define A23_CLK_MMC2 66 118 #define A23_CLK_USB_OHCI 78 119 120 struct sxiccmu_ccu_bit sun8i_a23_gates[] = { 121 [A23_CLK_BUS_MMC0] = { 0x0060, 8 }, 122 [A23_CLK_BUS_MMC1] = { 0x0060, 9 }, 123 [A23_CLK_BUS_MMC2] = { 0x0060, 10 }, 124 [A23_CLK_BUS_EHCI] = { 0x0060, 26 }, 125 [A23_CLK_BUS_OHCI] = { 0x0060, 29 }, 126 [A23_CLK_BUS_PIO] = { 0x0068, 5 }, 127 [A23_CLK_BUS_I2C0] = { 0x006c, 0, A23_CLK_APB2 }, 128 [A23_CLK_BUS_I2C1] = { 0x006c, 1, A23_CLK_APB2 }, 129 [A23_CLK_BUS_I2C2] = { 0x006c, 2, A23_CLK_APB2 }, 130 [A23_CLK_BUS_UART0] = { 0x006c, 16, A23_CLK_APB2 }, 131 [A23_CLK_BUS_UART1] = { 0x006c, 17, A23_CLK_APB2 }, 132 [A23_CLK_BUS_UART2] = { 0x006c, 18, A23_CLK_APB2 }, 133 [A23_CLK_BUS_UART3] = { 0x006c, 19, A23_CLK_APB2 }, 134 [A23_CLK_BUS_UART4] = { 0x006c, 20, A23_CLK_APB2 }, 135 [A23_CLK_MMC0] = { 0x0088, 31 }, 136 [A23_CLK_MMC1] = { 0x008c, 31 }, 137 [A23_CLK_MMC2] = { 0x0090, 31 }, 138 [A23_CLK_USB_OHCI] = { 0x00cc, 16 }, 139 }; 140 141 /* A64 */ 142 143 #define A64_CLK_PLL_PERIPH0 11 144 #define A64_CLK_PLL_PERIPH0_2X 12 145 146 #define A64_CLK_AXI 22 147 #define A64_CLK_APB 23 148 #define A64_CLK_AHB1 24 149 #define A64_CLK_APB1 25 150 #define A64_CLK_APB2 26 151 #define A64_CLK_AHB2 27 152 153 #define A64_CLK_BUS_MMC0 31 154 #define A64_CLK_BUS_MMC1 32 155 #define A64_CLK_BUS_MMC2 33 156 #define A64_CLK_BUS_EMAC 36 157 #define A64_CLK_BUS_EHCI0 42 158 #define A64_CLK_BUS_EHCI1 43 159 #define A64_CLK_BUS_OHCI0 44 160 #define A64_CLK_BUS_OHCI1 45 161 #define A64_CLK_BUS_PIO 58 162 #define A64_CLK_BUS_THS 59 163 #define A64_CLK_BUS_I2C0 63 164 #define A64_CLK_BUS_I2C1 64 165 #define A64_CLK_BUS_I2C2 65 166 #define A64_CLK_BUS_UART0 67 167 #define A64_CLK_BUS_UART1 68 168 #define A64_CLK_BUS_UART2 69 169 #define A64_CLK_BUS_UART3 70 170 #define A64_CLK_BUS_UART4 71 171 172 #define A64_CLK_THS 73 173 #define A64_CLK_MMC0 75 174 #define A64_CLK_MMC1 76 175 #define A64_CLK_MMC2 77 176 #define A64_CLK_USB_OHCI0 91 177 #define A64_CLK_USB_OHCI1 93 178 #define A64_CLK_USB_PHY0 86 179 #define A64_CLK_USB_PHY1 87 180 181 #define A64_CLK_LOSC 254 182 #define A64_CLK_HOSC 253 183 184 struct sxiccmu_ccu_bit sun50i_a64_gates[] = { 185 [A64_CLK_PLL_PERIPH0] = { 0x0028, 31 }, 186 [A64_CLK_BUS_MMC0] = { 0x0060, 8 }, 187 [A64_CLK_BUS_MMC1] = { 0x0060, 9 }, 188 [A64_CLK_BUS_MMC2] = { 0x0060, 10 }, 189 [A64_CLK_BUS_EMAC] = { 0x0060, 17, A64_CLK_AHB2 }, 190 [A64_CLK_BUS_EHCI0] = { 0x0060, 24 }, 191 [A64_CLK_BUS_EHCI1] = { 0x0060, 25 }, 192 [A64_CLK_BUS_OHCI0] = { 0x0060, 28 }, 193 [A64_CLK_BUS_OHCI1] = { 0x0060, 29 }, 194 [A64_CLK_BUS_PIO] = { 0x0068, 5 }, 195 [A64_CLK_BUS_THS] = { 0x0068, 8 }, 196 [A64_CLK_BUS_I2C0] = { 0x006c, 0, A64_CLK_APB2 }, 197 [A64_CLK_BUS_I2C1] = { 0x006c, 1, A64_CLK_APB2 }, 198 [A64_CLK_BUS_I2C2] = { 0x006c, 2, A64_CLK_APB2 }, 199 [A64_CLK_BUS_UART0] = { 0x006c, 16, A64_CLK_APB2 }, 200 [A64_CLK_BUS_UART1] = { 0x006c, 17, A64_CLK_APB2 }, 201 [A64_CLK_BUS_UART2] = { 0x006c, 18, A64_CLK_APB2 }, 202 [A64_CLK_BUS_UART3] = { 0x006c, 19, A64_CLK_APB2 }, 203 [A64_CLK_BUS_UART4] = { 0x006c, 20, A64_CLK_APB2 }, 204 [A64_CLK_THS] = { 0x0074, 31 }, 205 [A64_CLK_MMC0] = { 0x0088, 31 }, 206 [A64_CLK_MMC1] = { 0x008c, 31 }, 207 [A64_CLK_MMC2] = { 0x0090, 31 }, 208 [A64_CLK_USB_OHCI0] = { 0x00cc, 16 }, 209 [A64_CLK_USB_OHCI1] = { 0x00cc, 17 }, 210 [A64_CLK_USB_PHY0] = { 0x00cc, 8 }, 211 [A64_CLK_USB_PHY1] = { 0x00cc, 9 }, 212 }; 213 214 /* A80 */ 215 216 #define A80_CLK_PLL_PERIPH0 3 217 218 #define A80_CLK_APB1 23 219 220 #define A80_CLK_MMC0 33 221 #define A80_CLK_MMC1 36 222 #define A80_CLK_MMC2 39 223 #define A80_CLK_MMC3 42 224 225 #define A80_CLK_BUS_MMC 84 226 #define A80_CLK_BUS_USB 96 227 #define A80_CLK_BUS_PIO 111 228 #define A80_CLK_BUS_UART0 124 229 #define A80_CLK_BUS_UART1 125 230 #define A80_CLK_BUS_UART2 126 231 #define A80_CLK_BUS_UART3 127 232 #define A80_CLK_BUS_UART4 128 233 #define A80_CLK_BUS_UART5 129 234 235 struct sxiccmu_ccu_bit sun9i_a80_gates[] = { 236 [A80_CLK_MMC0] = { 0x0410, 31 }, 237 [A80_CLK_MMC1] = { 0x0414, 31 }, 238 [A80_CLK_MMC2] = { 0x0418, 31 }, 239 [A80_CLK_MMC3] = { 0x041c, 31 }, /* Undocumented */ 240 [A80_CLK_BUS_MMC] = { 0x0580, 8 }, 241 [A80_CLK_BUS_USB] = { 0x0584, 1 }, 242 [A80_CLK_BUS_PIO] = { 0x0590, 5 }, 243 [A80_CLK_BUS_UART0] = { 0x0594, 16, A80_CLK_APB1 }, 244 [A80_CLK_BUS_UART1] = { 0x0594, 17, A80_CLK_APB1 }, 245 [A80_CLK_BUS_UART2] = { 0x0594, 18, A80_CLK_APB1 }, 246 [A80_CLK_BUS_UART3] = { 0x0594, 19, A80_CLK_APB1 }, 247 [A80_CLK_BUS_UART4] = { 0x0594, 20, A80_CLK_APB1 }, 248 [A80_CLK_BUS_UART5] = { 0x0594, 21, A80_CLK_APB1 }, 249 }; 250 251 #define A80_USB_CLK_HCI0 0 252 #define A80_USB_CLK_OHCI0 1 253 #define A80_USB_CLK_HCI1 2 254 #define A80_USB_CLK_HCI2 3 255 #define A80_USB_CLK_OHCI2 4 256 257 #define A80_USB_CLK_HCI0_PHY 5 258 #define A80_USB_CLK_HCI1_HSIC 6 259 #define A80_USB_CLK_HCI1_PHY 7 260 #define A80_USB_CLK_HCI2_HSIC 8 261 #define A80_USB_CLK_HCI2_UTMIPHY 9 262 #define A80_USB_CLK_HCI1_HSIC_12M 10 263 264 struct sxiccmu_ccu_bit sun9i_a80_usb_gates[] = { 265 [A80_USB_CLK_HCI0] = { 0x0000, 1 }, 266 [A80_USB_CLK_OHCI0] = { 0x0000, 2 }, 267 [A80_USB_CLK_HCI1] = { 0x0000, 3 }, 268 [A80_USB_CLK_HCI2] = { 0x0000, 5 }, 269 [A80_USB_CLK_OHCI2] = { 0x0000, 6 }, 270 [A80_USB_CLK_HCI0_PHY] = { 0x0004, 1 }, 271 [A80_USB_CLK_HCI1_HSIC] = { 0x0004, 2 }, 272 [A80_USB_CLK_HCI1_PHY] = { 0x0004, 3 }, /* Undocumented */ 273 [A80_USB_CLK_HCI2_HSIC] = { 0x0004, 4 }, 274 [A80_USB_CLK_HCI2_UTMIPHY] = { 0x0004, 5 }, 275 [A80_USB_CLK_HCI1_HSIC_12M] = { 0x0004, 10 }, 276 }; 277 278 struct sxiccmu_ccu_bit sun9i_a80_mmc_gates[] = { 279 { 0x0000, 16 }, 280 { 0x0004, 16 }, 281 { 0x0008, 16 }, 282 { 0x000c, 16 }, 283 }; 284 285 /* H3/H5 */ 286 287 #define H3_CLK_PLL_CPUX 0 288 #define H3_CLK_PLL_PERIPH0 9 289 290 #define H3_CLK_CPUX 14 291 #define H3_CLK_AXI 15 292 #define H3_CLK_AHB1 16 293 #define H3_CLK_APB1 17 294 #define H3_CLK_APB2 18 295 #define H3_CLK_AHB2 19 296 297 #define H3_CLK_BUS_MMC0 22 298 #define H3_CLK_BUS_MMC1 23 299 #define H3_CLK_BUS_MMC2 24 300 #define H3_CLK_BUS_EMAC 27 301 #define H3_CLK_BUS_EHCI0 33 302 #define H3_CLK_BUS_EHCI1 34 303 #define H3_CLK_BUS_EHCI2 35 304 #define H3_CLK_BUS_EHCI3 36 305 #define H3_CLK_BUS_OHCI0 37 306 #define H3_CLK_BUS_OHCI1 38 307 #define H3_CLK_BUS_OHCI2 39 308 #define H3_CLK_BUS_OHCI3 40 309 #define H3_CLK_BUS_PIO 54 310 #define H3_CLK_BUS_THS 55 311 #define H3_CLK_BUS_I2C0 59 312 #define H3_CLK_BUS_I2C1 60 313 #define H3_CLK_BUS_I2C2 61 314 #define H3_CLK_BUS_UART0 62 315 #define H3_CLK_BUS_UART1 63 316 #define H3_CLK_BUS_UART2 64 317 #define H3_CLK_BUS_UART3 65 318 #define H3_CLK_BUS_EPHY 67 319 320 #define H3_CLK_THS 69 321 #define H3_CLK_MMC0 71 322 #define H3_CLK_MMC1 74 323 #define H3_CLK_MMC2 77 324 #define H3_CLK_USB_PHY0 88 325 #define H3_CLK_USB_PHY1 89 326 #define H3_CLK_USB_PHY2 90 327 #define H3_CLK_USB_PHY3 91 328 #define H3_CLK_USB_OHCI0 92 329 #define H3_CLK_USB_OHCI1 93 330 #define H3_CLK_USB_OHCI2 94 331 #define H3_CLK_USB_OHCI3 95 332 333 #define H3_CLK_LOSC 254 334 #define H3_CLK_HOSC 253 335 336 struct sxiccmu_ccu_bit sun8i_h3_gates[] = { 337 [H3_CLK_PLL_PERIPH0] = { 0x0028, 31 }, 338 [H3_CLK_BUS_MMC0] = { 0x0060, 8 }, 339 [H3_CLK_BUS_MMC1] = { 0x0060, 9 }, 340 [H3_CLK_BUS_MMC2] = { 0x0060, 10 }, 341 [H3_CLK_BUS_EMAC] = { 0x0060, 17, H3_CLK_AHB2 }, 342 [H3_CLK_BUS_EHCI0] = { 0x0060, 24 }, 343 [H3_CLK_BUS_EHCI1] = { 0x0060, 25 }, 344 [H3_CLK_BUS_EHCI2] = { 0x0060, 26 }, 345 [H3_CLK_BUS_EHCI3] = { 0x0060, 27 }, 346 [H3_CLK_BUS_OHCI0] = { 0x0060, 28 }, 347 [H3_CLK_BUS_OHCI1] = { 0x0060, 29 }, 348 [H3_CLK_BUS_OHCI2] = { 0x0060, 30 }, 349 [H3_CLK_BUS_OHCI3] = { 0x0060, 31 }, 350 [H3_CLK_BUS_PIO] = { 0x0068, 5 }, 351 [H3_CLK_BUS_THS] = { 0x0068, 8 }, 352 [H3_CLK_BUS_I2C0] = { 0x006c, 0, H3_CLK_APB2 }, 353 [H3_CLK_BUS_I2C1] = { 0x006c, 1, H3_CLK_APB2 }, 354 [H3_CLK_BUS_I2C2] = { 0x006c, 2, H3_CLK_APB2 }, 355 [H3_CLK_BUS_UART0] = { 0x006c, 16, H3_CLK_APB2 }, 356 [H3_CLK_BUS_UART1] = { 0x006c, 17, H3_CLK_APB2 }, 357 [H3_CLK_BUS_UART2] = { 0x006c, 18, H3_CLK_APB2 }, 358 [H3_CLK_BUS_UART3] = { 0x006c, 19, H3_CLK_APB2 }, 359 [H3_CLK_BUS_EPHY] = { 0x0070, 0 }, 360 [H3_CLK_THS] = { 0x0074, 31 }, 361 [H3_CLK_MMC0] = { 0x0088, 31 }, 362 [H3_CLK_MMC1] = { 0x008c, 31 }, 363 [H3_CLK_MMC2] = { 0x0090, 31 }, 364 [H3_CLK_USB_PHY0] = { 0x00cc, 8 }, 365 [H3_CLK_USB_PHY1] = { 0x00cc, 9 }, 366 [H3_CLK_USB_PHY2] = { 0x00cc, 10 }, 367 [H3_CLK_USB_PHY3] = { 0x00cc, 11 }, 368 [H3_CLK_USB_OHCI0] = { 0x00cc, 16 }, 369 [H3_CLK_USB_OHCI1] = { 0x00cc, 17 }, 370 [H3_CLK_USB_OHCI2] = { 0x00cc, 18 }, 371 [H3_CLK_USB_OHCI3] = { 0x00cc, 19 }, 372 }; 373 374 #define H3_R_CLK_AHB0 1 375 #define H3_R_CLK_APB0 2 376 377 #define H3_R_CLK_APB0_PIO 3 378 #define H3_R_CLK_APB0_RSB 6 379 #define H3_R_CLK_APB0_I2C 9 380 381 struct sxiccmu_ccu_bit sun8i_h3_r_gates[] = { 382 [H3_R_CLK_APB0_PIO] = { 0x0028, 0 }, 383 [H3_R_CLK_APB0_RSB] = { 0x0028, 3, H3_R_CLK_APB0 }, 384 [H3_R_CLK_APB0_I2C] = { 0x0028, 6, H3_R_CLK_APB0 }, 385 }; 386 387 /* R40 */ 388 389 #define R40_CLK_PLL_PERIPH0 11 390 #define R40_CLK_PLL_PERIPH0_2X 13 391 392 #define R40_CLK_AXI 25 393 #define R40_CLK_AHB1 26 394 #define R40_CLK_APB2 28 395 396 #define R40_CLK_BUS_MMC0 32 397 #define R40_CLK_BUS_MMC1 33 398 #define R40_CLK_BUS_MMC2 34 399 #define R40_CLK_BUS_MMC3 35 400 #define R40_CLK_BUS_SATA 45 401 #define R40_CLK_BUS_EHCI0 47 402 #define R40_CLK_BUS_EHCI1 48 403 #define R40_CLK_BUS_EHCI2 49 404 #define R40_CLK_BUS_OHCI0 50 405 #define R40_CLK_BUS_OHCI1 51 406 #define R40_CLK_BUS_OHCI2 52 407 #define R40_CLK_BUS_GMAC 64 408 #define R40_CLK_BUS_PIO 79 409 #define R40_CLK_BUS_THS 82 410 #define R40_CLK_BUS_I2C0 87 411 #define R40_CLK_BUS_I2C1 88 412 #define R40_CLK_BUS_I2C2 89 413 #define R40_CLK_BUS_I2C3 90 414 #define R40_CLK_BUS_I2C4 95 415 #define R40_CLK_BUS_UART0 96 416 #define R40_CLK_BUS_UART1 97 417 #define R40_CLK_BUS_UART2 98 418 #define R40_CLK_BUS_UART3 99 419 #define R40_CLK_BUS_UART4 100 420 #define R40_CLK_BUS_UART5 101 421 #define R40_CLK_BUS_UART6 102 422 #define R40_CLK_BUS_UART7 103 423 424 #define R40_CLK_THS 105 425 #define R40_CLK_MMC0 107 426 #define R40_CLK_MMC1 108 427 #define R40_CLK_MMC2 109 428 #define R40_CLK_MMC3 110 429 #define R40_CLK_SATA 123 430 #define R40_CLK_USB_PHY0 124 431 #define R40_CLK_USB_PHY1 125 432 #define R40_CLK_USB_PHY2 126 433 434 #define R40_CLK_HOSC 253 435 #define R40_CLK_LOSC 254 436 437 struct sxiccmu_ccu_bit sun8i_r40_gates[] = { 438 [R40_CLK_BUS_MMC0] = { 0x0060, 8 }, 439 [R40_CLK_BUS_MMC1] = { 0x0060, 9 }, 440 [R40_CLK_BUS_MMC2] = { 0x0060, 10 }, 441 [R40_CLK_BUS_MMC3] = { 0x0060, 11 }, 442 [R40_CLK_BUS_SATA] = { 0x0060, 24 }, 443 [R40_CLK_BUS_EHCI0] = { 0x0060, 26 }, 444 [R40_CLK_BUS_EHCI1] = { 0x0060, 27 }, 445 [R40_CLK_BUS_EHCI2] = { 0x0060, 28 }, 446 [R40_CLK_BUS_OHCI0] = { 0x0060, 29 }, 447 [R40_CLK_BUS_OHCI1] = { 0x0060, 30 }, 448 [R40_CLK_BUS_OHCI2] = { 0x0060, 31 }, 449 [R40_CLK_BUS_GMAC] = { 0x0064, 17, R40_CLK_AHB1 }, 450 [R40_CLK_BUS_PIO] = { 0x0068, 5 }, 451 [R40_CLK_BUS_THS] = { 0x0068, 8 }, 452 [R40_CLK_BUS_I2C0] = { 0x006c, 0, R40_CLK_APB2 }, 453 [R40_CLK_BUS_I2C1] = { 0x006c, 1, R40_CLK_APB2 }, 454 [R40_CLK_BUS_I2C2] = { 0x006c, 2, R40_CLK_APB2 }, 455 [R40_CLK_BUS_I2C3] = { 0x006c, 3, R40_CLK_APB2 }, 456 [R40_CLK_BUS_I2C4] = { 0x006c, 15, R40_CLK_APB2 }, 457 [R40_CLK_BUS_UART0] = { 0x006c, 16, R40_CLK_APB2 }, 458 [R40_CLK_BUS_UART1] = { 0x006c, 17, R40_CLK_APB2 }, 459 [R40_CLK_BUS_UART2] = { 0x006c, 18, R40_CLK_APB2 }, 460 [R40_CLK_BUS_UART3] = { 0x006c, 19, R40_CLK_APB2 }, 461 [R40_CLK_BUS_UART4] = { 0x006c, 20, R40_CLK_APB2 }, 462 [R40_CLK_BUS_UART5] = { 0x006c, 21, R40_CLK_APB2 }, 463 [R40_CLK_BUS_UART6] = { 0x006c, 22, R40_CLK_APB2 }, 464 [R40_CLK_BUS_UART7] = { 0x006c, 23, R40_CLK_APB2 }, 465 [R40_CLK_THS] = { 0x0074, 31 }, 466 [R40_CLK_MMC0] = { 0x0088, 31 }, 467 [R40_CLK_MMC1] = { 0x008c, 31 }, 468 [R40_CLK_MMC2] = { 0x0090, 31 }, 469 [R40_CLK_MMC3] = { 0x0094, 31 }, 470 [R40_CLK_SATA] = { 0x00c8, 31 }, 471 [R40_CLK_USB_PHY0] = { 0x00cc, 8 }, 472 [R40_CLK_USB_PHY1] = { 0x00cc, 9 }, 473 [R40_CLK_USB_PHY2] = { 0x00cc, 10 }, 474 }; 475 476 /* 477 * Reset Signals 478 */ 479 480 /* A10 */ 481 482 #define A10_RST_USB_PHY0 1 483 #define A10_RST_USB_PHY1 2 484 #define A10_RST_USB_PHY2 3 485 486 struct sxiccmu_ccu_bit sun4i_a10_resets[] = { 487 [A10_RST_USB_PHY0] = { 0x00cc, 0 }, 488 [A10_RST_USB_PHY1] = { 0x00cc, 1 }, 489 [A10_RST_USB_PHY2] = { 0x00cc, 2 }, 490 }; 491 492 /* A23/A33 */ 493 494 #define A23_RST_USB_PHY0 0 495 #define A23_RST_USB_PHY1 1 496 497 #define A23_RST_BUS_MMC0 7 498 #define A23_RST_BUS_MMC1 8 499 #define A23_RST_BUS_MMC2 9 500 501 #define A23_RST_BUS_EHCI 16 502 #define A23_RST_BUS_OHCI 17 503 504 #define A23_RST_BUS_I2C0 32 505 #define A23_RST_BUS_I2C1 33 506 #define A23_RST_BUS_I2C2 34 507 508 #define A23_CLK_HOSC 253 509 #define A23_CLK_LOSC 254 510 511 struct sxiccmu_ccu_bit sun8i_a23_resets[] = { 512 [A23_RST_USB_PHY0] = { 0x00cc, 0 }, 513 [A23_RST_USB_PHY1] = { 0x00cc, 1 }, 514 [A23_RST_BUS_MMC0] = { 0x02c0, 8 }, 515 [A23_RST_BUS_MMC1] = { 0x02c0, 9 }, 516 [A23_RST_BUS_MMC2] = { 0x02c0, 10 }, 517 [A23_RST_BUS_EHCI] = { 0x02c0, 26 }, 518 [A23_RST_BUS_OHCI] = { 0x02c0, 29 }, 519 [A23_RST_BUS_I2C0] = { 0x02d8, 0 }, 520 [A23_RST_BUS_I2C1] = { 0x02d8, 1 }, 521 [A23_RST_BUS_I2C2] = { 0x02d8, 2 }, 522 }; 523 524 /* A64 */ 525 526 #define A64_RST_USB_PHY0 0 527 #define A64_RST_USB_PHY1 1 528 529 #define A64_RST_BUS_MMC0 8 530 #define A64_RST_BUS_MMC1 9 531 #define A64_RST_BUS_MMC2 10 532 #define A64_RST_BUS_EMAC 13 533 #define A64_RST_BUS_EHCI0 19 534 #define A64_RST_BUS_EHCI1 20 535 #define A64_RST_BUS_OHCI0 21 536 #define A64_RST_BUS_OHCI1 22 537 #define A64_RST_BUS_THS 38 538 #define A64_RST_BUS_I2C0 42 539 #define A64_RST_BUS_I2C1 43 540 #define A64_RST_BUS_I2C2 44 541 542 struct sxiccmu_ccu_bit sun50i_a64_resets[] = { 543 [A64_RST_USB_PHY0] = { 0x00cc, 0 }, 544 [A64_RST_USB_PHY1] = { 0x00cc, 1 }, 545 [A64_RST_BUS_MMC0] = { 0x02c0, 8 }, 546 [A64_RST_BUS_MMC1] = { 0x02c0, 9 }, 547 [A64_RST_BUS_MMC2] = { 0x02c0, 10 }, 548 [A64_RST_BUS_EMAC] = { 0x02c0, 17 }, 549 [A64_RST_BUS_EHCI0] = { 0x02c0, 24 }, 550 [A64_RST_BUS_EHCI1] = { 0x02c0, 25 }, 551 [A64_RST_BUS_OHCI0] = { 0x02c0, 28 }, 552 [A64_RST_BUS_OHCI1] = { 0x02c0, 29 }, 553 [A64_RST_BUS_THS] = { 0x02d0, 8 }, 554 [A64_RST_BUS_I2C0] = { 0x02d8, 0 }, 555 [A64_RST_BUS_I2C1] = { 0x02d8, 1 }, 556 [A64_RST_BUS_I2C2] = { 0x02d8, 2 }, 557 }; 558 559 /* A80 */ 560 561 #define A80_RST_BUS_MMC 4 562 #define A80_RST_BUS_UART0 45 563 #define A80_RST_BUS_UART1 46 564 #define A80_RST_BUS_UART2 47 565 #define A80_RST_BUS_UART3 48 566 #define A80_RST_BUS_UART4 49 567 #define A80_RST_BUS_UART5 50 568 569 struct sxiccmu_ccu_bit sun9i_a80_resets[] = { 570 [A80_RST_BUS_MMC] = { 0x05a0, 8 }, 571 [A80_RST_BUS_UART0] = { 0x05b4, 16 }, 572 [A80_RST_BUS_UART1] = { 0x05b4, 17 }, 573 [A80_RST_BUS_UART2] = { 0x05b4, 18 }, 574 [A80_RST_BUS_UART3] = { 0x05b4, 19 }, 575 [A80_RST_BUS_UART4] = { 0x05b4, 20 }, 576 [A80_RST_BUS_UART5] = { 0x05b4, 21 }, 577 }; 578 579 #define A80_USB_RST_HCI0 0 580 #define A80_USB_RST_HCI1 1 581 #define A80_USB_RST_HCI2 2 582 583 #define A80_USB_RST_HCI0_PHY 3 584 #define A80_USB_RST_HCI1_HSIC 4 585 #define A80_USB_RST_HCI1_PHY 5 586 #define A80_USB_RST_HCI2_HSIC 6 587 #define A80_USB_RST_HCI2_UTMIPHY 7 588 589 struct sxiccmu_ccu_bit sun9i_a80_usb_resets[] = { 590 [A80_USB_RST_HCI0] = { 0x0000, 17 }, 591 [A80_USB_RST_HCI1] = { 0x0000, 18 }, 592 [A80_USB_RST_HCI2] = { 0x0000, 19 }, 593 [A80_USB_RST_HCI0_PHY] = { 0x0004, 17 }, 594 [A80_USB_RST_HCI1_HSIC]= { 0x0004, 18 }, 595 [A80_USB_RST_HCI1_PHY]= { 0x0004, 19 }, /* Undocumented */ 596 [A80_USB_RST_HCI2_HSIC]= { 0x0004, 20 }, /* Undocumented */ 597 [A80_USB_RST_HCI2_UTMIPHY] = { 0x0004, 21 }, 598 }; 599 600 struct sxiccmu_ccu_bit sun9i_a80_mmc_resets[] = { 601 { 0x0000, 18 }, 602 { 0x0004, 18 }, 603 { 0x0008, 18 }, 604 { 0x000c, 18 }, 605 }; 606 607 /* H3/H5 */ 608 609 #define H3_RST_USB_PHY0 0 610 #define H3_RST_USB_PHY1 1 611 #define H3_RST_USB_PHY2 2 612 #define H3_RST_USB_PHY3 3 613 614 #define H3_RST_BUS_MMC0 7 615 #define H3_RST_BUS_MMC1 8 616 #define H3_RST_BUS_MMC2 9 617 618 #define H3_RST_BUS_EMAC 12 619 620 #define H3_RST_BUS_EHCI0 18 621 #define H3_RST_BUS_EHCI1 19 622 #define H3_RST_BUS_EHCI2 20 623 #define H3_RST_BUS_EHCI3 21 624 #define H3_RST_BUS_OHCI0 22 625 #define H3_RST_BUS_OHCI1 23 626 #define H3_RST_BUS_OHCI2 24 627 #define H3_RST_BUS_OHCI3 25 628 #define H3_RST_BUS_EPHY 39 629 #define H3_RST_BUS_THS 42 630 #define H3_RST_BUS_I2C0 46 631 #define H3_RST_BUS_I2C1 47 632 #define H3_RST_BUS_I2C2 48 633 634 struct sxiccmu_ccu_bit sun8i_h3_resets[] = { 635 [H3_RST_USB_PHY0] = { 0x00cc, 0 }, 636 [H3_RST_USB_PHY1] = { 0x00cc, 1 }, 637 [H3_RST_USB_PHY2] = { 0x00cc, 2 }, 638 [H3_RST_USB_PHY3] = { 0x00cc, 3 }, 639 [H3_RST_BUS_MMC0] = { 0x02c0, 8 }, 640 [H3_RST_BUS_MMC1] = { 0x02c0, 9 }, 641 [H3_RST_BUS_MMC2] = { 0x02c0, 10 }, 642 [H3_RST_BUS_EMAC] = { 0x02c0, 17 }, 643 [H3_RST_BUS_EHCI0] = { 0x02c0, 24 }, 644 [H3_RST_BUS_EHCI1] = { 0x02c0, 25 }, 645 [H3_RST_BUS_EHCI2] = { 0x02c0, 26 }, 646 [H3_RST_BUS_EHCI3] = { 0x02c0, 27 }, 647 [H3_RST_BUS_OHCI0] = { 0x02c0, 28 }, 648 [H3_RST_BUS_OHCI1] = { 0x02c0, 29 }, 649 [H3_RST_BUS_OHCI2] = { 0x02c0, 30 }, 650 [H3_RST_BUS_OHCI3] = { 0x02c0, 31 }, 651 [H3_RST_BUS_EPHY] = { 0x02c8, 2 }, 652 [H3_RST_BUS_THS] = { 0x02d0, 8 }, 653 [H3_RST_BUS_I2C0] = { 0x02d8, 0 }, 654 [H3_RST_BUS_I2C1] = { 0x02d8, 1 }, 655 [H3_RST_BUS_I2C2] = { 0x02d8, 2 }, 656 }; 657 658 #define H3_R_RST_APB0_RSB 2 659 #define H3_R_RST_APB0_I2C 5 660 661 struct sxiccmu_ccu_bit sun8i_h3_r_resets[] = { 662 [H3_R_RST_APB0_RSB] = { 0x00b0, 3 }, 663 [H3_R_RST_APB0_I2C] = { 0x00b0, 6 }, 664 }; 665 666 /* R40 */ 667 668 #define R40_RST_USB_PHY0 0 669 #define R40_RST_USB_PHY1 1 670 #define R40_RST_USB_PHY2 2 671 672 #define R40_RST_BUS_MMC0 8 673 #define R40_RST_BUS_MMC1 9 674 #define R40_RST_BUS_MMC2 10 675 #define R40_RST_BUS_MMC3 11 676 #define R40_RST_BUS_SATA 21 677 #define R40_RST_BUS_EHCI0 23 678 #define R40_RST_BUS_EHCI1 24 679 #define R40_RST_BUS_EHCI2 25 680 #define R40_RST_BUS_OHCI0 26 681 #define R40_RST_BUS_OHCI1 27 682 #define R40_RST_BUS_OHCI2 28 683 #define R40_RST_BUS_GMAC 40 684 #define R40_RST_BUS_THS 59 685 #define R40_RST_BUS_I2C0 64 686 #define R40_RST_BUS_I2C1 65 687 #define R40_RST_BUS_I2C2 66 688 #define R40_RST_BUS_I2C3 67 689 #define R40_RST_BUS_I2C4 72 690 #define R40_RST_BUS_UART0 73 691 #define R40_RST_BUS_UART1 74 692 #define R40_RST_BUS_UART2 75 693 #define R40_RST_BUS_UART3 76 694 #define R40_RST_BUS_UART4 77 695 #define R40_RST_BUS_UART5 78 696 #define R40_RST_BUS_UART6 79 697 #define R40_RST_BUS_UART7 80 698 699 struct sxiccmu_ccu_bit sun8i_r40_resets[] = { 700 [R40_RST_USB_PHY0] = { 0x00cc, 0 }, 701 [R40_RST_USB_PHY1] = { 0x00cc, 1 }, 702 [R40_RST_USB_PHY2] = { 0x00cc, 2 }, 703 [R40_RST_BUS_MMC0] = { 0x02c0, 8 }, 704 [R40_RST_BUS_MMC1] = { 0x02c0, 9 }, 705 [R40_RST_BUS_MMC2] = { 0x02c0, 10 }, 706 [R40_RST_BUS_MMC3] = { 0x02c0, 11 }, 707 [R40_RST_BUS_SATA] = { 0x02c0, 24 }, 708 [R40_RST_BUS_EHCI0] = { 0x02c0, 26 }, 709 [R40_RST_BUS_EHCI1] = { 0x02c0, 27 }, 710 [R40_RST_BUS_EHCI2] = { 0x02c0, 28 }, 711 [R40_RST_BUS_OHCI0] = { 0x02c0, 29 }, 712 [R40_RST_BUS_OHCI1] = { 0x02c0, 30 }, 713 [R40_RST_BUS_OHCI2] = { 0x02c0, 31 }, 714 [R40_RST_BUS_GMAC] = { 0x02c4, 17 }, 715 [R40_RST_BUS_THS] = { 0x02d0, 8 }, 716 [R40_RST_BUS_I2C0] = { 0x02d8, 0 }, 717 [R40_RST_BUS_I2C1] = { 0x02d8, 1 }, 718 [R40_RST_BUS_I2C2] = { 0x02d8, 2 }, 719 [R40_RST_BUS_I2C3] = { 0x02d8, 3 }, 720 [R40_RST_BUS_I2C4] = { 0x02d8, 15 }, 721 [R40_RST_BUS_UART0] = { 0x02d8, 16 }, 722 [R40_RST_BUS_UART1] = { 0x02d8, 17 }, 723 [R40_RST_BUS_UART2] = { 0x02d8, 18 }, 724 [R40_RST_BUS_UART3] = { 0x02d8, 19 }, 725 [R40_RST_BUS_UART4] = { 0x02d8, 20 }, 726 [R40_RST_BUS_UART5] = { 0x02d8, 21 }, 727 [R40_RST_BUS_UART6] = { 0x02d8, 22 }, 728 [R40_RST_BUS_UART7] = { 0x02d8, 23 }, 729 }; 730