1 /* Public Domain */ 2 3 4 /* 5 * Clocks Signals 6 */ 7 8 #define A64_CLK_PLL_PERIPH0 11 9 #define A64_CLK_PLL_PERIPH0_2X 12 10 11 #define A64_CLK_AXI 22 12 #define A64_CLK_APB 23 13 #define A64_CLK_AHB1 24 14 #define A64_CLK_APB1 25 15 #define A64_CLK_APB2 26 16 #define A64_CLK_AHB2 27 17 18 #define A64_CLK_BUS_MMC0 31 19 #define A64_CLK_BUS_MMC1 32 20 #define A64_CLK_BUS_MMC2 33 21 22 #define A64_CLK_BUS_EMAC 36 23 24 #define A64_CLK_BUS_EHCI0 42 25 #define A64_CLK_BUS_EHCI1 43 26 #define A64_CLK_BUS_OHCI0 44 27 #define A64_CLK_BUS_OHCI1 45 28 29 #define A64_CLK_BUS_PIO 58 30 31 #define A64_CLK_BUS_UART0 67 32 #define A64_CLK_BUS_UART1 68 33 #define A64_CLK_BUS_UART2 69 34 #define A64_CLK_BUS_UART3 70 35 #define A64_CLK_BUS_UART4 71 36 37 #define A64_CLK_MMC0 75 38 #define A64_CLK_MMC1 76 39 #define A64_CLK_MMC2 77 40 41 #define A64_CLK_USB_OHCI0 91 42 #define A64_CLK_USB_OHCI1 93 43 #define A64_CLK_USB_PHY0 86 44 #define A64_CLK_USB_PHY1 87 45 46 #define A64_CLK_LOSC 254 47 #define A64_CLK_HOSC 253 48 49 struct sxiccmu_ccu_bit sun50i_a64_gates[] = { 50 [A64_CLK_BUS_MMC0] = { 0x0060, 8 }, 51 [A64_CLK_BUS_MMC1] = { 0x0060, 9 }, 52 [A64_CLK_BUS_MMC2] = { 0x0060, 10 }, 53 [A64_CLK_BUS_EMAC] = { 0x0060, 17, A64_CLK_AHB2 }, 54 [A64_CLK_BUS_EHCI0] = { 0x0060, 24 }, 55 [A64_CLK_BUS_EHCI1] = { 0x0060, 25 }, 56 [A64_CLK_BUS_OHCI0] = { 0x0060, 28 }, 57 [A64_CLK_BUS_OHCI1] = { 0x0060, 29 }, 58 [A64_CLK_BUS_PIO] = { 0x0068, 5 }, 59 [A64_CLK_BUS_UART0] = { 0x006c, 16, A64_CLK_APB2 }, 60 [A64_CLK_BUS_UART1] = { 0x006c, 17, A64_CLK_APB2 }, 61 [A64_CLK_BUS_UART2] = { 0x006c, 18, A64_CLK_APB2 }, 62 [A64_CLK_BUS_UART3] = { 0x006c, 19, A64_CLK_APB2 }, 63 [A64_CLK_BUS_UART4] = { 0x006c, 20, A64_CLK_APB2 }, 64 [A64_CLK_MMC0] = { 0x0088, 31 }, 65 [A64_CLK_MMC1] = { 0x008c, 31 }, 66 [A64_CLK_MMC2] = { 0x0090, 31 }, 67 [A64_CLK_USB_OHCI0] = { 0x00cc, 16 }, 68 [A64_CLK_USB_OHCI1] = { 0x00cc, 17 }, 69 [A64_CLK_USB_PHY0] = { 0x00cc, 8 }, 70 [A64_CLK_USB_PHY1] = { 0x00cc, 9 }, 71 }; 72 73 #define H3_CLK_PLL_PERIPH0 9 74 75 #define H3_CLK_AXI 15 76 #define H3_CLK_AHB1 16 77 #define H3_CLK_APB1 17 78 #define H3_CLK_APB2 18 79 #define H3_CLK_AHB2 19 80 81 #define H3_CLK_BUS_MMC0 22 82 #define H3_CLK_BUS_MMC1 23 83 #define H3_CLK_BUS_MMC2 24 84 85 #define H3_CLK_BUS_EMAC 27 86 87 #define H3_CLK_BUS_EHCI0 33 88 #define H3_CLK_BUS_EHCI1 34 89 #define H3_CLK_BUS_EHCI2 35 90 #define H3_CLK_BUS_EHCI3 36 91 #define H3_CLK_BUS_OHCI0 37 92 #define H3_CLK_BUS_OHCI1 38 93 #define H3_CLK_BUS_OHCI2 39 94 #define H3_CLK_BUS_OHCI3 40 95 96 #define H3_CLK_BUS_PIO 54 97 98 #define H3_CLK_BUS_UART0 62 99 #define H3_CLK_BUS_UART1 63 100 #define H3_CLK_BUS_UART2 64 101 #define H3_CLK_BUS_UART3 65 102 103 #define H3_CLK_BUS_EPHY 67 104 105 #define H3_CLK_MMC0 71 106 #define H3_CLK_MMC1 74 107 #define H3_CLK_MMC2 77 108 109 #define H3_CLK_USB_PHY0 88 110 #define H3_CLK_USB_PHY1 89 111 #define H3_CLK_USB_PHY2 90 112 #define H3_CLK_USB_PHY3 91 113 114 #define H3_CLK_LOSC 254 115 #define H3_CLK_HOSC 253 116 117 struct sxiccmu_ccu_bit sun8i_h3_gates[] = { 118 [H3_CLK_BUS_MMC0] = { 0x0060, 8 }, 119 [H3_CLK_BUS_MMC1] = { 0x0060, 9 }, 120 [H3_CLK_BUS_MMC2] = { 0x0060, 10 }, 121 [H3_CLK_BUS_EMAC] = { 0x0060, 17, H3_CLK_AHB2 }, 122 [H3_CLK_BUS_EHCI0] = { 0x0060, 24 }, 123 [H3_CLK_BUS_EHCI1] = { 0x0060, 25 }, 124 [H3_CLK_BUS_EHCI2] = { 0x0060, 26 }, 125 [H3_CLK_BUS_EHCI3] = { 0x0060, 27 }, 126 [H3_CLK_BUS_OHCI0] = { 0x0060, 28 }, 127 [H3_CLK_BUS_OHCI1] = { 0x0060, 29 }, 128 [H3_CLK_BUS_OHCI2] = { 0x0060, 30 }, 129 [H3_CLK_BUS_OHCI3] = { 0x0060, 31 }, 130 [H3_CLK_BUS_PIO] = { 0x0068, 5 }, 131 [H3_CLK_BUS_UART0] = { 0x006c, 16, H3_CLK_APB2 }, 132 [H3_CLK_BUS_UART1] = { 0x006c, 17, H3_CLK_APB2 }, 133 [H3_CLK_BUS_UART2] = { 0x006c, 18, H3_CLK_APB2 }, 134 [H3_CLK_BUS_UART3] = { 0x006c, 19, H3_CLK_APB2 }, 135 [H3_CLK_BUS_EPHY] = { 0x0070, 0 }, 136 [H3_CLK_MMC0] = { 0x0088, 31 }, 137 [H3_CLK_MMC1] = { 0x008c, 31 }, 138 [H3_CLK_MMC2] = { 0x0090, 31 }, 139 [H3_CLK_USB_PHY0] = { 0x00cc, 8 }, 140 [H3_CLK_USB_PHY1] = { 0x00cc, 9 }, 141 [H3_CLK_USB_PHY2] = { 0x00cc, 10 }, 142 [H3_CLK_USB_PHY3] = { 0x00cc, 11 }, 143 }; 144 145 /* 146 * Reset Signals 147 */ 148 149 #define A64_RST_USB_PHY0 0 150 #define A64_RST_USB_PHY1 1 151 152 #define A64_RST_BUS_MMC0 8 153 #define A64_RST_BUS_MMC1 9 154 #define A64_RST_BUS_MMC2 10 155 156 #define A64_RST_BUS_EMAC 13 157 158 #define A64_RST_BUS_EHCI0 19 159 #define A64_RST_BUS_EHCI1 20 160 #define A64_RST_BUS_OHCI0 21 161 #define A64_RST_BUS_OHCI1 22 162 163 struct sxiccmu_ccu_bit sun50i_a64_resets[] = { 164 [A64_RST_USB_PHY0] = { 0x00cc, 0 }, 165 [A64_RST_USB_PHY1] = { 0x00cc, 1 }, 166 [A64_RST_BUS_MMC0] = { 0x02c0, 8 }, 167 [A64_RST_BUS_MMC1] = { 0x02c0, 9 }, 168 [A64_RST_BUS_MMC2] = { 0x02c0, 10 }, 169 [A64_RST_BUS_EMAC] = { 0x02c0, 17 }, 170 [A64_RST_BUS_EHCI0] = { 0x02c0, 24 }, 171 [A64_RST_BUS_EHCI1] = { 0x02c0, 25 }, 172 [A64_RST_BUS_OHCI0] = { 0x02c0, 28 }, 173 [A64_RST_BUS_OHCI1] = { 0x02c0, 29 }, 174 }; 175 176 #define H3_RST_USB_PHY0 0 177 #define H3_RST_USB_PHY1 1 178 #define H3_RST_USB_PHY2 2 179 #define H3_RST_USB_PHY3 3 180 181 #define H3_RST_BUS_MMC0 7 182 #define H3_RST_BUS_MMC1 8 183 #define H3_RST_BUS_MMC2 9 184 185 #define H3_RST_BUS_EMAC 12 186 187 #define H3_RST_BUS_EHCI0 18 188 #define H3_RST_BUS_EHCI1 19 189 #define H3_RST_BUS_EHCI2 20 190 #define H3_RST_BUS_EHCI3 21 191 #define H3_RST_BUS_OHCI0 22 192 #define H3_RST_BUS_OHCI1 23 193 #define H3_RST_BUS_OHCI2 24 194 #define H3_RST_BUS_OHCI3 25 195 196 #define H3_RST_BUS_EPHY 39 197 198 struct sxiccmu_ccu_bit sun8i_h3_resets[] = { 199 [H3_RST_USB_PHY0] = { 0x00cc, 0 }, 200 [H3_RST_USB_PHY1] = { 0x00cc, 1 }, 201 [H3_RST_USB_PHY2] = { 0x00cc, 2 }, 202 [H3_RST_USB_PHY3] = { 0x00cc, 3 }, 203 [H3_RST_BUS_MMC0] = { 0x02c0, 8 }, 204 [H3_RST_BUS_MMC1] = { 0x02c0, 9 }, 205 [H3_RST_BUS_MMC2] = { 0x02c0, 10 }, 206 [H3_RST_BUS_EMAC] = { 0x02c0, 17 }, 207 [H3_RST_BUS_EHCI0] = { 0x02c0, 24 }, 208 [H3_RST_BUS_EHCI1] = { 0x02c0, 25 }, 209 [H3_RST_BUS_EHCI2] = { 0x02c0, 26 }, 210 [H3_RST_BUS_EHCI3] = { 0x02c0, 27 }, 211 [H3_RST_BUS_OHCI0] = { 0x02c0, 28 }, 212 [H3_RST_BUS_OHCI1] = { 0x02c0, 29 }, 213 [H3_RST_BUS_OHCI2] = { 0x02c0, 30 }, 214 [H3_RST_BUS_OHCI3] = { 0x02c0, 31 }, 215 [H3_RST_BUS_EPHY] = { 0x02c8, 2 }, 216 }; 217