1 /* Public Domain */ 2 3 4 /* 5 * Clocks Signals 6 */ 7 8 /* A10/A20 */ 9 10 #define A10_CLK_HOSC 1 11 #define A10_CLK_PLL_CORE 2 12 #define A10_CLK_PLL_PERIPH_BASE 14 13 #define A10_CLK_PLL_PERIPH 15 14 15 #define A10_CLK_CPU 20 16 #define A10_CLK_APB1 25 17 18 #define A10_CLK_AHB_EHCI0 27 19 #define A10_CLK_AHB_EHCI1 29 20 #define A10_CLK_AHB_MMC0 34 21 #define A10_CLK_AHB_MMC1 35 22 #define A10_CLK_AHB_MMC2 36 23 #define A10_CLK_AHB_MMC3 37 24 #define A10_CLK_AHB_EMAC 42 25 #define A10_CLK_AHB_SATA 49 26 #define A10_CLK_AHB_GMAC 66 27 #define A10_CLK_APB0_PIO 74 28 #define A10_CLK_APB1_I2C0 79 29 #define A10_CLK_APB1_I2C1 80 30 #define A10_CLK_APB1_I2C2 81 31 #define A10_CLK_APB1_I2C3 82 32 #define A10_CLK_APB1_I2C4 87 33 #define A10_CLK_APB1_UART0 88 34 #define A10_CLK_APB1_UART1 89 35 #define A10_CLK_APB1_UART2 90 36 #define A10_CLK_APB1_UART3 91 37 #define A10_CLK_APB1_UART4 92 38 #define A10_CLK_APB1_UART5 93 39 #define A10_CLK_APB1_UART6 94 40 #define A10_CLK_APB1_UART7 95 41 42 #define A10_CLK_MMC0 98 43 #define A10_CLK_MMC1 101 44 #define A10_CLK_MMC2 104 45 #define A10_CLK_MMC3 107 46 #define A10_CLK_SATA 122 47 #define A10_CLK_USB_PHY 125 48 49 #define A10_CLK_LOSC 254 50 51 struct sxiccmu_ccu_bit sun4i_a10_gates[] = { 52 [A10_CLK_AHB_EHCI0] = { 0x0060, 1 }, 53 [A10_CLK_AHB_EHCI1] = { 0x0060, 3 }, 54 [A10_CLK_AHB_MMC0] = { 0x0060, 8 }, 55 [A10_CLK_AHB_MMC1] = { 0x0060, 9 }, 56 [A10_CLK_AHB_MMC2] = { 0x0060, 10 }, 57 [A10_CLK_AHB_MMC3] = { 0x0060, 11 }, 58 [A10_CLK_AHB_EMAC] = { 0x0060, 17 }, 59 [A10_CLK_AHB_SATA] = { 0x0060, 25 }, 60 [A10_CLK_AHB_GMAC] = { 0x0064, 17 }, 61 [A10_CLK_APB0_PIO] = { 0x0068, 5 }, 62 [A10_CLK_APB1_I2C0] = { 0x006c, 0, A10_CLK_APB1 }, 63 [A10_CLK_APB1_I2C1] = { 0x006c, 1, A10_CLK_APB1 }, 64 [A10_CLK_APB1_I2C2] = { 0x006c, 2, A10_CLK_APB1 }, 65 [A10_CLK_APB1_I2C3] = { 0x006c, 3, A10_CLK_APB1 }, 66 [A10_CLK_APB1_I2C4] = { 0x006c, 15, A10_CLK_APB1 }, 67 [A10_CLK_APB1_UART0] = { 0x006c, 16, A10_CLK_APB1 }, 68 [A10_CLK_APB1_UART1] = { 0x006c, 17, A10_CLK_APB1 }, 69 [A10_CLK_APB1_UART2] = { 0x006c, 18, A10_CLK_APB1 }, 70 [A10_CLK_APB1_UART3] = { 0x006c, 19, A10_CLK_APB1 }, 71 [A10_CLK_APB1_UART4] = { 0x006c, 20, A10_CLK_APB1 }, 72 [A10_CLK_APB1_UART5] = { 0x006c, 21, A10_CLK_APB1 }, 73 [A10_CLK_APB1_UART6] = { 0x006c, 22, A10_CLK_APB1 }, 74 [A10_CLK_APB1_UART7] = { 0x006c, 23, A10_CLK_APB1 }, 75 [A10_CLK_MMC0] = { 0x0088, 31 }, 76 [A10_CLK_MMC1] = { 0x008c, 31 }, 77 [A10_CLK_MMC2] = { 0x0090, 31 }, 78 [A10_CLK_MMC3] = { 0x0094, 31 }, 79 [A10_CLK_SATA] = { 0x00c8, 31 }, 80 [A10_CLK_USB_PHY] = { 0x00cc, 8 }, 81 }; 82 83 /* A23/A33 */ 84 85 #define A23_CLK_PLL_PERIPH 10 86 87 #define A23_CLK_AXI 19 88 #define A23_CLK_AHB1 20 89 #define A23_CLK_APB1 21 90 #define A23_CLK_APB2 22 91 92 #define A23_CLK_BUS_MMC0 26 93 #define A23_CLK_BUS_MMC1 27 94 #define A23_CLK_BUS_MMC2 28 95 #define A23_CLK_BUS_EHCI 35 96 #define A23_CLK_BUS_OHCI 36 97 #define A23_CLK_BUS_PIO 48 98 #define A23_CLK_BUS_I2C0 51 99 #define A23_CLK_BUS_I2C1 52 100 #define A23_CLK_BUS_I2C2 53 101 #define A23_CLK_BUS_UART0 54 102 #define A23_CLK_BUS_UART1 55 103 #define A23_CLK_BUS_UART2 56 104 #define A23_CLK_BUS_UART3 57 105 #define A23_CLK_BUS_UART4 58 106 107 #define A23_CLK_MMC0 60 108 #define A23_CLK_MMC1 63 109 #define A23_CLK_MMC2 66 110 111 struct sxiccmu_ccu_bit sun8i_a23_gates[] = { 112 [A23_CLK_BUS_MMC0] = { 0x0060, 8 }, 113 [A23_CLK_BUS_MMC1] = { 0x0060, 9 }, 114 [A23_CLK_BUS_MMC2] = { 0x0060, 10 }, 115 [A23_CLK_BUS_EHCI] = { 0x0060, 26 }, 116 [A23_CLK_BUS_OHCI] = { 0x0060, 29 }, 117 [A23_CLK_BUS_PIO] = { 0x0068, 5 }, 118 [A23_CLK_BUS_I2C0] = { 0x006c, 0, A23_CLK_APB2 }, 119 [A23_CLK_BUS_I2C1] = { 0x006c, 1, A23_CLK_APB2 }, 120 [A23_CLK_BUS_I2C2] = { 0x006c, 2, A23_CLK_APB2 }, 121 [A23_CLK_BUS_UART0] = { 0x006c, 16, A23_CLK_APB2 }, 122 [A23_CLK_BUS_UART1] = { 0x006c, 17, A23_CLK_APB2 }, 123 [A23_CLK_BUS_UART2] = { 0x006c, 18, A23_CLK_APB2 }, 124 [A23_CLK_BUS_UART3] = { 0x006c, 19, A23_CLK_APB2 }, 125 [A23_CLK_BUS_UART4] = { 0x006c, 20, A23_CLK_APB2 }, 126 [A23_CLK_MMC0] = { 0x0088, 31 }, 127 [A23_CLK_MMC1] = { 0x008c, 31 }, 128 [A23_CLK_MMC2] = { 0x0090, 31 }, 129 }; 130 131 /* A64 */ 132 133 #define A64_CLK_PLL_PERIPH0 11 134 #define A64_CLK_PLL_PERIPH0_2X 12 135 136 #define A64_CLK_AXI 22 137 #define A64_CLK_APB 23 138 #define A64_CLK_AHB1 24 139 #define A64_CLK_APB1 25 140 #define A64_CLK_APB2 26 141 #define A64_CLK_AHB2 27 142 143 #define A64_CLK_BUS_MMC0 31 144 #define A64_CLK_BUS_MMC1 32 145 #define A64_CLK_BUS_MMC2 33 146 #define A64_CLK_BUS_EMAC 36 147 #define A64_CLK_BUS_EHCI0 42 148 #define A64_CLK_BUS_EHCI1 43 149 #define A64_CLK_BUS_OHCI0 44 150 #define A64_CLK_BUS_OHCI1 45 151 #define A64_CLK_BUS_PIO 58 152 #define A64_CLK_BUS_I2C0 63 153 #define A64_CLK_BUS_I2C1 64 154 #define A64_CLK_BUS_I2C2 65 155 #define A64_CLK_BUS_UART0 67 156 #define A64_CLK_BUS_UART1 68 157 #define A64_CLK_BUS_UART2 69 158 #define A64_CLK_BUS_UART3 70 159 #define A64_CLK_BUS_UART4 71 160 161 #define A64_CLK_MMC0 75 162 #define A64_CLK_MMC1 76 163 #define A64_CLK_MMC2 77 164 #define A64_CLK_USB_OHCI0 91 165 #define A64_CLK_USB_OHCI1 93 166 #define A64_CLK_USB_PHY0 86 167 #define A64_CLK_USB_PHY1 87 168 169 #define A64_CLK_LOSC 254 170 #define A64_CLK_HOSC 253 171 172 struct sxiccmu_ccu_bit sun50i_a64_gates[] = { 173 [A64_CLK_BUS_MMC0] = { 0x0060, 8 }, 174 [A64_CLK_BUS_MMC1] = { 0x0060, 9 }, 175 [A64_CLK_BUS_MMC2] = { 0x0060, 10 }, 176 [A64_CLK_BUS_EMAC] = { 0x0060, 17, A64_CLK_AHB2 }, 177 [A64_CLK_BUS_EHCI0] = { 0x0060, 24 }, 178 [A64_CLK_BUS_EHCI1] = { 0x0060, 25 }, 179 [A64_CLK_BUS_OHCI0] = { 0x0060, 28 }, 180 [A64_CLK_BUS_OHCI1] = { 0x0060, 29 }, 181 [A64_CLK_BUS_PIO] = { 0x0068, 5 }, 182 [A64_CLK_BUS_I2C0] = { 0x006c, 0, A64_CLK_APB2 }, 183 [A64_CLK_BUS_I2C1] = { 0x006c, 1, A64_CLK_APB2 }, 184 [A64_CLK_BUS_I2C2] = { 0x006c, 2, A64_CLK_APB2 }, 185 [A64_CLK_BUS_UART0] = { 0x006c, 16, A64_CLK_APB2 }, 186 [A64_CLK_BUS_UART1] = { 0x006c, 17, A64_CLK_APB2 }, 187 [A64_CLK_BUS_UART2] = { 0x006c, 18, A64_CLK_APB2 }, 188 [A64_CLK_BUS_UART3] = { 0x006c, 19, A64_CLK_APB2 }, 189 [A64_CLK_BUS_UART4] = { 0x006c, 20, A64_CLK_APB2 }, 190 [A64_CLK_MMC0] = { 0x0088, 31 }, 191 [A64_CLK_MMC1] = { 0x008c, 31 }, 192 [A64_CLK_MMC2] = { 0x0090, 31 }, 193 [A64_CLK_USB_OHCI0] = { 0x00cc, 16 }, 194 [A64_CLK_USB_OHCI1] = { 0x00cc, 17 }, 195 [A64_CLK_USB_PHY0] = { 0x00cc, 8 }, 196 [A64_CLK_USB_PHY1] = { 0x00cc, 9 }, 197 }; 198 199 /* A80 */ 200 201 #define A80_CLK_PLL_PERIPH0 3 202 203 #define A80_CLK_APB1 23 204 205 #define A80_CLK_MMC0 33 206 #define A80_CLK_MMC1 36 207 #define A80_CLK_MMC2 39 208 #define A80_CLK_MMC3 42 209 210 #define A80_CLK_BUS_MMC 84 211 #define A80_CLK_BUS_USB 96 212 #define A80_CLK_BUS_PIO 111 213 #define A80_CLK_BUS_UART0 124 214 #define A80_CLK_BUS_UART1 125 215 #define A80_CLK_BUS_UART2 126 216 #define A80_CLK_BUS_UART3 127 217 #define A80_CLK_BUS_UART4 128 218 #define A80_CLK_BUS_UART5 129 219 220 struct sxiccmu_ccu_bit sun9i_a80_gates[] = { 221 [A80_CLK_MMC0] = { 0x0410, 31 }, 222 [A80_CLK_MMC1] = { 0x0414, 31 }, 223 [A80_CLK_MMC2] = { 0x0418, 31 }, 224 [A80_CLK_MMC3] = { 0x041c, 31 }, /* Undocumented */ 225 [A80_CLK_BUS_MMC] = { 0x0580, 8 }, 226 [A80_CLK_BUS_USB] = { 0x0584, 1 }, 227 [A80_CLK_BUS_PIO] = { 0x0590, 5 }, 228 [A80_CLK_BUS_UART0] = { 0x0594, 16, A80_CLK_APB1 }, 229 [A80_CLK_BUS_UART1] = { 0x0594, 17, A80_CLK_APB1 }, 230 [A80_CLK_BUS_UART2] = { 0x0594, 18, A80_CLK_APB1 }, 231 [A80_CLK_BUS_UART3] = { 0x0594, 19, A80_CLK_APB1 }, 232 [A80_CLK_BUS_UART4] = { 0x0594, 20, A80_CLK_APB1 }, 233 [A80_CLK_BUS_UART5] = { 0x0594, 21, A80_CLK_APB1 }, 234 }; 235 236 #define A80_USB_CLK_HCI0 0 237 #define A80_USB_CLK_OHCI0 1 238 #define A80_USB_CLK_HCI1 2 239 #define A80_USB_CLK_HCI2 3 240 #define A80_USB_CLK_OHCI2 4 241 242 #define A80_USB_CLK_HCI0_PHY 5 243 #define A80_USB_CLK_HCI1_HSIC 6 244 #define A80_USB_CLK_HCI1_PHY 7 245 #define A80_USB_CLK_HCI2_HSIC 8 246 #define A80_USB_CLK_HCI2_UTMIPHY 9 247 #define A80_USB_CLK_HCI1_HSIC_12M 10 248 249 struct sxiccmu_ccu_bit sun9i_a80_usb_gates[] = { 250 [A80_USB_CLK_HCI0] = { 0x0000, 1 }, 251 [A80_USB_CLK_OHCI0] = { 0x0000, 2 }, 252 [A80_USB_CLK_HCI1] = { 0x0000, 3 }, 253 [A80_USB_CLK_HCI2] = { 0x0000, 5 }, 254 [A80_USB_CLK_OHCI2] = { 0x0000, 6 }, 255 [A80_USB_CLK_HCI0_PHY] = { 0x0004, 1 }, 256 [A80_USB_CLK_HCI1_HSIC] = { 0x0004, 2 }, 257 [A80_USB_CLK_HCI1_PHY] = { 0x0004, 3 }, /* Undocumented */ 258 [A80_USB_CLK_HCI2_HSIC] = { 0x0004, 4 }, 259 [A80_USB_CLK_HCI2_UTMIPHY] = { 0x0004, 5 }, 260 [A80_USB_CLK_HCI1_HSIC_12M] = { 0x0004, 10 }, 261 }; 262 263 struct sxiccmu_ccu_bit sun9i_a80_mmc_gates[] = { 264 { 0x0000, 16 }, 265 { 0x0004, 16 }, 266 { 0x0008, 16 }, 267 { 0x000c, 16 }, 268 }; 269 270 /* H3/H5 */ 271 272 #define H3_CLK_PLL_CPUX 0 273 #define H3_CLK_PLL_PERIPH0 9 274 275 #define H3_CLK_CPUX 14 276 #define H3_CLK_AXI 15 277 #define H3_CLK_AHB1 16 278 #define H3_CLK_APB1 17 279 #define H3_CLK_APB2 18 280 #define H3_CLK_AHB2 19 281 282 #define H3_CLK_BUS_MMC0 22 283 #define H3_CLK_BUS_MMC1 23 284 #define H3_CLK_BUS_MMC2 24 285 #define H3_CLK_BUS_EMAC 27 286 #define H3_CLK_BUS_EHCI0 33 287 #define H3_CLK_BUS_EHCI1 34 288 #define H3_CLK_BUS_EHCI2 35 289 #define H3_CLK_BUS_EHCI3 36 290 #define H3_CLK_BUS_OHCI0 37 291 #define H3_CLK_BUS_OHCI1 38 292 #define H3_CLK_BUS_OHCI2 39 293 #define H3_CLK_BUS_OHCI3 40 294 #define H3_CLK_BUS_PIO 54 295 #define H3_CLK_BUS_THS 55 296 #define H3_CLK_BUS_I2C0 59 297 #define H3_CLK_BUS_I2C1 60 298 #define H3_CLK_BUS_I2C2 61 299 #define H3_CLK_BUS_UART0 62 300 #define H3_CLK_BUS_UART1 63 301 #define H3_CLK_BUS_UART2 64 302 #define H3_CLK_BUS_UART3 65 303 #define H3_CLK_BUS_EPHY 67 304 305 #define H3_CLK_THS 69 306 #define H3_CLK_MMC0 71 307 #define H3_CLK_MMC1 74 308 #define H3_CLK_MMC2 77 309 #define H3_CLK_USB_PHY0 88 310 #define H3_CLK_USB_PHY1 89 311 #define H3_CLK_USB_PHY2 90 312 #define H3_CLK_USB_PHY3 91 313 314 #define H3_CLK_LOSC 254 315 #define H3_CLK_HOSC 253 316 317 struct sxiccmu_ccu_bit sun8i_h3_gates[] = { 318 [H3_CLK_PLL_PERIPH0] = { 0x0028, 31 }, 319 [H3_CLK_BUS_MMC0] = { 0x0060, 8 }, 320 [H3_CLK_BUS_MMC1] = { 0x0060, 9 }, 321 [H3_CLK_BUS_MMC2] = { 0x0060, 10 }, 322 [H3_CLK_BUS_EMAC] = { 0x0060, 17, H3_CLK_AHB2 }, 323 [H3_CLK_BUS_EHCI0] = { 0x0060, 24 }, 324 [H3_CLK_BUS_EHCI1] = { 0x0060, 25 }, 325 [H3_CLK_BUS_EHCI2] = { 0x0060, 26 }, 326 [H3_CLK_BUS_EHCI3] = { 0x0060, 27 }, 327 [H3_CLK_BUS_OHCI0] = { 0x0060, 28 }, 328 [H3_CLK_BUS_OHCI1] = { 0x0060, 29 }, 329 [H3_CLK_BUS_OHCI2] = { 0x0060, 30 }, 330 [H3_CLK_BUS_OHCI3] = { 0x0060, 31 }, 331 [H3_CLK_BUS_PIO] = { 0x0068, 5 }, 332 [H3_CLK_BUS_THS] = { 0x0068, 8 }, 333 [H3_CLK_BUS_I2C0] = { 0x006c, 0, H3_CLK_APB2 }, 334 [H3_CLK_BUS_I2C1] = { 0x006c, 1, H3_CLK_APB2 }, 335 [H3_CLK_BUS_I2C2] = { 0x006c, 2, H3_CLK_APB2 }, 336 [H3_CLK_BUS_UART0] = { 0x006c, 16, H3_CLK_APB2 }, 337 [H3_CLK_BUS_UART1] = { 0x006c, 17, H3_CLK_APB2 }, 338 [H3_CLK_BUS_UART2] = { 0x006c, 18, H3_CLK_APB2 }, 339 [H3_CLK_BUS_UART3] = { 0x006c, 19, H3_CLK_APB2 }, 340 [H3_CLK_BUS_EPHY] = { 0x0070, 0 }, 341 [H3_CLK_THS] = { 0x0074, 31 }, 342 [H3_CLK_MMC0] = { 0x0088, 31 }, 343 [H3_CLK_MMC1] = { 0x008c, 31 }, 344 [H3_CLK_MMC2] = { 0x0090, 31 }, 345 [H3_CLK_USB_PHY0] = { 0x00cc, 8 }, 346 [H3_CLK_USB_PHY1] = { 0x00cc, 9 }, 347 [H3_CLK_USB_PHY2] = { 0x00cc, 10 }, 348 [H3_CLK_USB_PHY3] = { 0x00cc, 11 }, 349 }; 350 351 #define H3_R_CLK_AHB0 1 352 #define H3_R_CLK_APB0 2 353 354 #define H3_R_CLK_APB0_PIO 3 355 #define H3_R_CLK_APB0_I2C 9 356 357 struct sxiccmu_ccu_bit sun8i_h3_r_gates[] = { 358 [H3_R_CLK_APB0_PIO] = { 0x0028, 0 }, 359 [H3_R_CLK_APB0_I2C] = { 0x0028, 6, H3_R_CLK_APB0 }, 360 }; 361 362 /* R40 */ 363 364 #define R40_CLK_PLL_PERIPH0 11 365 #define R40_CLK_PLL_PERIPH0_2X 13 366 367 #define R40_CLK_APB2 28 368 369 #define R40_CLK_BUS_MMC0 32 370 #define R40_CLK_BUS_MMC1 33 371 #define R40_CLK_BUS_MMC2 34 372 #define R40_CLK_BUS_MMC3 35 373 #define R40_CLK_BUS_SATA 45 374 #define R40_CLK_BUS_EHCI0 47 375 #define R40_CLK_BUS_EHCI1 48 376 #define R40_CLK_BUS_EHCI2 49 377 #define R40_CLK_BUS_OHCI0 50 378 #define R40_CLK_BUS_OHCI1 51 379 #define R40_CLK_BUS_OHCI2 52 380 #define R40_CLK_BUS_PIO 79 381 #define R40_CLK_BUS_THS 82 382 #define R40_CLK_BUS_I2C0 87 383 #define R40_CLK_BUS_I2C1 88 384 #define R40_CLK_BUS_I2C2 89 385 #define R40_CLK_BUS_I2C3 90 386 #define R40_CLK_BUS_I2C4 95 387 #define R40_CLK_BUS_UART0 96 388 #define R40_CLK_BUS_UART1 97 389 #define R40_CLK_BUS_UART2 98 390 #define R40_CLK_BUS_UART3 99 391 #define R40_CLK_BUS_UART4 100 392 #define R40_CLK_BUS_UART5 101 393 #define R40_CLK_BUS_UART6 102 394 #define R40_CLK_BUS_UART7 103 395 396 #define R40_CLK_THS 105 397 #define R40_CLK_MMC0 107 398 #define R40_CLK_MMC1 108 399 #define R40_CLK_MMC2 109 400 #define R40_CLK_MMC3 110 401 #define R40_CLK_SATA 123 402 #define R40_CLK_USB_PHY0 124 403 #define R40_CLK_USB_PHY1 125 404 #define R40_CLK_USB_PHY2 126 405 406 struct sxiccmu_ccu_bit sun8i_r40_gates[] = { 407 [R40_CLK_BUS_MMC0] = { 0x0060, 8 }, 408 [R40_CLK_BUS_MMC1] = { 0x0060, 9 }, 409 [R40_CLK_BUS_MMC2] = { 0x0060, 10 }, 410 [R40_CLK_BUS_MMC3] = { 0x0060, 11 }, 411 [R40_CLK_BUS_SATA] = { 0x0060, 24 }, 412 [R40_CLK_BUS_EHCI0] = { 0x0060, 26 }, 413 [R40_CLK_BUS_EHCI1] = { 0x0060, 27 }, 414 [R40_CLK_BUS_EHCI2] = { 0x0060, 28 }, 415 [R40_CLK_BUS_OHCI0] = { 0x0060, 29 }, 416 [R40_CLK_BUS_OHCI1] = { 0x0060, 30 }, 417 [R40_CLK_BUS_OHCI2] = { 0x0060, 31 }, 418 [R40_CLK_BUS_PIO] = { 0x0068, 5 }, 419 [R40_CLK_BUS_THS] = { 0x0068, 8 }, 420 [R40_CLK_BUS_I2C0] = { 0x006c, 0, R40_CLK_APB2 }, 421 [R40_CLK_BUS_I2C1] = { 0x006c, 1, R40_CLK_APB2 }, 422 [R40_CLK_BUS_I2C2] = { 0x006c, 2, R40_CLK_APB2 }, 423 [R40_CLK_BUS_I2C3] = { 0x006c, 3, R40_CLK_APB2 }, 424 [R40_CLK_BUS_I2C4] = { 0x006c, 15, R40_CLK_APB2 }, 425 [R40_CLK_BUS_UART0] = { 0x006c, 16, R40_CLK_APB2 }, 426 [R40_CLK_BUS_UART1] = { 0x006c, 17, R40_CLK_APB2 }, 427 [R40_CLK_BUS_UART2] = { 0x006c, 18, R40_CLK_APB2 }, 428 [R40_CLK_BUS_UART3] = { 0x006c, 19, R40_CLK_APB2 }, 429 [R40_CLK_BUS_UART4] = { 0x006c, 20, R40_CLK_APB2 }, 430 [R40_CLK_BUS_UART5] = { 0x006c, 21, R40_CLK_APB2 }, 431 [R40_CLK_BUS_UART6] = { 0x006c, 22, R40_CLK_APB2 }, 432 [R40_CLK_BUS_UART7] = { 0x006c, 23, R40_CLK_APB2 }, 433 [R40_CLK_THS] = { 0x0074, 31 }, 434 [R40_CLK_MMC0] = { 0x0088, 31 }, 435 [R40_CLK_MMC1] = { 0x008c, 31 }, 436 [R40_CLK_MMC2] = { 0x0090, 31 }, 437 [R40_CLK_MMC3] = { 0x0094, 31 }, 438 [R40_CLK_SATA] = { 0x00c8, 31 }, 439 [R40_CLK_USB_PHY0] = { 0x00cc, 8 }, 440 [R40_CLK_USB_PHY1] = { 0x00cc, 9 }, 441 [R40_CLK_USB_PHY2] = { 0x00cc, 10 }, 442 }; 443 444 /* 445 * Reset Signals 446 */ 447 448 /* A10 */ 449 450 #define A10_RST_USB_PHY0 1 451 #define A10_RST_USB_PHY1 2 452 #define A10_RST_USB_PHY2 3 453 454 struct sxiccmu_ccu_bit sun4i_a10_resets[] = { 455 [A10_RST_USB_PHY0] = { 0x00cc, 0 }, 456 [A10_RST_USB_PHY1] = { 0x00cc, 1 }, 457 [A10_RST_USB_PHY2] = { 0x00cc, 2 }, 458 }; 459 460 /* A23/A33 */ 461 462 #define A23_RST_USB_PHY0 0 463 #define A23_RST_USB_PHY1 1 464 465 #define A23_RST_BUS_MMC0 7 466 #define A23_RST_BUS_MMC1 8 467 #define A23_RST_BUS_MMC2 9 468 469 #define A23_RST_BUS_EHCI 16 470 #define A23_RST_BUS_OHCI 17 471 472 #define A23_RST_BUS_I2C0 32 473 #define A23_RST_BUS_I2C1 33 474 #define A23_RST_BUS_I2C2 34 475 476 #define A23_CLK_HOSC 253 477 #define A23_CLK_LOSC 254 478 479 struct sxiccmu_ccu_bit sun8i_a23_resets[] = { 480 [A23_RST_USB_PHY0] = { 0x00cc, 0 }, 481 [A23_RST_USB_PHY1] = { 0x00cc, 1 }, 482 [A23_RST_BUS_MMC0] = { 0x02c0, 8 }, 483 [A23_RST_BUS_MMC1] = { 0x02c0, 9 }, 484 [A23_RST_BUS_MMC2] = { 0x02c0, 10 }, 485 [A23_RST_BUS_EHCI] = { 0x02c0, 26 }, 486 [A23_RST_BUS_OHCI] = { 0x02c0, 29 }, 487 [A23_RST_BUS_I2C0] = { 0x02d8, 0 }, 488 [A23_RST_BUS_I2C1] = { 0x02d8, 1 }, 489 [A23_RST_BUS_I2C2] = { 0x02d8, 2 }, 490 }; 491 492 /* A64 */ 493 494 #define A64_RST_USB_PHY0 0 495 #define A64_RST_USB_PHY1 1 496 497 #define A64_RST_BUS_MMC0 8 498 #define A64_RST_BUS_MMC1 9 499 #define A64_RST_BUS_MMC2 10 500 501 #define A64_RST_BUS_EMAC 13 502 503 #define A64_RST_BUS_EHCI0 19 504 #define A64_RST_BUS_EHCI1 20 505 #define A64_RST_BUS_OHCI0 21 506 #define A64_RST_BUS_OHCI1 22 507 508 #define A64_RST_BUS_I2C0 42 509 #define A64_RST_BUS_I2C1 43 510 #define A64_RST_BUS_I2C2 44 511 512 struct sxiccmu_ccu_bit sun50i_a64_resets[] = { 513 [A64_RST_USB_PHY0] = { 0x00cc, 0 }, 514 [A64_RST_USB_PHY1] = { 0x00cc, 1 }, 515 [A64_RST_BUS_MMC0] = { 0x02c0, 8 }, 516 [A64_RST_BUS_MMC1] = { 0x02c0, 9 }, 517 [A64_RST_BUS_MMC2] = { 0x02c0, 10 }, 518 [A64_RST_BUS_EMAC] = { 0x02c0, 17 }, 519 [A64_RST_BUS_EHCI0] = { 0x02c0, 24 }, 520 [A64_RST_BUS_EHCI1] = { 0x02c0, 25 }, 521 [A64_RST_BUS_OHCI0] = { 0x02c0, 28 }, 522 [A64_RST_BUS_OHCI1] = { 0x02c0, 29 }, 523 [A64_RST_BUS_I2C0] = { 0x02d8, 0 }, 524 [A64_RST_BUS_I2C1] = { 0x02d8, 1 }, 525 [A64_RST_BUS_I2C2] = { 0x02d8, 2 }, 526 }; 527 528 /* A80 */ 529 530 #define A80_RST_BUS_MMC 4 531 #define A80_RST_BUS_UART0 45 532 #define A80_RST_BUS_UART1 46 533 #define A80_RST_BUS_UART2 47 534 #define A80_RST_BUS_UART3 48 535 #define A80_RST_BUS_UART4 49 536 #define A80_RST_BUS_UART5 50 537 538 struct sxiccmu_ccu_bit sun9i_a80_resets[] = { 539 [A80_RST_BUS_MMC] = { 0x05a0, 8 }, 540 [A80_RST_BUS_UART0] = { 0x05b4, 16 }, 541 [A80_RST_BUS_UART1] = { 0x05b4, 17 }, 542 [A80_RST_BUS_UART2] = { 0x05b4, 18 }, 543 [A80_RST_BUS_UART3] = { 0x05b4, 19 }, 544 [A80_RST_BUS_UART4] = { 0x05b4, 20 }, 545 [A80_RST_BUS_UART5] = { 0x05b4, 21 }, 546 }; 547 548 #define A80_USB_RST_HCI0 0 549 #define A80_USB_RST_HCI1 1 550 #define A80_USB_RST_HCI2 2 551 552 #define A80_USB_RST_HCI0_PHY 3 553 #define A80_USB_RST_HCI1_HSIC 4 554 #define A80_USB_RST_HCI1_PHY 5 555 #define A80_USB_RST_HCI2_HSIC 6 556 #define A80_USB_RST_HCI2_UTMIPHY 7 557 558 struct sxiccmu_ccu_bit sun9i_a80_usb_resets[] = { 559 [A80_USB_RST_HCI0] = { 0x0000, 17 }, 560 [A80_USB_RST_HCI1] = { 0x0000, 18 }, 561 [A80_USB_RST_HCI2] = { 0x0000, 19 }, 562 [A80_USB_RST_HCI0_PHY] = { 0x0004, 17 }, 563 [A80_USB_RST_HCI1_HSIC]= { 0x0004, 18 }, 564 [A80_USB_RST_HCI1_PHY]= { 0x0004, 19 }, /* Undocumented */ 565 [A80_USB_RST_HCI2_HSIC]= { 0x0004, 20 }, /* Undocumented */ 566 [A80_USB_RST_HCI2_UTMIPHY] = { 0x0004, 21 }, 567 }; 568 569 struct sxiccmu_ccu_bit sun9i_a80_mmc_resets[] = { 570 { 0x0000, 18 }, 571 { 0x0004, 18 }, 572 { 0x0008, 18 }, 573 { 0x000c, 18 }, 574 }; 575 576 /* H3/H5 */ 577 578 #define H3_RST_USB_PHY0 0 579 #define H3_RST_USB_PHY1 1 580 #define H3_RST_USB_PHY2 2 581 #define H3_RST_USB_PHY3 3 582 583 #define H3_RST_BUS_MMC0 7 584 #define H3_RST_BUS_MMC1 8 585 #define H3_RST_BUS_MMC2 9 586 587 #define H3_RST_BUS_EMAC 12 588 589 #define H3_RST_BUS_EHCI0 18 590 #define H3_RST_BUS_EHCI1 19 591 #define H3_RST_BUS_EHCI2 20 592 #define H3_RST_BUS_EHCI3 21 593 #define H3_RST_BUS_OHCI0 22 594 #define H3_RST_BUS_OHCI1 23 595 #define H3_RST_BUS_OHCI2 24 596 #define H3_RST_BUS_OHCI3 25 597 #define H3_RST_BUS_EPHY 39 598 #define H3_RST_BUS_THS 42 599 #define H3_RST_BUS_I2C0 46 600 #define H3_RST_BUS_I2C1 47 601 #define H3_RST_BUS_I2C2 48 602 603 struct sxiccmu_ccu_bit sun8i_h3_resets[] = { 604 [H3_RST_USB_PHY0] = { 0x00cc, 0 }, 605 [H3_RST_USB_PHY1] = { 0x00cc, 1 }, 606 [H3_RST_USB_PHY2] = { 0x00cc, 2 }, 607 [H3_RST_USB_PHY3] = { 0x00cc, 3 }, 608 [H3_RST_BUS_MMC0] = { 0x02c0, 8 }, 609 [H3_RST_BUS_MMC1] = { 0x02c0, 9 }, 610 [H3_RST_BUS_MMC2] = { 0x02c0, 10 }, 611 [H3_RST_BUS_EMAC] = { 0x02c0, 17 }, 612 [H3_RST_BUS_EHCI0] = { 0x02c0, 24 }, 613 [H3_RST_BUS_EHCI1] = { 0x02c0, 25 }, 614 [H3_RST_BUS_EHCI2] = { 0x02c0, 26 }, 615 [H3_RST_BUS_EHCI3] = { 0x02c0, 27 }, 616 [H3_RST_BUS_OHCI0] = { 0x02c0, 28 }, 617 [H3_RST_BUS_OHCI1] = { 0x02c0, 29 }, 618 [H3_RST_BUS_OHCI2] = { 0x02c0, 30 }, 619 [H3_RST_BUS_OHCI3] = { 0x02c0, 31 }, 620 [H3_RST_BUS_EPHY] = { 0x02c8, 2 }, 621 [H3_RST_BUS_THS] = { 0x02d0, 8 }, 622 [H3_RST_BUS_I2C0] = { 0x02d8, 0 }, 623 [H3_RST_BUS_I2C1] = { 0x02d8, 1 }, 624 [H3_RST_BUS_I2C2] = { 0x02d8, 2 }, 625 }; 626 627 #define H3_R_RST_APB0_I2C 5 628 629 struct sxiccmu_ccu_bit sun8i_h3_r_resets[] = { 630 [H3_R_RST_APB0_I2C] = { 0x00b0, 6 }, 631 }; 632 633 /* R40 */ 634 635 #define R40_RST_USB_PHY0 0 636 #define R40_RST_USB_PHY1 1 637 #define R40_RST_USB_PHY2 2 638 639 #define R40_RST_BUS_MMC0 8 640 #define R40_RST_BUS_MMC1 9 641 #define R40_RST_BUS_MMC2 10 642 #define R40_RST_BUS_MMC3 11 643 #define R40_RST_BUS_SATA 21 644 #define R40_RST_BUS_EHCI0 23 645 #define R40_RST_BUS_EHCI1 24 646 #define R40_RST_BUS_EHCI2 25 647 #define R40_RST_BUS_OHCI0 26 648 #define R40_RST_BUS_OHCI1 27 649 #define R40_RST_BUS_OHCI2 28 650 #define R40_RST_BUS_THS 59 651 #define R40_RST_BUS_I2C0 64 652 #define R40_RST_BUS_I2C1 65 653 #define R40_RST_BUS_I2C2 66 654 #define R40_RST_BUS_I2C3 67 655 #define R40_RST_BUS_I2C4 72 656 #define R40_RST_BUS_UART0 73 657 #define R40_RST_BUS_UART1 74 658 #define R40_RST_BUS_UART2 75 659 #define R40_RST_BUS_UART3 76 660 #define R40_RST_BUS_UART4 77 661 #define R40_RST_BUS_UART5 78 662 #define R40_RST_BUS_UART6 79 663 #define R40_RST_BUS_UART7 80 664 665 struct sxiccmu_ccu_bit sun8i_r40_resets[] = { 666 [R40_RST_USB_PHY0] = { 0x00cc, 0 }, 667 [R40_RST_USB_PHY1] = { 0x00cc, 1 }, 668 [R40_RST_USB_PHY2] = { 0x00cc, 2 }, 669 [R40_RST_BUS_MMC0] = { 0x02c0, 8 }, 670 [R40_RST_BUS_MMC1] = { 0x02c0, 9 }, 671 [R40_RST_BUS_MMC2] = { 0x02c0, 10 }, 672 [R40_RST_BUS_MMC3] = { 0x02c0, 11 }, 673 [R40_RST_BUS_SATA] = { 0x02c0, 24 }, 674 [R40_RST_BUS_EHCI0] = { 0x02c0, 26 }, 675 [R40_RST_BUS_EHCI1] = { 0x02c0, 27 }, 676 [R40_RST_BUS_EHCI2] = { 0x02c0, 28 }, 677 [R40_RST_BUS_OHCI0] = { 0x02c0, 29 }, 678 [R40_RST_BUS_OHCI1] = { 0x02c0, 30 }, 679 [R40_RST_BUS_OHCI2] = { 0x02c0, 31 }, 680 [R40_RST_BUS_THS] = { 0x02d0, 8 }, 681 [R40_RST_BUS_I2C0] = { 0x02d8, 0 }, 682 [R40_RST_BUS_I2C1] = { 0x02d8, 1 }, 683 [R40_RST_BUS_I2C2] = { 0x02d8, 2 }, 684 [R40_RST_BUS_I2C3] = { 0x02d8, 3 }, 685 [R40_RST_BUS_I2C4] = { 0x02d8, 15 }, 686 [R40_RST_BUS_UART0] = { 0x02d8, 16 }, 687 [R40_RST_BUS_UART1] = { 0x02d8, 17 }, 688 [R40_RST_BUS_UART2] = { 0x02d8, 18 }, 689 [R40_RST_BUS_UART3] = { 0x02d8, 19 }, 690 [R40_RST_BUS_UART4] = { 0x02d8, 20 }, 691 [R40_RST_BUS_UART5] = { 0x02d8, 21 }, 692 [R40_RST_BUS_UART6] = { 0x02d8, 22 }, 693 [R40_RST_BUS_UART7] = { 0x02d8, 23 }, 694 }; 695