1 /* Public Domain */ 2 3 4 /* 5 * Clocks Signals 6 */ 7 8 /* A10/A20 */ 9 10 #define A10_CLK_HOSC 1 11 #define A10_CLK_PLL_CORE 2 12 #define A10_CLK_PLL_PERIPH_BASE 14 13 #define A10_CLK_PLL_PERIPH 15 14 15 #define A10_CLK_CPU 20 16 #define A10_CLK_APB1 25 17 18 #define A10_CLK_AHB_EHCI0 27 19 #define A10_CLK_AHB_OHCI0 28 20 #define A10_CLK_AHB_EHCI1 29 21 #define A10_CLK_AHB_OHCI1 30 22 #define A10_CLK_AHB_MMC0 34 23 #define A10_CLK_AHB_MMC1 35 24 #define A10_CLK_AHB_MMC2 36 25 #define A10_CLK_AHB_MMC3 37 26 #define A10_CLK_AHB_EMAC 42 27 #define A10_CLK_AHB_SATA 49 28 #define A10_CLK_AHB_GMAC 66 29 #define A10_CLK_APB0_PIO 74 30 #define A10_CLK_APB1_I2C0 79 31 #define A10_CLK_APB1_I2C1 80 32 #define A10_CLK_APB1_I2C2 81 33 #define A10_CLK_APB1_I2C3 82 34 #define A10_CLK_APB1_I2C4 87 35 #define A10_CLK_APB1_UART0 88 36 #define A10_CLK_APB1_UART1 89 37 #define A10_CLK_APB1_UART2 90 38 #define A10_CLK_APB1_UART3 91 39 #define A10_CLK_APB1_UART4 92 40 #define A10_CLK_APB1_UART5 93 41 #define A10_CLK_APB1_UART6 94 42 #define A10_CLK_APB1_UART7 95 43 44 #define A10_CLK_MMC0 98 45 #define A10_CLK_MMC1 101 46 #define A10_CLK_MMC2 104 47 #define A10_CLK_MMC3 107 48 #define A10_CLK_SATA 122 49 #define A10_CLK_USB_OHCI0 123 50 #define A10_CLK_USB_OHCI1 124 51 #define A10_CLK_USB_PHY 125 52 53 #define A10_CLK_LOSC 254 54 55 struct sxiccmu_ccu_bit sun4i_a10_gates[] = { 56 [A10_CLK_AHB_EHCI0] = { 0x0060, 1 }, 57 [A10_CLK_AHB_OHCI0] = { 0x0060, 2 }, 58 [A10_CLK_AHB_EHCI1] = { 0x0060, 3 }, 59 [A10_CLK_AHB_OHCI1] = { 0x0060, 4 }, 60 [A10_CLK_AHB_MMC0] = { 0x0060, 8 }, 61 [A10_CLK_AHB_MMC1] = { 0x0060, 9 }, 62 [A10_CLK_AHB_MMC2] = { 0x0060, 10 }, 63 [A10_CLK_AHB_MMC3] = { 0x0060, 11 }, 64 [A10_CLK_AHB_EMAC] = { 0x0060, 17 }, 65 [A10_CLK_AHB_SATA] = { 0x0060, 25 }, 66 [A10_CLK_AHB_GMAC] = { 0x0064, 17 }, 67 [A10_CLK_APB0_PIO] = { 0x0068, 5 }, 68 [A10_CLK_APB1_I2C0] = { 0x006c, 0, A10_CLK_APB1 }, 69 [A10_CLK_APB1_I2C1] = { 0x006c, 1, A10_CLK_APB1 }, 70 [A10_CLK_APB1_I2C2] = { 0x006c, 2, A10_CLK_APB1 }, 71 [A10_CLK_APB1_I2C3] = { 0x006c, 3, A10_CLK_APB1 }, 72 [A10_CLK_APB1_I2C4] = { 0x006c, 15, A10_CLK_APB1 }, 73 [A10_CLK_APB1_UART0] = { 0x006c, 16, A10_CLK_APB1 }, 74 [A10_CLK_APB1_UART1] = { 0x006c, 17, A10_CLK_APB1 }, 75 [A10_CLK_APB1_UART2] = { 0x006c, 18, A10_CLK_APB1 }, 76 [A10_CLK_APB1_UART3] = { 0x006c, 19, A10_CLK_APB1 }, 77 [A10_CLK_APB1_UART4] = { 0x006c, 20, A10_CLK_APB1 }, 78 [A10_CLK_APB1_UART5] = { 0x006c, 21, A10_CLK_APB1 }, 79 [A10_CLK_APB1_UART6] = { 0x006c, 22, A10_CLK_APB1 }, 80 [A10_CLK_APB1_UART7] = { 0x006c, 23, A10_CLK_APB1 }, 81 [A10_CLK_MMC0] = { 0x0088, 31 }, 82 [A10_CLK_MMC1] = { 0x008c, 31 }, 83 [A10_CLK_MMC2] = { 0x0090, 31 }, 84 [A10_CLK_MMC3] = { 0x0094, 31 }, 85 [A10_CLK_SATA] = { 0x00c8, 31 }, 86 [A10_CLK_USB_OHCI0] = { 0x00cc, 6 }, 87 [A10_CLK_USB_OHCI1] = { 0x00cc, 7 }, 88 [A10_CLK_USB_PHY] = { 0x00cc, 8 }, 89 }; 90 91 /* A23/A33 */ 92 93 #define A23_CLK_PLL_PERIPH 10 94 95 #define A23_CLK_AXI 19 96 #define A23_CLK_AHB1 20 97 #define A23_CLK_APB1 21 98 #define A23_CLK_APB2 22 99 100 #define A23_CLK_BUS_MMC0 26 101 #define A23_CLK_BUS_MMC1 27 102 #define A23_CLK_BUS_MMC2 28 103 #define A23_CLK_BUS_EHCI 35 104 #define A23_CLK_BUS_OHCI 36 105 #define A23_CLK_BUS_PIO 48 106 #define A23_CLK_BUS_I2C0 51 107 #define A23_CLK_BUS_I2C1 52 108 #define A23_CLK_BUS_I2C2 53 109 #define A23_CLK_BUS_UART0 54 110 #define A23_CLK_BUS_UART1 55 111 #define A23_CLK_BUS_UART2 56 112 #define A23_CLK_BUS_UART3 57 113 #define A23_CLK_BUS_UART4 58 114 115 #define A23_CLK_MMC0 60 116 #define A23_CLK_MMC1 63 117 #define A23_CLK_MMC2 66 118 #define A23_CLK_USB_OHCI 78 119 120 struct sxiccmu_ccu_bit sun8i_a23_gates[] = { 121 [A23_CLK_BUS_MMC0] = { 0x0060, 8 }, 122 [A23_CLK_BUS_MMC1] = { 0x0060, 9 }, 123 [A23_CLK_BUS_MMC2] = { 0x0060, 10 }, 124 [A23_CLK_BUS_EHCI] = { 0x0060, 26 }, 125 [A23_CLK_BUS_OHCI] = { 0x0060, 29 }, 126 [A23_CLK_BUS_PIO] = { 0x0068, 5 }, 127 [A23_CLK_BUS_I2C0] = { 0x006c, 0, A23_CLK_APB2 }, 128 [A23_CLK_BUS_I2C1] = { 0x006c, 1, A23_CLK_APB2 }, 129 [A23_CLK_BUS_I2C2] = { 0x006c, 2, A23_CLK_APB2 }, 130 [A23_CLK_BUS_UART0] = { 0x006c, 16, A23_CLK_APB2 }, 131 [A23_CLK_BUS_UART1] = { 0x006c, 17, A23_CLK_APB2 }, 132 [A23_CLK_BUS_UART2] = { 0x006c, 18, A23_CLK_APB2 }, 133 [A23_CLK_BUS_UART3] = { 0x006c, 19, A23_CLK_APB2 }, 134 [A23_CLK_BUS_UART4] = { 0x006c, 20, A23_CLK_APB2 }, 135 [A23_CLK_MMC0] = { 0x0088, 31 }, 136 [A23_CLK_MMC1] = { 0x008c, 31 }, 137 [A23_CLK_MMC2] = { 0x0090, 31 }, 138 [A23_CLK_USB_OHCI] = { 0x00cc, 16 }, 139 }; 140 141 /* A64 */ 142 143 #define A64_CLK_PLL_PERIPH0 11 144 #define A64_CLK_PLL_PERIPH0_2X 12 145 146 #define A64_CLK_AXI 22 147 #define A64_CLK_APB 23 148 #define A64_CLK_AHB1 24 149 #define A64_CLK_APB1 25 150 #define A64_CLK_APB2 26 151 #define A64_CLK_AHB2 27 152 153 #define A64_CLK_BUS_MMC0 31 154 #define A64_CLK_BUS_MMC1 32 155 #define A64_CLK_BUS_MMC2 33 156 #define A64_CLK_BUS_EMAC 36 157 #define A64_CLK_BUS_EHCI0 42 158 #define A64_CLK_BUS_EHCI1 43 159 #define A64_CLK_BUS_OHCI0 44 160 #define A64_CLK_BUS_OHCI1 45 161 #define A64_CLK_BUS_PIO 58 162 #define A64_CLK_BUS_THS 59 163 #define A64_CLK_BUS_I2C0 63 164 #define A64_CLK_BUS_I2C1 64 165 #define A64_CLK_BUS_I2C2 65 166 #define A64_CLK_BUS_UART0 67 167 #define A64_CLK_BUS_UART1 68 168 #define A64_CLK_BUS_UART2 69 169 #define A64_CLK_BUS_UART3 70 170 #define A64_CLK_BUS_UART4 71 171 172 #define A64_CLK_THS 73 173 #define A64_CLK_MMC0 75 174 #define A64_CLK_MMC1 76 175 #define A64_CLK_MMC2 77 176 #define A64_CLK_USB_OHCI0 91 177 #define A64_CLK_USB_OHCI1 93 178 #define A64_CLK_USB_PHY0 86 179 #define A64_CLK_USB_PHY1 87 180 181 #define A64_CLK_LOSC 254 182 #define A64_CLK_HOSC 253 183 184 struct sxiccmu_ccu_bit sun50i_a64_gates[] = { 185 [A64_CLK_PLL_PERIPH0] = { 0x0028, 31 }, 186 [A64_CLK_BUS_MMC0] = { 0x0060, 8 }, 187 [A64_CLK_BUS_MMC1] = { 0x0060, 9 }, 188 [A64_CLK_BUS_MMC2] = { 0x0060, 10 }, 189 [A64_CLK_BUS_EMAC] = { 0x0060, 17, A64_CLK_AHB2 }, 190 [A64_CLK_BUS_EHCI0] = { 0x0060, 24 }, 191 [A64_CLK_BUS_EHCI1] = { 0x0060, 25 }, 192 [A64_CLK_BUS_OHCI0] = { 0x0060, 28 }, 193 [A64_CLK_BUS_OHCI1] = { 0x0060, 29 }, 194 [A64_CLK_BUS_PIO] = { 0x0068, 5 }, 195 [A64_CLK_BUS_THS] = { 0x0068, 8 }, 196 [A64_CLK_BUS_I2C0] = { 0x006c, 0, A64_CLK_APB2 }, 197 [A64_CLK_BUS_I2C1] = { 0x006c, 1, A64_CLK_APB2 }, 198 [A64_CLK_BUS_I2C2] = { 0x006c, 2, A64_CLK_APB2 }, 199 [A64_CLK_BUS_UART0] = { 0x006c, 16, A64_CLK_APB2 }, 200 [A64_CLK_BUS_UART1] = { 0x006c, 17, A64_CLK_APB2 }, 201 [A64_CLK_BUS_UART2] = { 0x006c, 18, A64_CLK_APB2 }, 202 [A64_CLK_BUS_UART3] = { 0x006c, 19, A64_CLK_APB2 }, 203 [A64_CLK_BUS_UART4] = { 0x006c, 20, A64_CLK_APB2 }, 204 [A64_CLK_THS] = { 0x0074, 31 }, 205 [A64_CLK_MMC0] = { 0x0088, 31 }, 206 [A64_CLK_MMC1] = { 0x008c, 31 }, 207 [A64_CLK_MMC2] = { 0x0090, 31 }, 208 [A64_CLK_USB_OHCI0] = { 0x00cc, 16 }, 209 [A64_CLK_USB_OHCI1] = { 0x00cc, 17 }, 210 [A64_CLK_USB_PHY0] = { 0x00cc, 8 }, 211 [A64_CLK_USB_PHY1] = { 0x00cc, 9 }, 212 }; 213 214 /* A80 */ 215 216 #define A80_CLK_PLL_PERIPH0 3 217 218 #define A80_CLK_APB1 23 219 220 #define A80_CLK_MMC0 33 221 #define A80_CLK_MMC1 36 222 #define A80_CLK_MMC2 39 223 #define A80_CLK_MMC3 42 224 225 #define A80_CLK_BUS_MMC 84 226 #define A80_CLK_BUS_USB 96 227 #define A80_CLK_BUS_PIO 111 228 #define A80_CLK_BUS_UART0 124 229 #define A80_CLK_BUS_UART1 125 230 #define A80_CLK_BUS_UART2 126 231 #define A80_CLK_BUS_UART3 127 232 #define A80_CLK_BUS_UART4 128 233 #define A80_CLK_BUS_UART5 129 234 235 struct sxiccmu_ccu_bit sun9i_a80_gates[] = { 236 [A80_CLK_MMC0] = { 0x0410, 31 }, 237 [A80_CLK_MMC1] = { 0x0414, 31 }, 238 [A80_CLK_MMC2] = { 0x0418, 31 }, 239 [A80_CLK_MMC3] = { 0x041c, 31 }, /* Undocumented */ 240 [A80_CLK_BUS_MMC] = { 0x0580, 8 }, 241 [A80_CLK_BUS_USB] = { 0x0584, 1 }, 242 [A80_CLK_BUS_PIO] = { 0x0590, 5 }, 243 [A80_CLK_BUS_UART0] = { 0x0594, 16, A80_CLK_APB1 }, 244 [A80_CLK_BUS_UART1] = { 0x0594, 17, A80_CLK_APB1 }, 245 [A80_CLK_BUS_UART2] = { 0x0594, 18, A80_CLK_APB1 }, 246 [A80_CLK_BUS_UART3] = { 0x0594, 19, A80_CLK_APB1 }, 247 [A80_CLK_BUS_UART4] = { 0x0594, 20, A80_CLK_APB1 }, 248 [A80_CLK_BUS_UART5] = { 0x0594, 21, A80_CLK_APB1 }, 249 }; 250 251 #define A80_USB_CLK_HCI0 0 252 #define A80_USB_CLK_OHCI0 1 253 #define A80_USB_CLK_HCI1 2 254 #define A80_USB_CLK_HCI2 3 255 #define A80_USB_CLK_OHCI2 4 256 257 #define A80_USB_CLK_HCI0_PHY 5 258 #define A80_USB_CLK_HCI1_HSIC 6 259 #define A80_USB_CLK_HCI1_PHY 7 260 #define A80_USB_CLK_HCI2_HSIC 8 261 #define A80_USB_CLK_HCI2_UTMIPHY 9 262 #define A80_USB_CLK_HCI1_HSIC_12M 10 263 264 struct sxiccmu_ccu_bit sun9i_a80_usb_gates[] = { 265 [A80_USB_CLK_HCI0] = { 0x0000, 1 }, 266 [A80_USB_CLK_OHCI0] = { 0x0000, 2 }, 267 [A80_USB_CLK_HCI1] = { 0x0000, 3 }, 268 [A80_USB_CLK_HCI2] = { 0x0000, 5 }, 269 [A80_USB_CLK_OHCI2] = { 0x0000, 6 }, 270 [A80_USB_CLK_HCI0_PHY] = { 0x0004, 1 }, 271 [A80_USB_CLK_HCI1_HSIC] = { 0x0004, 2 }, 272 [A80_USB_CLK_HCI1_PHY] = { 0x0004, 3 }, /* Undocumented */ 273 [A80_USB_CLK_HCI2_HSIC] = { 0x0004, 4 }, 274 [A80_USB_CLK_HCI2_UTMIPHY] = { 0x0004, 5 }, 275 [A80_USB_CLK_HCI1_HSIC_12M] = { 0x0004, 10 }, 276 }; 277 278 struct sxiccmu_ccu_bit sun9i_a80_mmc_gates[] = { 279 { 0x0000, 16 }, 280 { 0x0004, 16 }, 281 { 0x0008, 16 }, 282 { 0x000c, 16 }, 283 }; 284 285 /* H3/H5 */ 286 287 #define H3_CLK_PLL_CPUX 0 288 #define H3_CLK_PLL_PERIPH0 9 289 290 #define H3_CLK_CPUX 14 291 #define H3_CLK_AXI 15 292 #define H3_CLK_AHB1 16 293 #define H3_CLK_APB1 17 294 #define H3_CLK_APB2 18 295 #define H3_CLK_AHB2 19 296 297 #define H3_CLK_BUS_MMC0 22 298 #define H3_CLK_BUS_MMC1 23 299 #define H3_CLK_BUS_MMC2 24 300 #define H3_CLK_BUS_EMAC 27 301 #define H3_CLK_BUS_EHCI0 33 302 #define H3_CLK_BUS_EHCI1 34 303 #define H3_CLK_BUS_EHCI2 35 304 #define H3_CLK_BUS_EHCI3 36 305 #define H3_CLK_BUS_OHCI0 37 306 #define H3_CLK_BUS_OHCI1 38 307 #define H3_CLK_BUS_OHCI2 39 308 #define H3_CLK_BUS_OHCI3 40 309 #define H3_CLK_BUS_PIO 54 310 #define H3_CLK_BUS_THS 55 311 #define H3_CLK_BUS_I2C0 59 312 #define H3_CLK_BUS_I2C1 60 313 #define H3_CLK_BUS_I2C2 61 314 #define H3_CLK_BUS_UART0 62 315 #define H3_CLK_BUS_UART1 63 316 #define H3_CLK_BUS_UART2 64 317 #define H3_CLK_BUS_UART3 65 318 #define H3_CLK_BUS_EPHY 67 319 320 #define H3_CLK_THS 69 321 #define H3_CLK_MMC0 71 322 #define H3_CLK_MMC1 74 323 #define H3_CLK_MMC2 77 324 #define H3_CLK_USB_PHY0 88 325 #define H3_CLK_USB_PHY1 89 326 #define H3_CLK_USB_PHY2 90 327 #define H3_CLK_USB_PHY3 91 328 #define H3_CLK_USB_OHCI0 92 329 #define H3_CLK_USB_OHCI1 93 330 #define H3_CLK_USB_OHCI2 94 331 #define H3_CLK_USB_OHCI3 95 332 333 #define H3_CLK_LOSC 254 334 #define H3_CLK_HOSC 253 335 336 struct sxiccmu_ccu_bit sun8i_h3_gates[] = { 337 [H3_CLK_PLL_PERIPH0] = { 0x0028, 31 }, 338 [H3_CLK_BUS_MMC0] = { 0x0060, 8 }, 339 [H3_CLK_BUS_MMC1] = { 0x0060, 9 }, 340 [H3_CLK_BUS_MMC2] = { 0x0060, 10 }, 341 [H3_CLK_BUS_EMAC] = { 0x0060, 17, H3_CLK_AHB2 }, 342 [H3_CLK_BUS_EHCI0] = { 0x0060, 24 }, 343 [H3_CLK_BUS_EHCI1] = { 0x0060, 25 }, 344 [H3_CLK_BUS_EHCI2] = { 0x0060, 26 }, 345 [H3_CLK_BUS_EHCI3] = { 0x0060, 27 }, 346 [H3_CLK_BUS_OHCI0] = { 0x0060, 28 }, 347 [H3_CLK_BUS_OHCI1] = { 0x0060, 29 }, 348 [H3_CLK_BUS_OHCI2] = { 0x0060, 30 }, 349 [H3_CLK_BUS_OHCI3] = { 0x0060, 31 }, 350 [H3_CLK_BUS_PIO] = { 0x0068, 5 }, 351 [H3_CLK_BUS_THS] = { 0x0068, 8 }, 352 [H3_CLK_BUS_I2C0] = { 0x006c, 0, H3_CLK_APB2 }, 353 [H3_CLK_BUS_I2C1] = { 0x006c, 1, H3_CLK_APB2 }, 354 [H3_CLK_BUS_I2C2] = { 0x006c, 2, H3_CLK_APB2 }, 355 [H3_CLK_BUS_UART0] = { 0x006c, 16, H3_CLK_APB2 }, 356 [H3_CLK_BUS_UART1] = { 0x006c, 17, H3_CLK_APB2 }, 357 [H3_CLK_BUS_UART2] = { 0x006c, 18, H3_CLK_APB2 }, 358 [H3_CLK_BUS_UART3] = { 0x006c, 19, H3_CLK_APB2 }, 359 [H3_CLK_BUS_EPHY] = { 0x0070, 0 }, 360 [H3_CLK_THS] = { 0x0074, 31 }, 361 [H3_CLK_MMC0] = { 0x0088, 31 }, 362 [H3_CLK_MMC1] = { 0x008c, 31 }, 363 [H3_CLK_MMC2] = { 0x0090, 31 }, 364 [H3_CLK_USB_PHY0] = { 0x00cc, 8 }, 365 [H3_CLK_USB_PHY1] = { 0x00cc, 9 }, 366 [H3_CLK_USB_PHY2] = { 0x00cc, 10 }, 367 [H3_CLK_USB_PHY3] = { 0x00cc, 11 }, 368 [H3_CLK_USB_OHCI0] = { 0x00cc, 16 }, 369 [H3_CLK_USB_OHCI1] = { 0x00cc, 17 }, 370 [H3_CLK_USB_OHCI2] = { 0x00cc, 18 }, 371 [H3_CLK_USB_OHCI3] = { 0x00cc, 19 }, 372 }; 373 374 #define H3_R_CLK_AHB0 1 375 #define H3_R_CLK_APB0 2 376 377 #define H3_R_CLK_APB0_PIO 3 378 #define H3_R_CLK_APB0_RSB 6 379 #define H3_R_CLK_APB0_I2C 9 380 381 struct sxiccmu_ccu_bit sun8i_h3_r_gates[] = { 382 [H3_R_CLK_APB0_PIO] = { 0x0028, 0 }, 383 [H3_R_CLK_APB0_RSB] = { 0x0028, 3, H3_R_CLK_APB0 }, 384 [H3_R_CLK_APB0_I2C] = { 0x0028, 6, H3_R_CLK_APB0 }, 385 }; 386 387 /* R40 */ 388 389 #define R40_CLK_PLL_PERIPH0 11 390 #define R40_CLK_PLL_PERIPH0_2X 13 391 392 #define R40_CLK_AXI 25 393 #define R40_CLK_AHB1 26 394 #define R40_CLK_APB2 28 395 396 #define R40_CLK_BUS_MMC0 32 397 #define R40_CLK_BUS_MMC1 33 398 #define R40_CLK_BUS_MMC2 34 399 #define R40_CLK_BUS_MMC3 35 400 #define R40_CLK_BUS_SATA 45 401 #define R40_CLK_BUS_EHCI0 47 402 #define R40_CLK_BUS_EHCI1 48 403 #define R40_CLK_BUS_EHCI2 49 404 #define R40_CLK_BUS_OHCI0 50 405 #define R40_CLK_BUS_OHCI1 51 406 #define R40_CLK_BUS_OHCI2 52 407 #define R40_CLK_BUS_GMAC 64 408 #define R40_CLK_BUS_PIO 79 409 #define R40_CLK_BUS_THS 82 410 #define R40_CLK_BUS_I2C0 87 411 #define R40_CLK_BUS_I2C1 88 412 #define R40_CLK_BUS_I2C2 89 413 #define R40_CLK_BUS_I2C3 90 414 #define R40_CLK_BUS_I2C4 95 415 #define R40_CLK_BUS_UART0 96 416 #define R40_CLK_BUS_UART1 97 417 #define R40_CLK_BUS_UART2 98 418 #define R40_CLK_BUS_UART3 99 419 #define R40_CLK_BUS_UART4 100 420 #define R40_CLK_BUS_UART5 101 421 #define R40_CLK_BUS_UART6 102 422 #define R40_CLK_BUS_UART7 103 423 424 #define R40_CLK_THS 105 425 #define R40_CLK_MMC0 107 426 #define R40_CLK_MMC1 108 427 #define R40_CLK_MMC2 109 428 #define R40_CLK_MMC3 110 429 #define R40_CLK_SATA 123 430 #define R40_CLK_USB_PHY0 124 431 #define R40_CLK_USB_PHY1 125 432 #define R40_CLK_USB_PHY2 126 433 434 #define R40_CLK_HOSC 253 435 #define R40_CLK_LOSC 254 436 437 struct sxiccmu_ccu_bit sun8i_r40_gates[] = { 438 [R40_CLK_BUS_MMC0] = { 0x0060, 8 }, 439 [R40_CLK_BUS_MMC1] = { 0x0060, 9 }, 440 [R40_CLK_BUS_MMC2] = { 0x0060, 10 }, 441 [R40_CLK_BUS_MMC3] = { 0x0060, 11 }, 442 [R40_CLK_BUS_SATA] = { 0x0060, 24 }, 443 [R40_CLK_BUS_EHCI0] = { 0x0060, 26 }, 444 [R40_CLK_BUS_EHCI1] = { 0x0060, 27 }, 445 [R40_CLK_BUS_EHCI2] = { 0x0060, 28 }, 446 [R40_CLK_BUS_OHCI0] = { 0x0060, 29 }, 447 [R40_CLK_BUS_OHCI1] = { 0x0060, 30 }, 448 [R40_CLK_BUS_OHCI2] = { 0x0060, 31 }, 449 [R40_CLK_BUS_GMAC] = { 0x0064, 17, R40_CLK_AHB1 }, 450 [R40_CLK_BUS_PIO] = { 0x0068, 5 }, 451 [R40_CLK_BUS_THS] = { 0x0068, 8 }, 452 [R40_CLK_BUS_I2C0] = { 0x006c, 0, R40_CLK_APB2 }, 453 [R40_CLK_BUS_I2C1] = { 0x006c, 1, R40_CLK_APB2 }, 454 [R40_CLK_BUS_I2C2] = { 0x006c, 2, R40_CLK_APB2 }, 455 [R40_CLK_BUS_I2C3] = { 0x006c, 3, R40_CLK_APB2 }, 456 [R40_CLK_BUS_I2C4] = { 0x006c, 15, R40_CLK_APB2 }, 457 [R40_CLK_BUS_UART0] = { 0x006c, 16, R40_CLK_APB2 }, 458 [R40_CLK_BUS_UART1] = { 0x006c, 17, R40_CLK_APB2 }, 459 [R40_CLK_BUS_UART2] = { 0x006c, 18, R40_CLK_APB2 }, 460 [R40_CLK_BUS_UART3] = { 0x006c, 19, R40_CLK_APB2 }, 461 [R40_CLK_BUS_UART4] = { 0x006c, 20, R40_CLK_APB2 }, 462 [R40_CLK_BUS_UART5] = { 0x006c, 21, R40_CLK_APB2 }, 463 [R40_CLK_BUS_UART6] = { 0x006c, 22, R40_CLK_APB2 }, 464 [R40_CLK_BUS_UART7] = { 0x006c, 23, R40_CLK_APB2 }, 465 [R40_CLK_THS] = { 0x0074, 31 }, 466 [R40_CLK_MMC0] = { 0x0088, 31 }, 467 [R40_CLK_MMC1] = { 0x008c, 31 }, 468 [R40_CLK_MMC2] = { 0x0090, 31 }, 469 [R40_CLK_MMC3] = { 0x0094, 31 }, 470 [R40_CLK_SATA] = { 0x00c8, 31 }, 471 [R40_CLK_USB_PHY0] = { 0x00cc, 8 }, 472 [R40_CLK_USB_PHY1] = { 0x00cc, 9 }, 473 [R40_CLK_USB_PHY2] = { 0x00cc, 10 }, 474 }; 475 476 /* V3s */ 477 478 #define V3S_CLK_PLL_PERIPH0 9 479 #define V3S_CLK_AXI 15 480 #define V3S_CLK_AHB1 16 481 #define V3S_CLK_APB2 18 482 #define V3S_CLK_AHB2 19 483 484 #define V3S_CLK_BUS_MMC0 22 485 #define V3S_CLK_BUS_MMC1 23 486 #define V3S_CLK_BUS_MMC2 24 487 #define V3S_CLK_BUS_EMAC 26 488 #define V3S_CLK_BUS_EHCI0 30 489 #define V3S_CLK_BUS_OHCI0 31 490 #define V3S_CLK_BUS_PIO 37 491 #define V3S_CLK_BUS_I2C0 38 492 #define V3S_CLK_BUS_I2C1 39 493 #define V3S_CLK_BUS_UART0 40 494 #define V3S_CLK_BUS_UART1 41 495 #define V3S_CLK_BUS_UART2 42 496 #define V3S_CLK_BUS_EPHY 43 497 498 #define V3S_CLK_MMC0 45 499 #define V3S_CLK_MMC1 48 500 #define V3S_CLK_MMC2 51 501 #define V3S_CLK_USB_PHY0 56 502 #define V3S_CLK_USB_OHCI0 57 503 504 #define V3S_CLK_LOSC 254 505 #define V3S_CLK_HOSC 253 506 507 struct sxiccmu_ccu_bit sun8i_v3s_gates[] = { 508 [V3S_CLK_BUS_OHCI0] = { 0x0060, 29 }, 509 [V3S_CLK_BUS_EHCI0] = { 0x0060, 26 }, 510 [V3S_CLK_BUS_EMAC] = { 0x0060, 17, V3S_CLK_AHB2 }, 511 [V3S_CLK_BUS_MMC2] = { 0x0060, 10 }, 512 [V3S_CLK_BUS_MMC1] = { 0x0060, 9 }, 513 [V3S_CLK_BUS_MMC0] = { 0x0060, 8 }, 514 [V3S_CLK_BUS_PIO] = { 0x0068, 5 }, 515 [V3S_CLK_BUS_UART2] = { 0x006c, 18, V3S_CLK_APB2 }, 516 [V3S_CLK_BUS_UART1] = { 0x006c, 17, V3S_CLK_APB2 }, 517 [V3S_CLK_BUS_UART0] = { 0x006c, 16, V3S_CLK_APB2 }, 518 [V3S_CLK_BUS_I2C1] = { 0x006c, 1, V3S_CLK_APB2 }, 519 [V3S_CLK_BUS_I2C0] = { 0x006c, 0, V3S_CLK_APB2 }, 520 [V3S_CLK_BUS_EPHY] = { 0x0070, 0 }, 521 [V3S_CLK_MMC0] = { 0x0088, 31 }, 522 [V3S_CLK_MMC1] = { 0x008c, 31 }, 523 [V3S_CLK_MMC2] = { 0x0090, 31 }, 524 [V3S_CLK_USB_OHCI0] = { 0x00cc, 16 }, 525 [V3S_CLK_USB_PHY0] = { 0x00cc, 8 }, 526 }; 527 528 /* 529 * Reset Signals 530 */ 531 532 /* A10 */ 533 534 #define A10_RST_USB_PHY0 1 535 #define A10_RST_USB_PHY1 2 536 #define A10_RST_USB_PHY2 3 537 538 struct sxiccmu_ccu_bit sun4i_a10_resets[] = { 539 [A10_RST_USB_PHY0] = { 0x00cc, 0 }, 540 [A10_RST_USB_PHY1] = { 0x00cc, 1 }, 541 [A10_RST_USB_PHY2] = { 0x00cc, 2 }, 542 }; 543 544 /* A23/A33 */ 545 546 #define A23_RST_USB_PHY0 0 547 #define A23_RST_USB_PHY1 1 548 549 #define A23_RST_BUS_MMC0 7 550 #define A23_RST_BUS_MMC1 8 551 #define A23_RST_BUS_MMC2 9 552 553 #define A23_RST_BUS_EHCI 16 554 #define A23_RST_BUS_OHCI 17 555 556 #define A23_RST_BUS_I2C0 32 557 #define A23_RST_BUS_I2C1 33 558 #define A23_RST_BUS_I2C2 34 559 560 #define A23_CLK_HOSC 253 561 #define A23_CLK_LOSC 254 562 563 struct sxiccmu_ccu_bit sun8i_a23_resets[] = { 564 [A23_RST_USB_PHY0] = { 0x00cc, 0 }, 565 [A23_RST_USB_PHY1] = { 0x00cc, 1 }, 566 [A23_RST_BUS_MMC0] = { 0x02c0, 8 }, 567 [A23_RST_BUS_MMC1] = { 0x02c0, 9 }, 568 [A23_RST_BUS_MMC2] = { 0x02c0, 10 }, 569 [A23_RST_BUS_EHCI] = { 0x02c0, 26 }, 570 [A23_RST_BUS_OHCI] = { 0x02c0, 29 }, 571 [A23_RST_BUS_I2C0] = { 0x02d8, 0 }, 572 [A23_RST_BUS_I2C1] = { 0x02d8, 1 }, 573 [A23_RST_BUS_I2C2] = { 0x02d8, 2 }, 574 }; 575 576 /* A64 */ 577 578 #define A64_RST_USB_PHY0 0 579 #define A64_RST_USB_PHY1 1 580 581 #define A64_RST_BUS_MMC0 8 582 #define A64_RST_BUS_MMC1 9 583 #define A64_RST_BUS_MMC2 10 584 #define A64_RST_BUS_EMAC 13 585 #define A64_RST_BUS_EHCI0 19 586 #define A64_RST_BUS_EHCI1 20 587 #define A64_RST_BUS_OHCI0 21 588 #define A64_RST_BUS_OHCI1 22 589 #define A64_RST_BUS_THS 38 590 #define A64_RST_BUS_I2C0 42 591 #define A64_RST_BUS_I2C1 43 592 #define A64_RST_BUS_I2C2 44 593 594 struct sxiccmu_ccu_bit sun50i_a64_resets[] = { 595 [A64_RST_USB_PHY0] = { 0x00cc, 0 }, 596 [A64_RST_USB_PHY1] = { 0x00cc, 1 }, 597 [A64_RST_BUS_MMC0] = { 0x02c0, 8 }, 598 [A64_RST_BUS_MMC1] = { 0x02c0, 9 }, 599 [A64_RST_BUS_MMC2] = { 0x02c0, 10 }, 600 [A64_RST_BUS_EMAC] = { 0x02c0, 17 }, 601 [A64_RST_BUS_EHCI0] = { 0x02c0, 24 }, 602 [A64_RST_BUS_EHCI1] = { 0x02c0, 25 }, 603 [A64_RST_BUS_OHCI0] = { 0x02c0, 28 }, 604 [A64_RST_BUS_OHCI1] = { 0x02c0, 29 }, 605 [A64_RST_BUS_THS] = { 0x02d0, 8 }, 606 [A64_RST_BUS_I2C0] = { 0x02d8, 0 }, 607 [A64_RST_BUS_I2C1] = { 0x02d8, 1 }, 608 [A64_RST_BUS_I2C2] = { 0x02d8, 2 }, 609 }; 610 611 /* A80 */ 612 613 #define A80_RST_BUS_MMC 4 614 #define A80_RST_BUS_UART0 45 615 #define A80_RST_BUS_UART1 46 616 #define A80_RST_BUS_UART2 47 617 #define A80_RST_BUS_UART3 48 618 #define A80_RST_BUS_UART4 49 619 #define A80_RST_BUS_UART5 50 620 621 struct sxiccmu_ccu_bit sun9i_a80_resets[] = { 622 [A80_RST_BUS_MMC] = { 0x05a0, 8 }, 623 [A80_RST_BUS_UART0] = { 0x05b4, 16 }, 624 [A80_RST_BUS_UART1] = { 0x05b4, 17 }, 625 [A80_RST_BUS_UART2] = { 0x05b4, 18 }, 626 [A80_RST_BUS_UART3] = { 0x05b4, 19 }, 627 [A80_RST_BUS_UART4] = { 0x05b4, 20 }, 628 [A80_RST_BUS_UART5] = { 0x05b4, 21 }, 629 }; 630 631 #define A80_USB_RST_HCI0 0 632 #define A80_USB_RST_HCI1 1 633 #define A80_USB_RST_HCI2 2 634 635 #define A80_USB_RST_HCI0_PHY 3 636 #define A80_USB_RST_HCI1_HSIC 4 637 #define A80_USB_RST_HCI1_PHY 5 638 #define A80_USB_RST_HCI2_HSIC 6 639 #define A80_USB_RST_HCI2_UTMIPHY 7 640 641 struct sxiccmu_ccu_bit sun9i_a80_usb_resets[] = { 642 [A80_USB_RST_HCI0] = { 0x0000, 17 }, 643 [A80_USB_RST_HCI1] = { 0x0000, 18 }, 644 [A80_USB_RST_HCI2] = { 0x0000, 19 }, 645 [A80_USB_RST_HCI0_PHY] = { 0x0004, 17 }, 646 [A80_USB_RST_HCI1_HSIC]= { 0x0004, 18 }, 647 [A80_USB_RST_HCI1_PHY]= { 0x0004, 19 }, /* Undocumented */ 648 [A80_USB_RST_HCI2_HSIC]= { 0x0004, 20 }, /* Undocumented */ 649 [A80_USB_RST_HCI2_UTMIPHY] = { 0x0004, 21 }, 650 }; 651 652 struct sxiccmu_ccu_bit sun9i_a80_mmc_resets[] = { 653 { 0x0000, 18 }, 654 { 0x0004, 18 }, 655 { 0x0008, 18 }, 656 { 0x000c, 18 }, 657 }; 658 659 /* H3/H5 */ 660 661 #define H3_RST_USB_PHY0 0 662 #define H3_RST_USB_PHY1 1 663 #define H3_RST_USB_PHY2 2 664 #define H3_RST_USB_PHY3 3 665 666 #define H3_RST_BUS_MMC0 7 667 #define H3_RST_BUS_MMC1 8 668 #define H3_RST_BUS_MMC2 9 669 670 #define H3_RST_BUS_EMAC 12 671 672 #define H3_RST_BUS_EHCI0 18 673 #define H3_RST_BUS_EHCI1 19 674 #define H3_RST_BUS_EHCI2 20 675 #define H3_RST_BUS_EHCI3 21 676 #define H3_RST_BUS_OHCI0 22 677 #define H3_RST_BUS_OHCI1 23 678 #define H3_RST_BUS_OHCI2 24 679 #define H3_RST_BUS_OHCI3 25 680 #define H3_RST_BUS_EPHY 39 681 #define H3_RST_BUS_THS 42 682 #define H3_RST_BUS_I2C0 46 683 #define H3_RST_BUS_I2C1 47 684 #define H3_RST_BUS_I2C2 48 685 686 struct sxiccmu_ccu_bit sun8i_h3_resets[] = { 687 [H3_RST_USB_PHY0] = { 0x00cc, 0 }, 688 [H3_RST_USB_PHY1] = { 0x00cc, 1 }, 689 [H3_RST_USB_PHY2] = { 0x00cc, 2 }, 690 [H3_RST_USB_PHY3] = { 0x00cc, 3 }, 691 [H3_RST_BUS_MMC0] = { 0x02c0, 8 }, 692 [H3_RST_BUS_MMC1] = { 0x02c0, 9 }, 693 [H3_RST_BUS_MMC2] = { 0x02c0, 10 }, 694 [H3_RST_BUS_EMAC] = { 0x02c0, 17 }, 695 [H3_RST_BUS_EHCI0] = { 0x02c0, 24 }, 696 [H3_RST_BUS_EHCI1] = { 0x02c0, 25 }, 697 [H3_RST_BUS_EHCI2] = { 0x02c0, 26 }, 698 [H3_RST_BUS_EHCI3] = { 0x02c0, 27 }, 699 [H3_RST_BUS_OHCI0] = { 0x02c0, 28 }, 700 [H3_RST_BUS_OHCI1] = { 0x02c0, 29 }, 701 [H3_RST_BUS_OHCI2] = { 0x02c0, 30 }, 702 [H3_RST_BUS_OHCI3] = { 0x02c0, 31 }, 703 [H3_RST_BUS_EPHY] = { 0x02c8, 2 }, 704 [H3_RST_BUS_THS] = { 0x02d0, 8 }, 705 [H3_RST_BUS_I2C0] = { 0x02d8, 0 }, 706 [H3_RST_BUS_I2C1] = { 0x02d8, 1 }, 707 [H3_RST_BUS_I2C2] = { 0x02d8, 2 }, 708 }; 709 710 #define H3_R_RST_APB0_RSB 2 711 #define H3_R_RST_APB0_I2C 5 712 713 struct sxiccmu_ccu_bit sun8i_h3_r_resets[] = { 714 [H3_R_RST_APB0_RSB] = { 0x00b0, 3 }, 715 [H3_R_RST_APB0_I2C] = { 0x00b0, 6 }, 716 }; 717 718 /* R40 */ 719 720 #define R40_RST_USB_PHY0 0 721 #define R40_RST_USB_PHY1 1 722 #define R40_RST_USB_PHY2 2 723 724 #define R40_RST_BUS_MMC0 8 725 #define R40_RST_BUS_MMC1 9 726 #define R40_RST_BUS_MMC2 10 727 #define R40_RST_BUS_MMC3 11 728 #define R40_RST_BUS_SATA 21 729 #define R40_RST_BUS_EHCI0 23 730 #define R40_RST_BUS_EHCI1 24 731 #define R40_RST_BUS_EHCI2 25 732 #define R40_RST_BUS_OHCI0 26 733 #define R40_RST_BUS_OHCI1 27 734 #define R40_RST_BUS_OHCI2 28 735 #define R40_RST_BUS_GMAC 40 736 #define R40_RST_BUS_THS 59 737 #define R40_RST_BUS_I2C0 64 738 #define R40_RST_BUS_I2C1 65 739 #define R40_RST_BUS_I2C2 66 740 #define R40_RST_BUS_I2C3 67 741 #define R40_RST_BUS_I2C4 72 742 #define R40_RST_BUS_UART0 73 743 #define R40_RST_BUS_UART1 74 744 #define R40_RST_BUS_UART2 75 745 #define R40_RST_BUS_UART3 76 746 #define R40_RST_BUS_UART4 77 747 #define R40_RST_BUS_UART5 78 748 #define R40_RST_BUS_UART6 79 749 #define R40_RST_BUS_UART7 80 750 751 struct sxiccmu_ccu_bit sun8i_r40_resets[] = { 752 [R40_RST_USB_PHY0] = { 0x00cc, 0 }, 753 [R40_RST_USB_PHY1] = { 0x00cc, 1 }, 754 [R40_RST_USB_PHY2] = { 0x00cc, 2 }, 755 [R40_RST_BUS_MMC0] = { 0x02c0, 8 }, 756 [R40_RST_BUS_MMC1] = { 0x02c0, 9 }, 757 [R40_RST_BUS_MMC2] = { 0x02c0, 10 }, 758 [R40_RST_BUS_MMC3] = { 0x02c0, 11 }, 759 [R40_RST_BUS_SATA] = { 0x02c0, 24 }, 760 [R40_RST_BUS_EHCI0] = { 0x02c0, 26 }, 761 [R40_RST_BUS_EHCI1] = { 0x02c0, 27 }, 762 [R40_RST_BUS_EHCI2] = { 0x02c0, 28 }, 763 [R40_RST_BUS_OHCI0] = { 0x02c0, 29 }, 764 [R40_RST_BUS_OHCI1] = { 0x02c0, 30 }, 765 [R40_RST_BUS_OHCI2] = { 0x02c0, 31 }, 766 [R40_RST_BUS_GMAC] = { 0x02c4, 17 }, 767 [R40_RST_BUS_THS] = { 0x02d0, 8 }, 768 [R40_RST_BUS_I2C0] = { 0x02d8, 0 }, 769 [R40_RST_BUS_I2C1] = { 0x02d8, 1 }, 770 [R40_RST_BUS_I2C2] = { 0x02d8, 2 }, 771 [R40_RST_BUS_I2C3] = { 0x02d8, 3 }, 772 [R40_RST_BUS_I2C4] = { 0x02d8, 15 }, 773 [R40_RST_BUS_UART0] = { 0x02d8, 16 }, 774 [R40_RST_BUS_UART1] = { 0x02d8, 17 }, 775 [R40_RST_BUS_UART2] = { 0x02d8, 18 }, 776 [R40_RST_BUS_UART3] = { 0x02d8, 19 }, 777 [R40_RST_BUS_UART4] = { 0x02d8, 20 }, 778 [R40_RST_BUS_UART5] = { 0x02d8, 21 }, 779 [R40_RST_BUS_UART6] = { 0x02d8, 22 }, 780 [R40_RST_BUS_UART7] = { 0x02d8, 23 }, 781 }; 782 783 /* V3s */ 784 785 #define V3S_RST_USB_PHY0 0 786 787 #define V3S_RST_BUS_MMC0 7 788 #define V3S_RST_BUS_MMC1 8 789 #define V3S_RST_BUS_MMC2 9 790 #define V3S_RST_BUS_EMAC 12 791 #define V3S_RST_BUS_EHCI0 18 792 #define V3S_RST_BUS_OHCI0 22 793 #define V3S_RST_BUS_EPHY 39 794 #define V3S_RST_BUS_I2C0 46 795 #define V3S_RST_BUS_I2C1 47 796 #define V3S_RST_BUS_UART0 49 797 #define V3S_RST_BUS_UART1 50 798 #define V3S_RST_BUS_UART2 51 799 800 struct sxiccmu_ccu_bit sun8i_v3s_resets[] = { 801 [V3S_RST_USB_PHY0] = { 0x00cc, 0 }, 802 [V3S_RST_BUS_OHCI0] = { 0x02c0, 29 }, 803 [V3S_RST_BUS_EHCI0] = { 0x02c0, 26 }, 804 [V3S_RST_BUS_EMAC] = { 0x02c0, 17 }, 805 [V3S_RST_BUS_MMC2] = { 0x02c0, 10 }, 806 [V3S_RST_BUS_MMC1] = { 0x02c0, 9 }, 807 [V3S_RST_BUS_MMC0] = { 0x02c0, 8 }, 808 [V3S_RST_BUS_EPHY] = { 0x02c8, 2 }, 809 [V3S_RST_BUS_UART2] = { 0x02d8, 18 }, 810 [V3S_RST_BUS_UART1] = { 0x02d8, 17 }, 811 [V3S_RST_BUS_UART0] = { 0x02d8, 16 }, 812 [V3S_RST_BUS_I2C1] = { 0x02d8, 1 }, 813 [V3S_RST_BUS_I2C0] = { 0x02d8, 0 }, 814 }; 815