1 /* Public Domain */ 2 3 4 /* 5 * Clocks Signals 6 */ 7 8 /* A10/A20 */ 9 10 #define A10_CLK_HOSC 1 11 #define A10_CLK_PLL_CORE 2 12 #define A10_CLK_PLL_PERIPH_BASE 14 13 #define A10_CLK_PLL_PERIPH 15 14 15 #define A10_CLK_CPU 20 16 #define A10_CLK_AXI 21 17 #define A10_CLK_AHB 23 18 #define A10_CLK_APB1 25 19 20 #define A10_CLK_AHB_EHCI0 27 21 #define A10_CLK_AHB_OHCI0 28 22 #define A10_CLK_AHB_EHCI1 29 23 #define A10_CLK_AHB_OHCI1 30 24 #define A10_CLK_AHB_MMC0 34 25 #define A10_CLK_AHB_MMC1 35 26 #define A10_CLK_AHB_MMC2 36 27 #define A10_CLK_AHB_MMC3 37 28 #define A10_CLK_AHB_EMAC 42 29 #define A10_CLK_AHB_SATA 49 30 #define A10_CLK_AHB_GMAC 66 31 #define A10_CLK_APB0_PIO 74 32 #define A10_CLK_APB1_I2C0 79 33 #define A10_CLK_APB1_I2C1 80 34 #define A10_CLK_APB1_I2C2 81 35 #define A10_CLK_APB1_I2C3 82 36 #define A10_CLK_APB1_I2C4 87 37 #define A10_CLK_APB1_UART0 88 38 #define A10_CLK_APB1_UART1 89 39 #define A10_CLK_APB1_UART2 90 40 #define A10_CLK_APB1_UART3 91 41 #define A10_CLK_APB1_UART4 92 42 #define A10_CLK_APB1_UART5 93 43 #define A10_CLK_APB1_UART6 94 44 #define A10_CLK_APB1_UART7 95 45 46 #define A10_CLK_MMC0 98 47 #define A10_CLK_MMC1 101 48 #define A10_CLK_MMC2 104 49 #define A10_CLK_MMC3 107 50 #define A10_CLK_SATA 122 51 #define A10_CLK_USB_OHCI0 123 52 #define A10_CLK_USB_OHCI1 124 53 #define A10_CLK_USB_PHY 125 54 55 #define A10_CLK_LOSC 254 56 57 struct sxiccmu_ccu_bit sun4i_a10_gates[] = { 58 [A10_CLK_AHB_EHCI0] = { 0x0060, 1 }, 59 [A10_CLK_AHB_OHCI0] = { 0x0060, 2 }, 60 [A10_CLK_AHB_EHCI1] = { 0x0060, 3 }, 61 [A10_CLK_AHB_OHCI1] = { 0x0060, 4 }, 62 [A10_CLK_AHB_MMC0] = { 0x0060, 8 }, 63 [A10_CLK_AHB_MMC1] = { 0x0060, 9 }, 64 [A10_CLK_AHB_MMC2] = { 0x0060, 10 }, 65 [A10_CLK_AHB_MMC3] = { 0x0060, 11 }, 66 [A10_CLK_AHB_EMAC] = { 0x0060, 17 }, 67 [A10_CLK_AHB_SATA] = { 0x0060, 25 }, 68 [A10_CLK_AHB_GMAC] = { 0x0064, 17, A10_CLK_AHB }, 69 [A10_CLK_APB0_PIO] = { 0x0068, 5 }, 70 [A10_CLK_APB1_I2C0] = { 0x006c, 0, A10_CLK_APB1 }, 71 [A10_CLK_APB1_I2C1] = { 0x006c, 1, A10_CLK_APB1 }, 72 [A10_CLK_APB1_I2C2] = { 0x006c, 2, A10_CLK_APB1 }, 73 [A10_CLK_APB1_I2C3] = { 0x006c, 3, A10_CLK_APB1 }, 74 [A10_CLK_APB1_I2C4] = { 0x006c, 15, A10_CLK_APB1 }, 75 [A10_CLK_APB1_UART0] = { 0x006c, 16, A10_CLK_APB1 }, 76 [A10_CLK_APB1_UART1] = { 0x006c, 17, A10_CLK_APB1 }, 77 [A10_CLK_APB1_UART2] = { 0x006c, 18, A10_CLK_APB1 }, 78 [A10_CLK_APB1_UART3] = { 0x006c, 19, A10_CLK_APB1 }, 79 [A10_CLK_APB1_UART4] = { 0x006c, 20, A10_CLK_APB1 }, 80 [A10_CLK_APB1_UART5] = { 0x006c, 21, A10_CLK_APB1 }, 81 [A10_CLK_APB1_UART6] = { 0x006c, 22, A10_CLK_APB1 }, 82 [A10_CLK_APB1_UART7] = { 0x006c, 23, A10_CLK_APB1 }, 83 [A10_CLK_MMC0] = { 0x0088, 31 }, 84 [A10_CLK_MMC1] = { 0x008c, 31 }, 85 [A10_CLK_MMC2] = { 0x0090, 31 }, 86 [A10_CLK_MMC3] = { 0x0094, 31 }, 87 [A10_CLK_SATA] = { 0x00c8, 31 }, 88 [A10_CLK_USB_OHCI0] = { 0x00cc, 6 }, 89 [A10_CLK_USB_OHCI1] = { 0x00cc, 7 }, 90 [A10_CLK_USB_PHY] = { 0x00cc, 8 }, 91 }; 92 93 /* A23/A33 */ 94 95 #define A23_CLK_PLL_PERIPH 10 96 97 #define A23_CLK_AXI 19 98 #define A23_CLK_AHB1 20 99 #define A23_CLK_APB1 21 100 #define A23_CLK_APB2 22 101 102 #define A23_CLK_BUS_MMC0 26 103 #define A23_CLK_BUS_MMC1 27 104 #define A23_CLK_BUS_MMC2 28 105 #define A23_CLK_BUS_EHCI 35 106 #define A23_CLK_BUS_OHCI 36 107 #define A23_CLK_BUS_PIO 48 108 #define A23_CLK_BUS_I2C0 51 109 #define A23_CLK_BUS_I2C1 52 110 #define A23_CLK_BUS_I2C2 53 111 #define A23_CLK_BUS_UART0 54 112 #define A23_CLK_BUS_UART1 55 113 #define A23_CLK_BUS_UART2 56 114 #define A23_CLK_BUS_UART3 57 115 #define A23_CLK_BUS_UART4 58 116 117 #define A23_CLK_MMC0 60 118 #define A23_CLK_MMC1 63 119 #define A23_CLK_MMC2 66 120 #define A23_CLK_USB_OHCI 78 121 122 struct sxiccmu_ccu_bit sun8i_a23_gates[] = { 123 [A23_CLK_BUS_MMC0] = { 0x0060, 8 }, 124 [A23_CLK_BUS_MMC1] = { 0x0060, 9 }, 125 [A23_CLK_BUS_MMC2] = { 0x0060, 10 }, 126 [A23_CLK_BUS_EHCI] = { 0x0060, 26 }, 127 [A23_CLK_BUS_OHCI] = { 0x0060, 29 }, 128 [A23_CLK_BUS_PIO] = { 0x0068, 5 }, 129 [A23_CLK_BUS_I2C0] = { 0x006c, 0, A23_CLK_APB2 }, 130 [A23_CLK_BUS_I2C1] = { 0x006c, 1, A23_CLK_APB2 }, 131 [A23_CLK_BUS_I2C2] = { 0x006c, 2, A23_CLK_APB2 }, 132 [A23_CLK_BUS_UART0] = { 0x006c, 16, A23_CLK_APB2 }, 133 [A23_CLK_BUS_UART1] = { 0x006c, 17, A23_CLK_APB2 }, 134 [A23_CLK_BUS_UART2] = { 0x006c, 18, A23_CLK_APB2 }, 135 [A23_CLK_BUS_UART3] = { 0x006c, 19, A23_CLK_APB2 }, 136 [A23_CLK_BUS_UART4] = { 0x006c, 20, A23_CLK_APB2 }, 137 [A23_CLK_MMC0] = { 0x0088, 31 }, 138 [A23_CLK_MMC1] = { 0x008c, 31 }, 139 [A23_CLK_MMC2] = { 0x0090, 31 }, 140 [A23_CLK_USB_OHCI] = { 0x00cc, 16 }, 141 }; 142 143 /* A64 */ 144 145 #define A64_CLK_PLL_CPUX 1 146 147 #define A64_CLK_PLL_PERIPH0 11 148 #define A64_CLK_PLL_PERIPH0_2X 12 149 150 #define A64_CLK_CPUX 21 151 #define A64_CLK_AXI 22 152 #define A64_CLK_APB 23 153 #define A64_CLK_AHB1 24 154 #define A64_CLK_APB1 25 155 #define A64_CLK_APB2 26 156 #define A64_CLK_AHB2 27 157 158 #define A64_CLK_BUS_MMC0 31 159 #define A64_CLK_BUS_MMC1 32 160 #define A64_CLK_BUS_MMC2 33 161 #define A64_CLK_BUS_EMAC 36 162 #define A64_CLK_BUS_EHCI0 42 163 #define A64_CLK_BUS_EHCI1 43 164 #define A64_CLK_BUS_OHCI0 44 165 #define A64_CLK_BUS_OHCI1 45 166 #define A64_CLK_BUS_PIO 58 167 #define A64_CLK_BUS_THS 59 168 #define A64_CLK_BUS_I2C0 63 169 #define A64_CLK_BUS_I2C1 64 170 #define A64_CLK_BUS_I2C2 65 171 #define A64_CLK_BUS_UART0 67 172 #define A64_CLK_BUS_UART1 68 173 #define A64_CLK_BUS_UART2 69 174 #define A64_CLK_BUS_UART3 70 175 #define A64_CLK_BUS_UART4 71 176 177 #define A64_CLK_THS 73 178 #define A64_CLK_MMC0 75 179 #define A64_CLK_MMC1 76 180 #define A64_CLK_MMC2 77 181 #define A64_CLK_USB_OHCI0 91 182 #define A64_CLK_USB_OHCI1 93 183 #define A64_CLK_USB_PHY0 86 184 #define A64_CLK_USB_PHY1 87 185 186 #define A64_CLK_LOSC 254 187 #define A64_CLK_HOSC 253 188 189 struct sxiccmu_ccu_bit sun50i_a64_gates[] = { 190 [A64_CLK_PLL_PERIPH0] = { 0x0028, 31 }, 191 [A64_CLK_BUS_MMC0] = { 0x0060, 8 }, 192 [A64_CLK_BUS_MMC1] = { 0x0060, 9 }, 193 [A64_CLK_BUS_MMC2] = { 0x0060, 10 }, 194 [A64_CLK_BUS_EMAC] = { 0x0060, 17, A64_CLK_AHB2 }, 195 [A64_CLK_BUS_EHCI0] = { 0x0060, 24 }, 196 [A64_CLK_BUS_EHCI1] = { 0x0060, 25 }, 197 [A64_CLK_BUS_OHCI0] = { 0x0060, 28 }, 198 [A64_CLK_BUS_OHCI1] = { 0x0060, 29 }, 199 [A64_CLK_BUS_PIO] = { 0x0068, 5 }, 200 [A64_CLK_BUS_THS] = { 0x0068, 8 }, 201 [A64_CLK_BUS_I2C0] = { 0x006c, 0, A64_CLK_APB2 }, 202 [A64_CLK_BUS_I2C1] = { 0x006c, 1, A64_CLK_APB2 }, 203 [A64_CLK_BUS_I2C2] = { 0x006c, 2, A64_CLK_APB2 }, 204 [A64_CLK_BUS_UART0] = { 0x006c, 16, A64_CLK_APB2 }, 205 [A64_CLK_BUS_UART1] = { 0x006c, 17, A64_CLK_APB2 }, 206 [A64_CLK_BUS_UART2] = { 0x006c, 18, A64_CLK_APB2 }, 207 [A64_CLK_BUS_UART3] = { 0x006c, 19, A64_CLK_APB2 }, 208 [A64_CLK_BUS_UART4] = { 0x006c, 20, A64_CLK_APB2 }, 209 [A64_CLK_THS] = { 0x0074, 31 }, 210 [A64_CLK_MMC0] = { 0x0088, 31 }, 211 [A64_CLK_MMC1] = { 0x008c, 31 }, 212 [A64_CLK_MMC2] = { 0x0090, 31 }, 213 [A64_CLK_USB_OHCI0] = { 0x00cc, 16 }, 214 [A64_CLK_USB_OHCI1] = { 0x00cc, 17 }, 215 [A64_CLK_USB_PHY0] = { 0x00cc, 8 }, 216 [A64_CLK_USB_PHY1] = { 0x00cc, 9 }, 217 }; 218 219 /* A80 */ 220 221 #define A80_CLK_PLL_PERIPH0 3 222 223 #define A80_CLK_APB1 23 224 225 #define A80_CLK_MMC0 33 226 #define A80_CLK_MMC1 36 227 #define A80_CLK_MMC2 39 228 #define A80_CLK_MMC3 42 229 230 #define A80_CLK_BUS_MMC 84 231 #define A80_CLK_BUS_USB 96 232 #define A80_CLK_BUS_PIO 111 233 #define A80_CLK_BUS_UART0 124 234 #define A80_CLK_BUS_UART1 125 235 #define A80_CLK_BUS_UART2 126 236 #define A80_CLK_BUS_UART3 127 237 #define A80_CLK_BUS_UART4 128 238 #define A80_CLK_BUS_UART5 129 239 240 struct sxiccmu_ccu_bit sun9i_a80_gates[] = { 241 [A80_CLK_MMC0] = { 0x0410, 31 }, 242 [A80_CLK_MMC1] = { 0x0414, 31 }, 243 [A80_CLK_MMC2] = { 0x0418, 31 }, 244 [A80_CLK_MMC3] = { 0x041c, 31 }, /* Undocumented */ 245 [A80_CLK_BUS_MMC] = { 0x0580, 8 }, 246 [A80_CLK_BUS_USB] = { 0x0584, 1 }, 247 [A80_CLK_BUS_PIO] = { 0x0590, 5 }, 248 [A80_CLK_BUS_UART0] = { 0x0594, 16, A80_CLK_APB1 }, 249 [A80_CLK_BUS_UART1] = { 0x0594, 17, A80_CLK_APB1 }, 250 [A80_CLK_BUS_UART2] = { 0x0594, 18, A80_CLK_APB1 }, 251 [A80_CLK_BUS_UART3] = { 0x0594, 19, A80_CLK_APB1 }, 252 [A80_CLK_BUS_UART4] = { 0x0594, 20, A80_CLK_APB1 }, 253 [A80_CLK_BUS_UART5] = { 0x0594, 21, A80_CLK_APB1 }, 254 }; 255 256 #define A80_USB_CLK_HCI0 0 257 #define A80_USB_CLK_OHCI0 1 258 #define A80_USB_CLK_HCI1 2 259 #define A80_USB_CLK_HCI2 3 260 #define A80_USB_CLK_OHCI2 4 261 262 #define A80_USB_CLK_HCI0_PHY 5 263 #define A80_USB_CLK_HCI1_HSIC 6 264 #define A80_USB_CLK_HCI1_PHY 7 265 #define A80_USB_CLK_HCI2_HSIC 8 266 #define A80_USB_CLK_HCI2_UTMIPHY 9 267 #define A80_USB_CLK_HCI1_HSIC_12M 10 268 269 struct sxiccmu_ccu_bit sun9i_a80_usb_gates[] = { 270 [A80_USB_CLK_HCI0] = { 0x0000, 1 }, 271 [A80_USB_CLK_OHCI0] = { 0x0000, 2 }, 272 [A80_USB_CLK_HCI1] = { 0x0000, 3 }, 273 [A80_USB_CLK_HCI2] = { 0x0000, 5 }, 274 [A80_USB_CLK_OHCI2] = { 0x0000, 6 }, 275 [A80_USB_CLK_HCI0_PHY] = { 0x0004, 1 }, 276 [A80_USB_CLK_HCI1_HSIC] = { 0x0004, 2 }, 277 [A80_USB_CLK_HCI1_PHY] = { 0x0004, 3 }, /* Undocumented */ 278 [A80_USB_CLK_HCI2_HSIC] = { 0x0004, 4 }, 279 [A80_USB_CLK_HCI2_UTMIPHY] = { 0x0004, 5 }, 280 [A80_USB_CLK_HCI1_HSIC_12M] = { 0x0004, 10 }, 281 }; 282 283 struct sxiccmu_ccu_bit sun9i_a80_mmc_gates[] = { 284 { 0x0000, 16 }, 285 { 0x0004, 16 }, 286 { 0x0008, 16 }, 287 { 0x000c, 16 }, 288 }; 289 290 /* H3/H5 */ 291 292 #define H3_CLK_PLL_CPUX 0 293 #define H3_CLK_PLL_PERIPH0 9 294 295 #define H3_CLK_CPUX 14 296 #define H3_CLK_AXI 15 297 #define H3_CLK_AHB1 16 298 #define H3_CLK_APB1 17 299 #define H3_CLK_APB2 18 300 #define H3_CLK_AHB2 19 301 302 #define H3_CLK_BUS_MMC0 22 303 #define H3_CLK_BUS_MMC1 23 304 #define H3_CLK_BUS_MMC2 24 305 #define H3_CLK_BUS_EMAC 27 306 #define H3_CLK_BUS_EHCI0 33 307 #define H3_CLK_BUS_EHCI1 34 308 #define H3_CLK_BUS_EHCI2 35 309 #define H3_CLK_BUS_EHCI3 36 310 #define H3_CLK_BUS_OHCI0 37 311 #define H3_CLK_BUS_OHCI1 38 312 #define H3_CLK_BUS_OHCI2 39 313 #define H3_CLK_BUS_OHCI3 40 314 #define H3_CLK_BUS_PIO 54 315 #define H3_CLK_BUS_THS 55 316 #define H3_CLK_BUS_I2C0 59 317 #define H3_CLK_BUS_I2C1 60 318 #define H3_CLK_BUS_I2C2 61 319 #define H3_CLK_BUS_UART0 62 320 #define H3_CLK_BUS_UART1 63 321 #define H3_CLK_BUS_UART2 64 322 #define H3_CLK_BUS_UART3 65 323 #define H3_CLK_BUS_EPHY 67 324 325 #define H3_CLK_THS 69 326 #define H3_CLK_MMC0 71 327 #define H3_CLK_MMC1 74 328 #define H3_CLK_MMC2 77 329 #define H3_CLK_USB_PHY0 88 330 #define H3_CLK_USB_PHY1 89 331 #define H3_CLK_USB_PHY2 90 332 #define H3_CLK_USB_PHY3 91 333 #define H3_CLK_USB_OHCI0 92 334 #define H3_CLK_USB_OHCI1 93 335 #define H3_CLK_USB_OHCI2 94 336 #define H3_CLK_USB_OHCI3 95 337 338 #define H3_CLK_LOSC 254 339 #define H3_CLK_HOSC 253 340 341 struct sxiccmu_ccu_bit sun8i_h3_gates[] = { 342 [H3_CLK_PLL_PERIPH0] = { 0x0028, 31 }, 343 [H3_CLK_BUS_MMC0] = { 0x0060, 8 }, 344 [H3_CLK_BUS_MMC1] = { 0x0060, 9 }, 345 [H3_CLK_BUS_MMC2] = { 0x0060, 10 }, 346 [H3_CLK_BUS_EMAC] = { 0x0060, 17, H3_CLK_AHB2 }, 347 [H3_CLK_BUS_EHCI0] = { 0x0060, 24 }, 348 [H3_CLK_BUS_EHCI1] = { 0x0060, 25 }, 349 [H3_CLK_BUS_EHCI2] = { 0x0060, 26 }, 350 [H3_CLK_BUS_EHCI3] = { 0x0060, 27 }, 351 [H3_CLK_BUS_OHCI0] = { 0x0060, 28 }, 352 [H3_CLK_BUS_OHCI1] = { 0x0060, 29 }, 353 [H3_CLK_BUS_OHCI2] = { 0x0060, 30 }, 354 [H3_CLK_BUS_OHCI3] = { 0x0060, 31 }, 355 [H3_CLK_BUS_PIO] = { 0x0068, 5 }, 356 [H3_CLK_BUS_THS] = { 0x0068, 8 }, 357 [H3_CLK_BUS_I2C0] = { 0x006c, 0, H3_CLK_APB2 }, 358 [H3_CLK_BUS_I2C1] = { 0x006c, 1, H3_CLK_APB2 }, 359 [H3_CLK_BUS_I2C2] = { 0x006c, 2, H3_CLK_APB2 }, 360 [H3_CLK_BUS_UART0] = { 0x006c, 16, H3_CLK_APB2 }, 361 [H3_CLK_BUS_UART1] = { 0x006c, 17, H3_CLK_APB2 }, 362 [H3_CLK_BUS_UART2] = { 0x006c, 18, H3_CLK_APB2 }, 363 [H3_CLK_BUS_UART3] = { 0x006c, 19, H3_CLK_APB2 }, 364 [H3_CLK_BUS_EPHY] = { 0x0070, 0 }, 365 [H3_CLK_THS] = { 0x0074, 31 }, 366 [H3_CLK_MMC0] = { 0x0088, 31 }, 367 [H3_CLK_MMC1] = { 0x008c, 31 }, 368 [H3_CLK_MMC2] = { 0x0090, 31 }, 369 [H3_CLK_USB_PHY0] = { 0x00cc, 8 }, 370 [H3_CLK_USB_PHY1] = { 0x00cc, 9 }, 371 [H3_CLK_USB_PHY2] = { 0x00cc, 10 }, 372 [H3_CLK_USB_PHY3] = { 0x00cc, 11 }, 373 [H3_CLK_USB_OHCI0] = { 0x00cc, 16 }, 374 [H3_CLK_USB_OHCI1] = { 0x00cc, 17 }, 375 [H3_CLK_USB_OHCI2] = { 0x00cc, 18 }, 376 [H3_CLK_USB_OHCI3] = { 0x00cc, 19 }, 377 }; 378 379 #define H3_R_CLK_AHB0 1 380 #define H3_R_CLK_APB0 2 381 382 #define H3_R_CLK_APB0_PIO 3 383 #define H3_R_CLK_APB0_RSB 6 384 #define H3_R_CLK_APB0_I2C 9 385 386 struct sxiccmu_ccu_bit sun8i_h3_r_gates[] = { 387 [H3_R_CLK_APB0_PIO] = { 0x0028, 0 }, 388 [H3_R_CLK_APB0_RSB] = { 0x0028, 3, H3_R_CLK_APB0 }, 389 [H3_R_CLK_APB0_I2C] = { 0x0028, 6, H3_R_CLK_APB0 }, 390 }; 391 392 /* H6 */ 393 394 #define H6_CLK_PLL_PERIPH0 3 395 #define H6_CLK_PLL_PERIPH0_2X 4 396 #define H6_CLK_APB1 26 397 #define H6_CLK_APB2 27 398 #define H6_CLK_MMC0 64 399 #define H6_CLK_MMC1 65 400 #define H6_CLK_MMC2 66 401 #define H6_CLK_BUS_MMC0 67 402 #define H6_CLK_BUS_MMC1 68 403 #define H6_CLK_BUS_MMC2 69 404 #define H6_CLK_BUS_UART0 70 405 #define H6_CLK_BUS_UART1 71 406 #define H6_CLK_BUS_UART2 72 407 #define H6_CLK_BUS_UART3 73 408 #define H6_CLK_USB_OHCI0 104 409 #define H6_CLK_USB_OHCI3 107 410 #define H6_CLK_BUS_OHCI0 111 411 #define H6_CLK_BUS_OHCI3 112 412 #define H6_CLK_BUS_EHCI0 113 413 #define H6_CLK_BUS_EHCI3 115 414 415 struct sxiccmu_ccu_bit sun50i_h6_gates[] = { 416 [H6_CLK_PLL_PERIPH0] = { 0x0020, 31 }, 417 [H6_CLK_APB1] = { 0xffff, 0xff }, 418 [H6_CLK_MMC0] = { 0x0830, 31 }, 419 [H6_CLK_MMC1] = { 0x0834, 31 }, 420 [H6_CLK_MMC2] = { 0x0838, 31 }, 421 [H6_CLK_BUS_MMC0] = { 0x084c, 0 }, 422 [H6_CLK_BUS_MMC1] = { 0x084c, 1 }, 423 [H6_CLK_BUS_MMC2] = { 0x084c, 2 }, 424 [H6_CLK_BUS_UART0] = { 0x090c, 0, H6_CLK_APB2 }, 425 [H6_CLK_BUS_UART1] = { 0x090c, 1, H6_CLK_APB2 }, 426 [H6_CLK_BUS_UART2] = { 0x090c, 2, H6_CLK_APB2 }, 427 [H6_CLK_BUS_UART3] = { 0x090c, 3, H6_CLK_APB2 }, 428 [H6_CLK_USB_OHCI0] = { 0x0a70, 31 }, 429 [H6_CLK_USB_OHCI3] = { 0x0a7c, 31 }, 430 [H6_CLK_BUS_OHCI0] = { 0x0a8c, 0 }, 431 [H6_CLK_BUS_OHCI3] = { 0x0a8c, 3 }, 432 [H6_CLK_BUS_EHCI0] = { 0x0a8c, 4 }, 433 [H6_CLK_BUS_EHCI3] = { 0x0a8c, 7 }, 434 }; 435 436 #define H6_R_CLK_APB1 2 437 #define H6_R_CLK_APB2 3 438 #define H6_R_CLK_APB2_I2C 8 439 440 struct sxiccmu_ccu_bit sun50i_h6_r_gates[] = { 441 [H6_R_CLK_APB1] = { 0xffff, 0xff }, 442 [H6_R_CLK_APB2_I2C] = { 0x019c, 1, H6_R_CLK_APB2 }, 443 }; 444 445 /* R40 */ 446 447 #define R40_CLK_PLL_PERIPH0 11 448 #define R40_CLK_PLL_PERIPH0_2X 13 449 450 #define R40_CLK_AXI 25 451 #define R40_CLK_AHB1 26 452 #define R40_CLK_APB2 28 453 454 #define R40_CLK_BUS_MMC0 32 455 #define R40_CLK_BUS_MMC1 33 456 #define R40_CLK_BUS_MMC2 34 457 #define R40_CLK_BUS_MMC3 35 458 #define R40_CLK_BUS_SATA 45 459 #define R40_CLK_BUS_EHCI0 47 460 #define R40_CLK_BUS_EHCI1 48 461 #define R40_CLK_BUS_EHCI2 49 462 #define R40_CLK_BUS_OHCI0 50 463 #define R40_CLK_BUS_OHCI1 51 464 #define R40_CLK_BUS_OHCI2 52 465 #define R40_CLK_BUS_GMAC 64 466 #define R40_CLK_BUS_PIO 79 467 #define R40_CLK_BUS_THS 82 468 #define R40_CLK_BUS_I2C0 87 469 #define R40_CLK_BUS_I2C1 88 470 #define R40_CLK_BUS_I2C2 89 471 #define R40_CLK_BUS_I2C3 90 472 #define R40_CLK_BUS_I2C4 95 473 #define R40_CLK_BUS_UART0 96 474 #define R40_CLK_BUS_UART1 97 475 #define R40_CLK_BUS_UART2 98 476 #define R40_CLK_BUS_UART3 99 477 #define R40_CLK_BUS_UART4 100 478 #define R40_CLK_BUS_UART5 101 479 #define R40_CLK_BUS_UART6 102 480 #define R40_CLK_BUS_UART7 103 481 482 #define R40_CLK_THS 105 483 #define R40_CLK_MMC0 107 484 #define R40_CLK_MMC1 108 485 #define R40_CLK_MMC2 109 486 #define R40_CLK_MMC3 110 487 #define R40_CLK_SATA 123 488 #define R40_CLK_USB_PHY0 124 489 #define R40_CLK_USB_PHY1 125 490 #define R40_CLK_USB_PHY2 126 491 #define R40_CLK_USB_OHCI0 127 492 #define R40_CLK_USB_OHCI1 128 493 #define R40_CLK_USB_OHCI2 129 494 495 #define R40_CLK_HOSC 253 496 #define R40_CLK_LOSC 254 497 498 struct sxiccmu_ccu_bit sun8i_r40_gates[] = { 499 [R40_CLK_BUS_MMC0] = { 0x0060, 8 }, 500 [R40_CLK_BUS_MMC1] = { 0x0060, 9 }, 501 [R40_CLK_BUS_MMC2] = { 0x0060, 10 }, 502 [R40_CLK_BUS_MMC3] = { 0x0060, 11 }, 503 [R40_CLK_BUS_SATA] = { 0x0060, 24 }, 504 [R40_CLK_BUS_EHCI0] = { 0x0060, 26 }, 505 [R40_CLK_BUS_EHCI1] = { 0x0060, 27 }, 506 [R40_CLK_BUS_EHCI2] = { 0x0060, 28 }, 507 [R40_CLK_BUS_OHCI0] = { 0x0060, 29 }, 508 [R40_CLK_BUS_OHCI1] = { 0x0060, 30 }, 509 [R40_CLK_BUS_OHCI2] = { 0x0060, 31 }, 510 [R40_CLK_BUS_GMAC] = { 0x0064, 17, R40_CLK_AHB1 }, 511 [R40_CLK_BUS_PIO] = { 0x0068, 5 }, 512 [R40_CLK_BUS_THS] = { 0x0068, 8 }, 513 [R40_CLK_BUS_I2C0] = { 0x006c, 0, R40_CLK_APB2 }, 514 [R40_CLK_BUS_I2C1] = { 0x006c, 1, R40_CLK_APB2 }, 515 [R40_CLK_BUS_I2C2] = { 0x006c, 2, R40_CLK_APB2 }, 516 [R40_CLK_BUS_I2C3] = { 0x006c, 3, R40_CLK_APB2 }, 517 [R40_CLK_BUS_I2C4] = { 0x006c, 15, R40_CLK_APB2 }, 518 [R40_CLK_BUS_UART0] = { 0x006c, 16, R40_CLK_APB2 }, 519 [R40_CLK_BUS_UART1] = { 0x006c, 17, R40_CLK_APB2 }, 520 [R40_CLK_BUS_UART2] = { 0x006c, 18, R40_CLK_APB2 }, 521 [R40_CLK_BUS_UART3] = { 0x006c, 19, R40_CLK_APB2 }, 522 [R40_CLK_BUS_UART4] = { 0x006c, 20, R40_CLK_APB2 }, 523 [R40_CLK_BUS_UART5] = { 0x006c, 21, R40_CLK_APB2 }, 524 [R40_CLK_BUS_UART6] = { 0x006c, 22, R40_CLK_APB2 }, 525 [R40_CLK_BUS_UART7] = { 0x006c, 23, R40_CLK_APB2 }, 526 [R40_CLK_THS] = { 0x0074, 31 }, 527 [R40_CLK_MMC0] = { 0x0088, 31 }, 528 [R40_CLK_MMC1] = { 0x008c, 31 }, 529 [R40_CLK_MMC2] = { 0x0090, 31 }, 530 [R40_CLK_MMC3] = { 0x0094, 31 }, 531 [R40_CLK_SATA] = { 0x00c8, 31 }, 532 [R40_CLK_USB_PHY0] = { 0x00cc, 8 }, 533 [R40_CLK_USB_PHY1] = { 0x00cc, 9 }, 534 [R40_CLK_USB_PHY2] = { 0x00cc, 10 }, 535 [R40_CLK_USB_OHCI0] = { 0x00cc, 16 }, 536 [R40_CLK_USB_OHCI1] = { 0x00cc, 17 }, 537 [R40_CLK_USB_OHCI2] = { 0x00cc, 18 }, 538 }; 539 540 /* V3s */ 541 542 #define V3S_CLK_PLL_PERIPH0 9 543 #define V3S_CLK_AXI 15 544 #define V3S_CLK_AHB1 16 545 #define V3S_CLK_APB2 18 546 #define V3S_CLK_AHB2 19 547 548 #define V3S_CLK_BUS_MMC0 22 549 #define V3S_CLK_BUS_MMC1 23 550 #define V3S_CLK_BUS_MMC2 24 551 #define V3S_CLK_BUS_EMAC 26 552 #define V3S_CLK_BUS_EHCI0 30 553 #define V3S_CLK_BUS_OHCI0 31 554 #define V3S_CLK_BUS_PIO 37 555 #define V3S_CLK_BUS_I2C0 38 556 #define V3S_CLK_BUS_I2C1 39 557 #define V3S_CLK_BUS_UART0 40 558 #define V3S_CLK_BUS_UART1 41 559 #define V3S_CLK_BUS_UART2 42 560 #define V3S_CLK_BUS_EPHY 43 561 562 #define V3S_CLK_MMC0 45 563 #define V3S_CLK_MMC1 48 564 #define V3S_CLK_MMC2 51 565 #define V3S_CLK_USB_PHY0 56 566 #define V3S_CLK_USB_OHCI0 57 567 568 #define V3S_CLK_LOSC 254 569 #define V3S_CLK_HOSC 253 570 571 struct sxiccmu_ccu_bit sun8i_v3s_gates[] = { 572 [V3S_CLK_BUS_OHCI0] = { 0x0060, 29 }, 573 [V3S_CLK_BUS_EHCI0] = { 0x0060, 26 }, 574 [V3S_CLK_BUS_EMAC] = { 0x0060, 17, V3S_CLK_AHB2 }, 575 [V3S_CLK_BUS_MMC2] = { 0x0060, 10 }, 576 [V3S_CLK_BUS_MMC1] = { 0x0060, 9 }, 577 [V3S_CLK_BUS_MMC0] = { 0x0060, 8 }, 578 [V3S_CLK_BUS_PIO] = { 0x0068, 5 }, 579 [V3S_CLK_BUS_UART2] = { 0x006c, 18, V3S_CLK_APB2 }, 580 [V3S_CLK_BUS_UART1] = { 0x006c, 17, V3S_CLK_APB2 }, 581 [V3S_CLK_BUS_UART0] = { 0x006c, 16, V3S_CLK_APB2 }, 582 [V3S_CLK_BUS_I2C1] = { 0x006c, 1, V3S_CLK_APB2 }, 583 [V3S_CLK_BUS_I2C0] = { 0x006c, 0, V3S_CLK_APB2 }, 584 [V3S_CLK_BUS_EPHY] = { 0x0070, 0 }, 585 [V3S_CLK_MMC0] = { 0x0088, 31 }, 586 [V3S_CLK_MMC1] = { 0x008c, 31 }, 587 [V3S_CLK_MMC2] = { 0x0090, 31 }, 588 [V3S_CLK_USB_OHCI0] = { 0x00cc, 16 }, 589 [V3S_CLK_USB_PHY0] = { 0x00cc, 8 }, 590 }; 591 592 /* 593 * Reset Signals 594 */ 595 596 /* A10 */ 597 598 #define A10_RST_USB_PHY0 1 599 #define A10_RST_USB_PHY1 2 600 #define A10_RST_USB_PHY2 3 601 602 struct sxiccmu_ccu_bit sun4i_a10_resets[] = { 603 [A10_RST_USB_PHY0] = { 0x00cc, 0 }, 604 [A10_RST_USB_PHY1] = { 0x00cc, 1 }, 605 [A10_RST_USB_PHY2] = { 0x00cc, 2 }, 606 }; 607 608 /* A23/A33 */ 609 610 #define A23_RST_USB_PHY0 0 611 #define A23_RST_USB_PHY1 1 612 613 #define A23_RST_BUS_MMC0 7 614 #define A23_RST_BUS_MMC1 8 615 #define A23_RST_BUS_MMC2 9 616 617 #define A23_RST_BUS_EHCI 16 618 #define A23_RST_BUS_OHCI 17 619 620 #define A23_RST_BUS_I2C0 32 621 #define A23_RST_BUS_I2C1 33 622 #define A23_RST_BUS_I2C2 34 623 624 #define A23_CLK_HOSC 253 625 #define A23_CLK_LOSC 254 626 627 struct sxiccmu_ccu_bit sun8i_a23_resets[] = { 628 [A23_RST_USB_PHY0] = { 0x00cc, 0 }, 629 [A23_RST_USB_PHY1] = { 0x00cc, 1 }, 630 [A23_RST_BUS_MMC0] = { 0x02c0, 8 }, 631 [A23_RST_BUS_MMC1] = { 0x02c0, 9 }, 632 [A23_RST_BUS_MMC2] = { 0x02c0, 10 }, 633 [A23_RST_BUS_EHCI] = { 0x02c0, 26 }, 634 [A23_RST_BUS_OHCI] = { 0x02c0, 29 }, 635 [A23_RST_BUS_I2C0] = { 0x02d8, 0 }, 636 [A23_RST_BUS_I2C1] = { 0x02d8, 1 }, 637 [A23_RST_BUS_I2C2] = { 0x02d8, 2 }, 638 }; 639 640 /* A64 */ 641 642 #define A64_RST_USB_PHY0 0 643 #define A64_RST_USB_PHY1 1 644 645 #define A64_RST_BUS_MMC0 8 646 #define A64_RST_BUS_MMC1 9 647 #define A64_RST_BUS_MMC2 10 648 #define A64_RST_BUS_EMAC 13 649 #define A64_RST_BUS_EHCI0 19 650 #define A64_RST_BUS_EHCI1 20 651 #define A64_RST_BUS_OHCI0 21 652 #define A64_RST_BUS_OHCI1 22 653 #define A64_RST_BUS_THS 38 654 #define A64_RST_BUS_I2C0 42 655 #define A64_RST_BUS_I2C1 43 656 #define A64_RST_BUS_I2C2 44 657 658 struct sxiccmu_ccu_bit sun50i_a64_resets[] = { 659 [A64_RST_USB_PHY0] = { 0x00cc, 0 }, 660 [A64_RST_USB_PHY1] = { 0x00cc, 1 }, 661 [A64_RST_BUS_MMC0] = { 0x02c0, 8 }, 662 [A64_RST_BUS_MMC1] = { 0x02c0, 9 }, 663 [A64_RST_BUS_MMC2] = { 0x02c0, 10 }, 664 [A64_RST_BUS_EMAC] = { 0x02c0, 17 }, 665 [A64_RST_BUS_EHCI0] = { 0x02c0, 24 }, 666 [A64_RST_BUS_EHCI1] = { 0x02c0, 25 }, 667 [A64_RST_BUS_OHCI0] = { 0x02c0, 28 }, 668 [A64_RST_BUS_OHCI1] = { 0x02c0, 29 }, 669 [A64_RST_BUS_THS] = { 0x02d0, 8 }, 670 [A64_RST_BUS_I2C0] = { 0x02d8, 0 }, 671 [A64_RST_BUS_I2C1] = { 0x02d8, 1 }, 672 [A64_RST_BUS_I2C2] = { 0x02d8, 2 }, 673 }; 674 675 /* A80 */ 676 677 #define A80_RST_BUS_MMC 4 678 #define A80_RST_BUS_UART0 45 679 #define A80_RST_BUS_UART1 46 680 #define A80_RST_BUS_UART2 47 681 #define A80_RST_BUS_UART3 48 682 #define A80_RST_BUS_UART4 49 683 #define A80_RST_BUS_UART5 50 684 685 struct sxiccmu_ccu_bit sun9i_a80_resets[] = { 686 [A80_RST_BUS_MMC] = { 0x05a0, 8 }, 687 [A80_RST_BUS_UART0] = { 0x05b4, 16 }, 688 [A80_RST_BUS_UART1] = { 0x05b4, 17 }, 689 [A80_RST_BUS_UART2] = { 0x05b4, 18 }, 690 [A80_RST_BUS_UART3] = { 0x05b4, 19 }, 691 [A80_RST_BUS_UART4] = { 0x05b4, 20 }, 692 [A80_RST_BUS_UART5] = { 0x05b4, 21 }, 693 }; 694 695 #define A80_USB_RST_HCI0 0 696 #define A80_USB_RST_HCI1 1 697 #define A80_USB_RST_HCI2 2 698 699 #define A80_USB_RST_HCI0_PHY 3 700 #define A80_USB_RST_HCI1_HSIC 4 701 #define A80_USB_RST_HCI1_PHY 5 702 #define A80_USB_RST_HCI2_HSIC 6 703 #define A80_USB_RST_HCI2_UTMIPHY 7 704 705 struct sxiccmu_ccu_bit sun9i_a80_usb_resets[] = { 706 [A80_USB_RST_HCI0] = { 0x0000, 17 }, 707 [A80_USB_RST_HCI1] = { 0x0000, 18 }, 708 [A80_USB_RST_HCI2] = { 0x0000, 19 }, 709 [A80_USB_RST_HCI0_PHY] = { 0x0004, 17 }, 710 [A80_USB_RST_HCI1_HSIC]= { 0x0004, 18 }, 711 [A80_USB_RST_HCI1_PHY]= { 0x0004, 19 }, /* Undocumented */ 712 [A80_USB_RST_HCI2_HSIC]= { 0x0004, 20 }, /* Undocumented */ 713 [A80_USB_RST_HCI2_UTMIPHY] = { 0x0004, 21 }, 714 }; 715 716 struct sxiccmu_ccu_bit sun9i_a80_mmc_resets[] = { 717 { 0x0000, 18 }, 718 { 0x0004, 18 }, 719 { 0x0008, 18 }, 720 { 0x000c, 18 }, 721 }; 722 723 /* H3/H5 */ 724 725 #define H3_RST_USB_PHY0 0 726 #define H3_RST_USB_PHY1 1 727 #define H3_RST_USB_PHY2 2 728 #define H3_RST_USB_PHY3 3 729 730 #define H3_RST_BUS_MMC0 7 731 #define H3_RST_BUS_MMC1 8 732 #define H3_RST_BUS_MMC2 9 733 734 #define H3_RST_BUS_EMAC 12 735 736 #define H3_RST_BUS_EHCI0 18 737 #define H3_RST_BUS_EHCI1 19 738 #define H3_RST_BUS_EHCI2 20 739 #define H3_RST_BUS_EHCI3 21 740 #define H3_RST_BUS_OHCI0 22 741 #define H3_RST_BUS_OHCI1 23 742 #define H3_RST_BUS_OHCI2 24 743 #define H3_RST_BUS_OHCI3 25 744 #define H3_RST_BUS_EPHY 39 745 #define H3_RST_BUS_THS 42 746 #define H3_RST_BUS_I2C0 46 747 #define H3_RST_BUS_I2C1 47 748 #define H3_RST_BUS_I2C2 48 749 750 struct sxiccmu_ccu_bit sun8i_h3_resets[] = { 751 [H3_RST_USB_PHY0] = { 0x00cc, 0 }, 752 [H3_RST_USB_PHY1] = { 0x00cc, 1 }, 753 [H3_RST_USB_PHY2] = { 0x00cc, 2 }, 754 [H3_RST_USB_PHY3] = { 0x00cc, 3 }, 755 [H3_RST_BUS_MMC0] = { 0x02c0, 8 }, 756 [H3_RST_BUS_MMC1] = { 0x02c0, 9 }, 757 [H3_RST_BUS_MMC2] = { 0x02c0, 10 }, 758 [H3_RST_BUS_EMAC] = { 0x02c0, 17 }, 759 [H3_RST_BUS_EHCI0] = { 0x02c0, 24 }, 760 [H3_RST_BUS_EHCI1] = { 0x02c0, 25 }, 761 [H3_RST_BUS_EHCI2] = { 0x02c0, 26 }, 762 [H3_RST_BUS_EHCI3] = { 0x02c0, 27 }, 763 [H3_RST_BUS_OHCI0] = { 0x02c0, 28 }, 764 [H3_RST_BUS_OHCI1] = { 0x02c0, 29 }, 765 [H3_RST_BUS_OHCI2] = { 0x02c0, 30 }, 766 [H3_RST_BUS_OHCI3] = { 0x02c0, 31 }, 767 [H3_RST_BUS_EPHY] = { 0x02c8, 2 }, 768 [H3_RST_BUS_THS] = { 0x02d0, 8 }, 769 [H3_RST_BUS_I2C0] = { 0x02d8, 0 }, 770 [H3_RST_BUS_I2C1] = { 0x02d8, 1 }, 771 [H3_RST_BUS_I2C2] = { 0x02d8, 2 }, 772 }; 773 774 #define H3_R_RST_APB0_RSB 2 775 #define H3_R_RST_APB0_I2C 5 776 777 struct sxiccmu_ccu_bit sun8i_h3_r_resets[] = { 778 [H3_R_RST_APB0_RSB] = { 0x00b0, 3 }, 779 [H3_R_RST_APB0_I2C] = { 0x00b0, 6 }, 780 }; 781 782 /* H6 */ 783 784 #define H6_RST_BUS_MMC0 18 785 #define H6_RST_BUS_MMC1 19 786 #define H6_RST_BUS_MMC2 20 787 #define H6_RST_BUS_UART0 21 788 #define H6_RST_BUS_UART1 22 789 #define H6_RST_BUS_UART2 23 790 #define H6_RST_BUS_UART3 24 791 #define H6_RST_BUS_OHCI0 48 792 #define H6_RST_BUS_OHCI3 49 793 #define H6_RST_BUS_EHCI0 50 794 #define H6_RST_BUS_EHCI3 52 795 796 struct sxiccmu_ccu_bit sun50i_h6_resets[] = { 797 [H6_RST_BUS_MMC0] = { 0x084c, 16 }, 798 [H6_RST_BUS_MMC1] = { 0x084c, 17 }, 799 [H6_RST_BUS_MMC2] = { 0x084c, 18 }, 800 [H6_RST_BUS_UART0] = { 0x090c, 16 }, 801 [H6_RST_BUS_UART1] = { 0x090c, 17 }, 802 [H6_RST_BUS_UART2] = { 0x090c, 18 }, 803 [H6_RST_BUS_UART3] = { 0x090c, 19 }, 804 [H6_RST_BUS_OHCI0] = { 0x0a8c, 16 }, 805 [H6_RST_BUS_OHCI3] = { 0x0a8c, 19 }, 806 [H6_RST_BUS_EHCI0] = { 0x0a8c, 20 }, 807 [H6_RST_BUS_EHCI3] = { 0x0a8c, 23 }, 808 }; 809 810 #define H6_R_RST_APB2_I2C 4 811 812 struct sxiccmu_ccu_bit sun50i_h6_r_resets[] = { 813 [H6_R_RST_APB2_I2C] = { 0x019c, 16 }, 814 }; 815 816 /* R40 */ 817 818 #define R40_RST_USB_PHY0 0 819 #define R40_RST_USB_PHY1 1 820 #define R40_RST_USB_PHY2 2 821 822 #define R40_RST_BUS_MMC0 8 823 #define R40_RST_BUS_MMC1 9 824 #define R40_RST_BUS_MMC2 10 825 #define R40_RST_BUS_MMC3 11 826 #define R40_RST_BUS_SATA 21 827 #define R40_RST_BUS_EHCI0 23 828 #define R40_RST_BUS_EHCI1 24 829 #define R40_RST_BUS_EHCI2 25 830 #define R40_RST_BUS_OHCI0 26 831 #define R40_RST_BUS_OHCI1 27 832 #define R40_RST_BUS_OHCI2 28 833 #define R40_RST_BUS_GMAC 40 834 #define R40_RST_BUS_THS 59 835 #define R40_RST_BUS_I2C0 64 836 #define R40_RST_BUS_I2C1 65 837 #define R40_RST_BUS_I2C2 66 838 #define R40_RST_BUS_I2C3 67 839 #define R40_RST_BUS_I2C4 72 840 #define R40_RST_BUS_UART0 73 841 #define R40_RST_BUS_UART1 74 842 #define R40_RST_BUS_UART2 75 843 #define R40_RST_BUS_UART3 76 844 #define R40_RST_BUS_UART4 77 845 #define R40_RST_BUS_UART5 78 846 #define R40_RST_BUS_UART6 79 847 #define R40_RST_BUS_UART7 80 848 849 struct sxiccmu_ccu_bit sun8i_r40_resets[] = { 850 [R40_RST_USB_PHY0] = { 0x00cc, 0 }, 851 [R40_RST_USB_PHY1] = { 0x00cc, 1 }, 852 [R40_RST_USB_PHY2] = { 0x00cc, 2 }, 853 [R40_RST_BUS_MMC0] = { 0x02c0, 8 }, 854 [R40_RST_BUS_MMC1] = { 0x02c0, 9 }, 855 [R40_RST_BUS_MMC2] = { 0x02c0, 10 }, 856 [R40_RST_BUS_MMC3] = { 0x02c0, 11 }, 857 [R40_RST_BUS_SATA] = { 0x02c0, 24 }, 858 [R40_RST_BUS_EHCI0] = { 0x02c0, 26 }, 859 [R40_RST_BUS_EHCI1] = { 0x02c0, 27 }, 860 [R40_RST_BUS_EHCI2] = { 0x02c0, 28 }, 861 [R40_RST_BUS_OHCI0] = { 0x02c0, 29 }, 862 [R40_RST_BUS_OHCI1] = { 0x02c0, 30 }, 863 [R40_RST_BUS_OHCI2] = { 0x02c0, 31 }, 864 [R40_RST_BUS_GMAC] = { 0x02c4, 17 }, 865 [R40_RST_BUS_THS] = { 0x02d0, 8 }, 866 [R40_RST_BUS_I2C0] = { 0x02d8, 0 }, 867 [R40_RST_BUS_I2C1] = { 0x02d8, 1 }, 868 [R40_RST_BUS_I2C2] = { 0x02d8, 2 }, 869 [R40_RST_BUS_I2C3] = { 0x02d8, 3 }, 870 [R40_RST_BUS_I2C4] = { 0x02d8, 15 }, 871 [R40_RST_BUS_UART0] = { 0x02d8, 16 }, 872 [R40_RST_BUS_UART1] = { 0x02d8, 17 }, 873 [R40_RST_BUS_UART2] = { 0x02d8, 18 }, 874 [R40_RST_BUS_UART3] = { 0x02d8, 19 }, 875 [R40_RST_BUS_UART4] = { 0x02d8, 20 }, 876 [R40_RST_BUS_UART5] = { 0x02d8, 21 }, 877 [R40_RST_BUS_UART6] = { 0x02d8, 22 }, 878 [R40_RST_BUS_UART7] = { 0x02d8, 23 }, 879 }; 880 881 /* V3s */ 882 883 #define V3S_RST_USB_PHY0 0 884 885 #define V3S_RST_BUS_MMC0 7 886 #define V3S_RST_BUS_MMC1 8 887 #define V3S_RST_BUS_MMC2 9 888 #define V3S_RST_BUS_EMAC 12 889 #define V3S_RST_BUS_EHCI0 18 890 #define V3S_RST_BUS_OHCI0 22 891 #define V3S_RST_BUS_EPHY 39 892 #define V3S_RST_BUS_I2C0 46 893 #define V3S_RST_BUS_I2C1 47 894 #define V3S_RST_BUS_UART0 49 895 #define V3S_RST_BUS_UART1 50 896 #define V3S_RST_BUS_UART2 51 897 898 struct sxiccmu_ccu_bit sun8i_v3s_resets[] = { 899 [V3S_RST_USB_PHY0] = { 0x00cc, 0 }, 900 [V3S_RST_BUS_OHCI0] = { 0x02c0, 29 }, 901 [V3S_RST_BUS_EHCI0] = { 0x02c0, 26 }, 902 [V3S_RST_BUS_EMAC] = { 0x02c0, 17 }, 903 [V3S_RST_BUS_MMC2] = { 0x02c0, 10 }, 904 [V3S_RST_BUS_MMC1] = { 0x02c0, 9 }, 905 [V3S_RST_BUS_MMC0] = { 0x02c0, 8 }, 906 [V3S_RST_BUS_EPHY] = { 0x02c8, 2 }, 907 [V3S_RST_BUS_UART2] = { 0x02d8, 18 }, 908 [V3S_RST_BUS_UART1] = { 0x02d8, 17 }, 909 [V3S_RST_BUS_UART0] = { 0x02d8, 16 }, 910 [V3S_RST_BUS_I2C1] = { 0x02d8, 1 }, 911 [V3S_RST_BUS_I2C0] = { 0x02d8, 0 }, 912 }; 913