1 /* Public Domain */ 2 3 4 /* 5 * Clocks Signals 6 */ 7 8 /* A10/A20 */ 9 10 #define A10_CLK_HOSC 1 11 #define A10_CLK_PLL_CORE 2 12 #define A10_CLK_PLL_PERIPH_BASE 14 13 #define A10_CLK_PLL_PERIPH 15 14 15 #define A10_CLK_CPU 20 16 #define A10_CLK_AXI 21 17 #define A10_CLK_AHB 23 18 #define A10_CLK_APB1 25 19 20 #define A10_CLK_AHB_EHCI0 27 21 #define A10_CLK_AHB_OHCI0 28 22 #define A10_CLK_AHB_EHCI1 29 23 #define A10_CLK_AHB_OHCI1 30 24 #define A10_CLK_AHB_MMC0 34 25 #define A10_CLK_AHB_MMC1 35 26 #define A10_CLK_AHB_MMC2 36 27 #define A10_CLK_AHB_MMC3 37 28 #define A10_CLK_AHB_EMAC 42 29 #define A10_CLK_AHB_SATA 49 30 #define A10_CLK_AHB_GMAC 66 31 #define A10_CLK_APB0_PIO 74 32 #define A10_CLK_APB1_I2C0 79 33 #define A10_CLK_APB1_I2C1 80 34 #define A10_CLK_APB1_I2C2 81 35 #define A10_CLK_APB1_I2C3 82 36 #define A10_CLK_APB1_I2C4 87 37 #define A10_CLK_APB1_UART0 88 38 #define A10_CLK_APB1_UART1 89 39 #define A10_CLK_APB1_UART2 90 40 #define A10_CLK_APB1_UART3 91 41 #define A10_CLK_APB1_UART4 92 42 #define A10_CLK_APB1_UART5 93 43 #define A10_CLK_APB1_UART6 94 44 #define A10_CLK_APB1_UART7 95 45 46 #define A10_CLK_MMC0 98 47 #define A10_CLK_MMC1 101 48 #define A10_CLK_MMC2 104 49 #define A10_CLK_MMC3 107 50 #define A10_CLK_SATA 122 51 #define A10_CLK_USB_OHCI0 123 52 #define A10_CLK_USB_OHCI1 124 53 #define A10_CLK_USB_PHY 125 54 55 #define A10_CLK_LOSC 254 56 57 const struct sxiccmu_ccu_bit sun4i_a10_gates[] = { 58 [A10_CLK_AHB_EHCI0] = { 0x0060, 1 }, 59 [A10_CLK_AHB_OHCI0] = { 0x0060, 2 }, 60 [A10_CLK_AHB_EHCI1] = { 0x0060, 3 }, 61 [A10_CLK_AHB_OHCI1] = { 0x0060, 4 }, 62 [A10_CLK_AHB_MMC0] = { 0x0060, 8 }, 63 [A10_CLK_AHB_MMC1] = { 0x0060, 9 }, 64 [A10_CLK_AHB_MMC2] = { 0x0060, 10 }, 65 [A10_CLK_AHB_MMC3] = { 0x0060, 11 }, 66 [A10_CLK_AHB_EMAC] = { 0x0060, 17 }, 67 [A10_CLK_AHB_SATA] = { 0x0060, 25 }, 68 [A10_CLK_AHB_GMAC] = { 0x0064, 17, A10_CLK_AHB }, 69 [A10_CLK_APB0_PIO] = { 0x0068, 5 }, 70 [A10_CLK_APB1_I2C0] = { 0x006c, 0, A10_CLK_APB1 }, 71 [A10_CLK_APB1_I2C1] = { 0x006c, 1, A10_CLK_APB1 }, 72 [A10_CLK_APB1_I2C2] = { 0x006c, 2, A10_CLK_APB1 }, 73 [A10_CLK_APB1_I2C3] = { 0x006c, 3, A10_CLK_APB1 }, 74 [A10_CLK_APB1_I2C4] = { 0x006c, 15, A10_CLK_APB1 }, 75 [A10_CLK_APB1_UART0] = { 0x006c, 16, A10_CLK_APB1 }, 76 [A10_CLK_APB1_UART1] = { 0x006c, 17, A10_CLK_APB1 }, 77 [A10_CLK_APB1_UART2] = { 0x006c, 18, A10_CLK_APB1 }, 78 [A10_CLK_APB1_UART3] = { 0x006c, 19, A10_CLK_APB1 }, 79 [A10_CLK_APB1_UART4] = { 0x006c, 20, A10_CLK_APB1 }, 80 [A10_CLK_APB1_UART5] = { 0x006c, 21, A10_CLK_APB1 }, 81 [A10_CLK_APB1_UART6] = { 0x006c, 22, A10_CLK_APB1 }, 82 [A10_CLK_APB1_UART7] = { 0x006c, 23, A10_CLK_APB1 }, 83 [A10_CLK_MMC0] = { 0x0088, 31 }, 84 [A10_CLK_MMC1] = { 0x008c, 31 }, 85 [A10_CLK_MMC2] = { 0x0090, 31 }, 86 [A10_CLK_MMC3] = { 0x0094, 31 }, 87 [A10_CLK_SATA] = { 0x00c8, 31 }, 88 [A10_CLK_USB_OHCI0] = { 0x00cc, 6 }, 89 [A10_CLK_USB_OHCI1] = { 0x00cc, 7 }, 90 [A10_CLK_USB_PHY] = { 0x00cc, 8 }, 91 }; 92 93 /* A23/A33 */ 94 95 #define A23_CLK_PLL_PERIPH 10 96 97 #define A23_CLK_AXI 19 98 #define A23_CLK_AHB1 20 99 #define A23_CLK_APB1 21 100 #define A23_CLK_APB2 22 101 102 #define A23_CLK_BUS_MMC0 26 103 #define A23_CLK_BUS_MMC1 27 104 #define A23_CLK_BUS_MMC2 28 105 #define A23_CLK_BUS_EHCI 35 106 #define A23_CLK_BUS_OHCI 36 107 #define A23_CLK_BUS_PIO 48 108 #define A23_CLK_BUS_I2C0 51 109 #define A23_CLK_BUS_I2C1 52 110 #define A23_CLK_BUS_I2C2 53 111 #define A23_CLK_BUS_UART0 54 112 #define A23_CLK_BUS_UART1 55 113 #define A23_CLK_BUS_UART2 56 114 #define A23_CLK_BUS_UART3 57 115 #define A23_CLK_BUS_UART4 58 116 117 #define A23_CLK_MMC0 60 118 #define A23_CLK_MMC1 63 119 #define A23_CLK_MMC2 66 120 #define A23_CLK_USB_OHCI 78 121 122 const struct sxiccmu_ccu_bit sun8i_a23_gates[] = { 123 [A23_CLK_BUS_MMC0] = { 0x0060, 8 }, 124 [A23_CLK_BUS_MMC1] = { 0x0060, 9 }, 125 [A23_CLK_BUS_MMC2] = { 0x0060, 10 }, 126 [A23_CLK_BUS_EHCI] = { 0x0060, 26 }, 127 [A23_CLK_BUS_OHCI] = { 0x0060, 29 }, 128 [A23_CLK_BUS_PIO] = { 0x0068, 5 }, 129 [A23_CLK_BUS_I2C0] = { 0x006c, 0, A23_CLK_APB2 }, 130 [A23_CLK_BUS_I2C1] = { 0x006c, 1, A23_CLK_APB2 }, 131 [A23_CLK_BUS_I2C2] = { 0x006c, 2, A23_CLK_APB2 }, 132 [A23_CLK_BUS_UART0] = { 0x006c, 16, A23_CLK_APB2 }, 133 [A23_CLK_BUS_UART1] = { 0x006c, 17, A23_CLK_APB2 }, 134 [A23_CLK_BUS_UART2] = { 0x006c, 18, A23_CLK_APB2 }, 135 [A23_CLK_BUS_UART3] = { 0x006c, 19, A23_CLK_APB2 }, 136 [A23_CLK_BUS_UART4] = { 0x006c, 20, A23_CLK_APB2 }, 137 [A23_CLK_MMC0] = { 0x0088, 31 }, 138 [A23_CLK_MMC1] = { 0x008c, 31 }, 139 [A23_CLK_MMC2] = { 0x0090, 31 }, 140 [A23_CLK_USB_OHCI] = { 0x00cc, 16 }, 141 }; 142 143 /* A64 */ 144 145 #define A64_CLK_PLL_CPUX 1 146 147 #define A64_CLK_PLL_PERIPH0 11 148 #define A64_CLK_PLL_PERIPH0_2X 12 149 150 #define A64_CLK_CPUX 21 151 #define A64_CLK_AXI 22 152 #define A64_CLK_APB 23 153 #define A64_CLK_AHB1 24 154 #define A64_CLK_APB1 25 155 #define A64_CLK_APB2 26 156 #define A64_CLK_AHB2 27 157 158 #define A64_CLK_BUS_MMC0 31 159 #define A64_CLK_BUS_MMC1 32 160 #define A64_CLK_BUS_MMC2 33 161 #define A64_CLK_BUS_EMAC 36 162 #define A64_CLK_BUS_EHCI0 42 163 #define A64_CLK_BUS_EHCI1 43 164 #define A64_CLK_BUS_OHCI0 44 165 #define A64_CLK_BUS_OHCI1 45 166 #define A64_CLK_BUS_PIO 58 167 #define A64_CLK_BUS_THS 59 168 #define A64_CLK_BUS_I2C0 63 169 #define A64_CLK_BUS_I2C1 64 170 #define A64_CLK_BUS_I2C2 65 171 #define A64_CLK_BUS_UART0 67 172 #define A64_CLK_BUS_UART1 68 173 #define A64_CLK_BUS_UART2 69 174 #define A64_CLK_BUS_UART3 70 175 #define A64_CLK_BUS_UART4 71 176 177 #define A64_CLK_THS 73 178 #define A64_CLK_MMC0 75 179 #define A64_CLK_MMC1 76 180 #define A64_CLK_MMC2 77 181 #define A64_CLK_USB_OHCI0 91 182 #define A64_CLK_USB_OHCI1 93 183 #define A64_CLK_USB_PHY0 86 184 #define A64_CLK_USB_PHY1 87 185 186 #define A64_CLK_LOSC 254 187 #define A64_CLK_HOSC 253 188 189 const struct sxiccmu_ccu_bit sun50i_a64_gates[] = { 190 [A64_CLK_PLL_PERIPH0] = { 0x0028, 31 }, 191 [A64_CLK_BUS_MMC0] = { 0x0060, 8 }, 192 [A64_CLK_BUS_MMC1] = { 0x0060, 9 }, 193 [A64_CLK_BUS_MMC2] = { 0x0060, 10 }, 194 [A64_CLK_BUS_EMAC] = { 0x0060, 17, A64_CLK_AHB2 }, 195 [A64_CLK_BUS_EHCI0] = { 0x0060, 24 }, 196 [A64_CLK_BUS_EHCI1] = { 0x0060, 25 }, 197 [A64_CLK_BUS_OHCI0] = { 0x0060, 28 }, 198 [A64_CLK_BUS_OHCI1] = { 0x0060, 29 }, 199 [A64_CLK_BUS_PIO] = { 0x0068, 5 }, 200 [A64_CLK_BUS_THS] = { 0x0068, 8 }, 201 [A64_CLK_BUS_I2C0] = { 0x006c, 0, A64_CLK_APB2 }, 202 [A64_CLK_BUS_I2C1] = { 0x006c, 1, A64_CLK_APB2 }, 203 [A64_CLK_BUS_I2C2] = { 0x006c, 2, A64_CLK_APB2 }, 204 [A64_CLK_BUS_UART0] = { 0x006c, 16, A64_CLK_APB2 }, 205 [A64_CLK_BUS_UART1] = { 0x006c, 17, A64_CLK_APB2 }, 206 [A64_CLK_BUS_UART2] = { 0x006c, 18, A64_CLK_APB2 }, 207 [A64_CLK_BUS_UART3] = { 0x006c, 19, A64_CLK_APB2 }, 208 [A64_CLK_BUS_UART4] = { 0x006c, 20, A64_CLK_APB2 }, 209 [A64_CLK_THS] = { 0x0074, 31 }, 210 [A64_CLK_MMC0] = { 0x0088, 31 }, 211 [A64_CLK_MMC1] = { 0x008c, 31 }, 212 [A64_CLK_MMC2] = { 0x0090, 31 }, 213 [A64_CLK_USB_OHCI0] = { 0x00cc, 16 }, 214 [A64_CLK_USB_OHCI1] = { 0x00cc, 17 }, 215 [A64_CLK_USB_PHY0] = { 0x00cc, 8 }, 216 [A64_CLK_USB_PHY1] = { 0x00cc, 9 }, 217 }; 218 219 /* A80 */ 220 221 #define A80_CLK_PLL_PERIPH0 3 222 #define A80_CLK_PLL_PERIPH1 11 223 224 #define A80_CLK_GTBUS 18 225 #define A80_CLK_AHB1 20 226 #define A80_CLK_APB1 23 227 228 #define A80_CLK_MMC0 33 229 #define A80_CLK_MMC1 36 230 #define A80_CLK_MMC2 39 231 #define A80_CLK_MMC3 42 232 233 #define A80_CLK_BUS_MMC 84 234 #define A80_CLK_BUS_USB 96 235 #define A80_CLK_BUS_GMAC 97 236 #define A80_CLK_BUS_PIO 111 237 #define A80_CLK_BUS_I2C0 119 238 #define A80_CLK_BUS_I2C1 120 239 #define A80_CLK_BUS_I2C2 121 240 #define A80_CLK_BUS_I2C3 122 241 #define A80_CLK_BUS_I2C4 123 242 #define A80_CLK_BUS_UART0 124 243 #define A80_CLK_BUS_UART1 125 244 #define A80_CLK_BUS_UART2 126 245 #define A80_CLK_BUS_UART3 127 246 #define A80_CLK_BUS_UART4 128 247 #define A80_CLK_BUS_UART5 129 248 249 const struct sxiccmu_ccu_bit sun9i_a80_gates[] = { 250 [A80_CLK_MMC0] = { 0x0410, 31 }, 251 [A80_CLK_MMC1] = { 0x0414, 31 }, 252 [A80_CLK_MMC2] = { 0x0418, 31 }, 253 [A80_CLK_MMC3] = { 0x041c, 31 }, /* Undocumented */ 254 [A80_CLK_BUS_MMC] = { 0x0580, 8 }, 255 [A80_CLK_BUS_GMAC] = { 0x0584, 17, A80_CLK_AHB1 }, 256 [A80_CLK_BUS_USB] = { 0x0584, 1 }, 257 [A80_CLK_BUS_PIO] = { 0x0590, 5 }, 258 [A80_CLK_BUS_I2C0] = { 0x0594, 0, A80_CLK_APB1 }, 259 [A80_CLK_BUS_I2C1] = { 0x0594, 1, A80_CLK_APB1 }, 260 [A80_CLK_BUS_I2C2] = { 0x0594, 2, A80_CLK_APB1 }, 261 [A80_CLK_BUS_I2C3] = { 0x0594, 3, A80_CLK_APB1 }, 262 [A80_CLK_BUS_I2C4] = { 0x0594, 4, A80_CLK_APB1 }, 263 [A80_CLK_BUS_UART0] = { 0x0594, 16, A80_CLK_APB1 }, 264 [A80_CLK_BUS_UART1] = { 0x0594, 17, A80_CLK_APB1 }, 265 [A80_CLK_BUS_UART2] = { 0x0594, 18, A80_CLK_APB1 }, 266 [A80_CLK_BUS_UART3] = { 0x0594, 19, A80_CLK_APB1 }, 267 [A80_CLK_BUS_UART4] = { 0x0594, 20, A80_CLK_APB1 }, 268 [A80_CLK_BUS_UART5] = { 0x0594, 21, A80_CLK_APB1 }, 269 }; 270 271 #define A80_USB_CLK_HCI0 0 272 #define A80_USB_CLK_OHCI0 1 273 #define A80_USB_CLK_HCI1 2 274 #define A80_USB_CLK_HCI2 3 275 #define A80_USB_CLK_OHCI2 4 276 277 #define A80_USB_CLK_HCI0_PHY 5 278 #define A80_USB_CLK_HCI1_HSIC 6 279 #define A80_USB_CLK_HCI1_PHY 7 280 #define A80_USB_CLK_HCI2_HSIC 8 281 #define A80_USB_CLK_HCI2_UTMIPHY 9 282 #define A80_USB_CLK_HCI1_HSIC_12M 10 283 284 const struct sxiccmu_ccu_bit sun9i_a80_usb_gates[] = { 285 [A80_USB_CLK_HCI0] = { 0x0000, 1 }, 286 [A80_USB_CLK_OHCI0] = { 0x0000, 2 }, 287 [A80_USB_CLK_HCI1] = { 0x0000, 3 }, 288 [A80_USB_CLK_HCI2] = { 0x0000, 5 }, 289 [A80_USB_CLK_OHCI2] = { 0x0000, 6 }, 290 [A80_USB_CLK_HCI0_PHY] = { 0x0004, 1 }, 291 [A80_USB_CLK_HCI1_HSIC] = { 0x0004, 2 }, 292 [A80_USB_CLK_HCI1_PHY] = { 0x0004, 3 }, /* Undocumented */ 293 [A80_USB_CLK_HCI2_HSIC] = { 0x0004, 4 }, 294 [A80_USB_CLK_HCI2_UTMIPHY] = { 0x0004, 5 }, 295 [A80_USB_CLK_HCI1_HSIC_12M] = { 0x0004, 10 }, 296 }; 297 298 const struct sxiccmu_ccu_bit sun9i_a80_mmc_gates[] = { 299 { 0x0000, 16 }, 300 { 0x0004, 16 }, 301 { 0x0008, 16 }, 302 { 0x000c, 16 }, 303 }; 304 305 /* H3/H5 */ 306 307 #define H3_CLK_PLL_CPUX 0 308 #define H3_CLK_PLL_PERIPH0 9 309 310 #define H3_CLK_CPUX 14 311 #define H3_CLK_AXI 15 312 #define H3_CLK_AHB1 16 313 #define H3_CLK_APB1 17 314 #define H3_CLK_APB2 18 315 #define H3_CLK_AHB2 19 316 317 #define H3_CLK_BUS_MMC0 22 318 #define H3_CLK_BUS_MMC1 23 319 #define H3_CLK_BUS_MMC2 24 320 #define H3_CLK_BUS_EMAC 27 321 #define H3_CLK_BUS_EHCI0 33 322 #define H3_CLK_BUS_EHCI1 34 323 #define H3_CLK_BUS_EHCI2 35 324 #define H3_CLK_BUS_EHCI3 36 325 #define H3_CLK_BUS_OHCI0 37 326 #define H3_CLK_BUS_OHCI1 38 327 #define H3_CLK_BUS_OHCI2 39 328 #define H3_CLK_BUS_OHCI3 40 329 #define H3_CLK_BUS_PIO 54 330 #define H3_CLK_BUS_THS 55 331 #define H3_CLK_BUS_I2C0 59 332 #define H3_CLK_BUS_I2C1 60 333 #define H3_CLK_BUS_I2C2 61 334 #define H3_CLK_BUS_UART0 62 335 #define H3_CLK_BUS_UART1 63 336 #define H3_CLK_BUS_UART2 64 337 #define H3_CLK_BUS_UART3 65 338 #define H3_CLK_BUS_EPHY 67 339 340 #define H3_CLK_THS 69 341 #define H3_CLK_MMC0 71 342 #define H3_CLK_MMC1 74 343 #define H3_CLK_MMC2 77 344 #define H3_CLK_USB_PHY0 88 345 #define H3_CLK_USB_PHY1 89 346 #define H3_CLK_USB_PHY2 90 347 #define H3_CLK_USB_PHY3 91 348 #define H3_CLK_USB_OHCI0 92 349 #define H3_CLK_USB_OHCI1 93 350 #define H3_CLK_USB_OHCI2 94 351 #define H3_CLK_USB_OHCI3 95 352 353 #define H3_CLK_LOSC 254 354 #define H3_CLK_HOSC 253 355 356 const struct sxiccmu_ccu_bit sun8i_h3_gates[] = { 357 [H3_CLK_PLL_PERIPH0] = { 0x0028, 31 }, 358 [H3_CLK_BUS_MMC0] = { 0x0060, 8 }, 359 [H3_CLK_BUS_MMC1] = { 0x0060, 9 }, 360 [H3_CLK_BUS_MMC2] = { 0x0060, 10 }, 361 [H3_CLK_BUS_EMAC] = { 0x0060, 17, H3_CLK_AHB2 }, 362 [H3_CLK_BUS_EHCI0] = { 0x0060, 24 }, 363 [H3_CLK_BUS_EHCI1] = { 0x0060, 25 }, 364 [H3_CLK_BUS_EHCI2] = { 0x0060, 26 }, 365 [H3_CLK_BUS_EHCI3] = { 0x0060, 27 }, 366 [H3_CLK_BUS_OHCI0] = { 0x0060, 28 }, 367 [H3_CLK_BUS_OHCI1] = { 0x0060, 29 }, 368 [H3_CLK_BUS_OHCI2] = { 0x0060, 30 }, 369 [H3_CLK_BUS_OHCI3] = { 0x0060, 31 }, 370 [H3_CLK_BUS_PIO] = { 0x0068, 5 }, 371 [H3_CLK_BUS_THS] = { 0x0068, 8 }, 372 [H3_CLK_BUS_I2C0] = { 0x006c, 0, H3_CLK_APB2 }, 373 [H3_CLK_BUS_I2C1] = { 0x006c, 1, H3_CLK_APB2 }, 374 [H3_CLK_BUS_I2C2] = { 0x006c, 2, H3_CLK_APB2 }, 375 [H3_CLK_BUS_UART0] = { 0x006c, 16, H3_CLK_APB2 }, 376 [H3_CLK_BUS_UART1] = { 0x006c, 17, H3_CLK_APB2 }, 377 [H3_CLK_BUS_UART2] = { 0x006c, 18, H3_CLK_APB2 }, 378 [H3_CLK_BUS_UART3] = { 0x006c, 19, H3_CLK_APB2 }, 379 [H3_CLK_BUS_EPHY] = { 0x0070, 0 }, 380 [H3_CLK_THS] = { 0x0074, 31 }, 381 [H3_CLK_MMC0] = { 0x0088, 31 }, 382 [H3_CLK_MMC1] = { 0x008c, 31 }, 383 [H3_CLK_MMC2] = { 0x0090, 31 }, 384 [H3_CLK_USB_PHY0] = { 0x00cc, 8 }, 385 [H3_CLK_USB_PHY1] = { 0x00cc, 9 }, 386 [H3_CLK_USB_PHY2] = { 0x00cc, 10 }, 387 [H3_CLK_USB_PHY3] = { 0x00cc, 11 }, 388 [H3_CLK_USB_OHCI0] = { 0x00cc, 16 }, 389 [H3_CLK_USB_OHCI1] = { 0x00cc, 17 }, 390 [H3_CLK_USB_OHCI2] = { 0x00cc, 18 }, 391 [H3_CLK_USB_OHCI3] = { 0x00cc, 19 }, 392 }; 393 394 #define H3_R_CLK_AHB0 1 395 #define H3_R_CLK_APB0 2 396 397 #define H3_R_CLK_APB0_PIO 3 398 #define H3_R_CLK_APB0_RSB 6 399 #define H3_R_CLK_APB0_I2C 9 400 401 const struct sxiccmu_ccu_bit sun8i_h3_r_gates[] = { 402 [H3_R_CLK_APB0_PIO] = { 0x0028, 0 }, 403 [H3_R_CLK_APB0_RSB] = { 0x0028, 3, H3_R_CLK_APB0 }, 404 [H3_R_CLK_APB0_I2C] = { 0x0028, 6, H3_R_CLK_APB0 }, 405 }; 406 407 /* H6 */ 408 409 #define H6_CLK_PLL_PERIPH0 3 410 #define H6_CLK_PLL_PERIPH0_2X 4 411 #define H6_CLK_AHB3 25 412 #define H6_CLK_APB1 26 413 #define H6_CLK_APB2 27 414 #define H6_CLK_MMC0 64 415 #define H6_CLK_MMC1 65 416 #define H6_CLK_MMC2 66 417 #define H6_CLK_BUS_MMC0 67 418 #define H6_CLK_BUS_MMC1 68 419 #define H6_CLK_BUS_MMC2 69 420 #define H6_CLK_BUS_UART0 70 421 #define H6_CLK_BUS_UART1 71 422 #define H6_CLK_BUS_UART2 72 423 #define H6_CLK_BUS_UART3 73 424 #define H6_CLK_BUS_EMAC 84 425 #define H6_CLK_USB_OHCI0 104 426 #define H6_CLK_USB_PHY0 105 427 #define H6_CLK_USB_PHY1 106 428 #define H6_CLK_USB_OHCI3 107 429 #define H6_CLK_USB_PHY3 108 430 #define H6_CLK_BUS_OHCI0 111 431 #define H6_CLK_BUS_OHCI3 112 432 #define H6_CLK_BUS_EHCI0 113 433 #define H6_CLK_BUS_EHCI3 115 434 435 const struct sxiccmu_ccu_bit sun50i_h6_gates[] = { 436 [H6_CLK_PLL_PERIPH0] = { 0x0020, 31 }, 437 [H6_CLK_APB1] = { 0xffff, 0xff }, 438 [H6_CLK_MMC0] = { 0x0830, 31 }, 439 [H6_CLK_MMC1] = { 0x0834, 31 }, 440 [H6_CLK_MMC2] = { 0x0838, 31 }, 441 [H6_CLK_BUS_MMC0] = { 0x084c, 0 }, 442 [H6_CLK_BUS_MMC1] = { 0x084c, 1 }, 443 [H6_CLK_BUS_MMC2] = { 0x084c, 2 }, 444 [H6_CLK_BUS_UART0] = { 0x090c, 0, H6_CLK_APB2 }, 445 [H6_CLK_BUS_UART1] = { 0x090c, 1, H6_CLK_APB2 }, 446 [H6_CLK_BUS_UART2] = { 0x090c, 2, H6_CLK_APB2 }, 447 [H6_CLK_BUS_UART3] = { 0x090c, 3, H6_CLK_APB2 }, 448 [H6_CLK_BUS_EMAC] = { 0x097c, 0, H6_CLK_AHB3 }, 449 [H6_CLK_USB_OHCI0] = { 0x0a70, 31 }, 450 [H6_CLK_USB_PHY0] = { 0x0a70, 29 }, 451 [H6_CLK_USB_PHY1] = { 0x0a74, 29 }, 452 [H6_CLK_USB_OHCI3] = { 0x0a7c, 31 }, 453 [H6_CLK_USB_PHY3] = { 0x0a7c, 29 }, 454 [H6_CLK_BUS_OHCI0] = { 0x0a8c, 0 }, 455 [H6_CLK_BUS_OHCI3] = { 0x0a8c, 3 }, 456 [H6_CLK_BUS_EHCI0] = { 0x0a8c, 4 }, 457 [H6_CLK_BUS_EHCI3] = { 0x0a8c, 7 }, 458 }; 459 460 #define H6_R_CLK_APB1 2 461 #define H6_R_CLK_APB2 3 462 #define H6_R_CLK_APB2_I2C 8 463 #define H6_R_CLK_APB2_RSB 13 464 465 const struct sxiccmu_ccu_bit sun50i_h6_r_gates[] = { 466 [H6_R_CLK_APB1] = { 0xffff, 0xff }, 467 [H6_R_CLK_APB2_I2C] = { 0x019c, 0, H6_R_CLK_APB2 }, 468 [H6_R_CLK_APB2_RSB] = { 0x01bc, 0, H6_R_CLK_APB2 }, 469 }; 470 471 /* R40 */ 472 473 #define R40_CLK_PLL_PERIPH0 11 474 #define R40_CLK_PLL_PERIPH0_2X 13 475 476 #define R40_CLK_AXI 25 477 #define R40_CLK_AHB1 26 478 #define R40_CLK_APB2 28 479 480 #define R40_CLK_BUS_MMC0 32 481 #define R40_CLK_BUS_MMC1 33 482 #define R40_CLK_BUS_MMC2 34 483 #define R40_CLK_BUS_MMC3 35 484 #define R40_CLK_BUS_SATA 45 485 #define R40_CLK_BUS_EHCI0 47 486 #define R40_CLK_BUS_EHCI1 48 487 #define R40_CLK_BUS_EHCI2 49 488 #define R40_CLK_BUS_OHCI0 50 489 #define R40_CLK_BUS_OHCI1 51 490 #define R40_CLK_BUS_OHCI2 52 491 #define R40_CLK_BUS_GMAC 64 492 #define R40_CLK_BUS_PIO 79 493 #define R40_CLK_BUS_THS 82 494 #define R40_CLK_BUS_I2C0 87 495 #define R40_CLK_BUS_I2C1 88 496 #define R40_CLK_BUS_I2C2 89 497 #define R40_CLK_BUS_I2C3 90 498 #define R40_CLK_BUS_I2C4 95 499 #define R40_CLK_BUS_UART0 96 500 #define R40_CLK_BUS_UART1 97 501 #define R40_CLK_BUS_UART2 98 502 #define R40_CLK_BUS_UART3 99 503 #define R40_CLK_BUS_UART4 100 504 #define R40_CLK_BUS_UART5 101 505 #define R40_CLK_BUS_UART6 102 506 #define R40_CLK_BUS_UART7 103 507 508 #define R40_CLK_THS 105 509 #define R40_CLK_MMC0 107 510 #define R40_CLK_MMC1 108 511 #define R40_CLK_MMC2 109 512 #define R40_CLK_MMC3 110 513 #define R40_CLK_SATA 123 514 #define R40_CLK_USB_PHY0 124 515 #define R40_CLK_USB_PHY1 125 516 #define R40_CLK_USB_PHY2 126 517 #define R40_CLK_USB_OHCI0 127 518 #define R40_CLK_USB_OHCI1 128 519 #define R40_CLK_USB_OHCI2 129 520 521 #define R40_CLK_HOSC 253 522 #define R40_CLK_LOSC 254 523 524 const struct sxiccmu_ccu_bit sun8i_r40_gates[] = { 525 [R40_CLK_BUS_MMC0] = { 0x0060, 8 }, 526 [R40_CLK_BUS_MMC1] = { 0x0060, 9 }, 527 [R40_CLK_BUS_MMC2] = { 0x0060, 10 }, 528 [R40_CLK_BUS_MMC3] = { 0x0060, 11 }, 529 [R40_CLK_BUS_SATA] = { 0x0060, 24 }, 530 [R40_CLK_BUS_EHCI0] = { 0x0060, 26 }, 531 [R40_CLK_BUS_EHCI1] = { 0x0060, 27 }, 532 [R40_CLK_BUS_EHCI2] = { 0x0060, 28 }, 533 [R40_CLK_BUS_OHCI0] = { 0x0060, 29 }, 534 [R40_CLK_BUS_OHCI1] = { 0x0060, 30 }, 535 [R40_CLK_BUS_OHCI2] = { 0x0060, 31 }, 536 [R40_CLK_BUS_GMAC] = { 0x0064, 17, R40_CLK_AHB1 }, 537 [R40_CLK_BUS_PIO] = { 0x0068, 5 }, 538 [R40_CLK_BUS_THS] = { 0x0068, 8 }, 539 [R40_CLK_BUS_I2C0] = { 0x006c, 0, R40_CLK_APB2 }, 540 [R40_CLK_BUS_I2C1] = { 0x006c, 1, R40_CLK_APB2 }, 541 [R40_CLK_BUS_I2C2] = { 0x006c, 2, R40_CLK_APB2 }, 542 [R40_CLK_BUS_I2C3] = { 0x006c, 3, R40_CLK_APB2 }, 543 [R40_CLK_BUS_I2C4] = { 0x006c, 15, R40_CLK_APB2 }, 544 [R40_CLK_BUS_UART0] = { 0x006c, 16, R40_CLK_APB2 }, 545 [R40_CLK_BUS_UART1] = { 0x006c, 17, R40_CLK_APB2 }, 546 [R40_CLK_BUS_UART2] = { 0x006c, 18, R40_CLK_APB2 }, 547 [R40_CLK_BUS_UART3] = { 0x006c, 19, R40_CLK_APB2 }, 548 [R40_CLK_BUS_UART4] = { 0x006c, 20, R40_CLK_APB2 }, 549 [R40_CLK_BUS_UART5] = { 0x006c, 21, R40_CLK_APB2 }, 550 [R40_CLK_BUS_UART6] = { 0x006c, 22, R40_CLK_APB2 }, 551 [R40_CLK_BUS_UART7] = { 0x006c, 23, R40_CLK_APB2 }, 552 [R40_CLK_THS] = { 0x0074, 31 }, 553 [R40_CLK_MMC0] = { 0x0088, 31 }, 554 [R40_CLK_MMC1] = { 0x008c, 31 }, 555 [R40_CLK_MMC2] = { 0x0090, 31 }, 556 [R40_CLK_MMC3] = { 0x0094, 31 }, 557 [R40_CLK_SATA] = { 0x00c8, 31 }, 558 [R40_CLK_USB_PHY0] = { 0x00cc, 8 }, 559 [R40_CLK_USB_PHY1] = { 0x00cc, 9 }, 560 [R40_CLK_USB_PHY2] = { 0x00cc, 10 }, 561 [R40_CLK_USB_OHCI0] = { 0x00cc, 16 }, 562 [R40_CLK_USB_OHCI1] = { 0x00cc, 17 }, 563 [R40_CLK_USB_OHCI2] = { 0x00cc, 18 }, 564 }; 565 566 /* V3s */ 567 568 #define V3S_CLK_PLL_PERIPH0 9 569 #define V3S_CLK_AXI 15 570 #define V3S_CLK_AHB1 16 571 #define V3S_CLK_APB2 18 572 #define V3S_CLK_AHB2 19 573 574 #define V3S_CLK_BUS_MMC0 22 575 #define V3S_CLK_BUS_MMC1 23 576 #define V3S_CLK_BUS_MMC2 24 577 #define V3S_CLK_BUS_EMAC 26 578 #define V3S_CLK_BUS_EHCI0 30 579 #define V3S_CLK_BUS_OHCI0 31 580 #define V3S_CLK_BUS_PIO 37 581 #define V3S_CLK_BUS_I2C0 38 582 #define V3S_CLK_BUS_I2C1 39 583 #define V3S_CLK_BUS_UART0 40 584 #define V3S_CLK_BUS_UART1 41 585 #define V3S_CLK_BUS_UART2 42 586 #define V3S_CLK_BUS_EPHY 43 587 588 #define V3S_CLK_MMC0 45 589 #define V3S_CLK_MMC1 48 590 #define V3S_CLK_MMC2 51 591 #define V3S_CLK_USB_PHY0 56 592 #define V3S_CLK_USB_OHCI0 57 593 594 #define V3S_CLK_LOSC 254 595 #define V3S_CLK_HOSC 253 596 597 const struct sxiccmu_ccu_bit sun8i_v3s_gates[] = { 598 [V3S_CLK_BUS_OHCI0] = { 0x0060, 29 }, 599 [V3S_CLK_BUS_EHCI0] = { 0x0060, 26 }, 600 [V3S_CLK_BUS_EMAC] = { 0x0060, 17, V3S_CLK_AHB2 }, 601 [V3S_CLK_BUS_MMC2] = { 0x0060, 10 }, 602 [V3S_CLK_BUS_MMC1] = { 0x0060, 9 }, 603 [V3S_CLK_BUS_MMC0] = { 0x0060, 8 }, 604 [V3S_CLK_BUS_PIO] = { 0x0068, 5 }, 605 [V3S_CLK_BUS_UART2] = { 0x006c, 18, V3S_CLK_APB2 }, 606 [V3S_CLK_BUS_UART1] = { 0x006c, 17, V3S_CLK_APB2 }, 607 [V3S_CLK_BUS_UART0] = { 0x006c, 16, V3S_CLK_APB2 }, 608 [V3S_CLK_BUS_I2C1] = { 0x006c, 1, V3S_CLK_APB2 }, 609 [V3S_CLK_BUS_I2C0] = { 0x006c, 0, V3S_CLK_APB2 }, 610 [V3S_CLK_BUS_EPHY] = { 0x0070, 0 }, 611 [V3S_CLK_MMC0] = { 0x0088, 31 }, 612 [V3S_CLK_MMC1] = { 0x008c, 31 }, 613 [V3S_CLK_MMC2] = { 0x0090, 31 }, 614 [V3S_CLK_USB_OHCI0] = { 0x00cc, 16 }, 615 [V3S_CLK_USB_PHY0] = { 0x00cc, 8 }, 616 }; 617 618 /* 619 * Reset Signals 620 */ 621 622 /* A10 */ 623 624 #define A10_RST_USB_PHY0 1 625 #define A10_RST_USB_PHY1 2 626 #define A10_RST_USB_PHY2 3 627 628 const struct sxiccmu_ccu_bit sun4i_a10_resets[] = { 629 [A10_RST_USB_PHY0] = { 0x00cc, 0 }, 630 [A10_RST_USB_PHY1] = { 0x00cc, 1 }, 631 [A10_RST_USB_PHY2] = { 0x00cc, 2 }, 632 }; 633 634 /* A23/A33 */ 635 636 #define A23_RST_USB_PHY0 0 637 #define A23_RST_USB_PHY1 1 638 639 #define A23_RST_BUS_MMC0 7 640 #define A23_RST_BUS_MMC1 8 641 #define A23_RST_BUS_MMC2 9 642 643 #define A23_RST_BUS_EHCI 16 644 #define A23_RST_BUS_OHCI 17 645 646 #define A23_RST_BUS_I2C0 32 647 #define A23_RST_BUS_I2C1 33 648 #define A23_RST_BUS_I2C2 34 649 650 #define A23_CLK_HOSC 253 651 #define A23_CLK_LOSC 254 652 653 const struct sxiccmu_ccu_bit sun8i_a23_resets[] = { 654 [A23_RST_USB_PHY0] = { 0x00cc, 0 }, 655 [A23_RST_USB_PHY1] = { 0x00cc, 1 }, 656 [A23_RST_BUS_MMC0] = { 0x02c0, 8 }, 657 [A23_RST_BUS_MMC1] = { 0x02c0, 9 }, 658 [A23_RST_BUS_MMC2] = { 0x02c0, 10 }, 659 [A23_RST_BUS_EHCI] = { 0x02c0, 26 }, 660 [A23_RST_BUS_OHCI] = { 0x02c0, 29 }, 661 [A23_RST_BUS_I2C0] = { 0x02d8, 0 }, 662 [A23_RST_BUS_I2C1] = { 0x02d8, 1 }, 663 [A23_RST_BUS_I2C2] = { 0x02d8, 2 }, 664 }; 665 666 /* A64 */ 667 668 #define A64_RST_USB_PHY0 0 669 #define A64_RST_USB_PHY1 1 670 671 #define A64_RST_BUS_MMC0 8 672 #define A64_RST_BUS_MMC1 9 673 #define A64_RST_BUS_MMC2 10 674 #define A64_RST_BUS_EMAC 13 675 #define A64_RST_BUS_EHCI0 19 676 #define A64_RST_BUS_EHCI1 20 677 #define A64_RST_BUS_OHCI0 21 678 #define A64_RST_BUS_OHCI1 22 679 #define A64_RST_BUS_THS 38 680 #define A64_RST_BUS_I2C0 42 681 #define A64_RST_BUS_I2C1 43 682 #define A64_RST_BUS_I2C2 44 683 #define A64_RST_BUS_UART0 46 684 #define A64_RST_BUS_UART1 47 685 #define A64_RST_BUS_UART2 48 686 #define A64_RST_BUS_UART3 49 687 #define A64_RST_BUS_UART4 50 688 689 const struct sxiccmu_ccu_bit sun50i_a64_resets[] = { 690 [A64_RST_USB_PHY0] = { 0x00cc, 0 }, 691 [A64_RST_USB_PHY1] = { 0x00cc, 1 }, 692 [A64_RST_BUS_MMC0] = { 0x02c0, 8 }, 693 [A64_RST_BUS_MMC1] = { 0x02c0, 9 }, 694 [A64_RST_BUS_MMC2] = { 0x02c0, 10 }, 695 [A64_RST_BUS_EMAC] = { 0x02c0, 17 }, 696 [A64_RST_BUS_EHCI0] = { 0x02c0, 24 }, 697 [A64_RST_BUS_EHCI1] = { 0x02c0, 25 }, 698 [A64_RST_BUS_OHCI0] = { 0x02c0, 28 }, 699 [A64_RST_BUS_OHCI1] = { 0x02c0, 29 }, 700 [A64_RST_BUS_THS] = { 0x02d0, 8 }, 701 [A64_RST_BUS_I2C0] = { 0x02d8, 0 }, 702 [A64_RST_BUS_I2C1] = { 0x02d8, 1 }, 703 [A64_RST_BUS_I2C2] = { 0x02d8, 2 }, 704 [A64_RST_BUS_UART0] = { 0x02d8, 16 }, 705 [A64_RST_BUS_UART1] = { 0x02d8, 17 }, 706 [A64_RST_BUS_UART2] = { 0x02d8, 18 }, 707 [A64_RST_BUS_UART3] = { 0x02d8, 19 }, 708 [A64_RST_BUS_UART4] = { 0x02d8, 20 }, 709 }; 710 711 /* A80 */ 712 713 #define A80_RST_BUS_MMC 4 714 #define A80_RST_BUS_GMAC 17 715 #define A80_RST_BUS_I2C0 40 716 #define A80_RST_BUS_I2C1 41 717 #define A80_RST_BUS_I2C2 42 718 #define A80_RST_BUS_I2C3 43 719 #define A80_RST_BUS_I2C4 44 720 #define A80_RST_BUS_UART0 45 721 #define A80_RST_BUS_UART1 46 722 #define A80_RST_BUS_UART2 47 723 #define A80_RST_BUS_UART3 48 724 #define A80_RST_BUS_UART4 49 725 #define A80_RST_BUS_UART5 50 726 727 const struct sxiccmu_ccu_bit sun9i_a80_resets[] = { 728 [A80_RST_BUS_MMC] = { 0x05a0, 8 }, 729 [A80_RST_BUS_GMAC] = { 0x05a4, 17 }, 730 [A80_RST_BUS_I2C0] = { 0x05b4, 0 }, 731 [A80_RST_BUS_I2C1] = { 0x05b4, 1 }, 732 [A80_RST_BUS_I2C2] = { 0x05b4, 2 }, 733 [A80_RST_BUS_I2C3] = { 0x05b4, 3 }, 734 [A80_RST_BUS_I2C4] = { 0x05b4, 4 }, 735 [A80_RST_BUS_UART0] = { 0x05b4, 16 }, 736 [A80_RST_BUS_UART1] = { 0x05b4, 17 }, 737 [A80_RST_BUS_UART2] = { 0x05b4, 18 }, 738 [A80_RST_BUS_UART3] = { 0x05b4, 19 }, 739 [A80_RST_BUS_UART4] = { 0x05b4, 20 }, 740 [A80_RST_BUS_UART5] = { 0x05b4, 21 }, 741 }; 742 743 #define A80_USB_RST_HCI0 0 744 #define A80_USB_RST_HCI1 1 745 #define A80_USB_RST_HCI2 2 746 747 #define A80_USB_RST_HCI0_PHY 3 748 #define A80_USB_RST_HCI1_HSIC 4 749 #define A80_USB_RST_HCI1_PHY 5 750 #define A80_USB_RST_HCI2_HSIC 6 751 #define A80_USB_RST_HCI2_UTMIPHY 7 752 753 const struct sxiccmu_ccu_bit sun9i_a80_usb_resets[] = { 754 [A80_USB_RST_HCI0] = { 0x0000, 17 }, 755 [A80_USB_RST_HCI1] = { 0x0000, 18 }, 756 [A80_USB_RST_HCI2] = { 0x0000, 19 }, 757 [A80_USB_RST_HCI0_PHY] = { 0x0004, 17 }, 758 [A80_USB_RST_HCI1_HSIC]= { 0x0004, 18 }, 759 [A80_USB_RST_HCI1_PHY]= { 0x0004, 19 }, /* Undocumented */ 760 [A80_USB_RST_HCI2_HSIC]= { 0x0004, 20 }, /* Undocumented */ 761 [A80_USB_RST_HCI2_UTMIPHY] = { 0x0004, 21 }, 762 }; 763 764 const struct sxiccmu_ccu_bit sun9i_a80_mmc_resets[] = { 765 { 0x0000, 18 }, 766 { 0x0004, 18 }, 767 { 0x0008, 18 }, 768 { 0x000c, 18 }, 769 }; 770 771 /* H3/H5 */ 772 773 #define H3_RST_USB_PHY0 0 774 #define H3_RST_USB_PHY1 1 775 #define H3_RST_USB_PHY2 2 776 #define H3_RST_USB_PHY3 3 777 778 #define H3_RST_BUS_MMC0 7 779 #define H3_RST_BUS_MMC1 8 780 #define H3_RST_BUS_MMC2 9 781 782 #define H3_RST_BUS_EMAC 12 783 784 #define H3_RST_BUS_EHCI0 18 785 #define H3_RST_BUS_EHCI1 19 786 #define H3_RST_BUS_EHCI2 20 787 #define H3_RST_BUS_EHCI3 21 788 #define H3_RST_BUS_OHCI0 22 789 #define H3_RST_BUS_OHCI1 23 790 #define H3_RST_BUS_OHCI2 24 791 #define H3_RST_BUS_OHCI3 25 792 #define H3_RST_BUS_EPHY 39 793 #define H3_RST_BUS_THS 42 794 #define H3_RST_BUS_I2C0 46 795 #define H3_RST_BUS_I2C1 47 796 #define H3_RST_BUS_I2C2 48 797 #define H3_RST_BUS_UART0 49 798 #define H3_RST_BUS_UART1 50 799 #define H3_RST_BUS_UART2 51 800 #define H3_RST_BUS_UART3 52 801 802 const struct sxiccmu_ccu_bit sun8i_h3_resets[] = { 803 [H3_RST_USB_PHY0] = { 0x00cc, 0 }, 804 [H3_RST_USB_PHY1] = { 0x00cc, 1 }, 805 [H3_RST_USB_PHY2] = { 0x00cc, 2 }, 806 [H3_RST_USB_PHY3] = { 0x00cc, 3 }, 807 [H3_RST_BUS_MMC0] = { 0x02c0, 8 }, 808 [H3_RST_BUS_MMC1] = { 0x02c0, 9 }, 809 [H3_RST_BUS_MMC2] = { 0x02c0, 10 }, 810 [H3_RST_BUS_EMAC] = { 0x02c0, 17 }, 811 [H3_RST_BUS_EHCI0] = { 0x02c0, 24 }, 812 [H3_RST_BUS_EHCI1] = { 0x02c0, 25 }, 813 [H3_RST_BUS_EHCI2] = { 0x02c0, 26 }, 814 [H3_RST_BUS_EHCI3] = { 0x02c0, 27 }, 815 [H3_RST_BUS_OHCI0] = { 0x02c0, 28 }, 816 [H3_RST_BUS_OHCI1] = { 0x02c0, 29 }, 817 [H3_RST_BUS_OHCI2] = { 0x02c0, 30 }, 818 [H3_RST_BUS_OHCI3] = { 0x02c0, 31 }, 819 [H3_RST_BUS_EPHY] = { 0x02c8, 2 }, 820 [H3_RST_BUS_THS] = { 0x02d0, 8 }, 821 [H3_RST_BUS_I2C0] = { 0x02d8, 0 }, 822 [H3_RST_BUS_I2C1] = { 0x02d8, 1 }, 823 [H3_RST_BUS_I2C2] = { 0x02d8, 2 }, 824 [H3_RST_BUS_UART0] = { 0x02d8, 16 }, 825 [H3_RST_BUS_UART1] = { 0x02d8, 17 }, 826 [H3_RST_BUS_UART2] = { 0x02d8, 18 }, 827 [H3_RST_BUS_UART3] = { 0x02d8, 19 }, 828 }; 829 830 #define H3_R_RST_APB0_RSB 2 831 #define H3_R_RST_APB0_I2C 5 832 833 const struct sxiccmu_ccu_bit sun8i_h3_r_resets[] = { 834 [H3_R_RST_APB0_RSB] = { 0x00b0, 3 }, 835 [H3_R_RST_APB0_I2C] = { 0x00b0, 6 }, 836 }; 837 838 /* H6 */ 839 840 #define H6_RST_BUS_MMC0 18 841 #define H6_RST_BUS_MMC1 19 842 #define H6_RST_BUS_MMC2 20 843 #define H6_RST_BUS_UART0 21 844 #define H6_RST_BUS_UART1 22 845 #define H6_RST_BUS_UART2 23 846 #define H6_RST_BUS_UART3 24 847 #define H6_RST_BUS_EMAC 33 848 #define H6_RST_USB_PHY0 44 849 #define H6_RST_USB_PHY1 45 850 #define H6_RST_USB_PHY3 46 851 #define H6_RST_BUS_OHCI0 48 852 #define H6_RST_BUS_OHCI3 49 853 #define H6_RST_BUS_EHCI0 50 854 #define H6_RST_BUS_EHCI3 52 855 856 const struct sxiccmu_ccu_bit sun50i_h6_resets[] = { 857 [H6_RST_BUS_MMC0] = { 0x084c, 16 }, 858 [H6_RST_BUS_MMC1] = { 0x084c, 17 }, 859 [H6_RST_BUS_MMC2] = { 0x084c, 18 }, 860 [H6_RST_BUS_UART0] = { 0x090c, 16 }, 861 [H6_RST_BUS_UART1] = { 0x090c, 17 }, 862 [H6_RST_BUS_UART2] = { 0x090c, 18 }, 863 [H6_RST_BUS_UART3] = { 0x090c, 19 }, 864 [H6_RST_BUS_EMAC] = { 0x097c, 16 }, 865 [H6_RST_USB_PHY0] = { 0x0a70, 30 }, 866 [H6_RST_USB_PHY1] = { 0x0a74, 30 }, 867 [H6_RST_USB_PHY3] = { 0x0a7c, 30 }, 868 [H6_RST_BUS_OHCI0] = { 0x0a8c, 16 }, 869 [H6_RST_BUS_OHCI3] = { 0x0a8c, 19 }, 870 [H6_RST_BUS_EHCI0] = { 0x0a8c, 20 }, 871 [H6_RST_BUS_EHCI3] = { 0x0a8c, 23 }, 872 }; 873 874 #define H6_R_RST_APB2_I2C 4 875 #define H6_R_RST_APB2_RSB 7 876 877 const struct sxiccmu_ccu_bit sun50i_h6_r_resets[] = { 878 [H6_R_RST_APB2_I2C] = { 0x019c, 16 }, 879 [H6_R_RST_APB2_RSB] = { 0x01bc, 16 }, 880 }; 881 882 /* R40 */ 883 884 #define R40_RST_USB_PHY0 0 885 #define R40_RST_USB_PHY1 1 886 #define R40_RST_USB_PHY2 2 887 888 #define R40_RST_BUS_MMC0 8 889 #define R40_RST_BUS_MMC1 9 890 #define R40_RST_BUS_MMC2 10 891 #define R40_RST_BUS_MMC3 11 892 #define R40_RST_BUS_SATA 21 893 #define R40_RST_BUS_EHCI0 23 894 #define R40_RST_BUS_EHCI1 24 895 #define R40_RST_BUS_EHCI2 25 896 #define R40_RST_BUS_OHCI0 26 897 #define R40_RST_BUS_OHCI1 27 898 #define R40_RST_BUS_OHCI2 28 899 #define R40_RST_BUS_GMAC 40 900 #define R40_RST_BUS_THS 59 901 #define R40_RST_BUS_I2C0 64 902 #define R40_RST_BUS_I2C1 65 903 #define R40_RST_BUS_I2C2 66 904 #define R40_RST_BUS_I2C3 67 905 #define R40_RST_BUS_I2C4 72 906 #define R40_RST_BUS_UART0 73 907 #define R40_RST_BUS_UART1 74 908 #define R40_RST_BUS_UART2 75 909 #define R40_RST_BUS_UART3 76 910 #define R40_RST_BUS_UART4 77 911 #define R40_RST_BUS_UART5 78 912 #define R40_RST_BUS_UART6 79 913 #define R40_RST_BUS_UART7 80 914 915 const struct sxiccmu_ccu_bit sun8i_r40_resets[] = { 916 [R40_RST_USB_PHY0] = { 0x00cc, 0 }, 917 [R40_RST_USB_PHY1] = { 0x00cc, 1 }, 918 [R40_RST_USB_PHY2] = { 0x00cc, 2 }, 919 [R40_RST_BUS_MMC0] = { 0x02c0, 8 }, 920 [R40_RST_BUS_MMC1] = { 0x02c0, 9 }, 921 [R40_RST_BUS_MMC2] = { 0x02c0, 10 }, 922 [R40_RST_BUS_MMC3] = { 0x02c0, 11 }, 923 [R40_RST_BUS_SATA] = { 0x02c0, 24 }, 924 [R40_RST_BUS_EHCI0] = { 0x02c0, 26 }, 925 [R40_RST_BUS_EHCI1] = { 0x02c0, 27 }, 926 [R40_RST_BUS_EHCI2] = { 0x02c0, 28 }, 927 [R40_RST_BUS_OHCI0] = { 0x02c0, 29 }, 928 [R40_RST_BUS_OHCI1] = { 0x02c0, 30 }, 929 [R40_RST_BUS_OHCI2] = { 0x02c0, 31 }, 930 [R40_RST_BUS_GMAC] = { 0x02c4, 17 }, 931 [R40_RST_BUS_THS] = { 0x02d0, 8 }, 932 [R40_RST_BUS_I2C0] = { 0x02d8, 0 }, 933 [R40_RST_BUS_I2C1] = { 0x02d8, 1 }, 934 [R40_RST_BUS_I2C2] = { 0x02d8, 2 }, 935 [R40_RST_BUS_I2C3] = { 0x02d8, 3 }, 936 [R40_RST_BUS_I2C4] = { 0x02d8, 15 }, 937 [R40_RST_BUS_UART0] = { 0x02d8, 16 }, 938 [R40_RST_BUS_UART1] = { 0x02d8, 17 }, 939 [R40_RST_BUS_UART2] = { 0x02d8, 18 }, 940 [R40_RST_BUS_UART3] = { 0x02d8, 19 }, 941 [R40_RST_BUS_UART4] = { 0x02d8, 20 }, 942 [R40_RST_BUS_UART5] = { 0x02d8, 21 }, 943 [R40_RST_BUS_UART6] = { 0x02d8, 22 }, 944 [R40_RST_BUS_UART7] = { 0x02d8, 23 }, 945 }; 946 947 /* V3s */ 948 949 #define V3S_RST_USB_PHY0 0 950 951 #define V3S_RST_BUS_MMC0 7 952 #define V3S_RST_BUS_MMC1 8 953 #define V3S_RST_BUS_MMC2 9 954 #define V3S_RST_BUS_EMAC 12 955 #define V3S_RST_BUS_EHCI0 18 956 #define V3S_RST_BUS_OHCI0 22 957 #define V3S_RST_BUS_EPHY 39 958 #define V3S_RST_BUS_I2C0 46 959 #define V3S_RST_BUS_I2C1 47 960 #define V3S_RST_BUS_UART0 49 961 #define V3S_RST_BUS_UART1 50 962 #define V3S_RST_BUS_UART2 51 963 964 const struct sxiccmu_ccu_bit sun8i_v3s_resets[] = { 965 [V3S_RST_USB_PHY0] = { 0x00cc, 0 }, 966 [V3S_RST_BUS_OHCI0] = { 0x02c0, 29 }, 967 [V3S_RST_BUS_EHCI0] = { 0x02c0, 26 }, 968 [V3S_RST_BUS_EMAC] = { 0x02c0, 17 }, 969 [V3S_RST_BUS_MMC2] = { 0x02c0, 10 }, 970 [V3S_RST_BUS_MMC1] = { 0x02c0, 9 }, 971 [V3S_RST_BUS_MMC0] = { 0x02c0, 8 }, 972 [V3S_RST_BUS_EPHY] = { 0x02c8, 2 }, 973 [V3S_RST_BUS_UART2] = { 0x02d8, 18 }, 974 [V3S_RST_BUS_UART1] = { 0x02d8, 17 }, 975 [V3S_RST_BUS_UART0] = { 0x02d8, 16 }, 976 [V3S_RST_BUS_I2C1] = { 0x02d8, 1 }, 977 [V3S_RST_BUS_I2C0] = { 0x02d8, 0 }, 978 }; 979