1 /* $OpenBSD: rkpcie.c,v 1.6 2018/08/28 09:33:18 jsg Exp $ */ 2 /* 3 * Copyright (c) 2018 Mark Kettenis <kettenis@openbsd.org> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #include <sys/param.h> 19 #include <sys/systm.h> 20 #include <sys/device.h> 21 #include <sys/extent.h> 22 #include <sys/malloc.h> 23 24 #include <machine/intr.h> 25 #include <machine/bus.h> 26 #include <machine/fdt.h> 27 28 #include <dev/pci/pcidevs.h> 29 #include <dev/pci/pcireg.h> 30 #include <dev/pci/pcivar.h> 31 32 #include <dev/ofw/openfirm.h> 33 #include <dev/ofw/ofw_clock.h> 34 #include <dev/ofw/ofw_gpio.h> 35 #include <dev/ofw/ofw_misc.h> 36 #include <dev/ofw/fdt.h> 37 38 #define PCIE_CLIENT_BASIC_STRAP_CONF 0x0000 39 #define PCIE_CLIENT_PCIE_GEN_SEL_1 (((1 << 7) << 16) | (0 << 7)) 40 #define PCIE_CLIENT_PCIE_GEN_SEL_2 (((1 << 7) << 16) | (1 << 7)) 41 #define PCIE_CLIENT_MODE_SELECT_RC (((1 << 6) << 16) | (1 << 6)) 42 #define PCIE_CLIENT_LINK_TRAIN_EN (((1 << 1) << 16) | (1 << 1)) 43 #define PCIE_CLIENT_CONF_EN (((1 << 0) << 16) | (1 << 0)) 44 #define PCIE_CLIENT_BASIC_STATUS1 0x0048 45 #define PCIE_CLIENT_LINK_ST (0x3 << 20) 46 #define PCIE_CLIENT_LINK_ST_UP (0x3 << 20) 47 #define PCIE_CLIENT_INT_MASK 0x004c 48 #define PCIE_CLIENT_INTD_MASK (((1 << 8) << 16) | (1 << 8)) 49 #define PCIE_CLIENT_INTD_UNMASK (((1 << 8) << 16) | (0 << 8)) 50 #define PCIE_CLIENT_INTC_MASK (((1 << 7) << 16) | (1 << 7)) 51 #define PCIE_CLIENT_INTC_UNMASK (((1 << 7) << 16) | (0 << 7)) 52 #define PCIE_CLIENT_INTB_MASK (((1 << 6) << 16) | (1 << 6)) 53 #define PCIE_CLIENT_INTB_UNMASK (((1 << 6) << 16) | (0 << 6)) 54 #define PCIE_CLIENT_INTA_MASK (((1 << 5) << 16) | (1 << 5)) 55 #define PCIE_CLIENT_INTA_UNMASK (((1 << 5) << 16) | (0 << 5)) 56 57 #define PCIE_RC_NORMAL_BASE 0x800000 58 59 #define PCIE_LM_BASE 0x900000 60 #define PCIE_LM_VENDOR_ID (PCIE_LM_BASE + 0x44) 61 #define PCIE_LM_RCBAR (PCIE_LM_BASE + 0x300) 62 #define PCIE_LM_RCBARPIE (1 << 19) 63 #define PCIE_LM_RCBARPIS (1 << 20) 64 65 #define PCIE_RC_BASE 0xa00000 66 #define PCIE_RC_PCIE_LCAP (PCIE_RC_BASE + 0x0cc) 67 #define PCIE_RC_PCIE_LCAP_APMS_L0S (1 << 10) 68 69 #define PCIE_ATR_BASE 0xc00000 70 #define PCIE_ATR_OB_ADDR0(i) (PCIE_ATR_BASE + 0x000 + (i) * 0x20) 71 #define PCIE_ATR_OB_ADDR1(i) (PCIE_ATR_BASE + 0x004 + (i) * 0x20) 72 #define PCIE_ATR_OB_DESC0(i) (PCIE_ATR_BASE + 0x008 + (i) * 0x20) 73 #define PCIE_ATR_OB_DESC1(i) (PCIE_ATR_BASE + 0x00c + (i) * 0x20) 74 #define PCIE_ATR_IB_ADDR0(i) (PCIE_ATR_BASE + 0x800 + (i) * 0x8) 75 #define PCIE_ATR_IB_ADDR1(i) (PCIE_ATR_BASE + 0x804 + (i) * 0x8) 76 #define PCIE_ATR_HDR_MEM 0x2 77 #define PCIE_ATR_HDR_IO 0x6 78 #define PCIE_ATR_HDR_CFG_TYPE0 0xa 79 #define PCIE_ATR_HDR_CFG_TYPE1 0xb 80 #define PCIE_ATR_HDR_RID (1 << 23) 81 82 #define PCIE_ATR_OB_REGION0_SIZE (32 * 1024 * 1024) 83 #define PCIE_ATR_OB_REGION_SIZE (1 * 1024 * 1024) 84 85 #define HREAD4(sc, reg) \ 86 (bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg))) 87 #define HWRITE4(sc, reg, val) \ 88 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 89 90 struct rkpcie_softc { 91 struct device sc_dev; 92 bus_space_tag_t sc_iot; 93 bus_space_handle_t sc_ioh; 94 bus_space_handle_t sc_axi_ioh; 95 bus_addr_t sc_axi_addr; 96 bus_addr_t sc_apb_addr; 97 int sc_node; 98 int sc_phy_node; 99 100 struct arm64_pci_chipset sc_pc; 101 struct extent *sc_busex; 102 struct extent *sc_memex; 103 struct extent *sc_ioex; 104 int sc_bus; 105 }; 106 107 int rkpcie_match(struct device *, void *, void *); 108 void rkpcie_attach(struct device *, struct device *, void *); 109 110 struct cfattach rkpcie_ca = { 111 sizeof (struct rkpcie_softc), rkpcie_match, rkpcie_attach 112 }; 113 114 struct cfdriver rkpcie_cd = { 115 NULL, "rkpcie", DV_DULL 116 }; 117 118 int 119 rkpcie_match(struct device *parent, void *match, void *aux) 120 { 121 struct fdt_attach_args *faa = aux; 122 123 return OF_is_compatible(faa->fa_node, "rockchip,rk3399-pcie"); 124 } 125 126 void rkpcie_atr_init(struct rkpcie_softc *); 127 void rkpcie_phy_init(struct rkpcie_softc *); 128 void rkpcie_phy_poweron(struct rkpcie_softc *); 129 130 void rkpcie_attach_hook(struct device *, struct device *, 131 struct pcibus_attach_args *); 132 int rkpcie_bus_maxdevs(void *, int); 133 pcitag_t rkpcie_make_tag(void *, int, int, int); 134 void rkpcie_decompose_tag(void *, pcitag_t, int *, int *, int *); 135 int rkpcie_conf_size(void *, pcitag_t); 136 pcireg_t rkpcie_conf_read(void *, pcitag_t, int); 137 void rkpcie_conf_write(void *, pcitag_t, int, pcireg_t); 138 139 int rkpcie_intr_map(struct pci_attach_args *, pci_intr_handle_t *); 140 int rkpcie_intr_map_msi(struct pci_attach_args *, pci_intr_handle_t *); 141 int rkpcie_intr_map_msix(struct pci_attach_args *, int, 142 pci_intr_handle_t *); 143 const char *rkpcie_intr_string(void *, pci_intr_handle_t); 144 void *rkpcie_intr_establish(void *, pci_intr_handle_t, int, 145 int (*)(void *), void *, char *); 146 void rkpcie_intr_disestablish(void *, void *); 147 148 void 149 rkpcie_attach(struct device *parent, struct device *self, void *aux) 150 { 151 struct rkpcie_softc *sc = (struct rkpcie_softc *)self; 152 struct fdt_attach_args *faa = aux; 153 struct pcibus_attach_args pba; 154 uint32_t *ep_gpio; 155 uint32_t bus_range[2]; 156 uint32_t status; 157 int len, timo; 158 159 if (faa->fa_nreg < 2) { 160 printf(": no registers\n"); 161 return; 162 } 163 164 sc->sc_iot = faa->fa_iot; 165 166 if (bus_space_map(sc->sc_iot, faa->fa_reg[1].addr, 167 faa->fa_reg[1].size, 0, &sc->sc_ioh)) { 168 printf(": can't map registers\n"); 169 return; 170 } 171 172 if (bus_space_map(sc->sc_iot, faa->fa_reg[0].addr, 173 faa->fa_reg[0].size, 0, &sc->sc_axi_ioh)) { 174 printf(": can't map AXI registers\n"); 175 bus_space_unmap(sc->sc_iot, sc->sc_ioh, faa->fa_reg[1].size); 176 return; 177 } 178 179 sc->sc_axi_addr = faa->fa_reg[0].addr; 180 sc->sc_apb_addr = faa->fa_reg[1].addr; 181 sc->sc_node = faa->fa_node; 182 printf("\n"); 183 184 len = OF_getproplen(sc->sc_node, "ep-gpios"); 185 if (len < 0) 186 return; 187 188 ep_gpio = malloc(len, M_TEMP, M_WAITOK); 189 OF_getpropintarray(sc->sc_node, "ep-gpios", ep_gpio, len); 190 191 clock_enable_all(sc->sc_node); 192 193 gpio_controller_config_pin(ep_gpio, GPIO_CONFIG_OUTPUT); 194 gpio_controller_set_pin(ep_gpio, 0); 195 196 reset_assert(sc->sc_node, "aclk"); 197 reset_assert(sc->sc_node, "pclk"); 198 reset_assert(sc->sc_node, "pm"); 199 200 rkpcie_phy_init(sc); 201 202 reset_assert(sc->sc_node, "core"); 203 reset_assert(sc->sc_node, "mgmt"); 204 reset_assert(sc->sc_node, "mgmt-sticky"); 205 reset_assert(sc->sc_node, "pipe"); 206 207 delay(10); 208 209 reset_deassert(sc->sc_node, "pm"); 210 reset_deassert(sc->sc_node, "aclk"); 211 reset_deassert(sc->sc_node, "pclk"); 212 213 /* Only advertise Gen 1 support for now. */ 214 HWRITE4(sc, PCIE_CLIENT_BASIC_STRAP_CONF, PCIE_CLIENT_PCIE_GEN_SEL_1); 215 216 /* Switch into Root Complex mode. */ 217 HWRITE4(sc, PCIE_CLIENT_BASIC_STRAP_CONF, 218 PCIE_CLIENT_MODE_SELECT_RC | PCIE_CLIENT_CONF_EN); 219 220 rkpcie_phy_poweron(sc); 221 222 reset_deassert(sc->sc_node, "core"); 223 reset_deassert(sc->sc_node, "mgmt"); 224 reset_deassert(sc->sc_node, "mgmt-sticky"); 225 reset_deassert(sc->sc_node, "pipe"); 226 227 /* Start link training. */ 228 HWRITE4(sc, PCIE_CLIENT_BASIC_STRAP_CONF, PCIE_CLIENT_LINK_TRAIN_EN); 229 230 /* XXX Advertise power limits? */ 231 232 gpio_controller_set_pin(ep_gpio, 1); 233 free(ep_gpio, M_TEMP, len); 234 235 for (timo = 500; timo > 0; timo--) { 236 status = HREAD4(sc, PCIE_CLIENT_BASIC_STATUS1); 237 if ((status & PCIE_CLIENT_LINK_ST) == PCIE_CLIENT_LINK_ST_UP) 238 break; 239 delay(1000); 240 } 241 if (timo == 0) { 242 printf("%s: link training timeout\n", sc->sc_dev.dv_xname); 243 return; 244 } 245 246 /* Initialize Root Complex registers. */ 247 HWRITE4(sc, PCIE_LM_VENDOR_ID, PCI_VENDOR_ROCKCHIP); 248 HWRITE4(sc, PCIE_RC_BASE + PCI_CLASS_REG, 249 PCI_CLASS_BRIDGE << PCI_CLASS_SHIFT | 250 PCI_SUBCLASS_BRIDGE_PCI << PCI_SUBCLASS_SHIFT); 251 HWRITE4(sc, PCIE_LM_RCBAR, PCIE_LM_RCBARPIE | PCIE_LM_RCBARPIS); 252 253 if (OF_getproplen(sc->sc_node, "aspm-no-l0s") == 0) { 254 status = HREAD4(sc, PCIE_RC_PCIE_LCAP); 255 status &= ~PCIE_RC_PCIE_LCAP_APMS_L0S; 256 HWRITE4(sc, PCIE_RC_PCIE_LCAP, status); 257 } 258 259 /* Create extents for our address spaces. */ 260 sc->sc_busex = extent_create("pcibus", 0, 255, 261 M_DEVBUF, NULL, 0, EX_WAITOK | EX_FILLED); 262 sc->sc_memex = extent_create("pcimem", 0, (u_long)-1, 263 M_DEVBUF, NULL, 0, EX_WAITOK | EX_FILLED); 264 sc->sc_ioex = extent_create("pciio", 0, 0xffffffff, 265 M_DEVBUF, NULL, 0, EX_WAITOK | EX_FILLED); 266 267 /* Set up bus range. */ 268 if (OF_getpropintarray(sc->sc_node, "bus-range", bus_range, 269 sizeof(bus_range)) != sizeof(bus_range) || 270 bus_range[0] >= 32 || bus_range[1] >= 32) { 271 bus_range[0] = 0; 272 bus_range[1] = 31; 273 } 274 sc->sc_bus = bus_range[0]; 275 extent_free(sc->sc_busex, bus_range[0], 276 bus_range[1] - bus_range[0] + 1, EX_WAITOK); 277 278 /* Configure Address Translation. */ 279 rkpcie_atr_init(sc); 280 281 sc->sc_pc.pc_conf_v = sc; 282 sc->sc_pc.pc_attach_hook = rkpcie_attach_hook; 283 sc->sc_pc.pc_bus_maxdevs = rkpcie_bus_maxdevs; 284 sc->sc_pc.pc_make_tag = rkpcie_make_tag; 285 sc->sc_pc.pc_decompose_tag = rkpcie_decompose_tag; 286 sc->sc_pc.pc_conf_size = rkpcie_conf_size; 287 sc->sc_pc.pc_conf_read = rkpcie_conf_read; 288 sc->sc_pc.pc_conf_write = rkpcie_conf_write; 289 290 sc->sc_pc.pc_intr_v = sc; 291 sc->sc_pc.pc_intr_map = rkpcie_intr_map; 292 sc->sc_pc.pc_intr_map_msi = rkpcie_intr_map_msi; 293 sc->sc_pc.pc_intr_map_msix = rkpcie_intr_map_msix; 294 sc->sc_pc.pc_intr_string = rkpcie_intr_string; 295 sc->sc_pc.pc_intr_establish = rkpcie_intr_establish; 296 sc->sc_pc.pc_intr_disestablish = rkpcie_intr_disestablish; 297 298 memset(&pba, 0, sizeof(pba)); 299 pba.pba_busname = "pci"; 300 pba.pba_iot = faa->fa_iot; 301 pba.pba_memt = faa->fa_iot; 302 pba.pba_dmat = faa->fa_dmat; 303 pba.pba_pc = &sc->sc_pc; 304 pba.pba_busex = sc->sc_busex; 305 pba.pba_memex = sc->sc_memex; 306 pba.pba_ioex = sc->sc_ioex; 307 pba.pba_domain = pci_ndomains++; 308 pba.pba_bus = sc->sc_bus; 309 pba.pba_flags |= PCI_FLAGS_MSI_ENABLED; 310 311 config_found(self, &pba, NULL); 312 } 313 314 void 315 rkpcie_atr_init(struct rkpcie_softc *sc) 316 { 317 uint32_t *ranges = NULL; 318 struct extent *ex; 319 bus_addr_t addr; 320 bus_size_t size, offset; 321 uint32_t type; 322 int len, region; 323 int i; 324 325 /* Use region 0 to map PCI configuration space. */ 326 HWRITE4(sc, PCIE_ATR_OB_ADDR0(0), 25 - 1); 327 HWRITE4(sc, PCIE_ATR_OB_ADDR1(0), 0); 328 HWRITE4(sc, PCIE_ATR_OB_DESC0(0), 329 PCIE_ATR_HDR_CFG_TYPE0 | PCIE_ATR_HDR_RID); 330 HWRITE4(sc, PCIE_ATR_OB_DESC1(0), 0); 331 332 len = OF_getproplen(sc->sc_node, "ranges"); 333 if (len <= 0 || (len % (7 * sizeof(uint32_t))) != 0) 334 goto fail; 335 ranges = malloc(len, M_TEMP, M_WAITOK); 336 OF_getpropintarray(sc->sc_node, "ranges", ranges, len); 337 338 for (i = 0; i < len / sizeof(uint32_t); i += 7) { 339 /* Handle IO and MMIO. */ 340 switch (ranges[i] & 0x03000000) { 341 case 0x01000000: 342 type = PCIE_ATR_HDR_IO; 343 ex = sc->sc_ioex; 344 break; 345 case 0x02000000: 346 case 0x03000000: 347 type = PCIE_ATR_HDR_MEM; 348 ex = sc->sc_memex; 349 break; 350 default: 351 continue; 352 } 353 354 /* Only support identity mappings. */ 355 if (ranges[i + 1] != ranges[i + 3] || 356 ranges[i + 2] != ranges[i + 4]) 357 goto fail; 358 359 /* Only support mappings aligned on a region boundary. */ 360 addr = ((uint64_t)ranges[i + 1] << 32) + ranges[i + 2]; 361 if (addr & (PCIE_ATR_OB_REGION_SIZE - 1)) 362 goto fail; 363 364 /* Mappings should lie between AXI and APB regions. */ 365 size = ranges[i + 6]; 366 if (addr < sc->sc_axi_addr + PCIE_ATR_OB_REGION0_SIZE) 367 goto fail; 368 if (addr + size > sc->sc_apb_addr) 369 goto fail; 370 371 offset = addr - sc->sc_axi_addr - PCIE_ATR_OB_REGION0_SIZE; 372 region = 1 + (offset / PCIE_ATR_OB_REGION_SIZE); 373 while (size > 0) { 374 HWRITE4(sc, PCIE_ATR_OB_ADDR0(region), 32 - 1); 375 HWRITE4(sc, PCIE_ATR_OB_ADDR1(region), 0); 376 HWRITE4(sc, PCIE_ATR_OB_DESC0(region), 377 type | PCIE_ATR_HDR_RID); 378 HWRITE4(sc, PCIE_ATR_OB_DESC1(region), 0); 379 380 extent_free(ex, addr, PCIE_ATR_OB_REGION_SIZE, 381 EX_WAITOK); 382 addr += PCIE_ATR_OB_REGION_SIZE; 383 size -= PCIE_ATR_OB_REGION_SIZE; 384 region++; 385 } 386 } 387 388 /* Passthrought inbound translations unmodified. */ 389 HWRITE4(sc, PCIE_ATR_IB_ADDR0(2), 32 - 1); 390 HWRITE4(sc, PCIE_ATR_IB_ADDR1(2), 0); 391 392 free(ranges, M_TEMP, len); 393 return; 394 395 fail: 396 printf("%s: can't map ranges\n", sc->sc_dev.dv_xname); 397 free(ranges, M_TEMP, len); 398 } 399 400 void 401 rkpcie_attach_hook(struct device *parent, struct device *self, 402 struct pcibus_attach_args *pba) 403 { 404 } 405 406 int 407 rkpcie_bus_maxdevs(void *v, int bus) 408 { 409 struct rkpcie_softc *sc = v; 410 411 if (bus == sc->sc_bus || bus == sc->sc_bus + 1) 412 return 1; 413 return 32; 414 } 415 416 pcitag_t 417 rkpcie_make_tag(void *v, int bus, int device, int function) 418 { 419 /* Return ECAM address. */ 420 return ((bus << 20) | (device << 15) | (function << 12)); 421 } 422 423 void 424 rkpcie_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 425 { 426 if (bp != NULL) 427 *bp = (tag >> 20) & 0xff; 428 if (dp != NULL) 429 *dp = (tag >> 15) & 0x1f; 430 if (fp != NULL) 431 *fp = (tag >> 12) & 0x7; 432 } 433 434 int 435 rkpcie_conf_size(void *v, pcitag_t tag) 436 { 437 return PCIE_CONFIG_SPACE_SIZE; 438 } 439 440 pcireg_t 441 rkpcie_conf_read(void *v, pcitag_t tag, int reg) 442 { 443 struct rkpcie_softc *sc = v; 444 int bus, dev, fn; 445 446 rkpcie_decompose_tag(sc, tag, &bus, &dev, &fn); 447 if (bus == sc->sc_bus) { 448 KASSERT(dev == 0); 449 return HREAD4(sc, PCIE_RC_NORMAL_BASE + tag | reg); 450 } 451 if (bus == sc->sc_bus + 1) { 452 KASSERT(dev == 0); 453 return bus_space_read_4(sc->sc_iot, sc->sc_axi_ioh, tag | reg); 454 } 455 456 return 0xffffffff; 457 } 458 459 void 460 rkpcie_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data) 461 { 462 struct rkpcie_softc *sc = v; 463 int bus, dev, fn; 464 465 rkpcie_decompose_tag(sc, tag, &bus, &dev, &fn); 466 if (bus == sc->sc_bus) { 467 KASSERT(dev == 0); 468 HWRITE4(sc, PCIE_RC_NORMAL_BASE + tag | reg, data); 469 return; 470 } 471 if (bus == sc->sc_bus + 1) { 472 KASSERT(dev == 0); 473 bus_space_write_4(sc->sc_iot, sc->sc_axi_ioh, tag | reg, data); 474 return; 475 } 476 } 477 478 struct rkpcie_intr_handle { 479 pci_chipset_tag_t ih_pc; 480 pcitag_t ih_tag; 481 int ih_intrpin; 482 int ih_msi; 483 }; 484 485 int 486 rkpcie_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 487 { 488 struct rkpcie_intr_handle *ih; 489 int pin = pa->pa_rawintrpin; 490 491 if (pin == 0 || pin > PCI_INTERRUPT_PIN_MAX) 492 return -1; 493 494 if (pa->pa_tag == 0) 495 return -1; 496 497 ih = malloc(sizeof(struct rkpcie_intr_handle), M_DEVBUF, M_WAITOK); 498 ih->ih_pc = pa->pa_pc; 499 ih->ih_tag = pa->pa_intrtag; 500 ih->ih_intrpin = pa->pa_intrpin; 501 ih->ih_msi = 0; 502 *ihp = (pci_intr_handle_t)ih; 503 504 return 0; 505 } 506 507 int 508 rkpcie_intr_map_msi(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 509 { 510 pci_chipset_tag_t pc = pa->pa_pc; 511 pcitag_t tag = pa->pa_tag; 512 struct rkpcie_intr_handle *ih; 513 514 if ((pa->pa_flags & PCI_FLAGS_MSI_ENABLED) == 0 || 515 pci_get_capability(pc, tag, PCI_CAP_MSI, NULL, NULL) == 0) 516 return -1; 517 518 ih = malloc(sizeof(struct rkpcie_intr_handle), M_DEVBUF, M_WAITOK); 519 ih->ih_pc = pa->pa_pc; 520 ih->ih_tag = pa->pa_tag; 521 ih->ih_intrpin = pa->pa_intrpin; 522 ih->ih_msi = 1; 523 *ihp = (pci_intr_handle_t)ih; 524 525 return 0; 526 } 527 528 int 529 rkpcie_intr_map_msix(struct pci_attach_args *pa, int vec, 530 pci_intr_handle_t *ihp) 531 { 532 return -1; 533 } 534 535 const char * 536 rkpcie_intr_string(void *v, pci_intr_handle_t ihp) 537 { 538 struct rkpcie_intr_handle *ih = (struct rkpcie_intr_handle *)ihp; 539 540 if (ih->ih_msi) 541 return "msi"; 542 543 return "intx"; 544 } 545 546 void * 547 rkpcie_intr_establish(void *v, pci_intr_handle_t ihp, int level, 548 int (*func)(void *), void *arg, char *name) 549 { 550 struct rkpcie_softc *sc = v; 551 struct rkpcie_intr_handle *ih = (struct rkpcie_intr_handle *)ihp; 552 void *cookie; 553 554 if (ih->ih_msi) { 555 uint64_t addr, data; 556 pcireg_t reg; 557 int off; 558 559 /* Assume hardware passes Requester ID as sideband data. */ 560 data = pci_requester_id(ih->ih_pc, ih->ih_tag); 561 cookie = fdt_intr_establish_msi(sc->sc_node, &addr, 562 &data, level, func, arg, name); 563 if (cookie == NULL) 564 return NULL; 565 566 /* TODO: translate address to the PCI device's view */ 567 568 if (pci_get_capability(ih->ih_pc, ih->ih_tag, PCI_CAP_MSI, 569 &off, ®) == 0) 570 panic("%s: no msi capability", __func__); 571 572 if (reg & PCI_MSI_MC_C64) { 573 pci_conf_write(ih->ih_pc, ih->ih_tag, 574 off + PCI_MSI_MA, addr); 575 pci_conf_write(ih->ih_pc, ih->ih_tag, 576 off + PCI_MSI_MAU32, addr >> 32); 577 pci_conf_write(ih->ih_pc, ih->ih_tag, 578 off + PCI_MSI_MD64, data); 579 } else { 580 pci_conf_write(ih->ih_pc, ih->ih_tag, 581 off + PCI_MSI_MA, addr); 582 pci_conf_write(ih->ih_pc, ih->ih_tag, 583 off + PCI_MSI_MD32, data); 584 } 585 pci_conf_write(ih->ih_pc, ih->ih_tag, 586 off, reg | PCI_MSI_MC_MSIE); 587 } else { 588 /* Unmask legacy interrupts. */ 589 HWRITE4(sc, PCIE_CLIENT_INT_MASK, 590 PCIE_CLIENT_INTA_UNMASK | PCIE_CLIENT_INTB_UNMASK | 591 PCIE_CLIENT_INTC_UNMASK | PCIE_CLIENT_INTD_UNMASK); 592 593 cookie = fdt_intr_establish_idx(sc->sc_node, 1, level, 594 func, arg, name); 595 } 596 597 free(ih, M_DEVBUF, sizeof(struct rkpcie_intr_handle)); 598 return cookie; 599 } 600 601 void 602 rkpcie_intr_disestablish(void *v, void *cookie) 603 { 604 } 605 606 /* 607 * PHY Support. 608 */ 609 610 #define RK3399_GRF_SOC_CON5_PCIE 0xe214 611 #define RK3399_TX_ELEC_IDLE_OFF_MASK ((1 << 3) << 16) 612 #define RK3399_TX_ELEC_IDLE_OFF (1 << 3) 613 #define RK3399_GRF_SOC_CON8 0xe220 614 #define RK3399_PCIE_TEST_DATA_MASK ((0xf << 7) << 16) 615 #define RK3399_PCIE_TEST_DATA_SHIFT 7 616 #define RK3399_PCIE_TEST_ADDR_MASK ((0x3f << 1) << 16) 617 #define RK3399_PCIE_TEST_ADDR_SHIFT 1 618 #define RK3399_PCIE_TEST_WRITE_ENABLE (((1 << 0) << 16) | (1 << 0)) 619 #define RK3399_PCIE_TEST_WRITE_DISABLE (((1 << 0) << 16) | (0 << 0)) 620 #define RK3399_GRF_SOC_STATUS1 0xe2a4 621 #define RK3399_PCIE_PHY_PLL_LOCKED (1 << 9) 622 #define RK3399_PCIE_PHY_PLL_OUTPUT (1 << 10) 623 624 #define RK3399_PCIE_PHY_CFG_PLL_LOCK 0x10 625 #define RK3399_PCIE_PHY_CFG_CLK_TEST 0x10 626 #define RK3399_PCIE_PHY_CFG_SEPE_RATE (1 << 3) 627 #define RK3399_PCIE_PHY_CFG_CLK_SCC 0x12 628 #define RK3399_PCIE_PHY_CFG_PLL_100M (1 << 3) 629 630 void 631 rkpcie_phy_init(struct rkpcie_softc *sc) 632 { 633 uint32_t phys[8]; 634 int len; 635 636 len = OF_getpropintarray(sc->sc_node, "phys", phys, sizeof(phys)); 637 if (len < sizeof(phys[0])) 638 return; 639 640 sc->sc_phy_node = OF_getnodebyphandle(phys[0]); 641 if (sc->sc_phy_node == 0) 642 return; 643 644 clock_enable(sc->sc_phy_node, "refclk"); 645 reset_assert(sc->sc_phy_node, "phy"); 646 } 647 648 void 649 rkpcie_phy_write_conf(struct regmap *rm, uint8_t addr, uint8_t data) 650 { 651 regmap_write_4(rm, RK3399_GRF_SOC_CON8, 652 RK3399_PCIE_TEST_ADDR_MASK | 653 (addr << RK3399_PCIE_TEST_ADDR_SHIFT) | 654 RK3399_PCIE_TEST_DATA_MASK | 655 (data << RK3399_PCIE_TEST_DATA_SHIFT) | 656 RK3399_PCIE_TEST_WRITE_DISABLE); 657 delay(1); 658 regmap_write_4(rm, RK3399_GRF_SOC_CON8, 659 RK3399_PCIE_TEST_WRITE_ENABLE); 660 delay(1); 661 regmap_write_4(rm, RK3399_GRF_SOC_CON8, 662 RK3399_PCIE_TEST_WRITE_DISABLE); 663 } 664 665 void 666 rkpcie_phy_poweron(struct rkpcie_softc *sc) 667 { 668 struct regmap *rm; 669 uint32_t status; 670 int lane = 0; 671 int timo; 672 673 reset_deassert(sc->sc_phy_node, "phy"); 674 675 rm = regmap_bynode(OF_parent(sc->sc_phy_node)); 676 if (rm == NULL) 677 return; 678 679 regmap_write_4(rm, RK3399_GRF_SOC_CON8, 680 RK3399_PCIE_TEST_ADDR_MASK | 681 RK3399_PCIE_PHY_CFG_PLL_LOCK << RK3399_PCIE_TEST_ADDR_SHIFT); 682 regmap_write_4(rm, RK3399_GRF_SOC_CON5_PCIE, 683 RK3399_TX_ELEC_IDLE_OFF_MASK << lane | 0); 684 685 for (timo = 50; timo > 0; timo--) { 686 status = regmap_read_4(rm, RK3399_GRF_SOC_STATUS1); 687 if (status & RK3399_PCIE_PHY_PLL_LOCKED) 688 break; 689 delay(20000); 690 } 691 if (timo == 0) { 692 printf("%s: PHY PLL lock timeout\n", sc->sc_dev.dv_xname); 693 return; 694 } 695 696 rkpcie_phy_write_conf(rm, RK3399_PCIE_PHY_CFG_CLK_TEST, 697 RK3399_PCIE_PHY_CFG_SEPE_RATE); 698 rkpcie_phy_write_conf(rm, RK3399_PCIE_PHY_CFG_CLK_SCC, 699 RK3399_PCIE_PHY_CFG_PLL_100M); 700 701 for (timo = 50; timo > 0; timo--) { 702 status = regmap_read_4(rm, RK3399_GRF_SOC_STATUS1); 703 if ((status & RK3399_PCIE_PHY_PLL_OUTPUT) == 0) 704 break; 705 delay(20000); 706 } 707 if (timo == 0) { 708 printf("%s: PHY PLL output enable timeout\n", 709 sc->sc_dev.dv_xname); 710 return; 711 } 712 713 regmap_write_4(rm, RK3399_GRF_SOC_CON8, 714 RK3399_PCIE_TEST_ADDR_MASK | 715 RK3399_PCIE_PHY_CFG_PLL_LOCK << RK3399_PCIE_TEST_ADDR_SHIFT); 716 717 for (timo = 50; timo > 0; timo--) { 718 status = regmap_read_4(rm, RK3399_GRF_SOC_STATUS1); 719 if (status & RK3399_PCIE_PHY_PLL_LOCKED) 720 break; 721 delay(20000); 722 } 723 if (timo == 0) { 724 printf("%s: PHY PLL relock timeout\n", sc->sc_dev.dv_xname); 725 return; 726 } 727 } 728