1 /* $OpenBSD: rkpcie.c,v 1.8 2019/06/03 00:43:26 kettenis Exp $ */ 2 /* 3 * Copyright (c) 2018 Mark Kettenis <kettenis@openbsd.org> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #include <sys/param.h> 19 #include <sys/systm.h> 20 #include <sys/device.h> 21 #include <sys/extent.h> 22 #include <sys/malloc.h> 23 24 #include <machine/intr.h> 25 #include <machine/bus.h> 26 #include <machine/fdt.h> 27 28 #include <dev/pci/pcidevs.h> 29 #include <dev/pci/pcireg.h> 30 #include <dev/pci/pcivar.h> 31 32 #include <dev/ofw/openfirm.h> 33 #include <dev/ofw/ofw_clock.h> 34 #include <dev/ofw/ofw_gpio.h> 35 #include <dev/ofw/ofw_misc.h> 36 #include <dev/ofw/fdt.h> 37 38 #define PCIE_CLIENT_BASIC_STRAP_CONF 0x0000 39 #define PCIE_CLIENT_PCIE_GEN_SEL_1 (((1 << 7) << 16) | (0 << 7)) 40 #define PCIE_CLIENT_PCIE_GEN_SEL_2 (((1 << 7) << 16) | (1 << 7)) 41 #define PCIE_CLIENT_MODE_SELECT_RC (((1 << 6) << 16) | (1 << 6)) 42 #define PCIE_CLIENT_LINK_TRAIN_EN (((1 << 1) << 16) | (1 << 1)) 43 #define PCIE_CLIENT_CONF_EN (((1 << 0) << 16) | (1 << 0)) 44 #define PCIE_CLIENT_BASIC_STATUS1 0x0048 45 #define PCIE_CLIENT_LINK_ST (0x3 << 20) 46 #define PCIE_CLIENT_LINK_ST_UP (0x3 << 20) 47 #define PCIE_CLIENT_INT_MASK 0x004c 48 #define PCIE_CLIENT_INTD_MASK (((1 << 8) << 16) | (1 << 8)) 49 #define PCIE_CLIENT_INTD_UNMASK (((1 << 8) << 16) | (0 << 8)) 50 #define PCIE_CLIENT_INTC_MASK (((1 << 7) << 16) | (1 << 7)) 51 #define PCIE_CLIENT_INTC_UNMASK (((1 << 7) << 16) | (0 << 7)) 52 #define PCIE_CLIENT_INTB_MASK (((1 << 6) << 16) | (1 << 6)) 53 #define PCIE_CLIENT_INTB_UNMASK (((1 << 6) << 16) | (0 << 6)) 54 #define PCIE_CLIENT_INTA_MASK (((1 << 5) << 16) | (1 << 5)) 55 #define PCIE_CLIENT_INTA_UNMASK (((1 << 5) << 16) | (0 << 5)) 56 57 #define PCIE_RC_NORMAL_BASE 0x800000 58 59 #define PCIE_LM_BASE 0x900000 60 #define PCIE_LM_VENDOR_ID (PCIE_LM_BASE + 0x44) 61 #define PCIE_LM_RCBAR (PCIE_LM_BASE + 0x300) 62 #define PCIE_LM_RCBARPIE (1 << 19) 63 #define PCIE_LM_RCBARPIS (1 << 20) 64 65 #define PCIE_RC_BASE 0xa00000 66 #define PCIE_RC_PCIE_LCAP (PCIE_RC_BASE + 0x0cc) 67 #define PCIE_RC_PCIE_LCAP_APMS_L0S (1 << 10) 68 69 #define PCIE_ATR_BASE 0xc00000 70 #define PCIE_ATR_OB_ADDR0(i) (PCIE_ATR_BASE + 0x000 + (i) * 0x20) 71 #define PCIE_ATR_OB_ADDR1(i) (PCIE_ATR_BASE + 0x004 + (i) * 0x20) 72 #define PCIE_ATR_OB_DESC0(i) (PCIE_ATR_BASE + 0x008 + (i) * 0x20) 73 #define PCIE_ATR_OB_DESC1(i) (PCIE_ATR_BASE + 0x00c + (i) * 0x20) 74 #define PCIE_ATR_IB_ADDR0(i) (PCIE_ATR_BASE + 0x800 + (i) * 0x8) 75 #define PCIE_ATR_IB_ADDR1(i) (PCIE_ATR_BASE + 0x804 + (i) * 0x8) 76 #define PCIE_ATR_HDR_MEM 0x2 77 #define PCIE_ATR_HDR_IO 0x6 78 #define PCIE_ATR_HDR_CFG_TYPE0 0xa 79 #define PCIE_ATR_HDR_CFG_TYPE1 0xb 80 #define PCIE_ATR_HDR_RID (1 << 23) 81 82 #define PCIE_ATR_OB_REGION0_SIZE (32 * 1024 * 1024) 83 #define PCIE_ATR_OB_REGION_SIZE (1 * 1024 * 1024) 84 85 #define HREAD4(sc, reg) \ 86 (bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg))) 87 #define HWRITE4(sc, reg, val) \ 88 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 89 90 struct rkpcie_softc { 91 struct device sc_dev; 92 bus_space_tag_t sc_iot; 93 bus_space_handle_t sc_ioh; 94 bus_space_handle_t sc_axi_ioh; 95 bus_addr_t sc_axi_addr; 96 bus_addr_t sc_apb_addr; 97 int sc_node; 98 int sc_phy_node; 99 100 struct arm64_pci_chipset sc_pc; 101 struct extent *sc_busex; 102 struct extent *sc_memex; 103 struct extent *sc_ioex; 104 int sc_bus; 105 }; 106 107 int rkpcie_match(struct device *, void *, void *); 108 void rkpcie_attach(struct device *, struct device *, void *); 109 110 struct cfattach rkpcie_ca = { 111 sizeof (struct rkpcie_softc), rkpcie_match, rkpcie_attach 112 }; 113 114 struct cfdriver rkpcie_cd = { 115 NULL, "rkpcie", DV_DULL 116 }; 117 118 int 119 rkpcie_match(struct device *parent, void *match, void *aux) 120 { 121 struct fdt_attach_args *faa = aux; 122 123 return OF_is_compatible(faa->fa_node, "rockchip,rk3399-pcie"); 124 } 125 126 void rkpcie_atr_init(struct rkpcie_softc *); 127 void rkpcie_phy_init(struct rkpcie_softc *); 128 void rkpcie_phy_poweron(struct rkpcie_softc *); 129 130 void rkpcie_attach_hook(struct device *, struct device *, 131 struct pcibus_attach_args *); 132 int rkpcie_bus_maxdevs(void *, int); 133 pcitag_t rkpcie_make_tag(void *, int, int, int); 134 void rkpcie_decompose_tag(void *, pcitag_t, int *, int *, int *); 135 int rkpcie_conf_size(void *, pcitag_t); 136 pcireg_t rkpcie_conf_read(void *, pcitag_t, int); 137 void rkpcie_conf_write(void *, pcitag_t, int, pcireg_t); 138 139 int rkpcie_intr_map(struct pci_attach_args *, pci_intr_handle_t *); 140 const char *rkpcie_intr_string(void *, pci_intr_handle_t); 141 void *rkpcie_intr_establish(void *, pci_intr_handle_t, int, 142 int (*)(void *), void *, char *); 143 void rkpcie_intr_disestablish(void *, void *); 144 145 void 146 rkpcie_attach(struct device *parent, struct device *self, void *aux) 147 { 148 struct rkpcie_softc *sc = (struct rkpcie_softc *)self; 149 struct fdt_attach_args *faa = aux; 150 struct pcibus_attach_args pba; 151 uint32_t *ep_gpio; 152 uint32_t bus_range[2]; 153 uint32_t status; 154 int len, timo; 155 156 if (faa->fa_nreg < 2) { 157 printf(": no registers\n"); 158 return; 159 } 160 161 sc->sc_iot = faa->fa_iot; 162 163 if (bus_space_map(sc->sc_iot, faa->fa_reg[1].addr, 164 faa->fa_reg[1].size, 0, &sc->sc_ioh)) { 165 printf(": can't map registers\n"); 166 return; 167 } 168 169 if (bus_space_map(sc->sc_iot, faa->fa_reg[0].addr, 170 faa->fa_reg[0].size, 0, &sc->sc_axi_ioh)) { 171 printf(": can't map AXI registers\n"); 172 bus_space_unmap(sc->sc_iot, sc->sc_ioh, faa->fa_reg[1].size); 173 return; 174 } 175 176 sc->sc_axi_addr = faa->fa_reg[0].addr; 177 sc->sc_apb_addr = faa->fa_reg[1].addr; 178 sc->sc_node = faa->fa_node; 179 printf("\n"); 180 181 len = OF_getproplen(sc->sc_node, "ep-gpios"); 182 if (len < 0) 183 return; 184 185 ep_gpio = malloc(len, M_TEMP, M_WAITOK); 186 OF_getpropintarray(sc->sc_node, "ep-gpios", ep_gpio, len); 187 188 clock_enable_all(sc->sc_node); 189 190 gpio_controller_config_pin(ep_gpio, GPIO_CONFIG_OUTPUT); 191 gpio_controller_set_pin(ep_gpio, 0); 192 193 reset_assert(sc->sc_node, "aclk"); 194 reset_assert(sc->sc_node, "pclk"); 195 reset_assert(sc->sc_node, "pm"); 196 197 rkpcie_phy_init(sc); 198 199 reset_assert(sc->sc_node, "core"); 200 reset_assert(sc->sc_node, "mgmt"); 201 reset_assert(sc->sc_node, "mgmt-sticky"); 202 reset_assert(sc->sc_node, "pipe"); 203 204 delay(10); 205 206 reset_deassert(sc->sc_node, "pm"); 207 reset_deassert(sc->sc_node, "aclk"); 208 reset_deassert(sc->sc_node, "pclk"); 209 210 /* Only advertise Gen 1 support for now. */ 211 HWRITE4(sc, PCIE_CLIENT_BASIC_STRAP_CONF, PCIE_CLIENT_PCIE_GEN_SEL_1); 212 213 /* Switch into Root Complex mode. */ 214 HWRITE4(sc, PCIE_CLIENT_BASIC_STRAP_CONF, 215 PCIE_CLIENT_MODE_SELECT_RC | PCIE_CLIENT_CONF_EN); 216 217 rkpcie_phy_poweron(sc); 218 219 reset_deassert(sc->sc_node, "core"); 220 reset_deassert(sc->sc_node, "mgmt"); 221 reset_deassert(sc->sc_node, "mgmt-sticky"); 222 reset_deassert(sc->sc_node, "pipe"); 223 224 /* Start link training. */ 225 HWRITE4(sc, PCIE_CLIENT_BASIC_STRAP_CONF, PCIE_CLIENT_LINK_TRAIN_EN); 226 227 /* XXX Advertise power limits? */ 228 229 gpio_controller_set_pin(ep_gpio, 1); 230 free(ep_gpio, M_TEMP, len); 231 232 for (timo = 500; timo > 0; timo--) { 233 status = HREAD4(sc, PCIE_CLIENT_BASIC_STATUS1); 234 if ((status & PCIE_CLIENT_LINK_ST) == PCIE_CLIENT_LINK_ST_UP) 235 break; 236 delay(1000); 237 } 238 if (timo == 0) { 239 printf("%s: link training timeout\n", sc->sc_dev.dv_xname); 240 return; 241 } 242 243 /* Initialize Root Complex registers. */ 244 HWRITE4(sc, PCIE_LM_VENDOR_ID, PCI_VENDOR_ROCKCHIP); 245 HWRITE4(sc, PCIE_RC_BASE + PCI_CLASS_REG, 246 PCI_CLASS_BRIDGE << PCI_CLASS_SHIFT | 247 PCI_SUBCLASS_BRIDGE_PCI << PCI_SUBCLASS_SHIFT); 248 HWRITE4(sc, PCIE_LM_RCBAR, PCIE_LM_RCBARPIE | PCIE_LM_RCBARPIS); 249 250 if (OF_getproplen(sc->sc_node, "aspm-no-l0s") == 0) { 251 status = HREAD4(sc, PCIE_RC_PCIE_LCAP); 252 status &= ~PCIE_RC_PCIE_LCAP_APMS_L0S; 253 HWRITE4(sc, PCIE_RC_PCIE_LCAP, status); 254 } 255 256 /* Create extents for our address spaces. */ 257 sc->sc_busex = extent_create("pcibus", 0, 255, 258 M_DEVBUF, NULL, 0, EX_WAITOK | EX_FILLED); 259 sc->sc_memex = extent_create("pcimem", 0, (u_long)-1, 260 M_DEVBUF, NULL, 0, EX_WAITOK | EX_FILLED); 261 sc->sc_ioex = extent_create("pciio", 0, 0xffffffff, 262 M_DEVBUF, NULL, 0, EX_WAITOK | EX_FILLED); 263 264 /* Set up bus range. */ 265 if (OF_getpropintarray(sc->sc_node, "bus-range", bus_range, 266 sizeof(bus_range)) != sizeof(bus_range) || 267 bus_range[0] >= 32 || bus_range[1] >= 32) { 268 bus_range[0] = 0; 269 bus_range[1] = 31; 270 } 271 sc->sc_bus = bus_range[0]; 272 extent_free(sc->sc_busex, bus_range[0], 273 bus_range[1] - bus_range[0] + 1, EX_WAITOK); 274 275 /* Configure Address Translation. */ 276 rkpcie_atr_init(sc); 277 278 sc->sc_pc.pc_conf_v = sc; 279 sc->sc_pc.pc_attach_hook = rkpcie_attach_hook; 280 sc->sc_pc.pc_bus_maxdevs = rkpcie_bus_maxdevs; 281 sc->sc_pc.pc_make_tag = rkpcie_make_tag; 282 sc->sc_pc.pc_decompose_tag = rkpcie_decompose_tag; 283 sc->sc_pc.pc_conf_size = rkpcie_conf_size; 284 sc->sc_pc.pc_conf_read = rkpcie_conf_read; 285 sc->sc_pc.pc_conf_write = rkpcie_conf_write; 286 287 sc->sc_pc.pc_intr_v = sc; 288 sc->sc_pc.pc_intr_map = rkpcie_intr_map; 289 sc->sc_pc.pc_intr_map_msi = _pci_intr_map_msi; 290 sc->sc_pc.pc_intr_map_msix = _pci_intr_map_msix; 291 sc->sc_pc.pc_intr_string = rkpcie_intr_string; 292 sc->sc_pc.pc_intr_establish = rkpcie_intr_establish; 293 sc->sc_pc.pc_intr_disestablish = rkpcie_intr_disestablish; 294 295 memset(&pba, 0, sizeof(pba)); 296 pba.pba_busname = "pci"; 297 pba.pba_iot = faa->fa_iot; 298 pba.pba_memt = faa->fa_iot; 299 pba.pba_dmat = faa->fa_dmat; 300 pba.pba_pc = &sc->sc_pc; 301 pba.pba_busex = sc->sc_busex; 302 pba.pba_memex = sc->sc_memex; 303 pba.pba_ioex = sc->sc_ioex; 304 pba.pba_domain = pci_ndomains++; 305 pba.pba_bus = sc->sc_bus; 306 pba.pba_flags |= PCI_FLAGS_MSI_ENABLED; 307 308 config_found(self, &pba, NULL); 309 } 310 311 void 312 rkpcie_atr_init(struct rkpcie_softc *sc) 313 { 314 uint32_t *ranges = NULL; 315 struct extent *ex; 316 bus_addr_t addr; 317 bus_size_t size, offset; 318 uint32_t type; 319 int len, region; 320 int i; 321 322 /* Use region 0 to map PCI configuration space. */ 323 HWRITE4(sc, PCIE_ATR_OB_ADDR0(0), 25 - 1); 324 HWRITE4(sc, PCIE_ATR_OB_ADDR1(0), 0); 325 HWRITE4(sc, PCIE_ATR_OB_DESC0(0), 326 PCIE_ATR_HDR_CFG_TYPE0 | PCIE_ATR_HDR_RID); 327 HWRITE4(sc, PCIE_ATR_OB_DESC1(0), 0); 328 329 len = OF_getproplen(sc->sc_node, "ranges"); 330 if (len <= 0 || (len % (7 * sizeof(uint32_t))) != 0) 331 goto fail; 332 ranges = malloc(len, M_TEMP, M_WAITOK); 333 OF_getpropintarray(sc->sc_node, "ranges", ranges, len); 334 335 for (i = 0; i < len / sizeof(uint32_t); i += 7) { 336 /* Handle IO and MMIO. */ 337 switch (ranges[i] & 0x03000000) { 338 case 0x01000000: 339 type = PCIE_ATR_HDR_IO; 340 ex = sc->sc_ioex; 341 break; 342 case 0x02000000: 343 case 0x03000000: 344 type = PCIE_ATR_HDR_MEM; 345 ex = sc->sc_memex; 346 break; 347 default: 348 continue; 349 } 350 351 /* Only support identity mappings. */ 352 if (ranges[i + 1] != ranges[i + 3] || 353 ranges[i + 2] != ranges[i + 4]) 354 goto fail; 355 356 /* Only support mappings aligned on a region boundary. */ 357 addr = ((uint64_t)ranges[i + 1] << 32) + ranges[i + 2]; 358 if (addr & (PCIE_ATR_OB_REGION_SIZE - 1)) 359 goto fail; 360 361 /* Mappings should lie between AXI and APB regions. */ 362 size = ranges[i + 6]; 363 if (addr < sc->sc_axi_addr + PCIE_ATR_OB_REGION0_SIZE) 364 goto fail; 365 if (addr + size > sc->sc_apb_addr) 366 goto fail; 367 368 offset = addr - sc->sc_axi_addr - PCIE_ATR_OB_REGION0_SIZE; 369 region = 1 + (offset / PCIE_ATR_OB_REGION_SIZE); 370 while (size > 0) { 371 HWRITE4(sc, PCIE_ATR_OB_ADDR0(region), 32 - 1); 372 HWRITE4(sc, PCIE_ATR_OB_ADDR1(region), 0); 373 HWRITE4(sc, PCIE_ATR_OB_DESC0(region), 374 type | PCIE_ATR_HDR_RID); 375 HWRITE4(sc, PCIE_ATR_OB_DESC1(region), 0); 376 377 extent_free(ex, addr, PCIE_ATR_OB_REGION_SIZE, 378 EX_WAITOK); 379 addr += PCIE_ATR_OB_REGION_SIZE; 380 size -= PCIE_ATR_OB_REGION_SIZE; 381 region++; 382 } 383 } 384 385 /* Passthrought inbound translations unmodified. */ 386 HWRITE4(sc, PCIE_ATR_IB_ADDR0(2), 32 - 1); 387 HWRITE4(sc, PCIE_ATR_IB_ADDR1(2), 0); 388 389 free(ranges, M_TEMP, len); 390 return; 391 392 fail: 393 printf("%s: can't map ranges\n", sc->sc_dev.dv_xname); 394 free(ranges, M_TEMP, len); 395 } 396 397 void 398 rkpcie_attach_hook(struct device *parent, struct device *self, 399 struct pcibus_attach_args *pba) 400 { 401 } 402 403 int 404 rkpcie_bus_maxdevs(void *v, int bus) 405 { 406 struct rkpcie_softc *sc = v; 407 408 if (bus == sc->sc_bus || bus == sc->sc_bus + 1) 409 return 1; 410 return 32; 411 } 412 413 pcitag_t 414 rkpcie_make_tag(void *v, int bus, int device, int function) 415 { 416 /* Return ECAM address. */ 417 return ((bus << 20) | (device << 15) | (function << 12)); 418 } 419 420 void 421 rkpcie_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 422 { 423 if (bp != NULL) 424 *bp = (tag >> 20) & 0xff; 425 if (dp != NULL) 426 *dp = (tag >> 15) & 0x1f; 427 if (fp != NULL) 428 *fp = (tag >> 12) & 0x7; 429 } 430 431 int 432 rkpcie_conf_size(void *v, pcitag_t tag) 433 { 434 return PCIE_CONFIG_SPACE_SIZE; 435 } 436 437 pcireg_t 438 rkpcie_conf_read(void *v, pcitag_t tag, int reg) 439 { 440 struct rkpcie_softc *sc = v; 441 int bus, dev, fn; 442 443 rkpcie_decompose_tag(sc, tag, &bus, &dev, &fn); 444 if (bus == sc->sc_bus) { 445 KASSERT(dev == 0); 446 return HREAD4(sc, PCIE_RC_NORMAL_BASE + tag | reg); 447 } 448 if (bus == sc->sc_bus + 1) { 449 KASSERT(dev == 0); 450 return bus_space_read_4(sc->sc_iot, sc->sc_axi_ioh, tag | reg); 451 } 452 453 return 0xffffffff; 454 } 455 456 void 457 rkpcie_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data) 458 { 459 struct rkpcie_softc *sc = v; 460 int bus, dev, fn; 461 462 rkpcie_decompose_tag(sc, tag, &bus, &dev, &fn); 463 if (bus == sc->sc_bus) { 464 KASSERT(dev == 0); 465 HWRITE4(sc, PCIE_RC_NORMAL_BASE + tag | reg, data); 466 return; 467 } 468 if (bus == sc->sc_bus + 1) { 469 KASSERT(dev == 0); 470 bus_space_write_4(sc->sc_iot, sc->sc_axi_ioh, tag | reg, data); 471 return; 472 } 473 } 474 475 int 476 rkpcie_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 477 { 478 int pin = pa->pa_rawintrpin; 479 480 if (pin == 0 || pin > PCI_INTERRUPT_PIN_MAX) 481 return -1; 482 483 if (pa->pa_tag == 0) 484 return -1; 485 486 ihp->ih_pc = pa->pa_pc; 487 ihp->ih_tag = pa->pa_intrtag; 488 ihp->ih_intrpin = pa->pa_intrpin; 489 ihp->ih_type = PCI_INTX; 490 491 return 0; 492 } 493 494 const char * 495 rkpcie_intr_string(void *v, pci_intr_handle_t ih) 496 { 497 switch (ih.ih_type) { 498 case PCI_MSI: 499 return "msi"; 500 case PCI_MSIX: 501 return "msix"; 502 } 503 504 return "intx"; 505 } 506 507 void * 508 rkpcie_intr_establish(void *v, pci_intr_handle_t ih, int level, 509 int (*func)(void *), void *arg, char *name) 510 { 511 struct rkpcie_softc *sc = v; 512 void *cookie; 513 514 KASSERT(ih.ih_type != PCI_NONE); 515 516 if (ih.ih_type != PCI_INTX) { 517 uint64_t addr, data; 518 519 /* Assume hardware passes Requester ID as sideband data. */ 520 data = pci_requester_id(ih.ih_pc, ih.ih_tag); 521 cookie = fdt_intr_establish_msi(sc->sc_node, &addr, 522 &data, level, func, arg, name); 523 if (cookie == NULL) 524 return NULL; 525 526 /* TODO: translate address to the PCI device's view */ 527 528 if (ih.ih_type == PCI_MSIX) { 529 pci_msix_enable(ih.ih_pc, ih.ih_tag, 530 sc->sc_iot, ih.ih_intrpin, addr, data); 531 } else 532 pci_msi_enable(ih.ih_pc, ih.ih_tag, addr, data); 533 } else { 534 /* Unmask legacy interrupts. */ 535 HWRITE4(sc, PCIE_CLIENT_INT_MASK, 536 PCIE_CLIENT_INTA_UNMASK | PCIE_CLIENT_INTB_UNMASK | 537 PCIE_CLIENT_INTC_UNMASK | PCIE_CLIENT_INTD_UNMASK); 538 539 cookie = fdt_intr_establish_idx(sc->sc_node, 1, level, 540 func, arg, name); 541 } 542 543 return cookie; 544 } 545 546 void 547 rkpcie_intr_disestablish(void *v, void *cookie) 548 { 549 } 550 551 /* 552 * PHY Support. 553 */ 554 555 #define RK3399_GRF_SOC_CON5_PCIE 0xe214 556 #define RK3399_TX_ELEC_IDLE_OFF_MASK ((1 << 3) << 16) 557 #define RK3399_TX_ELEC_IDLE_OFF (1 << 3) 558 #define RK3399_GRF_SOC_CON8 0xe220 559 #define RK3399_PCIE_TEST_DATA_MASK ((0xf << 7) << 16) 560 #define RK3399_PCIE_TEST_DATA_SHIFT 7 561 #define RK3399_PCIE_TEST_ADDR_MASK ((0x3f << 1) << 16) 562 #define RK3399_PCIE_TEST_ADDR_SHIFT 1 563 #define RK3399_PCIE_TEST_WRITE_ENABLE (((1 << 0) << 16) | (1 << 0)) 564 #define RK3399_PCIE_TEST_WRITE_DISABLE (((1 << 0) << 16) | (0 << 0)) 565 #define RK3399_GRF_SOC_STATUS1 0xe2a4 566 #define RK3399_PCIE_PHY_PLL_LOCKED (1 << 9) 567 #define RK3399_PCIE_PHY_PLL_OUTPUT (1 << 10) 568 569 #define RK3399_PCIE_PHY_CFG_PLL_LOCK 0x10 570 #define RK3399_PCIE_PHY_CFG_CLK_TEST 0x10 571 #define RK3399_PCIE_PHY_CFG_SEPE_RATE (1 << 3) 572 #define RK3399_PCIE_PHY_CFG_CLK_SCC 0x12 573 #define RK3399_PCIE_PHY_CFG_PLL_100M (1 << 3) 574 575 void 576 rkpcie_phy_init(struct rkpcie_softc *sc) 577 { 578 uint32_t phys[8]; 579 int len; 580 581 len = OF_getpropintarray(sc->sc_node, "phys", phys, sizeof(phys)); 582 if (len < sizeof(phys[0])) 583 return; 584 585 sc->sc_phy_node = OF_getnodebyphandle(phys[0]); 586 if (sc->sc_phy_node == 0) 587 return; 588 589 clock_enable(sc->sc_phy_node, "refclk"); 590 reset_assert(sc->sc_phy_node, "phy"); 591 } 592 593 void 594 rkpcie_phy_write_conf(struct regmap *rm, uint8_t addr, uint8_t data) 595 { 596 regmap_write_4(rm, RK3399_GRF_SOC_CON8, 597 RK3399_PCIE_TEST_ADDR_MASK | 598 (addr << RK3399_PCIE_TEST_ADDR_SHIFT) | 599 RK3399_PCIE_TEST_DATA_MASK | 600 (data << RK3399_PCIE_TEST_DATA_SHIFT) | 601 RK3399_PCIE_TEST_WRITE_DISABLE); 602 delay(1); 603 regmap_write_4(rm, RK3399_GRF_SOC_CON8, 604 RK3399_PCIE_TEST_WRITE_ENABLE); 605 delay(1); 606 regmap_write_4(rm, RK3399_GRF_SOC_CON8, 607 RK3399_PCIE_TEST_WRITE_DISABLE); 608 } 609 610 void 611 rkpcie_phy_poweron(struct rkpcie_softc *sc) 612 { 613 struct regmap *rm; 614 uint32_t status; 615 int lane = 0; 616 int timo; 617 618 reset_deassert(sc->sc_phy_node, "phy"); 619 620 rm = regmap_bynode(OF_parent(sc->sc_phy_node)); 621 if (rm == NULL) 622 return; 623 624 regmap_write_4(rm, RK3399_GRF_SOC_CON8, 625 RK3399_PCIE_TEST_ADDR_MASK | 626 RK3399_PCIE_PHY_CFG_PLL_LOCK << RK3399_PCIE_TEST_ADDR_SHIFT); 627 regmap_write_4(rm, RK3399_GRF_SOC_CON5_PCIE, 628 RK3399_TX_ELEC_IDLE_OFF_MASK << lane | 0); 629 630 for (timo = 50; timo > 0; timo--) { 631 status = regmap_read_4(rm, RK3399_GRF_SOC_STATUS1); 632 if (status & RK3399_PCIE_PHY_PLL_LOCKED) 633 break; 634 delay(20000); 635 } 636 if (timo == 0) { 637 printf("%s: PHY PLL lock timeout\n", sc->sc_dev.dv_xname); 638 return; 639 } 640 641 rkpcie_phy_write_conf(rm, RK3399_PCIE_PHY_CFG_CLK_TEST, 642 RK3399_PCIE_PHY_CFG_SEPE_RATE); 643 rkpcie_phy_write_conf(rm, RK3399_PCIE_PHY_CFG_CLK_SCC, 644 RK3399_PCIE_PHY_CFG_PLL_100M); 645 646 for (timo = 50; timo > 0; timo--) { 647 status = regmap_read_4(rm, RK3399_GRF_SOC_STATUS1); 648 if ((status & RK3399_PCIE_PHY_PLL_OUTPUT) == 0) 649 break; 650 delay(20000); 651 } 652 if (timo == 0) { 653 printf("%s: PHY PLL output enable timeout\n", 654 sc->sc_dev.dv_xname); 655 return; 656 } 657 658 regmap_write_4(rm, RK3399_GRF_SOC_CON8, 659 RK3399_PCIE_TEST_ADDR_MASK | 660 RK3399_PCIE_PHY_CFG_PLL_LOCK << RK3399_PCIE_TEST_ADDR_SHIFT); 661 662 for (timo = 50; timo > 0; timo--) { 663 status = regmap_read_4(rm, RK3399_GRF_SOC_STATUS1); 664 if (status & RK3399_PCIE_PHY_PLL_LOCKED) 665 break; 666 delay(20000); 667 } 668 if (timo == 0) { 669 printf("%s: PHY PLL relock timeout\n", sc->sc_dev.dv_xname); 670 return; 671 } 672 } 673