1 /* $OpenBSD: rkpcie.c,v 1.11 2020/07/14 15:42:19 patrick Exp $ */ 2 /* 3 * Copyright (c) 2018 Mark Kettenis <kettenis@openbsd.org> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #include <sys/param.h> 19 #include <sys/systm.h> 20 #include <sys/device.h> 21 #include <sys/extent.h> 22 #include <sys/malloc.h> 23 24 #include <machine/intr.h> 25 #include <machine/bus.h> 26 #include <machine/fdt.h> 27 28 #include <dev/pci/pcidevs.h> 29 #include <dev/pci/pcireg.h> 30 #include <dev/pci/pcivar.h> 31 32 #include <dev/ofw/openfirm.h> 33 #include <dev/ofw/ofw_clock.h> 34 #include <dev/ofw/ofw_gpio.h> 35 #include <dev/ofw/ofw_misc.h> 36 #include <dev/ofw/fdt.h> 37 38 #define PCIE_CLIENT_BASIC_STRAP_CONF 0x0000 39 #define PCIE_CLIENT_PCIE_GEN_SEL_1 (((1 << 7) << 16) | (0 << 7)) 40 #define PCIE_CLIENT_PCIE_GEN_SEL_2 (((1 << 7) << 16) | (1 << 7)) 41 #define PCIE_CLIENT_MODE_SELECT_RC (((1 << 6) << 16) | (1 << 6)) 42 #define PCIE_CLIENT_LINK_TRAIN_EN (((1 << 1) << 16) | (1 << 1)) 43 #define PCIE_CLIENT_CONF_EN (((1 << 0) << 16) | (1 << 0)) 44 #define PCIE_CLIENT_DEBUG_OUT_0 0x003c 45 #define PCIE_CLIENT_DEBUG_LTSSM_MASK 0x0000001f 46 #define PCIE_CLIENT_DEBUG_LTSSM_L0 0x00000010 47 #define PCIE_CLIENT_BASIC_STATUS1 0x0048 48 #define PCIE_CLIENT_LINK_ST (0x3 << 20) 49 #define PCIE_CLIENT_LINK_ST_UP (0x3 << 20) 50 #define PCIE_CLIENT_INT_MASK 0x004c 51 #define PCIE_CLIENT_INTD_MASK (((1 << 8) << 16) | (1 << 8)) 52 #define PCIE_CLIENT_INTD_UNMASK (((1 << 8) << 16) | (0 << 8)) 53 #define PCIE_CLIENT_INTC_MASK (((1 << 7) << 16) | (1 << 7)) 54 #define PCIE_CLIENT_INTC_UNMASK (((1 << 7) << 16) | (0 << 7)) 55 #define PCIE_CLIENT_INTB_MASK (((1 << 6) << 16) | (1 << 6)) 56 #define PCIE_CLIENT_INTB_UNMASK (((1 << 6) << 16) | (0 << 6)) 57 #define PCIE_CLIENT_INTA_MASK (((1 << 5) << 16) | (1 << 5)) 58 #define PCIE_CLIENT_INTA_UNMASK (((1 << 5) << 16) | (0 << 5)) 59 60 #define PCIE_RC_NORMAL_BASE 0x800000 61 62 #define PCIE_LM_BASE 0x900000 63 #define PCIE_LM_VENDOR_ID (PCIE_LM_BASE + 0x44) 64 #define PCIE_LM_RCBAR (PCIE_LM_BASE + 0x300) 65 #define PCIE_LM_RCBARPIE (1 << 19) 66 #define PCIE_LM_RCBARPIS (1 << 20) 67 68 #define PCIE_RC_BASE 0xa00000 69 #define PCIE_RC_PCIE_LCAP (PCIE_RC_BASE + 0x0cc) 70 #define PCIE_RC_PCIE_LCAP_APMS_L0S (1 << 10) 71 #define PCIE_RC_LCSR (PCIE_RC_BASE + 0x0d0) 72 #define PCIE_RC_LCSR2 (PCIE_RC_BASE + 0x0f0) 73 74 #define PCIE_ATR_BASE 0xc00000 75 #define PCIE_ATR_OB_ADDR0(i) (PCIE_ATR_BASE + 0x000 + (i) * 0x20) 76 #define PCIE_ATR_OB_ADDR1(i) (PCIE_ATR_BASE + 0x004 + (i) * 0x20) 77 #define PCIE_ATR_OB_DESC0(i) (PCIE_ATR_BASE + 0x008 + (i) * 0x20) 78 #define PCIE_ATR_OB_DESC1(i) (PCIE_ATR_BASE + 0x00c + (i) * 0x20) 79 #define PCIE_ATR_IB_ADDR0(i) (PCIE_ATR_BASE + 0x800 + (i) * 0x8) 80 #define PCIE_ATR_IB_ADDR1(i) (PCIE_ATR_BASE + 0x804 + (i) * 0x8) 81 #define PCIE_ATR_HDR_MEM 0x2 82 #define PCIE_ATR_HDR_IO 0x6 83 #define PCIE_ATR_HDR_CFG_TYPE0 0xa 84 #define PCIE_ATR_HDR_CFG_TYPE1 0xb 85 #define PCIE_ATR_HDR_RID (1 << 23) 86 87 #define PCIE_ATR_OB_REGION0_SIZE (32 * 1024 * 1024) 88 #define PCIE_ATR_OB_REGION_SIZE (1 * 1024 * 1024) 89 90 #define HREAD4(sc, reg) \ 91 (bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg))) 92 #define HWRITE4(sc, reg, val) \ 93 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 94 95 struct rkpcie_softc { 96 struct device sc_dev; 97 bus_space_tag_t sc_iot; 98 bus_space_handle_t sc_ioh; 99 bus_space_handle_t sc_axi_ioh; 100 bus_addr_t sc_axi_addr; 101 bus_addr_t sc_apb_addr; 102 int sc_node; 103 int sc_phy_node; 104 105 struct arm64_pci_chipset sc_pc; 106 struct extent *sc_busex; 107 struct extent *sc_memex; 108 struct extent *sc_ioex; 109 int sc_bus; 110 }; 111 112 int rkpcie_match(struct device *, void *, void *); 113 void rkpcie_attach(struct device *, struct device *, void *); 114 115 struct cfattach rkpcie_ca = { 116 sizeof (struct rkpcie_softc), rkpcie_match, rkpcie_attach 117 }; 118 119 struct cfdriver rkpcie_cd = { 120 NULL, "rkpcie", DV_DULL 121 }; 122 123 int 124 rkpcie_match(struct device *parent, void *match, void *aux) 125 { 126 struct fdt_attach_args *faa = aux; 127 128 return OF_is_compatible(faa->fa_node, "rockchip,rk3399-pcie"); 129 } 130 131 void rkpcie_atr_init(struct rkpcie_softc *); 132 void rkpcie_phy_init(struct rkpcie_softc *); 133 void rkpcie_phy_poweron(struct rkpcie_softc *); 134 135 void rkpcie_attach_hook(struct device *, struct device *, 136 struct pcibus_attach_args *); 137 int rkpcie_bus_maxdevs(void *, int); 138 pcitag_t rkpcie_make_tag(void *, int, int, int); 139 void rkpcie_decompose_tag(void *, pcitag_t, int *, int *, int *); 140 int rkpcie_conf_size(void *, pcitag_t); 141 pcireg_t rkpcie_conf_read(void *, pcitag_t, int); 142 void rkpcie_conf_write(void *, pcitag_t, int, pcireg_t); 143 144 int rkpcie_intr_map(struct pci_attach_args *, pci_intr_handle_t *); 145 const char *rkpcie_intr_string(void *, pci_intr_handle_t); 146 void *rkpcie_intr_establish(void *, pci_intr_handle_t, int, 147 struct cpu_info *, int (*)(void *), void *, char *); 148 void rkpcie_intr_disestablish(void *, void *); 149 150 /* 151 * When link training, the LTSSM configuration state exits to L0 state upon 152 * success. Wait for L0 state before proceeding after link training has been 153 * initiated either by PCIE_CLIENT_LINK_TRAIN_EN or when triggered via 154 * LCSR Retrain Link bit. See PCIE 2.0 Base Specification, 4.2.6.3.6 155 * Configuration.Idle. 156 * 157 * Checking link up alone is not sufficient for checking for L0 state. LTSSM 158 * state L0 can be detected when link up is set and link training is cleared. 159 * See PCIE 2.0 Base Specification, 4.2.6 Link Training and Status State Rules, 160 * Table 4-8 Link Status Mapped to the LTSSM. 161 * 162 * However, RC doesn't set the link training bit when initially training via 163 * PCIE_CLIENT_LINK_TRAIN_EN. Fortunately, RC has provided a debug register 164 * that has the LTSSM state which can be checked instead. 165 * 166 * It is important to have reached L0 state before beginning Gen 2 training, 167 * as it is documented that setting the Retrain Link bit while currently 168 * in Recovery or Configuration states is a race condition that may result 169 * in missing the retraining. See See PCIE 2.0 Base Specification, 7.8.7 170 * Link Control Register implementation notes on Retrain Link bit. 171 */ 172 173 static int 174 rkpcie_link_training_wait(struct rkpcie_softc *sc) 175 { 176 uint32_t status; 177 int timo; 178 for (timo = 500; timo > 0; timo--) { 179 status = HREAD4(sc, PCIE_CLIENT_DEBUG_OUT_0); 180 if ((status & PCIE_CLIENT_DEBUG_LTSSM_MASK) == 181 PCIE_CLIENT_DEBUG_LTSSM_L0) 182 break; 183 delay(1000); 184 } 185 return timo == 0; 186 } 187 188 void 189 rkpcie_attach(struct device *parent, struct device *self, void *aux) 190 { 191 struct rkpcie_softc *sc = (struct rkpcie_softc *)self; 192 struct fdt_attach_args *faa = aux; 193 struct pcibus_attach_args pba; 194 uint32_t *ep_gpio; 195 uint32_t bus_range[2]; 196 uint32_t status; 197 uint32_t max_link_speed; 198 int len; 199 200 if (faa->fa_nreg < 2) { 201 printf(": no registers\n"); 202 return; 203 } 204 205 sc->sc_iot = faa->fa_iot; 206 207 if (bus_space_map(sc->sc_iot, faa->fa_reg[1].addr, 208 faa->fa_reg[1].size, 0, &sc->sc_ioh)) { 209 printf(": can't map registers\n"); 210 return; 211 } 212 213 if (bus_space_map(sc->sc_iot, faa->fa_reg[0].addr, 214 faa->fa_reg[0].size, 0, &sc->sc_axi_ioh)) { 215 printf(": can't map AXI registers\n"); 216 bus_space_unmap(sc->sc_iot, sc->sc_ioh, faa->fa_reg[1].size); 217 return; 218 } 219 220 sc->sc_axi_addr = faa->fa_reg[0].addr; 221 sc->sc_apb_addr = faa->fa_reg[1].addr; 222 sc->sc_node = faa->fa_node; 223 printf("\n"); 224 225 len = OF_getproplen(sc->sc_node, "ep-gpios"); 226 if (len < 0) 227 return; 228 229 ep_gpio = malloc(len, M_TEMP, M_WAITOK); 230 OF_getpropintarray(sc->sc_node, "ep-gpios", ep_gpio, len); 231 232 max_link_speed = OF_getpropint(sc->sc_node, "max-link-speed", 1); 233 234 clock_enable_all(sc->sc_node); 235 236 gpio_controller_config_pin(ep_gpio, GPIO_CONFIG_OUTPUT); 237 gpio_controller_set_pin(ep_gpio, 0); 238 239 reset_assert(sc->sc_node, "aclk"); 240 reset_assert(sc->sc_node, "pclk"); 241 reset_assert(sc->sc_node, "pm"); 242 243 rkpcie_phy_init(sc); 244 245 reset_assert(sc->sc_node, "core"); 246 reset_assert(sc->sc_node, "mgmt"); 247 reset_assert(sc->sc_node, "mgmt-sticky"); 248 reset_assert(sc->sc_node, "pipe"); 249 250 delay(10); 251 252 reset_deassert(sc->sc_node, "pm"); 253 reset_deassert(sc->sc_node, "aclk"); 254 reset_deassert(sc->sc_node, "pclk"); 255 256 if (max_link_speed > 1) 257 status = PCIE_CLIENT_PCIE_GEN_SEL_2; 258 else 259 status = PCIE_CLIENT_PCIE_GEN_SEL_1; 260 261 /* Switch into Root Complex mode. */ 262 HWRITE4(sc, PCIE_CLIENT_BASIC_STRAP_CONF, PCIE_CLIENT_MODE_SELECT_RC 263 | PCIE_CLIENT_CONF_EN | status); 264 265 rkpcie_phy_poweron(sc); 266 267 reset_deassert(sc->sc_node, "core"); 268 reset_deassert(sc->sc_node, "mgmt"); 269 reset_deassert(sc->sc_node, "mgmt-sticky"); 270 reset_deassert(sc->sc_node, "pipe"); 271 272 /* 273 * Workaround RC bug where Target Link Speed is not set by GEN_SEL_2 274 */ 275 if (max_link_speed > 1) { 276 status = HREAD4(sc, PCIE_RC_LCSR2); 277 status &= ~PCI_PCIE_LCSR2_TLS; 278 status |= PCI_PCIE_LCSR2_TLS_5; 279 HWRITE4(sc, PCIE_RC_LCSR2, status); 280 } 281 282 /* Start link training. */ 283 HWRITE4(sc, PCIE_CLIENT_BASIC_STRAP_CONF, PCIE_CLIENT_LINK_TRAIN_EN); 284 285 /* XXX Advertise power limits? */ 286 287 gpio_controller_set_pin(ep_gpio, 1); 288 free(ep_gpio, M_TEMP, len); 289 290 if (rkpcie_link_training_wait(sc)) { 291 printf("%s: link training timeout\n", sc->sc_dev.dv_xname); 292 return; 293 } 294 295 if (max_link_speed > 1) { 296 status = HREAD4(sc, PCIE_RC_LCSR); 297 if ((status & PCI_PCIE_LCSR_CLS) == PCI_PCIE_LCSR_CLS_2_5) { 298 HWRITE4(sc, PCIE_RC_LCSR, HREAD4(sc, PCIE_RC_LCSR) | 299 PCI_PCIE_LCSR_RL); 300 301 if (rkpcie_link_training_wait(sc)) { 302 /* didn't make it back to L0 state */ 303 printf("%s: gen2 link training timeout\n", 304 sc->sc_dev.dv_xname); 305 return; 306 } 307 } 308 } 309 310 /* 311 * XXX On at least the RockPro64, many cards will panic when first 312 * accessing PCIe config space during bus scanning. A delay after 313 * link training allows some of these cards to function. 314 */ 315 delay(2000000); 316 317 /* Initialize Root Complex registers. */ 318 HWRITE4(sc, PCIE_LM_VENDOR_ID, PCI_VENDOR_ROCKCHIP); 319 HWRITE4(sc, PCIE_RC_BASE + PCI_CLASS_REG, 320 PCI_CLASS_BRIDGE << PCI_CLASS_SHIFT | 321 PCI_SUBCLASS_BRIDGE_PCI << PCI_SUBCLASS_SHIFT); 322 HWRITE4(sc, PCIE_LM_RCBAR, PCIE_LM_RCBARPIE | PCIE_LM_RCBARPIS); 323 324 if (OF_getproplen(sc->sc_node, "aspm-no-l0s") == 0) { 325 status = HREAD4(sc, PCIE_RC_PCIE_LCAP); 326 status &= ~PCIE_RC_PCIE_LCAP_APMS_L0S; 327 HWRITE4(sc, PCIE_RC_PCIE_LCAP, status); 328 } 329 330 /* Create extents for our address spaces. */ 331 sc->sc_busex = extent_create("pcibus", 0, 255, 332 M_DEVBUF, NULL, 0, EX_WAITOK | EX_FILLED); 333 sc->sc_memex = extent_create("pcimem", 0, (u_long)-1, 334 M_DEVBUF, NULL, 0, EX_WAITOK | EX_FILLED); 335 sc->sc_ioex = extent_create("pciio", 0, 0xffffffff, 336 M_DEVBUF, NULL, 0, EX_WAITOK | EX_FILLED); 337 338 /* Set up bus range. */ 339 if (OF_getpropintarray(sc->sc_node, "bus-range", bus_range, 340 sizeof(bus_range)) != sizeof(bus_range) || 341 bus_range[0] >= 32 || bus_range[1] >= 32) { 342 bus_range[0] = 0; 343 bus_range[1] = 31; 344 } 345 sc->sc_bus = bus_range[0]; 346 extent_free(sc->sc_busex, bus_range[0], 347 bus_range[1] - bus_range[0] + 1, EX_WAITOK); 348 349 /* Configure Address Translation. */ 350 rkpcie_atr_init(sc); 351 352 sc->sc_pc.pc_conf_v = sc; 353 sc->sc_pc.pc_attach_hook = rkpcie_attach_hook; 354 sc->sc_pc.pc_bus_maxdevs = rkpcie_bus_maxdevs; 355 sc->sc_pc.pc_make_tag = rkpcie_make_tag; 356 sc->sc_pc.pc_decompose_tag = rkpcie_decompose_tag; 357 sc->sc_pc.pc_conf_size = rkpcie_conf_size; 358 sc->sc_pc.pc_conf_read = rkpcie_conf_read; 359 sc->sc_pc.pc_conf_write = rkpcie_conf_write; 360 361 sc->sc_pc.pc_intr_v = sc; 362 sc->sc_pc.pc_intr_map = rkpcie_intr_map; 363 sc->sc_pc.pc_intr_map_msi = _pci_intr_map_msi; 364 sc->sc_pc.pc_intr_map_msix = _pci_intr_map_msix; 365 sc->sc_pc.pc_intr_string = rkpcie_intr_string; 366 sc->sc_pc.pc_intr_establish = rkpcie_intr_establish; 367 sc->sc_pc.pc_intr_disestablish = rkpcie_intr_disestablish; 368 369 memset(&pba, 0, sizeof(pba)); 370 pba.pba_busname = "pci"; 371 pba.pba_iot = faa->fa_iot; 372 pba.pba_memt = faa->fa_iot; 373 pba.pba_dmat = faa->fa_dmat; 374 pba.pba_pc = &sc->sc_pc; 375 pba.pba_busex = sc->sc_busex; 376 pba.pba_memex = sc->sc_memex; 377 pba.pba_ioex = sc->sc_ioex; 378 pba.pba_domain = pci_ndomains++; 379 pba.pba_bus = sc->sc_bus; 380 pba.pba_flags |= PCI_FLAGS_MSI_ENABLED; 381 382 config_found(self, &pba, NULL); 383 } 384 385 void 386 rkpcie_atr_init(struct rkpcie_softc *sc) 387 { 388 uint32_t *ranges = NULL; 389 struct extent *ex; 390 bus_addr_t addr; 391 bus_size_t size, offset; 392 uint32_t type; 393 int len, region; 394 int i; 395 396 /* Use region 0 to map PCI configuration space. */ 397 HWRITE4(sc, PCIE_ATR_OB_ADDR0(0), 25 - 1); 398 HWRITE4(sc, PCIE_ATR_OB_ADDR1(0), 0); 399 HWRITE4(sc, PCIE_ATR_OB_DESC0(0), 400 PCIE_ATR_HDR_CFG_TYPE0 | PCIE_ATR_HDR_RID); 401 HWRITE4(sc, PCIE_ATR_OB_DESC1(0), 0); 402 403 len = OF_getproplen(sc->sc_node, "ranges"); 404 if (len <= 0 || (len % (7 * sizeof(uint32_t))) != 0) 405 goto fail; 406 ranges = malloc(len, M_TEMP, M_WAITOK); 407 OF_getpropintarray(sc->sc_node, "ranges", ranges, len); 408 409 for (i = 0; i < len / sizeof(uint32_t); i += 7) { 410 /* Handle IO and MMIO. */ 411 switch (ranges[i] & 0x03000000) { 412 case 0x01000000: 413 type = PCIE_ATR_HDR_IO; 414 ex = sc->sc_ioex; 415 break; 416 case 0x02000000: 417 case 0x03000000: 418 type = PCIE_ATR_HDR_MEM; 419 ex = sc->sc_memex; 420 break; 421 default: 422 continue; 423 } 424 425 /* Only support identity mappings. */ 426 if (ranges[i + 1] != ranges[i + 3] || 427 ranges[i + 2] != ranges[i + 4]) 428 goto fail; 429 430 /* Only support mappings aligned on a region boundary. */ 431 addr = ((uint64_t)ranges[i + 1] << 32) + ranges[i + 2]; 432 if (addr & (PCIE_ATR_OB_REGION_SIZE - 1)) 433 goto fail; 434 435 /* Mappings should lie between AXI and APB regions. */ 436 size = ranges[i + 6]; 437 if (addr < sc->sc_axi_addr + PCIE_ATR_OB_REGION0_SIZE) 438 goto fail; 439 if (addr + size > sc->sc_apb_addr) 440 goto fail; 441 442 offset = addr - sc->sc_axi_addr - PCIE_ATR_OB_REGION0_SIZE; 443 region = 1 + (offset / PCIE_ATR_OB_REGION_SIZE); 444 while (size > 0) { 445 HWRITE4(sc, PCIE_ATR_OB_ADDR0(region), 32 - 1); 446 HWRITE4(sc, PCIE_ATR_OB_ADDR1(region), 0); 447 HWRITE4(sc, PCIE_ATR_OB_DESC0(region), 448 type | PCIE_ATR_HDR_RID); 449 HWRITE4(sc, PCIE_ATR_OB_DESC1(region), 0); 450 451 extent_free(ex, addr, PCIE_ATR_OB_REGION_SIZE, 452 EX_WAITOK); 453 addr += PCIE_ATR_OB_REGION_SIZE; 454 size -= PCIE_ATR_OB_REGION_SIZE; 455 region++; 456 } 457 } 458 459 /* Passthrought inbound translations unmodified. */ 460 HWRITE4(sc, PCIE_ATR_IB_ADDR0(2), 32 - 1); 461 HWRITE4(sc, PCIE_ATR_IB_ADDR1(2), 0); 462 463 free(ranges, M_TEMP, len); 464 return; 465 466 fail: 467 printf("%s: can't map ranges\n", sc->sc_dev.dv_xname); 468 free(ranges, M_TEMP, len); 469 } 470 471 void 472 rkpcie_attach_hook(struct device *parent, struct device *self, 473 struct pcibus_attach_args *pba) 474 { 475 } 476 477 int 478 rkpcie_bus_maxdevs(void *v, int bus) 479 { 480 struct rkpcie_softc *sc = v; 481 482 if (bus == sc->sc_bus || bus == sc->sc_bus + 1) 483 return 1; 484 return 32; 485 } 486 487 pcitag_t 488 rkpcie_make_tag(void *v, int bus, int device, int function) 489 { 490 /* Return ECAM address. */ 491 return ((bus << 20) | (device << 15) | (function << 12)); 492 } 493 494 void 495 rkpcie_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 496 { 497 if (bp != NULL) 498 *bp = (tag >> 20) & 0xff; 499 if (dp != NULL) 500 *dp = (tag >> 15) & 0x1f; 501 if (fp != NULL) 502 *fp = (tag >> 12) & 0x7; 503 } 504 505 int 506 rkpcie_conf_size(void *v, pcitag_t tag) 507 { 508 return PCIE_CONFIG_SPACE_SIZE; 509 } 510 511 pcireg_t 512 rkpcie_conf_read(void *v, pcitag_t tag, int reg) 513 { 514 struct rkpcie_softc *sc = v; 515 int bus, dev, fn; 516 517 rkpcie_decompose_tag(sc, tag, &bus, &dev, &fn); 518 if (bus == sc->sc_bus) { 519 KASSERT(dev == 0); 520 return HREAD4(sc, PCIE_RC_NORMAL_BASE + tag | reg); 521 } 522 if (bus == sc->sc_bus + 1) { 523 KASSERT(dev == 0); 524 return bus_space_read_4(sc->sc_iot, sc->sc_axi_ioh, tag | reg); 525 } 526 527 return 0xffffffff; 528 } 529 530 void 531 rkpcie_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data) 532 { 533 struct rkpcie_softc *sc = v; 534 int bus, dev, fn; 535 536 rkpcie_decompose_tag(sc, tag, &bus, &dev, &fn); 537 if (bus == sc->sc_bus) { 538 KASSERT(dev == 0); 539 HWRITE4(sc, PCIE_RC_NORMAL_BASE + tag | reg, data); 540 return; 541 } 542 if (bus == sc->sc_bus + 1) { 543 KASSERT(dev == 0); 544 bus_space_write_4(sc->sc_iot, sc->sc_axi_ioh, tag | reg, data); 545 return; 546 } 547 } 548 549 int 550 rkpcie_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 551 { 552 int pin = pa->pa_rawintrpin; 553 554 if (pin == 0 || pin > PCI_INTERRUPT_PIN_MAX) 555 return -1; 556 557 if (pa->pa_tag == 0) 558 return -1; 559 560 ihp->ih_pc = pa->pa_pc; 561 ihp->ih_tag = pa->pa_intrtag; 562 ihp->ih_intrpin = pa->pa_intrpin; 563 ihp->ih_type = PCI_INTX; 564 565 return 0; 566 } 567 568 const char * 569 rkpcie_intr_string(void *v, pci_intr_handle_t ih) 570 { 571 switch (ih.ih_type) { 572 case PCI_MSI: 573 return "msi"; 574 case PCI_MSIX: 575 return "msix"; 576 } 577 578 return "intx"; 579 } 580 581 void * 582 rkpcie_intr_establish(void *v, pci_intr_handle_t ih, int level, 583 struct cpu_info *ci, int (*func)(void *), void *arg, char *name) 584 { 585 struct rkpcie_softc *sc = v; 586 void *cookie; 587 588 KASSERT(ih.ih_type != PCI_NONE); 589 590 if (ih.ih_type != PCI_INTX) { 591 uint64_t addr, data; 592 593 /* Assume hardware passes Requester ID as sideband data. */ 594 data = pci_requester_id(ih.ih_pc, ih.ih_tag); 595 cookie = fdt_intr_establish_msi_cpu(sc->sc_node, &addr, 596 &data, level, ci, func, arg, name); 597 if (cookie == NULL) 598 return NULL; 599 600 /* TODO: translate address to the PCI device's view */ 601 602 if (ih.ih_type == PCI_MSIX) { 603 pci_msix_enable(ih.ih_pc, ih.ih_tag, 604 sc->sc_iot, ih.ih_intrpin, addr, data); 605 } else 606 pci_msi_enable(ih.ih_pc, ih.ih_tag, addr, data); 607 } else { 608 /* Unmask legacy interrupts. */ 609 HWRITE4(sc, PCIE_CLIENT_INT_MASK, 610 PCIE_CLIENT_INTA_UNMASK | PCIE_CLIENT_INTB_UNMASK | 611 PCIE_CLIENT_INTC_UNMASK | PCIE_CLIENT_INTD_UNMASK); 612 613 cookie = fdt_intr_establish_idx_cpu(sc->sc_node, 1, level, 614 ci, func, arg, name); 615 } 616 617 return cookie; 618 } 619 620 void 621 rkpcie_intr_disestablish(void *v, void *cookie) 622 { 623 } 624 625 /* 626 * PHY Support. 627 */ 628 629 #define RK3399_GRF_SOC_CON5_PCIE 0xe214 630 #define RK3399_TX_ELEC_IDLE_OFF_MASK ((1 << 3) << 16) 631 #define RK3399_TX_ELEC_IDLE_OFF (1 << 3) 632 #define RK3399_GRF_SOC_CON8 0xe220 633 #define RK3399_PCIE_TEST_DATA_MASK ((0xf << 7) << 16) 634 #define RK3399_PCIE_TEST_DATA_SHIFT 7 635 #define RK3399_PCIE_TEST_ADDR_MASK ((0x3f << 1) << 16) 636 #define RK3399_PCIE_TEST_ADDR_SHIFT 1 637 #define RK3399_PCIE_TEST_WRITE_ENABLE (((1 << 0) << 16) | (1 << 0)) 638 #define RK3399_PCIE_TEST_WRITE_DISABLE (((1 << 0) << 16) | (0 << 0)) 639 #define RK3399_GRF_SOC_STATUS1 0xe2a4 640 #define RK3399_PCIE_PHY_PLL_LOCKED (1 << 9) 641 #define RK3399_PCIE_PHY_PLL_OUTPUT (1 << 10) 642 643 #define RK3399_PCIE_PHY_CFG_PLL_LOCK 0x10 644 #define RK3399_PCIE_PHY_CFG_CLK_TEST 0x10 645 #define RK3399_PCIE_PHY_CFG_SEPE_RATE (1 << 3) 646 #define RK3399_PCIE_PHY_CFG_CLK_SCC 0x12 647 #define RK3399_PCIE_PHY_CFG_PLL_100M (1 << 3) 648 649 void 650 rkpcie_phy_init(struct rkpcie_softc *sc) 651 { 652 uint32_t phys[8]; 653 int len; 654 655 len = OF_getpropintarray(sc->sc_node, "phys", phys, sizeof(phys)); 656 if (len < sizeof(phys[0])) 657 return; 658 659 sc->sc_phy_node = OF_getnodebyphandle(phys[0]); 660 if (sc->sc_phy_node == 0) 661 return; 662 663 clock_enable(sc->sc_phy_node, "refclk"); 664 reset_assert(sc->sc_phy_node, "phy"); 665 } 666 667 void 668 rkpcie_phy_write_conf(struct regmap *rm, uint8_t addr, uint8_t data) 669 { 670 regmap_write_4(rm, RK3399_GRF_SOC_CON8, 671 RK3399_PCIE_TEST_ADDR_MASK | 672 (addr << RK3399_PCIE_TEST_ADDR_SHIFT) | 673 RK3399_PCIE_TEST_DATA_MASK | 674 (data << RK3399_PCIE_TEST_DATA_SHIFT) | 675 RK3399_PCIE_TEST_WRITE_DISABLE); 676 delay(1); 677 regmap_write_4(rm, RK3399_GRF_SOC_CON8, 678 RK3399_PCIE_TEST_WRITE_ENABLE); 679 delay(1); 680 regmap_write_4(rm, RK3399_GRF_SOC_CON8, 681 RK3399_PCIE_TEST_WRITE_DISABLE); 682 } 683 684 void 685 rkpcie_phy_poweron(struct rkpcie_softc *sc) 686 { 687 struct regmap *rm; 688 uint32_t status; 689 int lane = 0; 690 int timo; 691 692 reset_deassert(sc->sc_phy_node, "phy"); 693 694 rm = regmap_bynode(OF_parent(sc->sc_phy_node)); 695 if (rm == NULL) 696 return; 697 698 regmap_write_4(rm, RK3399_GRF_SOC_CON8, 699 RK3399_PCIE_TEST_ADDR_MASK | 700 RK3399_PCIE_PHY_CFG_PLL_LOCK << RK3399_PCIE_TEST_ADDR_SHIFT); 701 regmap_write_4(rm, RK3399_GRF_SOC_CON5_PCIE, 702 RK3399_TX_ELEC_IDLE_OFF_MASK << lane | 0); 703 704 for (timo = 50; timo > 0; timo--) { 705 status = regmap_read_4(rm, RK3399_GRF_SOC_STATUS1); 706 if (status & RK3399_PCIE_PHY_PLL_LOCKED) 707 break; 708 delay(20000); 709 } 710 if (timo == 0) { 711 printf("%s: PHY PLL lock timeout\n", sc->sc_dev.dv_xname); 712 return; 713 } 714 715 rkpcie_phy_write_conf(rm, RK3399_PCIE_PHY_CFG_CLK_TEST, 716 RK3399_PCIE_PHY_CFG_SEPE_RATE); 717 rkpcie_phy_write_conf(rm, RK3399_PCIE_PHY_CFG_CLK_SCC, 718 RK3399_PCIE_PHY_CFG_PLL_100M); 719 720 for (timo = 50; timo > 0; timo--) { 721 status = regmap_read_4(rm, RK3399_GRF_SOC_STATUS1); 722 if ((status & RK3399_PCIE_PHY_PLL_OUTPUT) == 0) 723 break; 724 delay(20000); 725 } 726 if (timo == 0) { 727 printf("%s: PHY PLL output enable timeout\n", 728 sc->sc_dev.dv_xname); 729 return; 730 } 731 732 regmap_write_4(rm, RK3399_GRF_SOC_CON8, 733 RK3399_PCIE_TEST_ADDR_MASK | 734 RK3399_PCIE_PHY_CFG_PLL_LOCK << RK3399_PCIE_TEST_ADDR_SHIFT); 735 736 for (timo = 50; timo > 0; timo--) { 737 status = regmap_read_4(rm, RK3399_GRF_SOC_STATUS1); 738 if (status & RK3399_PCIE_PHY_PLL_LOCKED) 739 break; 740 delay(20000); 741 } 742 if (timo == 0) { 743 printf("%s: PHY PLL relock timeout\n", sc->sc_dev.dv_xname); 744 return; 745 } 746 } 747