1 /* Public Domain */ 2 3 /* 4 * RK3288 clocks. 5 */ 6 7 #define RK3288_PLL_APLL 1 8 #define RK3288_PLL_CPLL 3 9 #define RK3288_PLL_GPLL 4 10 #define RK3288_ARMCLK 6 11 12 #define RK3288_CLK_SDMMC 68 13 #define RK3288_CLK_TSADC 72 14 #define RK3288_CLK_UART0 77 15 #define RK3288_CLK_UART1 78 16 #define RK3288_CLK_UART2 79 17 #define RK3288_CLK_UART3 80 18 #define RK3288_CLK_UART4 81 19 #define RK3288_CLK_MAC_RX 102 20 #define RK3288_CLK_MAC_TX 103 21 #define RK3288_CLK_SDMMC_DRV 114 22 #define RK3288_CLK_SDMMC_SAMPLE 118 23 #define RK3288_CLK_MAC 151 24 25 #define RK3288_ACLK_GMAC 196 26 27 #define RK3288_PCLK_I2C0 332 28 #define RK3288_PCLK_I2C1 333 29 #define RK3288_PCLK_I2C2 334 30 #define RK3288_PCLK_I2C3 335 31 #define RK3288_PCLK_I2C4 336 32 #define RK3288_PCLK_I2C5 337 33 #define RK3288_PCLK_TSADC 346 34 #define RK3288_PCLK_GMAC 349 35 36 #define RK3288_HCLK_HOST0 450 37 #define RK3288_HCLK_SDMMC 456 38 39 /* 40 * RK3328 clocks. 41 */ 42 43 #define RK3328_PLL_APLL 1 44 #define RK3328_PLL_DPLL 2 45 #define RK3328_PLL_CPLL 3 46 #define RK3328_PLL_GPLL 4 47 #define RK3328_PLL_NPLL 5 48 #define RK3328_ARMCLK 6 49 50 #define RK3328_CLK_SDMMC 33 51 #define RK3328_CLK_SDIO 34 52 #define RK3328_CLK_EMMC 35 53 #define RK3328_CLK_UART0 38 54 #define RK3328_CLK_UART1 39 55 #define RK3328_CLK_UART2 40 56 #define RK3328_CLK_I2C0 55 57 #define RK3328_CLK_I2C1 56 58 #define RK3328_CLK_I2C2 57 59 #define RK3328_CLK_I2C3 58 60 61 /* 62 * RK3399 clocks. 63 */ 64 65 #define RK3399_PLL_ALPLL 1 66 #define RK3399_PLL_ABPLL 2 67 #define RK3399_PLL_DPLL 3 68 #define RK3399_PLL_CPLL 4 69 #define RK3399_PLL_GPLL 5 70 #define RK3399_PLL_NPLL 6 71 #define RK3399_PLL_VPLL 7 72 #define RK3399_ARMCLKL 8 73 #define RK3399_ARMCLKB 9 74 75 #define RK3399_CLK_I2C1 65 76 #define RK3399_CLK_I2C2 66 77 #define RK3399_CLK_I2C3 67 78 #define RK3399_CLK_I2C5 68 79 #define RK3399_CLK_I2C6 69 80 #define RK3399_CLK_I2C7 70 81 #define RK3399_CLK_SDMMC 76 82 #define RK3399_CLK_SDIO 77 83 #define RK3399_CLK_EMMC 78 84 #define RK3399_CLK_TSADC 79 85 #define RK3399_CLK_UART0 81 86 #define RK3399_CLK_UART1 82 87 #define RK3399_CLK_UART2 83 88 #define RK3399_CLK_UART3 84 89 #define RK3399_CLK_MAC_RX 103 90 #define RK3399_CLK_MAC_TX 104 91 #define RK3399_CLK_MAC 105 92 #define RK3399_CLK_USB3OTG0_REF 129 93 #define RK3399_CLK_USB3OTG1_REF 130 94 #define RK3399_CLK_USB3OTG0_SUSPEND 131 95 #define RK3399_CLK_USB3OTG1_SUSPEND 132 96 #define RK3399_CLK_SDMMC_DRV 154 97 #define RK3399_CLK_SDMMC_SAMPLE 155 98 99 #define RK3399_ACLK_PERIPH 192 100 #define RK3399_ACLK_PERILP0 194 101 #define RK3399_ACLK_CCI 201 102 #define RK3399_ACLK_GMAC 213 103 #define RK3399_ACLK_VIO 227 104 #define RK3399_ACLK_EMMC 240 105 #define RK3399_ACLK_USB3OTG0 246 106 #define RK3399_ACLK_USB3OTG1 247 107 #define RK3399_ACLK_USB3_GRF 249 108 109 #define RK3399_PCLK_PERIPH 320 110 #define RK3399_PCLK_PERILP0 322 111 #define RK3399_PCLK_PERILP1 323 112 #define RK3399_PCLK_I2C1 341 113 #define RK3399_PCLK_I2C2 342 114 #define RK3399_PCLK_I2C3 343 115 #define RK3399_PCLK_I2C5 344 116 #define RK3399_PCLK_I2C6 345 117 #define RK3399_PCLK_I2C7 346 118 #define RK3399_PCLK_TSADC 356 119 #define RK3399_PCLK_GMAC 358 120 121 #define RK3399_HCLK_PERIPH 448 122 #define RK3399_HCLK_PERILP0 449 123 #define RK3399_HCLK_PERILP1 450 124 #define RK3399_HCLK_HOST0 456 125 #define RK3399_HCLK_HOST0_ARB 457 126 #define RK3399_HCLK_HOST1 458 127 #define RK3399_HCLK_HOST1_ARB 459 128 #define RK3399_HCLK_SDMMC 462 129 130 /* PMUCRU */ 131 132 #define RK3399_PLL_PPLL 1 133 134 #define RK3399_CLK_I2C0 9 135 #define RK3399_CLK_I2C4 10 136 #define RK3399_CLK_I2C8 11 137 138 #define RK3399_PCLK_I2C0 27 139 #define RK3399_PCLK_I2C4 28 140 #define RK3399_PCLK_I2C8 29 141