1 /* Public Domain */ 2 3 /* 4 * RK3288 clocks. 5 */ 6 7 #define RK3288_PLL_APLL 1 8 #define RK3288_PLL_CPLL 3 9 #define RK3288_PLL_GPLL 4 10 #define RK3288_ARMCLK 6 11 12 #define RK3288_CLK_SDMMC 68 13 #define RK3288_CLK_TSADC 72 14 #define RK3288_CLK_UART0 77 15 #define RK3288_CLK_UART1 78 16 #define RK3288_CLK_UART2 79 17 #define RK3288_CLK_UART3 80 18 #define RK3288_CLK_UART4 81 19 #define RK3288_CLK_MAC_RX 102 20 #define RK3288_CLK_MAC_TX 103 21 #define RK3288_CLK_SDMMC_DRV 114 22 #define RK3288_CLK_SDMMC_SAMPLE 118 23 #define RK3288_CLK_MAC 151 24 25 #define RK3288_ACLK_GMAC 196 26 27 #define RK3288_PCLK_I2C0 332 28 #define RK3288_PCLK_I2C1 333 29 #define RK3288_PCLK_I2C2 334 30 #define RK3288_PCLK_I2C3 335 31 #define RK3288_PCLK_I2C4 336 32 #define RK3288_PCLK_I2C5 337 33 #define RK3288_PCLK_TSADC 346 34 #define RK3288_PCLK_GMAC 349 35 36 #define RK3288_HCLK_HOST0 450 37 #define RK3288_HCLK_SDMMC 456 38 39 /* 40 * RK3328 clocks. 41 */ 42 43 #define RK3328_PLL_APLL 1 44 #define RK3328_PLL_DPLL 2 45 #define RK3328_PLL_CPLL 3 46 #define RK3328_PLL_GPLL 4 47 #define RK3328_PLL_NPLL 5 48 #define RK3328_ARMCLK 6 49 50 #define RK3328_CLK_RTC32K 30 51 #define RK3328_CLK_SDMMC 33 52 #define RK3328_CLK_SDIO 34 53 #define RK3328_CLK_EMMC 35 54 #define RK3328_CLK_TSADC 36 55 #define RK3328_CLK_UART0 38 56 #define RK3328_CLK_UART1 39 57 #define RK3328_CLK_UART2 40 58 #define RK3328_CLK_WIFI 53 59 #define RK3328_CLK_I2C0 55 60 #define RK3328_CLK_I2C1 56 61 #define RK3328_CLK_I2C2 57 62 #define RK3328_CLK_I2C3 58 63 #define RK3328_CLK_PDM 61 64 #define RK3328_CLK_VDEC_CABAC 65 65 #define RK3328_CLK_VDEC_CORE 66 66 #define RK3328_CLK_VENC_DSP 67 67 #define RK3328_CLK_VENC_CORE 68 68 #define RK3328_CLK_TSP 92 69 70 #define RK3328_DCLK_LCDC 120 71 #define RK3328_HDMIPHY 122 72 #define RK3328_USB480M 123 73 #define RK3328_DCLK_LCDC_SRC 124 74 75 #define RK3328_ACLK_VOP_PRE 131 76 #define RK3328_ACLK_RGA_PRE 133 77 #define RK3328_ACLK_BUS_PRE 136 78 #define RK3328_ACLK_PERI_PRE 137 79 #define RK3328_ACLK_RKVDEC_PRE 138 80 #define RK3328_ACLK_RKVENC 140 81 #define RK3328_ACLK_VPU_PRE 141 82 #define RK3328_ACLK_VIO_PRE 142 83 84 #define RK3328_PCLK_BUS_PRE 216 85 #define RK3328_PCLK_PERI 230 86 87 #define RK3328_HCLK_PERI 308 88 #define RK3328_HCLK_BUS_PRE 328 89 90 #define RK3328_XIN24M 1023 91 #define RK3328_CLK_24M 1022 92 93 /* 94 * RK3399 clocks. 95 */ 96 97 #define RK3399_PLL_ALPLL 1 98 #define RK3399_PLL_ABPLL 2 99 #define RK3399_PLL_DPLL 3 100 #define RK3399_PLL_CPLL 4 101 #define RK3399_PLL_GPLL 5 102 #define RK3399_PLL_NPLL 6 103 #define RK3399_PLL_VPLL 7 104 #define RK3399_ARMCLKL 8 105 #define RK3399_ARMCLKB 9 106 107 #define RK3399_CLK_I2C1 65 108 #define RK3399_CLK_I2C2 66 109 #define RK3399_CLK_I2C3 67 110 #define RK3399_CLK_I2C5 68 111 #define RK3399_CLK_I2C6 69 112 #define RK3399_CLK_I2C7 70 113 #define RK3399_CLK_SDMMC 76 114 #define RK3399_CLK_SDIO 77 115 #define RK3399_CLK_EMMC 78 116 #define RK3399_CLK_TSADC 79 117 #define RK3399_CLK_UART0 81 118 #define RK3399_CLK_UART1 82 119 #define RK3399_CLK_UART2 83 120 #define RK3399_CLK_UART3 84 121 #define RK3399_CLK_MAC_RX 103 122 #define RK3399_CLK_MAC_TX 104 123 #define RK3399_CLK_MAC 105 124 #define RK3399_CLK_USB3OTG0_REF 129 125 #define RK3399_CLK_USB3OTG1_REF 130 126 #define RK3399_CLK_USB3OTG0_SUSPEND 131 127 #define RK3399_CLK_USB3OTG1_SUSPEND 132 128 #define RK3399_CLK_SDMMC_DRV 154 129 #define RK3399_CLK_SDMMC_SAMPLE 155 130 131 #define RK3399_ACLK_PERIPH 192 132 #define RK3399_ACLK_PERILP0 194 133 #define RK3399_ACLK_CCI 201 134 #define RK3399_ACLK_GMAC 213 135 #define RK3399_ACLK_HDCP 222 136 #define RK3399_ACLK_VIO 227 137 #define RK3399_ACLK_EMMC 240 138 #define RK3399_ACLK_USB3OTG0 246 139 #define RK3399_ACLK_USB3OTG1 247 140 #define RK3399_ACLK_USB3_GRF 249 141 #define RK3399_ACLK_GIC_PRE 262 142 143 #define RK3399_PCLK_PERIPH 320 144 #define RK3399_PCLK_PERILP0 322 145 #define RK3399_PCLK_PERILP1 323 146 #define RK3399_PCLK_I2C1 341 147 #define RK3399_PCLK_I2C2 342 148 #define RK3399_PCLK_I2C3 343 149 #define RK3399_PCLK_I2C5 344 150 #define RK3399_PCLK_I2C6 345 151 #define RK3399_PCLK_I2C7 346 152 #define RK3399_PCLK_TSADC 356 153 #define RK3399_PCLK_GMAC 358 154 #define RK3399_PCLK_DDR 376 155 156 #define RK3399_HCLK_PERIPH 448 157 #define RK3399_HCLK_PERILP0 449 158 #define RK3399_HCLK_PERILP1 450 159 #define RK3399_HCLK_HOST0 456 160 #define RK3399_HCLK_HOST0_ARB 457 161 #define RK3399_HCLK_HOST1 458 162 #define RK3399_HCLK_HOST1_ARB 459 163 #define RK3399_HCLK_SDMMC 462 164 165 /* PMUCRU */ 166 167 #define RK3399_PLL_PPLL 1 168 169 #define RK3399_CLK_I2C0 9 170 #define RK3399_CLK_I2C4 10 171 #define RK3399_CLK_I2C8 11 172 173 #define RK3399_PCLK_I2C0 27 174 #define RK3399_PCLK_I2C4 28 175 #define RK3399_PCLK_I2C8 29 176 177 #define RK3399_XIN24M 1023 178 #define RK3399_CLK_32K 1022 179