1 /* Public Domain */ 2 3 /* 4 * RK3288 clocks. 5 */ 6 7 #define RK3288_PLL_APLL 1 8 #define RK3288_PLL_CPLL 3 9 #define RK3288_PLL_GPLL 4 10 #define RK3288_PLL_NPLL 5 11 #define RK3288_ARMCLK 6 12 13 #define RK3288_CLK_SDMMC 68 14 #define RK3288_CLK_TSADC 72 15 #define RK3288_CLK_UART0 77 16 #define RK3288_CLK_UART1 78 17 #define RK3288_CLK_UART2 79 18 #define RK3288_CLK_UART3 80 19 #define RK3288_CLK_UART4 81 20 #define RK3288_CLK_MAC_RX 102 21 #define RK3288_CLK_MAC_TX 103 22 #define RK3288_CLK_SDMMC_DRV 114 23 #define RK3288_CLK_SDMMC_SAMPLE 118 24 #define RK3288_CLK_MAC 151 25 26 #define RK3288_ACLK_GMAC 196 27 28 #define RK3288_PCLK_I2C0 332 29 #define RK3288_PCLK_I2C1 333 30 #define RK3288_PCLK_I2C2 334 31 #define RK3288_PCLK_I2C3 335 32 #define RK3288_PCLK_I2C4 336 33 #define RK3288_PCLK_I2C5 337 34 #define RK3288_PCLK_TSADC 346 35 #define RK3288_PCLK_GMAC 349 36 37 #define RK3288_HCLK_HOST0 450 38 #define RK3288_HCLK_SDMMC 456 39 40 #define RK3288_XIN24M 1023 41 42 /* 43 * RK3328 clocks. 44 */ 45 46 #define RK3328_PLL_APLL 1 47 #define RK3328_PLL_DPLL 2 48 #define RK3328_PLL_CPLL 3 49 #define RK3328_PLL_GPLL 4 50 #define RK3328_PLL_NPLL 5 51 #define RK3328_ARMCLK 6 52 53 #define RK3328_CLK_RTC32K 30 54 #define RK3328_CLK_SDMMC 33 55 #define RK3328_CLK_SDIO 34 56 #define RK3328_CLK_EMMC 35 57 #define RK3328_CLK_TSADC 36 58 #define RK3328_CLK_UART0 38 59 #define RK3328_CLK_UART1 39 60 #define RK3328_CLK_UART2 40 61 #define RK3328_CLK_WIFI 53 62 #define RK3328_CLK_I2C0 55 63 #define RK3328_CLK_I2C1 56 64 #define RK3328_CLK_I2C2 57 65 #define RK3328_CLK_I2C3 58 66 #define RK3328_CLK_PDM 61 67 #define RK3328_CLK_VDEC_CABAC 65 68 #define RK3328_CLK_VDEC_CORE 66 69 #define RK3328_CLK_VENC_DSP 67 70 #define RK3328_CLK_VENC_CORE 68 71 #define RK3328_CLK_TSP 92 72 #define RK3328_CLK_MAC2IO_SRC 99 73 #define RK3328_CLK_MAC2IO 100 74 #define RK3328_CLK_MAC2IO_EXT 102 75 76 #define RK3328_DCLK_LCDC 120 77 #define RK3328_HDMIPHY 122 78 #define RK3328_USB480M 123 79 #define RK3328_DCLK_LCDC_SRC 124 80 81 #define RK3328_ACLK_VOP_PRE 131 82 #define RK3328_ACLK_RGA_PRE 133 83 #define RK3328_ACLK_BUS_PRE 136 84 #define RK3328_ACLK_PERI_PRE 137 85 #define RK3328_ACLK_RKVDEC_PRE 138 86 #define RK3328_ACLK_RKVENC 140 87 #define RK3328_ACLK_VPU_PRE 141 88 #define RK3328_ACLK_VIO_PRE 142 89 90 #define RK3328_PCLK_BUS_PRE 216 91 #define RK3328_PCLK_PERI 230 92 93 #define RK3328_HCLK_PERI 308 94 #define RK3328_HCLK_BUS_PRE 328 95 96 #define RK3328_XIN24M 1023 97 #define RK3328_CLK_24M 1022 98 #define RK3328_GMAC_CLKIN 1021 99 100 /* 101 * RK3399 clocks. 102 */ 103 104 #define RK3399_PLL_ALPLL 1 105 #define RK3399_PLL_ABPLL 2 106 #define RK3399_PLL_DPLL 3 107 #define RK3399_PLL_CPLL 4 108 #define RK3399_PLL_GPLL 5 109 #define RK3399_PLL_NPLL 6 110 #define RK3399_PLL_VPLL 7 111 #define RK3399_ARMCLKL 8 112 #define RK3399_ARMCLKB 9 113 114 #define RK3399_CLK_I2C1 65 115 #define RK3399_CLK_I2C2 66 116 #define RK3399_CLK_I2C3 67 117 #define RK3399_CLK_I2C5 68 118 #define RK3399_CLK_I2C6 69 119 #define RK3399_CLK_I2C7 70 120 #define RK3399_CLK_SDMMC 76 121 #define RK3399_CLK_SDIO 77 122 #define RK3399_CLK_EMMC 78 123 #define RK3399_CLK_TSADC 79 124 #define RK3399_CLK_UART0 81 125 #define RK3399_CLK_UART1 82 126 #define RK3399_CLK_UART2 83 127 #define RK3399_CLK_UART3 84 128 #define RK3399_CLK_MAC_RX 103 129 #define RK3399_CLK_MAC_TX 104 130 #define RK3399_CLK_MAC 105 131 #define RK3399_CLK_USB3OTG0_REF 129 132 #define RK3399_CLK_USB3OTG1_REF 130 133 #define RK3399_CLK_USB3OTG0_SUSPEND 131 134 #define RK3399_CLK_USB3OTG1_SUSPEND 132 135 #define RK3399_CLK_SDMMC_DRV 154 136 #define RK3399_CLK_SDMMC_SAMPLE 155 137 138 #define RK3399_DCLK_VOP0 180 139 #define RK3399_DCLK_VOP1 181 140 #define RK3399_DCLK_VOP0_DIV 182 141 #define RK3399_DCLK_VOP1_DIV 183 142 #define RK3399_DCLK_VOP0_FRAC 185 143 #define RK3399_DCLK_VOP1_FRAC 186 144 145 #define RK3399_ACLK_PERIPH 192 146 #define RK3399_ACLK_PERILP0 194 147 #define RK3399_ACLK_CCI 201 148 #define RK3399_ACLK_GMAC 213 149 #define RK3399_ACLK_VOP0_NOC 216 150 #define RK3399_ACLK_VOP0 217 151 #define RK3399_ACLK_VOP1_NOC 218 152 #define RK3399_ACLK_VOP1 219 153 #define RK3399_ACLK_HDCP 222 154 #define RK3399_ACLK_VIO 227 155 #define RK3399_ACLK_EMMC 240 156 #define RK3399_ACLK_USB3OTG0 246 157 #define RK3399_ACLK_USB3OTG1 247 158 #define RK3399_ACLK_USB3_GRF 249 159 #define RK3399_ACLK_GIC_PRE 262 160 161 #define RK3399_PCLK_PERIPH 320 162 #define RK3399_PCLK_PERILP0 322 163 #define RK3399_PCLK_PERILP1 323 164 #define RK3399_PCLK_I2C1 341 165 #define RK3399_PCLK_I2C2 342 166 #define RK3399_PCLK_I2C3 343 167 #define RK3399_PCLK_I2C5 344 168 #define RK3399_PCLK_I2C6 345 169 #define RK3399_PCLK_I2C7 346 170 #define RK3399_PCLK_TSADC 356 171 #define RK3399_PCLK_GMAC 358 172 #define RK3399_PCLK_DDR 376 173 174 #define RK3399_HCLK_PERIPH 448 175 #define RK3399_HCLK_PERILP0 449 176 #define RK3399_HCLK_PERILP1 450 177 #define RK3399_HCLK_HOST0 456 178 #define RK3399_HCLK_HOST0_ARB 457 179 #define RK3399_HCLK_HOST1 458 180 #define RK3399_HCLK_HOST1_ARB 459 181 #define RK3399_HCLK_SDMMC 462 182 #define RK3399_HCLK_VOP0_NOC 472 183 #define RK3399_HCLK_VOP0 473 184 #define RK3399_HCLK_VOP1_NOC 474 185 #define RK3399_HCLK_VOP1 475 186 187 /* PMUCRU */ 188 189 #define RK3399_PLL_PPLL 1 190 191 #define RK3399_CLK_I2C0 9 192 #define RK3399_CLK_I2C4 10 193 #define RK3399_CLK_I2C8 11 194 195 #define RK3399_PCLK_I2C0 27 196 #define RK3399_PCLK_I2C4 28 197 #define RK3399_PCLK_I2C8 29 198 #define RK3399_PCLK_RKPWM 30 199 200 #define RK3399_XIN24M 1023 201 #define RK3399_CLK_32K 1022 202