1 /* $OpenBSD: rkclock.c,v 1.22 2018/02/25 20:42:13 kettenis Exp $ */ 2 /* 3 * Copyright (c) 2017, 2018 Mark Kettenis <kettenis@openbsd.org> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #include <sys/param.h> 19 #include <sys/systm.h> 20 #include <sys/sysctl.h> 21 #include <sys/device.h> 22 23 #include <machine/intr.h> 24 #include <machine/bus.h> 25 #include <machine/fdt.h> 26 27 #include <dev/ofw/openfirm.h> 28 #include <dev/ofw/ofw_clock.h> 29 #include <dev/ofw/fdt.h> 30 31 /* RK3288 registers */ 32 #define RK3288_CRU_APLL_CON(i) (0x0000 + (i) * 4) 33 #define RK3288_CRU_CPLL_CON(i) (0x0020 + (i) * 4) 34 #define RK3288_CRU_GPLL_CON(i) (0x0030 + (i) * 4) 35 #define RK3288_CRU_PLL_CLKR_MASK (0x3f << 8) 36 #define RK3288_CRU_PLL_CLKR_SHIFT 8 37 #define RK3288_CRU_PLL_CLKOD_MASK (0xf << 0) 38 #define RK3288_CRU_PLL_CLKOD_SHIFT 0 39 #define RK3288_CRU_PLL_CLKF_MASK (0x1fff << 0) 40 #define RK3288_CRU_PLL_CLKF_SHIFT 0 41 #define RK3288_CRU_PLL_RESET (1 << 5) 42 #define RK3288_CRU_MODE_CON 0x0050 43 #define RK3288_CRU_MODE_PLL_WORK_MODE_MASK 0x3 44 #define RK3288_CRU_MODE_PLL_WORK_MODE_SLOW 0x0 45 #define RK3288_CRU_MODE_PLL_WORK_MODE_NORMAL 0x1 46 #define RK3288_CRU_CLKSEL_CON(i) (0x0060 + (i) * 4) 47 48 /* RK3328 registers */ 49 #define RK3328_CRU_APLL_CON(i) (0x0000 + (i) * 4) 50 #define RK3328_CRU_DPLL_CON(i) (0x0020 + (i) * 4) 51 #define RK3328_CRU_CPLL_CON(i) (0x0040 + (i) * 4) 52 #define RK3328_CRU_GPLL_CON(i) (0x0060 + (i) * 4) 53 #define RK3328_CRU_NPLL_CON(i) (0x0080 + (i) * 4) 54 #define RK3328_CRU_CLKSEL_CON(i) (0x0100 + (i) * 4) 55 #define RK3328_CRU_PLL_POSTDIV1_MASK (0x7 << 12) 56 #define RK3328_CRU_PLL_POSTDIV1_SHIFT 12 57 #define RK3328_CRU_PLL_FBDIV_MASK (0xfff << 0) 58 #define RK3328_CRU_PLL_FBDIV_SHIFT 0 59 #define RK3328_CRU_PLL_POSTDIV2_MASK (0x7 << 6) 60 #define RK3328_CRU_PLL_POSTDIV2_SHIFT 6 61 #define RK3328_CRU_PLL_REFDIV_MASK (0x3f << 0) 62 #define RK3328_CRU_PLL_REFDIV_SHIFT 0 63 #define RK3328_CRU_CLKGATE_CON(i) (0x0200 + (i) * 4) 64 #define RK3328_CRU_SOFTRST_CON(i) (0x0300 + (i) * 4) 65 66 /* RK3399 registers */ 67 #define RK3399_CRU_LPLL_CON(i) (0x0000 + (i) * 4) 68 #define RK3399_CRU_BPLL_CON(i) (0x0020 + (i) * 4) 69 #define RK3399_CRU_DPLL_CON(i) (0x0020 + (i) * 4) 70 #define RK3399_CRU_CPLL_CON(i) (0x0060 + (i) * 4) 71 #define RK3399_CRU_GPLL_CON(i) (0x0080 + (i) * 4) 72 #define RK3399_CRU_NPLL_CON(i) (0x00a0 + (i) * 4) 73 #define RK3399_CRU_PLL_FBDIV_MASK (0xfff << 0) 74 #define RK3399_CRU_PLL_FBDIV_SHIFT 0 75 #define RK3399_CRU_PLL_POSTDIV2_MASK (0x7 << 12) 76 #define RK3399_CRU_PLL_POSTDIV2_SHIFT 12 77 #define RK3399_CRU_PLL_POSTDIV1_MASK (0x7 << 8) 78 #define RK3399_CRU_PLL_POSTDIV1_SHIFT 8 79 #define RK3399_CRU_PLL_REFDIV_MASK (0x3f << 0) 80 #define RK3399_CRU_PLL_REFDIV_SHIFT 0 81 #define RK3399_CRU_PLL_PLL_WORK_MODE_MASK (0x3 << 8) 82 #define RK3399_CRU_PLL_PLL_WORK_MODE_SLOW (0x0 << 8) 83 #define RK3399_CRU_PLL_PLL_WORK_MODE_NORMAL (0x1 << 8) 84 #define RK3399_CRU_PLL_PLL_WORK_MODE_DEEP_SLOW (0x2 << 8) 85 #define RK3399_CRU_PLL_PLL_LOCK (1U << 31) 86 #define RK3399_CRU_CLKSEL_CON(i) (0x0100 + (i) * 4) 87 #define RK3399_CRU_ACLKM_CORE_DIV_CON_MASK (0x1f << 8) 88 #define RK3399_CRU_ACLKM_CORE_DIV_CON_SHIFT 8 89 #define RK3399_CRU_CORE_PLL_SEL_MASK (0x3 << 6) 90 #define RK3399_CRU_CORE_PLL_SEL_SHIFT 6 91 #define RK3399_CRU_CLK_CORE_DIV_CON_MASK (0x1f << 0) 92 #define RK3399_CRU_CLK_CORE_DIV_CON_SHIFT 0 93 #define RK3399_CRU_PCLK_DBG_DIV_CON_MASK (0x1f << 8) 94 #define RK3399_CRU_PCLK_DBG_DIV_CON_SHIFT 8 95 #define RK3399_CRU_ATCLK_CORE_DIV_CON_MASK (0x1f << 0) 96 #define RK3399_CRU_ATCLK_CORE_DIV_CON_SHIFT 0 97 #define RK3399_CRU_CLKGATE_CON(i) (0x0300 + (i) * 4) 98 #define RK3399_CRU_SOFTRST_CON(i) (0x0400 + (i) * 4) 99 #define RK3399_CRU_SDMMC_CON(i) (0x0580 + (i) * 4) 100 101 #define RK3399_PMUCRU_PPLL_CON(i) (0x0000 + (i) * 4) 102 #define RK3399_PMUCRU_CLKSEL_CON(i) (0x0080 + (i) * 4) 103 104 #include "rkclock_clocks.h" 105 106 #define HREAD4(sc, reg) \ 107 (bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg))) 108 #define HWRITE4(sc, reg, val) \ 109 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 110 #define HSET4(sc, reg, bits) \ 111 HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits)) 112 #define HCLR4(sc, reg, bits) \ 113 HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits)) 114 115 struct rkclock_softc { 116 struct device sc_dev; 117 bus_space_tag_t sc_iot; 118 bus_space_handle_t sc_ioh; 119 120 struct clock_device sc_cd; 121 struct reset_device sc_rd; 122 }; 123 124 int rkclock_match(struct device *, void *, void *); 125 void rkclock_attach(struct device *, struct device *, void *); 126 127 struct cfattach rkclock_ca = { 128 sizeof (struct rkclock_softc), rkclock_match, rkclock_attach 129 }; 130 131 struct cfdriver rkclock_cd = { 132 NULL, "rkclock", DV_DULL 133 }; 134 135 void rk3288_init(struct rkclock_softc *); 136 uint32_t rk3288_get_frequency(void *, uint32_t *); 137 int rk3288_set_frequency(void *, uint32_t *, uint32_t); 138 void rk3288_enable(void *, uint32_t *, int); 139 void rk3288_reset(void *, uint32_t *, int); 140 141 void rk3328_init(struct rkclock_softc *); 142 uint32_t rk3328_get_frequency(void *, uint32_t *); 143 int rk3328_set_frequency(void *, uint32_t *, uint32_t); 144 void rk3328_enable(void *, uint32_t *, int); 145 void rk3328_reset(void *, uint32_t *, int); 146 147 void rk3399_init(struct rkclock_softc *); 148 uint32_t rk3399_get_frequency(void *, uint32_t *); 149 int rk3399_set_frequency(void *, uint32_t *, uint32_t); 150 void rk3399_enable(void *, uint32_t *, int); 151 void rk3399_reset(void *, uint32_t *, int); 152 153 void rk3399_pmu_init(struct rkclock_softc *); 154 uint32_t rk3399_pmu_get_frequency(void *, uint32_t *); 155 int rk3399_pmu_set_frequency(void *, uint32_t *, uint32_t); 156 void rk3399_pmu_enable(void *, uint32_t *, int); 157 void rk3399_pmu_reset(void *, uint32_t *, int); 158 159 struct rkclock_compat { 160 const char *compat; 161 void (*init)(struct rkclock_softc *); 162 void (*enable)(void *, uint32_t *, int); 163 uint32_t (*get_frequency)(void *, uint32_t *); 164 int (*set_frequency)(void *, uint32_t *, uint32_t); 165 void (*reset)(void *, uint32_t *, int); 166 }; 167 168 struct rkclock_compat rkclock_compat[] = { 169 { 170 "rockchip,rk3288-cru", rk3288_init, 171 rk3288_enable, rk3288_get_frequency, 172 rk3288_set_frequency, rk3288_reset 173 }, 174 { 175 "rockchip,rk3328-cru", rk3328_init, 176 rk3328_enable, rk3328_get_frequency, 177 rk3328_set_frequency, rk3328_reset 178 }, 179 { 180 "rockchip,rk3399-cru", rk3399_init, 181 rk3399_enable, rk3399_get_frequency, 182 rk3399_set_frequency, rk3399_reset, 183 }, 184 { 185 "rockchip,rk3399-pmucru", rk3399_pmu_init, 186 rk3399_pmu_enable, rk3399_pmu_get_frequency, 187 rk3399_pmu_set_frequency, rk3399_pmu_reset 188 } 189 }; 190 191 int 192 rkclock_match(struct device *parent, void *match, void *aux) 193 { 194 struct fdt_attach_args *faa = aux; 195 int i; 196 197 for (i = 0; i < nitems(rkclock_compat); i++) { 198 if (OF_is_compatible(faa->fa_node, rkclock_compat[i].compat)) 199 return 10; 200 } 201 202 return 0; 203 } 204 205 void 206 rkclock_attach(struct device *parent, struct device *self, void *aux) 207 { 208 struct rkclock_softc *sc = (struct rkclock_softc *)self; 209 struct fdt_attach_args *faa = aux; 210 int i; 211 212 if (faa->fa_nreg < 1) { 213 printf(": no registers\n"); 214 return; 215 } 216 217 sc->sc_iot = faa->fa_iot; 218 219 if (bus_space_map(sc->sc_iot, faa->fa_reg[0].addr, 220 faa->fa_reg[0].size, 0, &sc->sc_ioh)) { 221 printf(": can't map registers\n"); 222 return; 223 } 224 225 printf("\n"); 226 227 for (i = 0; i < nitems(rkclock_compat); i++) { 228 if (OF_is_compatible(faa->fa_node, rkclock_compat[i].compat)) { 229 break; 230 } 231 } 232 KASSERT(i < nitems(rkclock_compat)); 233 234 if (rkclock_compat[i].init) 235 rkclock_compat[i].init(sc); 236 237 sc->sc_cd.cd_node = faa->fa_node; 238 sc->sc_cd.cd_cookie = sc; 239 sc->sc_cd.cd_enable = rkclock_compat[i].enable; 240 sc->sc_cd.cd_get_frequency = rkclock_compat[i].get_frequency; 241 sc->sc_cd.cd_set_frequency = rkclock_compat[i].set_frequency; 242 clock_register(&sc->sc_cd); 243 244 sc->sc_rd.rd_node = faa->fa_node; 245 sc->sc_rd.rd_cookie = sc; 246 sc->sc_rd.rd_reset = rkclock_compat[i].reset; 247 reset_register(&sc->sc_rd); 248 } 249 250 /* 251 * Rockchip RK3288 252 */ 253 254 void 255 rk3288_init(struct rkclock_softc *sc) 256 { 257 int node; 258 259 /* 260 * Since the hardware comes up with a really conservative CPU 261 * clock frequency, and U-Boot doesn't set it to a more 262 * reasonable default, try to do so here. These defaults were 263 * chosen assuming that the CPU voltage is at least 1.1 V. 264 * Only do this on the Tinker-RK3288 for now where this is 265 * likely to be true given the default voltages for the 266 * regulators on that board. 267 */ 268 node = OF_finddevice("/"); 269 if (OF_is_compatible(node, "rockchip,rk3288-tinker")) { 270 uint32_t idx; 271 272 /* Run at 1.2 GHz. */ 273 idx = RK3288_ARMCLK; 274 rk3288_set_frequency(sc, &idx, 1200000000); 275 } 276 } 277 278 uint32_t 279 rk3288_get_pll(struct rkclock_softc *sc, bus_size_t base) 280 { 281 uint32_t clkod, clkr, clkf; 282 uint32_t reg; 283 284 reg = HREAD4(sc, base); 285 clkod = (reg & RK3288_CRU_PLL_CLKOD_MASK) >> 286 RK3288_CRU_PLL_CLKOD_SHIFT; 287 clkr = (reg & RK3288_CRU_PLL_CLKR_MASK) >> 288 RK3288_CRU_PLL_CLKR_SHIFT; 289 reg = HREAD4(sc, base + 4); 290 clkf = (reg & RK3288_CRU_PLL_CLKF_MASK) >> 291 RK3288_CRU_PLL_CLKF_SHIFT; 292 return 24000000ULL * (clkf + 1) / (clkr + 1) / (clkod + 1); 293 } 294 295 int 296 rk3288_set_pll(struct rkclock_softc *sc, bus_size_t base, uint32_t freq) 297 { 298 int shift = 4 * (base / RK3288_CRU_CPLL_CON(0)); 299 uint32_t no, nr, nf; 300 301 /* 302 * It is not clear whether all combinations of the clock 303 * dividers result in a stable clock. Therefore this function 304 * only supports a limited set of PLL clock rates. For now 305 * this set covers all the CPU frequencies supported by the 306 * Linux kernel. 307 */ 308 switch (freq) { 309 case 1800000000: 310 case 1704000000: 311 case 1608000000: 312 case 1512000000: 313 case 1488000000: 314 case 1416000000: 315 case 1200000000: 316 nr = no = 1; 317 break; 318 case 1008000000: 319 case 816000000: 320 case 696000000: 321 case 600000000: 322 nr = 1; no = 2; 323 break; 324 case 408000000: 325 case 312000000: 326 nr = 1; no = 4; 327 break; 328 case 216000000: 329 case 126000000: 330 nr = 1; no = 8; 331 break; 332 default: 333 printf("%s: %d MHz\n", __func__, freq); 334 return -1; 335 } 336 337 /* Calculate feedback divider. */ 338 nf = freq * nr * no / 24000000; 339 340 /* 341 * Select slow mode to guarantee a stable clock while we're 342 * adjusting the PLL. 343 */ 344 HWRITE4(sc, RK3288_CRU_MODE_CON, 345 (RK3288_CRU_MODE_PLL_WORK_MODE_MASK << 16 | 346 RK3288_CRU_MODE_PLL_WORK_MODE_SLOW) << shift); 347 348 /* Assert reset. */ 349 HWRITE4(sc, base + 0x000c, 350 RK3288_CRU_PLL_RESET << 16 | RK3288_CRU_PLL_RESET); 351 352 /* Set PLL rate. */ 353 HWRITE4(sc, base + 0x0000, 354 RK3288_CRU_PLL_CLKR_MASK << 16 | 355 (nr - 1) << RK3288_CRU_PLL_CLKR_SHIFT | 356 RK3288_CRU_PLL_CLKOD_MASK << 16 | 357 (no - 1) << RK3288_CRU_PLL_CLKOD_SHIFT); 358 HWRITE4(sc, base + 0x0004, 359 RK3288_CRU_PLL_CLKF_MASK << 16 | 360 (nf - 1) << RK3288_CRU_PLL_CLKF_SHIFT); 361 362 /* Deassert reset and wait. */ 363 HWRITE4(sc, base + 0x000c, 364 RK3288_CRU_PLL_RESET << 16); 365 delay((nr * 500 / 24) + 1); 366 367 /* Switch back to normal mode. */ 368 HWRITE4(sc, RK3288_CRU_MODE_CON, 369 (RK3288_CRU_MODE_PLL_WORK_MODE_MASK << 16 | 370 RK3288_CRU_MODE_PLL_WORK_MODE_NORMAL) << shift); 371 372 return 0; 373 } 374 375 uint32_t 376 rk3288_get_frequency(void *cookie, uint32_t *cells) 377 { 378 struct rkclock_softc *sc = cookie; 379 uint32_t idx = cells[0]; 380 uint32_t reg, mux, div_con, aclk_div_con; 381 382 switch (idx) { 383 case RK3288_PLL_APLL: 384 return rk3288_get_pll(sc, RK3288_CRU_APLL_CON(0)); 385 case RK3288_PLL_CPLL: 386 return rk3288_get_pll(sc, RK3288_CRU_CPLL_CON(0)); 387 case RK3288_PLL_GPLL: 388 return rk3288_get_pll(sc, RK3288_CRU_GPLL_CON(0)); 389 case RK3288_ARMCLK: 390 reg = HREAD4(sc, RK3288_CRU_CLKSEL_CON(0)); 391 mux = (reg >> 15) & 0x1; 392 div_con = (reg >> 8) & 0x1f; 393 idx = (mux == 0) ? RK3288_PLL_APLL : RK3288_PLL_GPLL; 394 return rk3288_get_frequency(sc, &idx) / (div_con + 1); 395 case RK3288_CLK_SDMMC: 396 reg = HREAD4(sc, RK3288_CRU_CLKSEL_CON(11)); 397 mux = (reg >> 6) & 0x3; 398 div_con = reg & 0x3f; 399 switch (mux) { 400 case 0: 401 idx = RK3288_PLL_CPLL; 402 break; 403 case 1: 404 idx = RK3288_PLL_GPLL; 405 break; 406 case 2: 407 return 24000000 / (div_con + 1); 408 default: 409 return 0; 410 } 411 return rk3288_get_frequency(sc, &idx) / (div_con + 1); 412 break; 413 case RK3288_CLK_UART0: 414 reg = HREAD4(sc, RK3288_CRU_CLKSEL_CON(13)); 415 mux = (reg >> 8) & 0x3; 416 div_con = reg & 0x7f; 417 if (mux == 2) 418 return 24000000 / (div_con + 1); 419 break; 420 case RK3288_CLK_UART1: 421 reg = HREAD4(sc, RK3288_CRU_CLKSEL_CON(14)); 422 mux = (reg >> 8) & 0x3; 423 div_con = reg & 0x7f; 424 if (mux == 2) 425 return 24000000 / (div_con + 1); 426 break; 427 case RK3288_CLK_UART2: 428 reg = HREAD4(sc, RK3288_CRU_CLKSEL_CON(15)); 429 mux = (reg >> 8) & 0x3; 430 div_con = reg & 0x7f; 431 if (mux == 2) 432 return 24000000 / (div_con + 1); 433 break; 434 case RK3288_CLK_UART3: 435 reg = HREAD4(sc, RK3288_CRU_CLKSEL_CON(16)); 436 mux = (reg >> 8) & 0x3; 437 div_con = reg & 0x7f; 438 if (mux == 2) 439 return 24000000 / (div_con + 1); 440 break; 441 case RK3288_CLK_UART4: 442 reg = HREAD4(sc, RK3288_CRU_CLKSEL_CON(3)); 443 mux = (reg >> 8) & 0x3; 444 div_con = reg & 0x7f; 445 if (mux == 2) 446 return 24000000 / (div_con + 1); 447 break; 448 case RK3288_PCLK_I2C0: 449 case RK3288_PCLK_I2C2: 450 reg = HREAD4(sc, RK3288_CRU_CLKSEL_CON(1)); 451 mux = (reg >> 15) & 0x1; 452 /* pd_bus_pclk_div_con */ 453 div_con = (reg >> 12) & 0x7; 454 if (mux == 1) 455 idx = RK3288_PLL_GPLL; 456 else 457 idx = RK3288_PLL_CPLL; 458 return rk3288_get_frequency(sc, &idx) / (div_con + 1); 459 case RK3288_PCLK_I2C1: 460 case RK3288_PCLK_I2C3: 461 case RK3288_PCLK_I2C4: 462 case RK3288_PCLK_I2C5: 463 reg = HREAD4(sc, RK3288_CRU_CLKSEL_CON(10)); 464 mux = (reg >> 15) & 0x1; 465 /* peri_pclk_div_con */ 466 div_con = (reg >> 12) & 0x3; 467 /* peri_aclk_div_con */ 468 aclk_div_con = reg & 0xf; 469 if (mux == 1) 470 idx = RK3288_PLL_GPLL; 471 else 472 idx = RK3288_PLL_CPLL; 473 return (rk3288_get_frequency(sc, &idx) / (aclk_div_con + 1)) >> 474 div_con; 475 default: 476 break; 477 } 478 479 printf("%s: 0x%08x\n", __func__, idx); 480 return 0; 481 } 482 483 int 484 rk3288_set_frequency(void *cookie, uint32_t *cells, uint32_t freq) 485 { 486 struct rkclock_softc *sc = cookie; 487 uint32_t idx = cells[0]; 488 int error; 489 490 switch (idx) { 491 case RK3288_PLL_APLL: 492 return rk3288_set_pll(sc, RK3288_CRU_APLL_CON(0), freq); 493 case RK3288_ARMCLK: 494 idx = RK3288_PLL_APLL; 495 error = rk3288_set_frequency(sc, &idx, freq); 496 if (error == 0) { 497 HWRITE4(sc, RK3288_CRU_CLKSEL_CON(0), 498 ((1 << 15) | (0x1f << 8)) << 16); 499 } 500 return error; 501 } 502 503 printf("%s: 0x%08x\n", __func__, idx); 504 return -1; 505 } 506 507 void 508 rk3288_enable(void *cookie, uint32_t *cells, int on) 509 { 510 uint32_t idx = cells[0]; 511 512 switch (idx) { 513 case RK3288_CLK_SDMMC: 514 case RK3288_CLK_UART0: 515 case RK3288_CLK_UART1: 516 case RK3288_CLK_UART2: 517 case RK3288_CLK_UART3: 518 case RK3288_CLK_UART4: 519 case RK3288_CLK_MAC_RX: 520 case RK3288_CLK_MAC_TX: 521 case RK3288_CLK_SDMMC_DRV: 522 case RK3288_CLK_SDMMC_SAMPLE: 523 case RK3288_CLK_MAC: 524 case RK3288_ACLK_GMAC: 525 case RK3288_PCLK_GMAC: 526 case RK3288_PCLK_I2C0: 527 case RK3288_PCLK_I2C1: 528 case RK3288_PCLK_I2C2: 529 case RK3288_PCLK_I2C3: 530 case RK3288_PCLK_I2C4: 531 case RK3288_PCLK_I2C5: 532 case RK3288_HCLK_HOST0: 533 case RK3288_HCLK_SDMMC: 534 /* Enabled by default. */ 535 break; 536 default: 537 printf("%s: 0x%08x\n", __func__, idx); 538 break; 539 } 540 } 541 542 void 543 rk3288_reset(void *cookie, uint32_t *cells, int on) 544 { 545 uint32_t idx = cells[0]; 546 547 printf("%s: 0x%08x\n", __func__, idx); 548 } 549 550 /* 551 * Rockchip RK3328 552 */ 553 554 void 555 rk3328_init(struct rkclock_softc *sc) 556 { 557 int i; 558 559 /* The code below assumes all clocks are enabled. Check this!. */ 560 for (i = 0; i <= 28; i++) { 561 if (HREAD4(sc, RK3328_CRU_CLKGATE_CON(i)) != 0x00000000) { 562 printf("CRU_CLKGATE_CON%d: 0x%08x\n", i, 563 HREAD4(sc, RK3328_CRU_CLKGATE_CON(i))); 564 } 565 } 566 } 567 568 uint32_t 569 rk3328_get_pll(struct rkclock_softc *sc, bus_size_t base) 570 { 571 uint32_t fbdiv, postdiv1, postdiv2, refdiv; 572 uint32_t reg; 573 574 reg = HREAD4(sc, base + 0x0000); 575 postdiv1 = (reg & RK3328_CRU_PLL_POSTDIV1_MASK) >> 576 RK3328_CRU_PLL_POSTDIV1_SHIFT; 577 fbdiv = (reg & RK3328_CRU_PLL_FBDIV_MASK) >> 578 RK3328_CRU_PLL_FBDIV_SHIFT; 579 reg = HREAD4(sc, base + 0x0004); 580 postdiv2 = (reg & RK3328_CRU_PLL_POSTDIV2_MASK) >> 581 RK3328_CRU_PLL_POSTDIV2_SHIFT; 582 refdiv = (reg & RK3328_CRU_PLL_REFDIV_MASK) >> 583 RK3399_CRU_PLL_REFDIV_SHIFT; 584 return 24000000ULL * fbdiv / refdiv / postdiv1 / postdiv2; 585 } 586 587 uint32_t 588 rk3328_get_sdmmc(struct rkclock_softc *sc, bus_size_t base) 589 { 590 uint32_t reg, mux, div_con; 591 uint32_t idx; 592 593 reg = HREAD4(sc, base); 594 mux = (reg >> 8) & 0x3; 595 div_con = reg & 0xff; 596 switch (mux) { 597 case 0: 598 idx = RK3328_PLL_CPLL; 599 break; 600 case 1: 601 idx = RK3328_PLL_GPLL; 602 break; 603 case 2: 604 return 24000000 / (div_con + 1); 605 #ifdef notyet 606 case 3: 607 idx = RK3328_USB_480M; 608 break; 609 #endif 610 default: 611 return 0; 612 } 613 return rk3328_get_frequency(sc, &idx) / (div_con + 1); 614 } 615 616 uint32_t 617 rk3328_get_i2c(struct rkclock_softc *sc, size_t base, int shift) 618 { 619 uint32_t reg, mux, div_con; 620 uint32_t idx; 621 622 reg = HREAD4(sc, base); 623 mux = (reg >> (7 + shift)) & 0x1; 624 div_con = (reg >> shift) & 0x7f; 625 idx = (mux == 0) ? RK3328_PLL_CPLL : RK3328_PLL_GPLL; 626 return rk3328_get_frequency(sc, &idx) / (div_con + 1); 627 } 628 629 uint32_t 630 rk3328_get_frequency(void *cookie, uint32_t *cells) 631 { 632 struct rkclock_softc *sc = cookie; 633 uint32_t idx = cells[0]; 634 uint32_t reg, mux, div_con; 635 636 switch (idx) { 637 case RK3328_PLL_APLL: 638 return rk3328_get_pll(sc, RK3328_CRU_APLL_CON(0)); 639 break; 640 case RK3328_PLL_DPLL: 641 return rk3328_get_pll(sc, RK3328_CRU_DPLL_CON(0)); 642 break; 643 case RK3328_PLL_CPLL: 644 return rk3328_get_pll(sc, RK3328_CRU_CPLL_CON(0)); 645 break; 646 case RK3328_PLL_GPLL: 647 return rk3328_get_pll(sc, RK3328_CRU_GPLL_CON(0)); 648 break; 649 case RK3328_PLL_NPLL: 650 return rk3328_get_pll(sc, RK3328_CRU_NPLL_CON(0)); 651 break; 652 case RK3328_ARMCLK: 653 reg = HREAD4(sc, RK3288_CRU_CLKSEL_CON(0)); 654 mux = (reg >> 6) & 0x3; 655 div_con = reg & 0x1f; 656 switch (mux) { 657 case 0: 658 idx = RK3328_PLL_APLL; 659 break; 660 case 1: 661 idx = RK3328_PLL_GPLL; 662 break; 663 case 2: 664 idx = RK3328_PLL_DPLL; 665 break; 666 case 3: 667 idx = RK3328_PLL_NPLL; 668 break; 669 } 670 return rk3328_get_frequency(sc, &idx) / (div_con + 1); 671 case RK3328_CLK_SDMMC: 672 return rk3328_get_sdmmc(sc, RK3328_CRU_CLKSEL_CON(30)); 673 case RK3328_CLK_SDIO: 674 return rk3328_get_sdmmc(sc, RK3328_CRU_CLKSEL_CON(31)); 675 case RK3328_CLK_EMMC: 676 return rk3328_get_sdmmc(sc, RK3328_CRU_CLKSEL_CON(32)); 677 case RK3328_CLK_UART0: 678 reg = HREAD4(sc, RK3328_CRU_CLKSEL_CON(14)); 679 mux = (reg >> 8) & 0x3; 680 if (mux == 2) 681 return 24000000; 682 break; 683 case RK3328_CLK_UART1: 684 reg = HREAD4(sc, RK3328_CRU_CLKSEL_CON(16)); 685 mux = (reg >> 8) & 0x3; 686 if (mux == 2) 687 return 24000000; 688 break; 689 case RK3328_CLK_UART2: 690 reg = HREAD4(sc, RK3328_CRU_CLKSEL_CON(18)); 691 mux = (reg >> 8) & 0x3; 692 if (mux == 2) 693 return 24000000; 694 break; 695 case RK3328_CLK_I2C0: 696 return rk3328_get_i2c(sc, RK3399_CRU_CLKSEL_CON(34), 0); 697 case RK3328_CLK_I2C1: 698 return rk3328_get_i2c(sc, RK3399_CRU_CLKSEL_CON(34), 8); 699 case RK3328_CLK_I2C2: 700 return rk3328_get_i2c(sc, RK3399_CRU_CLKSEL_CON(35), 0); 701 case RK3328_CLK_I2C3: 702 return rk3328_get_i2c(sc, RK3399_CRU_CLKSEL_CON(35), 8); 703 } 704 705 printf("%s: 0x%08x\n", __func__, idx); 706 return 0; 707 } 708 709 int 710 rk3328_set_frequency(void *cookie, uint32_t *cells, uint32_t freq) 711 { 712 uint32_t idx = cells[0]; 713 714 printf("%s: 0x%08x\n", __func__, idx); 715 return -1; 716 } 717 718 void 719 rk3328_enable(void *cookie, uint32_t *cells, int on) 720 { 721 uint32_t idx = cells[0]; 722 723 /* 724 * All clocks are enabled by default, so there is nothing for 725 * us to do until we start disabling clocks. 726 */ 727 if (!on) 728 printf("%s: 0x%08x\n", __func__, idx); 729 } 730 731 void 732 rk3328_reset(void *cookie, uint32_t *cells, int on) 733 { 734 struct rkclock_softc *sc = cookie; 735 uint32_t idx = cells[0]; 736 uint32_t mask = (1 << (idx % 16)); 737 738 HWRITE4(sc, RK3328_CRU_SOFTRST_CON(idx / 16), 739 mask << 16 | (on ? mask : 0)); 740 } 741 742 /* 743 * Rockchip RK3399 744 */ 745 746 /* Some of our parent clocks live in the PMUCRU. */ 747 struct rkclock_softc *rk3399_pmucru_sc; 748 749 void 750 rk3399_init(struct rkclock_softc *sc) 751 { 752 int node; 753 int i; 754 755 /* PMUCRU instance should attach before us. */ 756 KASSERT(rk3399_pmucru_sc != NULL); 757 758 /* 759 * Since the hardware comes up with a really conservative CPU 760 * clock frequency, and U-Boot doesn't set it to a more 761 * reasonable default, try to do so here. These defaults were 762 * chosen assuming that the voltage for both clusters is at 763 * least 1.0 V. Only do this on the Firefly-RK3399 for now 764 * where this is likely to be true given the default voltages 765 * for the regulators on that board. 766 */ 767 node = OF_finddevice("/"); 768 if (OF_is_compatible(node, "firefly,firefly-rk3399")) { 769 uint32_t idx; 770 771 /* Run the "LITTLE" cluster at 1.2 GHz. */ 772 idx = RK3399_ARMCLKL; 773 rk3399_set_frequency(sc, &idx, 1200000000); 774 775 #ifdef MULTIPROCESSOR 776 /* Switch PLL of the "big" cluster into normal mode. */ 777 HWRITE4(sc, RK3399_CRU_BPLL_CON(3), 778 RK3399_CRU_PLL_PLL_WORK_MODE_MASK << 16 | 779 RK3399_CRU_PLL_PLL_WORK_MODE_NORMAL); 780 #endif 781 } 782 783 /* The code below assumes all clocks are enabled. Check this!. */ 784 for (i = 0; i <= 34; i++) { 785 if (HREAD4(sc, RK3399_CRU_CLKGATE_CON(i)) != 0x00000000) { 786 printf("CRU_CLKGATE_CON%d: 0x%08x\n", i, 787 HREAD4(sc, RK3399_CRU_CLKGATE_CON(i))); 788 } 789 } 790 } 791 792 uint32_t 793 rk3399_get_pll(struct rkclock_softc *sc, bus_size_t base) 794 { 795 uint32_t fbdiv, postdiv1, postdiv2, refdiv; 796 uint32_t pll_work_mode; 797 uint32_t reg; 798 799 reg = HREAD4(sc, base + 0x000c); 800 pll_work_mode = reg & RK3399_CRU_PLL_PLL_WORK_MODE_MASK; 801 if (pll_work_mode == RK3399_CRU_PLL_PLL_WORK_MODE_SLOW) 802 return 24000000; 803 if (pll_work_mode == RK3399_CRU_PLL_PLL_WORK_MODE_DEEP_SLOW) 804 return 32768; 805 806 reg = HREAD4(sc, base + 0x0000); 807 fbdiv = (reg & RK3399_CRU_PLL_FBDIV_MASK) >> 808 RK3399_CRU_PLL_FBDIV_SHIFT; 809 reg = HREAD4(sc, base + 0x0004); 810 postdiv2 = (reg & RK3399_CRU_PLL_POSTDIV2_MASK) >> 811 RK3399_CRU_PLL_POSTDIV2_SHIFT; 812 postdiv1 = (reg & RK3399_CRU_PLL_POSTDIV1_MASK) >> 813 RK3399_CRU_PLL_POSTDIV1_SHIFT; 814 refdiv = (reg & RK3399_CRU_PLL_REFDIV_MASK) >> 815 RK3399_CRU_PLL_REFDIV_SHIFT; 816 return 24000000ULL * fbdiv / refdiv / postdiv1 / postdiv2; 817 } 818 819 int 820 rk3399_set_pll(struct rkclock_softc *sc, bus_size_t base, uint32_t freq) 821 { 822 uint32_t fbdiv, postdiv1, postdiv2, refdiv; 823 824 /* 825 * It is not clear whether all combinations of the clock 826 * dividers result in a stable clock. Therefore this function 827 * only supports a limited set of PLL clock rates. For now 828 * this set covers all the CPU frequencies supported by the 829 * Linux kernel. 830 */ 831 switch (freq) { 832 case 2208000000U: 833 case 2184000000U: 834 case 2088000000U: 835 case 2040000000U: 836 case 2016000000U: 837 case 1992000000U: 838 case 1896000000U: 839 case 1800000000U: 840 case 1704000000U: 841 case 1608000000U: 842 case 1512000000U: 843 case 1488000000U: 844 case 1416000000U: 845 case 1200000000U: 846 postdiv1 = postdiv2 = refdiv = 1; 847 break; 848 case 1008000000U: 849 case 816000000U: 850 case 696000000U: 851 postdiv1 = 2; postdiv2 = refdiv = 1; 852 break; 853 case 600000000U: 854 postdiv1 = 3; postdiv2 = refdiv = 1; 855 break; 856 case 408000000U: 857 postdiv1 = postdiv2 = 2; refdiv = 1; 858 break; 859 case 216000000U: 860 postdiv1 = 4; postdiv2 = 2; refdiv = 1; 861 break; 862 case 96000000U: 863 postdiv1 = postdiv2 = 4; refdiv = 1; 864 break; 865 default: 866 printf("%s: %d MHz\n", __func__, freq); 867 return -1; 868 } 869 870 /* Calculate feedback divider. */ 871 fbdiv = freq * postdiv1 * postdiv2 * refdiv / 24000000; 872 873 /* 874 * Select slow mode to guarantee a stable clock while we're 875 * adjusting the PLL. 876 */ 877 HWRITE4(sc, base + 0x000c, 878 RK3399_CRU_PLL_PLL_WORK_MODE_MASK << 16 | 879 RK3399_CRU_PLL_PLL_WORK_MODE_SLOW); 880 881 /* Set PLL rate. */ 882 HWRITE4(sc, base + 0x0000, 883 RK3399_CRU_PLL_FBDIV_MASK << 16 | 884 fbdiv << RK3399_CRU_PLL_FBDIV_SHIFT); 885 HWRITE4(sc, base + 0x0004, 886 RK3399_CRU_PLL_POSTDIV2_MASK << 16 | 887 postdiv2 << RK3399_CRU_PLL_POSTDIV2_SHIFT | 888 RK3399_CRU_PLL_POSTDIV1_MASK << 16 | 889 postdiv1 << RK3399_CRU_PLL_POSTDIV1_SHIFT | 890 RK3399_CRU_PLL_REFDIV_MASK << 16 | 891 refdiv << RK3399_CRU_PLL_REFDIV_SHIFT); 892 893 /* Wait for PLL to stabilize. */ 894 while ((HREAD4(sc, base + 0x0008) & RK3399_CRU_PLL_PLL_LOCK) == 0) 895 delay(10); 896 897 /* Switch back to normal mode. */ 898 HWRITE4(sc, base + 0x000c, 899 RK3399_CRU_PLL_PLL_WORK_MODE_MASK << 16 | 900 RK3399_CRU_PLL_PLL_WORK_MODE_NORMAL); 901 902 return 0; 903 } 904 905 uint32_t 906 rk3399_armclk_parent(uint32_t mux) 907 { 908 switch (mux) { 909 case 0: 910 return RK3399_PLL_ALPLL; 911 case 1: 912 return RK3399_PLL_ABPLL; 913 case 2: 914 return RK3399_PLL_DPLL; 915 case 3: 916 return RK3399_PLL_GPLL; 917 } 918 919 return 0; 920 } 921 922 uint32_t 923 rk3399_get_armclk(struct rkclock_softc *sc, bus_size_t clksel) 924 { 925 uint32_t reg, mux, div_con; 926 uint32_t idx; 927 928 reg = HREAD4(sc, clksel); 929 mux = (reg & RK3399_CRU_CORE_PLL_SEL_MASK) >> 930 RK3399_CRU_CORE_PLL_SEL_SHIFT; 931 div_con = (reg & RK3399_CRU_CLK_CORE_DIV_CON_MASK) >> 932 RK3399_CRU_CLK_CORE_DIV_CON_SHIFT; 933 idx = rk3399_armclk_parent(mux); 934 935 return rk3399_get_frequency(sc, &idx) / (div_con + 1); 936 } 937 938 int 939 rk3399_set_armclk(struct rkclock_softc *sc, bus_size_t clksel, uint32_t freq) 940 { 941 uint32_t reg, mux; 942 uint32_t old_freq, div; 943 uint32_t idx; 944 945 old_freq = rk3399_get_armclk(sc, clksel); 946 if (freq == old_freq) 947 return 0; 948 949 reg = HREAD4(sc, clksel); 950 mux = (reg & RK3399_CRU_CORE_PLL_SEL_MASK) >> 951 RK3399_CRU_CORE_PLL_SEL_SHIFT; 952 idx = rk3399_armclk_parent(mux); 953 954 /* Keep the atclk_core and pclk_dbg clocks at or below 200 MHz. */ 955 div = 1; 956 while (freq / (div + 1) > 200000000) 957 div++; 958 959 /* When ramping up, set clock dividers first. */ 960 if (freq > old_freq) { 961 HWRITE4(sc, RK3399_CRU_CLKSEL_CON(0), 962 RK3399_CRU_CLK_CORE_DIV_CON_MASK << 16 | 963 0 << RK3399_CRU_CLK_CORE_DIV_CON_SHIFT | 964 RK3399_CRU_ACLKM_CORE_DIV_CON_MASK << 16 | 965 1 << RK3399_CRU_ACLKM_CORE_DIV_CON_SHIFT); 966 HWRITE4(sc, RK3399_CRU_CLKSEL_CON(1), 967 RK3399_CRU_PCLK_DBG_DIV_CON_MASK << 16 | 968 div << RK3399_CRU_PCLK_DBG_DIV_CON_SHIFT | 969 RK3399_CRU_ATCLK_CORE_DIV_CON_MASK << 16 | 970 div << RK3399_CRU_ATCLK_CORE_DIV_CON_SHIFT); 971 } 972 973 rk3399_set_frequency(sc, &idx, freq); 974 975 /* When ramping dowm, set clock dividers last. */ 976 if (freq < old_freq) { 977 HWRITE4(sc, RK3399_CRU_CLKSEL_CON(0), 978 RK3399_CRU_CLK_CORE_DIV_CON_MASK << 16 | 979 0 << RK3399_CRU_CLK_CORE_DIV_CON_SHIFT | 980 RK3399_CRU_ACLKM_CORE_DIV_CON_MASK << 16 | 981 1 << RK3399_CRU_ACLKM_CORE_DIV_CON_SHIFT); 982 HWRITE4(sc, RK3399_CRU_CLKSEL_CON(1), 983 RK3399_CRU_PCLK_DBG_DIV_CON_MASK << 16 | 984 div << RK3399_CRU_PCLK_DBG_DIV_CON_SHIFT | 985 RK3399_CRU_ATCLK_CORE_DIV_CON_MASK << 16 | 986 div << RK3399_CRU_ATCLK_CORE_DIV_CON_SHIFT); 987 } 988 989 return 0; 990 } 991 992 uint32_t 993 rk3399_get_i2c(struct rkclock_softc *sc, size_t base, int shift) 994 { 995 uint32_t reg, mux, div_con; 996 uint32_t idx, freq; 997 998 reg = HREAD4(sc, base); 999 mux = (reg >> (7 + shift)) & 0x1; 1000 div_con = (reg >> shift) & 0x7f; 1001 if (mux == 1) { 1002 idx = RK3399_PLL_PPLL; 1003 freq = rk3399_pmu_get_frequency(rk3399_pmucru_sc, &idx); 1004 } else { 1005 idx = RK3399_PLL_CPLL; 1006 freq = rk3399_get_frequency(sc, &idx); 1007 } 1008 1009 return freq / (div_con + 1); 1010 } 1011 1012 uint32_t 1013 rk3399_get_frequency(void *cookie, uint32_t *cells) 1014 { 1015 struct rkclock_softc *sc = cookie; 1016 uint32_t idx = cells[0]; 1017 uint32_t reg, mux, div_con; 1018 1019 switch (idx) { 1020 case RK3399_PLL_ALPLL: 1021 return rk3399_get_pll(sc, RK3399_CRU_LPLL_CON(0)); 1022 case RK3399_PLL_ABPLL: 1023 return rk3399_get_pll(sc, RK3399_CRU_BPLL_CON(0)); 1024 case RK3399_PLL_DPLL: 1025 return rk3399_get_pll(sc, RK3399_CRU_DPLL_CON(0)); 1026 case RK3399_PLL_CPLL: 1027 return rk3399_get_pll(sc, RK3399_CRU_CPLL_CON(0)); 1028 case RK3399_PLL_GPLL: 1029 return rk3399_get_pll(sc, RK3399_CRU_GPLL_CON(0)); 1030 case RK3399_PLL_NPLL: 1031 return rk3399_get_pll(sc, RK3399_CRU_NPLL_CON(0)); 1032 case RK3399_ARMCLKL: 1033 return rk3399_get_armclk(sc, RK3399_CRU_CLKSEL_CON(0)); 1034 case RK3399_ARMCLKB: 1035 return rk3399_get_armclk(sc, RK3399_CRU_CLKSEL_CON(2)); 1036 case RK3399_CLK_I2C1: 1037 return rk3399_get_i2c(sc, RK3399_CRU_CLKSEL_CON(61), 0); 1038 case RK3399_CLK_I2C2: 1039 return rk3399_get_i2c(sc, RK3399_CRU_CLKSEL_CON(62), 0); 1040 case RK3399_CLK_I2C3: 1041 return rk3399_get_i2c(sc, RK3399_CRU_CLKSEL_CON(63), 0); 1042 case RK3399_CLK_I2C5: 1043 return rk3399_get_i2c(sc, RK3399_CRU_CLKSEL_CON(61), 8); 1044 case RK3399_CLK_I2C6: 1045 return rk3399_get_i2c(sc, RK3399_CRU_CLKSEL_CON(61), 8); 1046 case RK3399_CLK_I2C7: 1047 return rk3399_get_i2c(sc, RK3399_CRU_CLKSEL_CON(61), 8); 1048 case RK3399_CLK_SDMMC: 1049 reg = HREAD4(sc, RK3399_CRU_CLKSEL_CON(16)); 1050 mux = (reg >> 8) & 0x7; 1051 div_con = reg & 0x7f; 1052 switch (mux) { 1053 case 0: 1054 idx = RK3399_PLL_CPLL; 1055 break; 1056 case 1: 1057 idx = RK3399_PLL_GPLL; 1058 break; 1059 case 2: 1060 idx = RK3399_PLL_NPLL; 1061 break; 1062 #ifdef notyet 1063 case 3: 1064 idx = RK3399_PLL_PPLL; 1065 break; 1066 case 4: 1067 idx = RK3399_USB_480M; 1068 break; 1069 #endif 1070 case 5: 1071 return 24000000 / (div_con + 1); 1072 default: 1073 return 0; 1074 } 1075 return rk3399_get_frequency(sc, &idx) / (div_con + 1); 1076 break; 1077 case RK3399_CLK_UART0: 1078 reg = HREAD4(sc, RK3399_CRU_CLKSEL_CON(33)); 1079 mux = (reg >> 8) & 0x3; 1080 div_con = reg & 0x7f; 1081 if (mux == 2) 1082 return 24000000 / (div_con + 1); 1083 break; 1084 case RK3399_CLK_UART1: 1085 reg = HREAD4(sc, RK3399_CRU_CLKSEL_CON(34)); 1086 mux = (reg >> 8) & 0x3; 1087 div_con = reg & 0x7f; 1088 if (mux == 2) 1089 return 24000000 / (div_con + 1); 1090 break; 1091 case RK3399_CLK_UART2: 1092 reg = HREAD4(sc, RK3399_CRU_CLKSEL_CON(35)); 1093 mux = (reg >> 8) & 0x3; 1094 div_con = reg & 0x7f; 1095 if (mux == 2) 1096 return 24000000 / (div_con + 1); 1097 break; 1098 case RK3399_CLK_UART3: 1099 reg = HREAD4(sc, RK3399_CRU_CLKSEL_CON(36)); 1100 mux = (reg >> 8) & 0x3; 1101 div_con = reg & 0x7f; 1102 if (mux == 2) 1103 return 24000000 / (div_con + 1); 1104 break; 1105 case RK3399_HCLK_SDMMC: 1106 reg = HREAD4(sc, RK3399_CRU_CLKSEL_CON(13)); 1107 mux = (reg >> 15) & 0x1; 1108 div_con = (reg >> 8) & 0x1f; 1109 idx = mux ? RK3399_PLL_CPLL : RK3399_PLL_GPLL; 1110 return rk3399_get_frequency(sc, &idx) / (div_con + 1); 1111 default: 1112 break; 1113 } 1114 1115 printf("%s: 0x%08x\n", __func__, idx); 1116 return 0; 1117 } 1118 1119 int 1120 rk3399_set_frequency(void *cookie, uint32_t *cells, uint32_t freq) 1121 { 1122 struct rkclock_softc *sc = cookie; 1123 uint32_t idx = cells[0]; 1124 1125 switch (idx) { 1126 case RK3399_PLL_ALPLL: 1127 return rk3399_set_pll(sc, RK3399_CRU_LPLL_CON(0), freq); 1128 case RK3399_PLL_ABPLL: 1129 return rk3399_set_pll(sc, RK3399_CRU_BPLL_CON(0), freq); 1130 case RK3399_ARMCLKL: 1131 return rk3399_set_armclk(sc, RK3399_CRU_CLKSEL_CON(0), freq); 1132 case RK3399_ARMCLKB: 1133 return rk3399_set_armclk(sc, RK3399_CRU_CLKSEL_CON(2), freq); 1134 } 1135 1136 printf("%s: 0x%08x\n", __func__, idx); 1137 return -1; 1138 } 1139 1140 void 1141 rk3399_enable(void *cookie, uint32_t *cells, int on) 1142 { 1143 uint32_t idx = cells[0]; 1144 1145 /* 1146 * All clocks are enabled by default, so there is nothing for 1147 * us to do until we start disabling clocks. 1148 */ 1149 if (!on) 1150 printf("%s: 0x%08x\n", __func__, idx); 1151 } 1152 1153 void 1154 rk3399_reset(void *cookie, uint32_t *cells, int on) 1155 { 1156 struct rkclock_softc *sc = cookie; 1157 uint32_t idx = cells[0]; 1158 uint32_t mask = (1 << (idx % 16)); 1159 1160 HWRITE4(sc, RK3399_CRU_SOFTRST_CON(idx / 16), 1161 mask << 16 | (on ? mask : 0)); 1162 } 1163 1164 /* PMUCRU */ 1165 1166 void 1167 rk3399_pmu_init(struct rkclock_softc *sc) 1168 { 1169 rk3399_pmucru_sc = sc; 1170 } 1171 1172 uint32_t 1173 rk3399_pmu_get_i2c(struct rkclock_softc *sc, size_t base, int shift) 1174 { 1175 uint32_t reg, div_con; 1176 uint32_t idx; 1177 1178 reg = HREAD4(sc, base); 1179 div_con = (reg >> shift) & 0x7f; 1180 idx = RK3399_PLL_PPLL; 1181 return rk3399_get_frequency(sc, &idx) / (div_con + 1); 1182 } 1183 1184 uint32_t 1185 rk3399_pmu_get_frequency(void *cookie, uint32_t *cells) 1186 { 1187 struct rkclock_softc *sc = cookie; 1188 uint32_t idx = cells[0]; 1189 1190 switch (idx) { 1191 case RK3399_PLL_PPLL: 1192 return rk3399_get_pll(sc, RK3399_PMUCRU_PPLL_CON(0)); 1193 case RK3399_CLK_I2C0: 1194 return rk3399_pmu_get_i2c(sc, RK3399_PMUCRU_CLKSEL_CON(2), 0); 1195 case RK3399_CLK_I2C4: 1196 return rk3399_pmu_get_i2c(sc, RK3399_PMUCRU_CLKSEL_CON(3), 0); 1197 case RK3399_CLK_I2C8: 1198 return rk3399_pmu_get_i2c(sc, RK3399_PMUCRU_CLKSEL_CON(2), 8); 1199 default: 1200 break; 1201 } 1202 1203 printf("%s: 0x%08x\n", __func__, idx); 1204 return 0; 1205 } 1206 1207 int 1208 rk3399_pmu_set_frequency(void *cookie, uint32_t *cells, uint32_t freq) 1209 { 1210 uint32_t idx = cells[0]; 1211 1212 printf("%s: 0x%08x\n", __func__, idx); 1213 return -1; 1214 } 1215 1216 void 1217 rk3399_pmu_enable(void *cookie, uint32_t *cells, int on) 1218 { 1219 uint32_t idx = cells[0]; 1220 1221 switch (idx) { 1222 case RK3399_CLK_I2C0: 1223 case RK3399_CLK_I2C4: 1224 case RK3399_CLK_I2C8: 1225 case RK3399_PCLK_I2C0: 1226 case RK3399_PCLK_I2C4: 1227 case RK3399_PCLK_I2C8: 1228 /* Enabled by default. */ 1229 break; 1230 default: 1231 printf("%s: 0x%08x\n", __func__, idx); 1232 break; 1233 } 1234 } 1235 1236 void 1237 rk3399_pmu_reset(void *cookie, uint32_t *cells, int on) 1238 { 1239 uint32_t idx = cells[0]; 1240 1241 printf("%s: 0x%08x\n", __func__, idx); 1242 } 1243