1 /* $OpenBSD: imxsrc.c,v 1.3 2019/09/09 20:00:51 patrick Exp $ */ 2 /* 3 * Copyright (c) 2019 Patrick Wildt <patrick@blueri.se> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #include <sys/types.h> 19 #include <sys/systm.h> 20 #include <sys/device.h> 21 #include <sys/malloc.h> 22 23 #include <machine/cpufunc.h> 24 #include <machine/fdt.h> 25 26 #include <dev/ofw/openfirm.h> 27 #include <dev/ofw/ofw_clock.h> 28 #include <dev/ofw/fdt.h> 29 30 #define IMX8M_RESET_PCIEPHY 26 31 #define IMX8M_RESET_PCIEPHY_PERST 27 32 #define IMX8M_RESET_PCIE_CTRL_APPS_EN 28 33 #define IMX8M_RESET_PCIE_CTRL_APPS_TURNOFF 29 34 #define IMX8M_RESET_PCIE2PHY 34 35 #define IMX8M_RESET_PCIE2PHY_PERST 35 36 #define IMX8M_RESET_PCIE2_CTRL_APPS_EN 36 37 #define IMX8M_RESET_PCIE2_CTRL_APPS_TURNOFF 37 38 39 #define SRC_PCIE1_RCR 0x2c 40 #define SRC_PCIE2_RCR 0x48 41 #define SRC_PCIE_RCR_PCIEPHY_G_RST (1 << 1) 42 #define SRC_PCIE_RCR_PCIEPHY_BTN (1 << 2) 43 #define SRC_PCIE_RCR_PCIEPHY_PERST (1 << 3) 44 #define SRC_PCIE_RCR_PCIE_CTRL_APPS_EN (1 << 6) 45 #define SRC_PCIE_RCR_PCIE_CTRL_APPS_TURNOFF (1 << 11) 46 47 struct imxsrc_reset { 48 uint32_t reg; 49 uint32_t bit; 50 }; 51 52 struct imxsrc_reset imx8m_resets[] = { 53 [IMX8M_RESET_PCIEPHY] = { SRC_PCIE1_RCR, SRC_PCIE_RCR_PCIEPHY_G_RST | SRC_PCIE_RCR_PCIEPHY_BTN }, 54 [IMX8M_RESET_PCIEPHY_PERST] = { SRC_PCIE1_RCR, SRC_PCIE_RCR_PCIEPHY_PERST }, 55 [IMX8M_RESET_PCIE_CTRL_APPS_EN] = { SRC_PCIE1_RCR, SRC_PCIE_RCR_PCIE_CTRL_APPS_EN }, 56 [IMX8M_RESET_PCIE_CTRL_APPS_TURNOFF] = { SRC_PCIE1_RCR, SRC_PCIE_RCR_PCIE_CTRL_APPS_TURNOFF }, 57 [IMX8M_RESET_PCIE2PHY] = { SRC_PCIE2_RCR, SRC_PCIE_RCR_PCIEPHY_G_RST | SRC_PCIE_RCR_PCIEPHY_BTN }, 58 [IMX8M_RESET_PCIE2PHY_PERST] = { SRC_PCIE2_RCR, SRC_PCIE_RCR_PCIEPHY_PERST }, 59 [IMX8M_RESET_PCIE2_CTRL_APPS_EN] = { SRC_PCIE2_RCR, SRC_PCIE_RCR_PCIE_CTRL_APPS_EN }, 60 [IMX8M_RESET_PCIE2_CTRL_APPS_TURNOFF] = { SRC_PCIE2_RCR, SRC_PCIE_RCR_PCIE_CTRL_APPS_TURNOFF }, 61 }; 62 63 #define HREAD4(sc, reg) \ 64 (bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg))) 65 #define HWRITE4(sc, reg, val) \ 66 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 67 #define HSET4(sc, reg, bits) \ 68 HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits)) 69 #define HCLR4(sc, reg, bits) \ 70 HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits)) 71 72 struct imxsrc_softc { 73 struct device sc_dev; 74 bus_space_tag_t sc_iot; 75 bus_space_handle_t sc_ioh; 76 struct reset_device sc_rd; 77 struct imxsrc_reset *sc_resets; 78 int sc_nresets; 79 }; 80 81 int imxsrc_match(struct device *, void *, void *); 82 void imxsrc_attach(struct device *, struct device *, void *); 83 void imxsrc_reset(void *, uint32_t *, int); 84 85 struct cfattach imxsrc_ca = { 86 sizeof (struct imxsrc_softc), imxsrc_match, imxsrc_attach 87 }; 88 89 struct cfdriver imxsrc_cd = { 90 NULL, "imxsrc", DV_DULL 91 }; 92 93 int 94 imxsrc_match(struct device *parent, void *match, void *aux) 95 { 96 struct fdt_attach_args *faa = aux; 97 98 if (OF_is_compatible(faa->fa_node, "fsl,imx8mq-src")) 99 return 10; /* Must beat syscon(4). */ 100 101 return 0; 102 } 103 104 void 105 imxsrc_attach(struct device *parent, struct device *self, void *aux) 106 { 107 struct imxsrc_softc *sc = (struct imxsrc_softc *)self; 108 struct fdt_attach_args *faa = aux; 109 110 KASSERT(faa->fa_nreg >= 1); 111 112 sc->sc_iot = faa->fa_iot; 113 if (bus_space_map(sc->sc_iot, faa->fa_reg[0].addr, 114 faa->fa_reg[0].size, 0, &sc->sc_ioh)) 115 panic("%s: bus_space_map failed!", __func__); 116 117 sc->sc_resets = imx8m_resets; 118 sc->sc_nresets = nitems(imx8m_resets); 119 120 sc->sc_rd.rd_node = faa->fa_node; 121 sc->sc_rd.rd_cookie = sc; 122 sc->sc_rd.rd_reset = imxsrc_reset; 123 reset_register(&sc->sc_rd); 124 125 printf("\n"); 126 } 127 128 void 129 imxsrc_reset(void *cookie, uint32_t *cells, int assert) 130 { 131 struct imxsrc_softc *sc = cookie; 132 int idx = cells[0]; 133 uint32_t reg; 134 135 if (idx >= sc->sc_nresets || sc->sc_resets[idx].bit == 0) { 136 printf("%s: 0x%08x\n", __func__, idx); 137 return; 138 } 139 140 switch (idx) { 141 case IMX8M_RESET_PCIEPHY: 142 case IMX8M_RESET_PCIE2PHY: 143 if (!assert) 144 delay(10); 145 break; 146 case IMX8M_RESET_PCIE_CTRL_APPS_EN: 147 case IMX8M_RESET_PCIE2_CTRL_APPS_EN: 148 assert = !assert; 149 break; 150 } 151 152 reg = HREAD4(sc, sc->sc_resets[idx].reg); 153 if (assert) 154 reg |= sc->sc_resets[idx].bit; 155 else 156 reg &= ~sc->sc_resets[idx].bit; 157 HWRITE4(sc, sc->sc_resets[idx].reg, reg); 158 } 159