1 /* Public Domain */ 2 3 /* 4 * i.MX6Q clocks. 5 */ 6 7 #define IMX6_CLK_IPG 0x3e 8 #define IMX6_CLK_IPG_PER 0x3f 9 #define IMX6_CLK_ARM 0x68 10 #define IMX6_CLK_AHB 0x69 11 #define IMX6_CLK_ENET 0x75 12 #define IMX6_CLK_I2C1 0x7d 13 #define IMX6_CLK_I2C2 0x7e 14 #define IMX6_CLK_I2C3 0x7f 15 #define IMX6_CLK_SATA 0x9a 16 #define IMX6_CLK_UART_IPG 0xa0 17 #define IMX6_CLK_UART_SERIAL 0xa1 18 #define IMX6_CLK_USBOH3 0xa2 19 #define IMX6_CLK_USDHC1 0xa3 20 #define IMX6_CLK_USDHC2 0xa4 21 #define IMX6_CLK_USDHC3 0xa5 22 #define IMX6_CLK_USDHC4 0xa6 23 #define IMX6_CLK_USBPHY1 0xb6 24 #define IMX6_CLK_USBPHY2 0xb7 25 #define IMX6_CLK_SATA_REF 0xba 26 #define IMX6_CLK_SATA_REF_100 0xbb 27 #define IMX6_CLK_ENET_REF 0xbe 28 29 struct imxccm_gate imx6_gates[] = { 30 [IMX6_CLK_ENET] = { CCM_CCGR1, 5, IMX6_CLK_IPG }, 31 [IMX6_CLK_I2C1] = { CCM_CCGR2, 3, IMX6_CLK_IPG_PER }, 32 [IMX6_CLK_I2C2] = { CCM_CCGR2, 4, IMX6_CLK_IPG_PER }, 33 [IMX6_CLK_I2C3] = { CCM_CCGR2, 5, IMX6_CLK_IPG_PER }, 34 [IMX6_CLK_SATA] = { CCM_CCGR5, 2 }, 35 [IMX6_CLK_UART_IPG] = { CCM_CCGR5, 12, IMX6_CLK_IPG }, 36 [IMX6_CLK_UART_SERIAL] = { CCM_CCGR5, 13 }, 37 [IMX6_CLK_USBOH3] = { CCM_CCGR6, 0 }, 38 [IMX6_CLK_USDHC1] = { CCM_CCGR6, 1 }, 39 [IMX6_CLK_USDHC2] = { CCM_CCGR6, 2 }, 40 [IMX6_CLK_USDHC3] = { CCM_CCGR6, 3 }, 41 [IMX6_CLK_USDHC4] = { CCM_CCGR6, 4 }, 42 }; 43 44 /* 45 * i.MX6UL clocks. 46 */ 47 48 #define IMX6UL_CLK_ARM 0x5d 49 #define IMX6UL_CLK_PERCLK 0x63 50 #define IMX6UL_CLK_IPG 0x64 51 #define IMX6UL_CLK_GPT1_BUS 0x98 52 #define IMX6UL_CLK_GPT1_SERIAL 0x99 53 #define IMX6UL_CLK_I2C1 0x9c 54 #define IMX6UL_CLK_I2C2 0x9d 55 #define IMX6UL_CLK_I2C3 0x9e 56 #define IMX6UL_CLK_I2C4 0x9f 57 #define IMX6UL_CLK_UART1_IPG 0xbd 58 #define IMX6UL_CLK_UART1_SERIAL 0xbe 59 #define IMX6UL_CLK_USBOH3 0xcd 60 #define IMX6UL_CLK_USDHC1 0xce 61 #define IMX6UL_CLK_USDHC2 0xcf 62 63 struct imxccm_gate imx6ul_gates[] = 64 { 65 [IMX6UL_CLK_GPT1_BUS] = { CCM_CCGR1, 10, IMX6UL_CLK_PERCLK }, 66 [IMX6UL_CLK_GPT1_SERIAL] = { CCM_CCGR1, 11, IMX6UL_CLK_PERCLK }, 67 [IMX6UL_CLK_I2C1] = { CCM_CCGR2, 3, IMX6UL_CLK_PERCLK }, 68 [IMX6UL_CLK_I2C2] = { CCM_CCGR2, 4, IMX6UL_CLK_PERCLK }, 69 [IMX6UL_CLK_I2C3] = { CCM_CCGR2, 5, IMX6UL_CLK_PERCLK }, 70 [IMX6UL_CLK_I2C4] = { CCM_CCGR6, 12, IMX6UL_CLK_PERCLK }, 71 [IMX6UL_CLK_UART1_IPG] = { CCM_CCGR5, 12, IMX6UL_CLK_IPG }, 72 [IMX6UL_CLK_UART1_SERIAL] = { CCM_CCGR5, 12 }, 73 [IMX6UL_CLK_USBOH3] = { CCM_CCGR6, 0 }, 74 [IMX6UL_CLK_USDHC1] = { CCM_CCGR6, 1 }, 75 [IMX6UL_CLK_USDHC2] = { CCM_CCGR6, 2 }, 76 }; 77