1 /* Public Domain */ 2 3 /* 4 * i.MX6Q clocks. 5 */ 6 7 #define IMX6_CLK_IPG 0x3e 8 #define IMX6_CLK_IPG_PER 0x3f 9 #define IMX6_CLK_ECSPI_ROOT 0x47 10 #define IMX6_CLK_ARM 0x68 11 #define IMX6_CLK_AHB 0x69 12 #define IMX6_CLK_ECSPI2 0x71 13 #define IMX6_CLK_ENET 0x75 14 #define IMX6_CLK_I2C1 0x7d 15 #define IMX6_CLK_I2C2 0x7e 16 #define IMX6_CLK_I2C3 0x7f 17 #define IMX6_CLK_SATA 0x9a 18 #define IMX6_CLK_UART_IPG 0xa0 19 #define IMX6_CLK_UART_SERIAL 0xa1 20 #define IMX6_CLK_USBOH3 0xa2 21 #define IMX6_CLK_USDHC1 0xa3 22 #define IMX6_CLK_USDHC2 0xa4 23 #define IMX6_CLK_USDHC3 0xa5 24 #define IMX6_CLK_USDHC4 0xa6 25 #define IMX6_CLK_PLL3_USB_OTG 0xac 26 #define IMX6_CLK_PLL7_USB_HOST 0xb0 27 #define IMX6_CLK_PLL6_ENET 0xb1 28 #define IMX6_CLK_USBPHY1 0xb6 29 #define IMX6_CLK_USBPHY2 0xb7 30 #define IMX6_CLK_SATA_REF 0xba 31 #define IMX6_CLK_SATA_REF_100 0xbb 32 #define IMX6_CLK_ENET_REF 0xbe 33 #define IMX6_CLK_PLL3 0xe1 34 #define IMX6_CLK_PLL6 0xe4 35 #define IMX6_CLK_PLL7 0xe5 36 37 struct imxccm_gate imx6_gates[] = { 38 [IMX6_CLK_ECSPI2] = { CCM_CCGR1, 1, IMX6_CLK_ECSPI_ROOT }, 39 [IMX6_CLK_ENET] = { CCM_CCGR1, 5, IMX6_CLK_IPG }, 40 [IMX6_CLK_I2C1] = { CCM_CCGR2, 3, IMX6_CLK_IPG_PER }, 41 [IMX6_CLK_I2C2] = { CCM_CCGR2, 4, IMX6_CLK_IPG_PER }, 42 [IMX6_CLK_I2C3] = { CCM_CCGR2, 5, IMX6_CLK_IPG_PER }, 43 [IMX6_CLK_SATA] = { CCM_CCGR5, 2 }, 44 [IMX6_CLK_UART_IPG] = { CCM_CCGR5, 12, IMX6_CLK_IPG }, 45 [IMX6_CLK_UART_SERIAL] = { CCM_CCGR5, 13 }, 46 [IMX6_CLK_USBOH3] = { CCM_CCGR6, 0 }, 47 [IMX6_CLK_USDHC1] = { CCM_CCGR6, 1 }, 48 [IMX6_CLK_USDHC2] = { CCM_CCGR6, 2 }, 49 [IMX6_CLK_USDHC3] = { CCM_CCGR6, 3 }, 50 [IMX6_CLK_USDHC4] = { CCM_CCGR6, 4 }, 51 }; 52 53 /* 54 * i.MX6UL clocks. 55 */ 56 57 #define IMX6UL_CLK_ARM 0x5d 58 #define IMX6UL_CLK_PERCLK 0x63 59 #define IMX6UL_CLK_IPG 0x64 60 #define IMX6UL_CLK_GPT1_BUS 0x98 61 #define IMX6UL_CLK_GPT1_SERIAL 0x99 62 #define IMX6UL_CLK_I2C1 0x9c 63 #define IMX6UL_CLK_I2C2 0x9d 64 #define IMX6UL_CLK_I2C3 0x9e 65 #define IMX6UL_CLK_I2C4 0x9f 66 #define IMX6UL_CLK_UART1_IPG 0xbd 67 #define IMX6UL_CLK_UART1_SERIAL 0xbe 68 #define IMX6UL_CLK_USBOH3 0xcd 69 #define IMX6UL_CLK_USDHC1 0xce 70 #define IMX6UL_CLK_USDHC2 0xcf 71 72 struct imxccm_gate imx6ul_gates[] = { 73 [IMX6UL_CLK_GPT1_BUS] = { CCM_CCGR1, 10, IMX6UL_CLK_PERCLK }, 74 [IMX6UL_CLK_GPT1_SERIAL] = { CCM_CCGR1, 11, IMX6UL_CLK_PERCLK }, 75 [IMX6UL_CLK_I2C1] = { CCM_CCGR2, 3, IMX6UL_CLK_PERCLK }, 76 [IMX6UL_CLK_I2C2] = { CCM_CCGR2, 4, IMX6UL_CLK_PERCLK }, 77 [IMX6UL_CLK_I2C3] = { CCM_CCGR2, 5, IMX6UL_CLK_PERCLK }, 78 [IMX6UL_CLK_I2C4] = { CCM_CCGR6, 12, IMX6UL_CLK_PERCLK }, 79 [IMX6UL_CLK_UART1_IPG] = { CCM_CCGR5, 12, IMX6UL_CLK_IPG }, 80 [IMX6UL_CLK_UART1_SERIAL] = { CCM_CCGR5, 12 }, 81 [IMX6UL_CLK_USBOH3] = { CCM_CCGR6, 0 }, 82 [IMX6UL_CLK_USDHC1] = { CCM_CCGR6, 1 }, 83 [IMX6UL_CLK_USDHC2] = { CCM_CCGR6, 2 }, 84 }; 85 86 /* 87 * i.MX7D clocks. 88 */ 89 90 #define IMX7D_PLL_ENET_MAIN_125M_CLK 0x2a 91 #define IMX7D_ENET_AXI_ROOT_CLK 0x52 92 #define IMX7D_ENET_AXI_ROOT_SRC 0x53 93 #define IMX7D_ENET_AXI_ROOT_CG 0x54 94 #define IMX7D_ENET_AXI_ROOT_DIV 0x55 95 #define IMX7D_ENET1_IPG_ROOT_CLK 0x9e 96 #define IMX7D_ENET1_TIME_ROOT_CLK 0xa2 97 #define IMX7D_ENET1_TIME_ROOT_SRC 0xa3 98 #define IMX7D_ENET1_TIME_ROOT_CG 0xa4 99 #define IMX7D_ENET1_TIME_ROOT_DIV 0xa5 100 #define IMX7D_ENET2_IPG_ROOT_CLK 0xa6 101 #define IMX7D_ENET2_TIME_ROOT_CLK 0xaa 102 #define IMX7D_ENET2_TIME_ROOT_SRC 0xab 103 #define IMX7D_ENET2_TIME_ROOT_CG 0xac 104 #define IMX7D_ENET2_TIME_ROOT_DIV 0xad 105 #define IMX7D_ENET_PHY_REF_ROOT_CLK 0xae 106 #define IMX7D_ENET_PHY_REF_ROOT_SRC 0xaf 107 #define IMX7D_ENET_PHY_REF_ROOT_CG 0xb0 108 #define IMX7D_ENET_PHY_REF_ROOT_DIV 0xb1 109 #define IMX7D_USDHC1_ROOT_CLK 0xbe 110 #define IMX7D_USDHC1_ROOT_SRC 0xbf 111 #define IMX7D_USDHC1_ROOT_CG 0xc0 112 #define IMX7D_USDHC1_ROOT_DIV 0xc1 113 #define IMX7D_USDHC2_ROOT_CLK 0xc2 114 #define IMX7D_USDHC2_ROOT_SRC 0xc3 115 #define IMX7D_USDHC2_ROOT_CG 0xc4 116 #define IMX7D_USDHC2_ROOT_DIV 0xc5 117 #define IMX7D_USDHC3_ROOT_CLK 0xc6 118 #define IMX7D_USDHC3_ROOT_SRC 0xc7 119 #define IMX7D_USDHC3_ROOT_CG 0xc8 120 #define IMX7D_USDHC3_ROOT_DIV 0xc9 121 #define IMX7D_I2C1_ROOT_CLK 0xd2 122 #define IMX7D_I2C1_ROOT_SRC 0xd3 123 #define IMX7D_I2C1_ROOT_CG 0xd4 124 #define IMX7D_I2C1_ROOT_DIV 0xd5 125 #define IMX7D_I2C2_ROOT_CLK 0xd6 126 #define IMX7D_I2C2_ROOT_SRC 0xd7 127 #define IMX7D_I2C2_ROOT_CG 0xd8 128 #define IMX7D_I2C2_ROOT_DIV 0xd9 129 #define IMX7D_I2C3_ROOT_CLK 0xda 130 #define IMX7D_I2C3_ROOT_SRC 0xdb 131 #define IMX7D_I2C3_ROOT_CG 0xdc 132 #define IMX7D_I2C3_ROOT_DIV 0xdd 133 #define IMX7D_I2C4_ROOT_CLK 0xde 134 #define IMX7D_I2C4_ROOT_SRC 0xdf 135 #define IMX7D_I2C4_ROOT_CG 0xe0 136 #define IMX7D_I2C4_ROOT_DIV 0xe1 137 #define IMX7D_UART1_ROOT_CLK 0xe2 138 #define IMX7D_UART1_ROOT_SRC 0xe3 139 #define IMX7D_UART1_ROOT_CG 0xe4 140 #define IMX7D_UART1_ROOT_DIV 0xe5 141 #define IMX7D_UART2_ROOT_CLK 0xe6 142 #define IMX7D_UART2_ROOT_SRC 0xe7 143 #define IMX7D_UART2_ROOT_CG 0xe8 144 #define IMX7D_UART2_ROOT_DIV 0xe9 145 #define IMX7D_UART3_ROOT_CLK 0xea 146 #define IMX7D_UART3_ROOT_SRC 0xeb 147 #define IMX7D_UART3_ROOT_CG 0xec 148 #define IMX7D_UART3_ROOT_DIV 0xed 149 #define IMX7D_UART4_ROOT_CLK 0xee 150 #define IMX7D_UART4_ROOT_SRC 0xef 151 #define IMX7D_UART4_ROOT_CG 0xf0 152 #define IMX7D_UART4_ROOT_DIV 0xf1 153 #define IMX7D_UART5_ROOT_CLK 0xf2 154 #define IMX7D_UART5_ROOT_SRC 0xf3 155 #define IMX7D_UART5_ROOT_CG 0xf4 156 #define IMX7D_UART5_ROOT_DIV 0xf5 157 #define IMX7D_UART6_ROOT_CLK 0xf6 158 #define IMX7D_UART6_ROOT_SRC 0xf7 159 #define IMX7D_UART6_ROOT_CG 0xf8 160 #define IMX7D_UART6_ROOT_DIV 0xf9 161 #define IMX7D_UART7_ROOT_CLK 0xfa 162 #define IMX7D_UART7_ROOT_SRC 0xfb 163 #define IMX7D_UART7_ROOT_CG 0xfc 164 #define IMX7D_UART7_ROOT_DIV 0xfd 165 #define IMX7D_ENET_AXI_ROOT_PRE_DIV 0x15a 166 #define IMX7D_ENET1_TIME_ROOT_PRE_DIV 0x16a 167 #define IMX7D_ENET2_TIME_ROOT_PRE_DIV 0x16c 168 #define IMX7D_ENET_PHY_REF_ROOT_PRE_DIV 0x16d 169 #define IMX7D_USDHC1_ROOT_PRE_DIV 0x171 170 #define IMX7D_USDHC2_ROOT_PRE_DIV 0x172 171 #define IMX7D_USDHC3_ROOT_PRE_DIV 0x173 172 #define IMX7D_I2C1_ROOT_PRE_DIV 0x176 173 #define IMX7D_I2C2_ROOT_PRE_DIV 0x177 174 #define IMX7D_I2C3_ROOT_PRE_DIV 0x178 175 #define IMX7D_I2C4_ROOT_PRE_DIV 0x179 176 #define IMX7D_UART1_ROOT_PRE_DIV 0x17a 177 #define IMX7D_UART2_ROOT_PRE_DIV 0x17b 178 #define IMX7D_UART3_ROOT_PRE_DIV 0x17c 179 #define IMX7D_UART4_ROOT_PRE_DIV 0x17d 180 #define IMX7D_UART5_ROOT_PRE_DIV 0x17e 181 #define IMX7D_UART6_ROOT_PRE_DIV 0x17f 182 #define IMX7D_UART7_ROOT_PRE_DIV 0x180 183 #define IMX7D_USB_CTRL_CLK 0x1a6 184 #define IMX7D_USB_PHY1_CLK 0x1a7 185 #define IMX7D_USB_PHY2_CLK 0x1a8 186 187 struct imxccm_gate imx7d_gates[] = { 188 [IMX7D_ENET_AXI_ROOT_CG] = { 0x8900, 28, IMX7D_ENET_AXI_ROOT_SRC }, 189 [IMX7D_ENET1_TIME_ROOT_CG] = { 0xa780, 28, IMX7D_ENET1_TIME_ROOT_SRC }, 190 [IMX7D_ENET2_TIME_ROOT_CG] = { 0xa880, 28, IMX7D_ENET2_TIME_ROOT_SRC }, 191 [IMX7D_ENET_PHY_REF_ROOT_CG] = { 0xa900, 28, IMX7D_ENET_PHY_REF_ROOT_SRC }, 192 [IMX7D_USDHC1_ROOT_CG] = { 0xab00, 28, IMX7D_USDHC1_ROOT_SRC }, 193 [IMX7D_USDHC2_ROOT_CG] = { 0xab80, 28, IMX7D_USDHC2_ROOT_SRC }, 194 [IMX7D_USDHC3_ROOT_CG] = { 0xabc0, 28, IMX7D_USDHC3_ROOT_SRC }, 195 [IMX7D_I2C1_ROOT_CG] = { 0xad80, 28, IMX7D_I2C1_ROOT_SRC }, 196 [IMX7D_I2C2_ROOT_CG] = { 0xae00, 28, IMX7D_I2C2_ROOT_SRC }, 197 [IMX7D_I2C3_ROOT_CG] = { 0xae80, 28, IMX7D_I2C3_ROOT_SRC }, 198 [IMX7D_I2C4_ROOT_CG] = { 0xaf00, 28, IMX7D_I2C4_ROOT_SRC }, 199 [IMX7D_UART1_ROOT_CG] = { 0xaf80, 28, IMX7D_UART1_ROOT_SRC }, 200 [IMX7D_UART2_ROOT_CG] = { 0xb000, 28, IMX7D_UART2_ROOT_SRC }, 201 [IMX7D_UART3_ROOT_CG] = { 0xb080, 28, IMX7D_UART3_ROOT_SRC }, 202 [IMX7D_UART4_ROOT_CG] = { 0xb100, 28, IMX7D_UART4_ROOT_SRC }, 203 [IMX7D_UART5_ROOT_CG] = { 0xb180, 28, IMX7D_UART5_ROOT_SRC }, 204 [IMX7D_UART6_ROOT_CG] = { 0xb200, 28, IMX7D_UART6_ROOT_SRC }, 205 [IMX7D_UART7_ROOT_CG] = { 0xb280, 28, IMX7D_UART7_ROOT_SRC }, 206 [IMX7D_ENET_AXI_ROOT_CLK] = { 0x4060, 0, IMX7D_ENET_AXI_ROOT_DIV }, 207 [IMX7D_USB_CTRL_CLK] = { 0x4680, 0 }, 208 [IMX7D_USB_PHY1_CLK] = { 0x46a0, 0 }, 209 [IMX7D_USB_PHY2_CLK] = { 0x46b0, 0 }, 210 [IMX7D_USDHC1_ROOT_CLK] = { 0x46c0, 0, IMX7D_USDHC1_ROOT_DIV }, 211 [IMX7D_USDHC2_ROOT_CLK] = { 0x46d0, 0, IMX7D_USDHC2_ROOT_DIV }, 212 [IMX7D_USDHC3_ROOT_CLK] = { 0x46e0, 0, IMX7D_USDHC3_ROOT_DIV }, 213 [IMX7D_ENET1_IPG_ROOT_CLK] = { 0x4700, 0, IMX7D_ENET_AXI_ROOT_DIV }, 214 [IMX7D_ENET1_TIME_ROOT_CLK] = { 0x4700, 0, IMX7D_ENET1_TIME_ROOT_DIV }, 215 [IMX7D_ENET2_IPG_ROOT_CLK] = { 0x4710, 0, IMX7D_ENET_AXI_ROOT_DIV }, 216 [IMX7D_ENET2_TIME_ROOT_CLK] = { 0x4710, 0, IMX7D_ENET1_TIME_ROOT_DIV }, 217 [IMX7D_I2C1_ROOT_CLK] = { 0x4880, 0, IMX7D_I2C1_ROOT_DIV }, 218 [IMX7D_I2C2_ROOT_CLK] = { 0x4890, 0, IMX7D_I2C2_ROOT_DIV }, 219 [IMX7D_I2C3_ROOT_CLK] = { 0x48a0, 0, IMX7D_I2C3_ROOT_DIV }, 220 [IMX7D_I2C4_ROOT_CLK] = { 0x48b0, 0, IMX7D_I2C4_ROOT_DIV }, 221 [IMX7D_UART1_ROOT_CLK] = { 0x4940, 0, IMX7D_UART1_ROOT_DIV }, 222 [IMX7D_UART2_ROOT_CLK] = { 0x4950, 0, IMX7D_UART2_ROOT_DIV }, 223 [IMX7D_UART3_ROOT_CLK] = { 0x4960, 0, IMX7D_UART3_ROOT_DIV }, 224 [IMX7D_UART4_ROOT_CLK] = { 0x4970, 0, IMX7D_UART4_ROOT_DIV }, 225 [IMX7D_UART5_ROOT_CLK] = { 0x4980, 0, IMX7D_UART5_ROOT_DIV }, 226 [IMX7D_UART6_ROOT_CLK] = { 0x4990, 0, IMX7D_UART6_ROOT_DIV }, 227 [IMX7D_UART7_ROOT_CLK] = { 0x49a0, 0, IMX7D_UART7_ROOT_DIV }, 228 }; 229 230 struct imxccm_divider imx7d_divs[] = { 231 [IMX7D_ENET_AXI_ROOT_PRE_DIV] = { 0x8900, 16, 0x7, IMX7D_ENET_AXI_ROOT_CG }, 232 [IMX7D_ENET1_TIME_ROOT_PRE_DIV] = { 0xa780, 16, 0x7, IMX7D_ENET1_TIME_ROOT_CG }, 233 [IMX7D_ENET2_TIME_ROOT_PRE_DIV] = { 0xa880, 16, 0x7, IMX7D_ENET2_TIME_ROOT_CG }, 234 [IMX7D_ENET_PHY_REF_ROOT_PRE_DIV] = { 0xa900, 16, 0x7, IMX7D_ENET_PHY_REF_ROOT_CG }, 235 [IMX7D_USDHC1_ROOT_PRE_DIV] = { 0xab00, 16, 0x7, IMX7D_USDHC1_ROOT_CG }, 236 [IMX7D_USDHC2_ROOT_PRE_DIV] = { 0xab80, 16, 0x7, IMX7D_USDHC2_ROOT_CG }, 237 [IMX7D_USDHC3_ROOT_PRE_DIV] = { 0xac00, 16, 0x7, IMX7D_USDHC3_ROOT_CG }, 238 [IMX7D_I2C1_ROOT_PRE_DIV] = { 0xad80, 16, 0x7, IMX7D_I2C1_ROOT_CG }, 239 [IMX7D_I2C2_ROOT_PRE_DIV] = { 0xae00, 16, 0x7, IMX7D_I2C2_ROOT_CG }, 240 [IMX7D_I2C3_ROOT_PRE_DIV] = { 0xae80, 16, 0x7, IMX7D_I2C3_ROOT_CG }, 241 [IMX7D_I2C4_ROOT_PRE_DIV] = { 0xaf00, 16, 0x7, IMX7D_I2C4_ROOT_CG }, 242 [IMX7D_UART1_ROOT_PRE_DIV] = { 0xaf80, 16, 0x7, IMX7D_UART1_ROOT_CG }, 243 [IMX7D_UART2_ROOT_PRE_DIV] = { 0xb000, 16, 0x7, IMX7D_UART2_ROOT_CG }, 244 [IMX7D_UART3_ROOT_PRE_DIV] = { 0xb080, 16, 0x7, IMX7D_UART3_ROOT_CG }, 245 [IMX7D_UART4_ROOT_PRE_DIV] = { 0xb100, 16, 0x7, IMX7D_UART4_ROOT_CG }, 246 [IMX7D_UART5_ROOT_PRE_DIV] = { 0xb180, 16, 0x7, IMX7D_UART5_ROOT_CG }, 247 [IMX7D_UART6_ROOT_PRE_DIV] = { 0xb200, 16, 0x7, IMX7D_UART6_ROOT_CG }, 248 [IMX7D_UART7_ROOT_PRE_DIV] = { 0xb280, 16, 0x7, IMX7D_UART7_ROOT_CG }, 249 [IMX7D_ENET_AXI_ROOT_DIV] = { 0x8900, 0, 0x3f, IMX7D_ENET_AXI_ROOT_PRE_DIV }, 250 [IMX7D_ENET1_TIME_ROOT_DIV] = { 0xa780, 0, 0x3f, IMX7D_ENET1_TIME_ROOT_PRE_DIV }, 251 [IMX7D_ENET2_TIME_ROOT_DIV] = { 0xa880, 0, 0x3f, IMX7D_ENET2_TIME_ROOT_PRE_DIV }, 252 [IMX7D_ENET_PHY_REF_ROOT_CLK] = { 0xa900, 0, 0x3f, IMX7D_ENET_PHY_REF_ROOT_PRE_DIV }, 253 [IMX7D_USDHC1_ROOT_DIV] = { 0xab00, 0, 0x3f, IMX7D_USDHC1_ROOT_PRE_DIV }, 254 [IMX7D_USDHC2_ROOT_DIV] = { 0xab80, 0, 0x3f, IMX7D_USDHC2_ROOT_PRE_DIV }, 255 [IMX7D_USDHC3_ROOT_DIV] = { 0xac00, 0, 0x3f, IMX7D_USDHC3_ROOT_PRE_DIV }, 256 [IMX7D_I2C1_ROOT_DIV] = { 0xad80, 0, 0x3f, IMX7D_I2C1_ROOT_PRE_DIV }, 257 [IMX7D_I2C2_ROOT_DIV] = { 0xae00, 0, 0x3f, IMX7D_I2C2_ROOT_PRE_DIV }, 258 [IMX7D_I2C3_ROOT_DIV] = { 0xae80, 0, 0x3f, IMX7D_I2C3_ROOT_PRE_DIV }, 259 [IMX7D_I2C4_ROOT_DIV] = { 0xaf00, 0, 0x3f, IMX7D_I2C4_ROOT_PRE_DIV }, 260 [IMX7D_UART1_ROOT_DIV] = { 0xaf80, 0, 0x3f, IMX7D_UART1_ROOT_PRE_DIV }, 261 [IMX7D_UART2_ROOT_DIV] = { 0xb000, 0, 0x3f, IMX7D_UART2_ROOT_PRE_DIV }, 262 [IMX7D_UART3_ROOT_DIV] = { 0xb080, 0, 0x3f, IMX7D_UART3_ROOT_PRE_DIV }, 263 [IMX7D_UART4_ROOT_DIV] = { 0xb100, 0, 0x3f, IMX7D_UART4_ROOT_PRE_DIV }, 264 [IMX7D_UART5_ROOT_DIV] = { 0xb180, 0, 0x3f, IMX7D_UART5_ROOT_PRE_DIV }, 265 [IMX7D_UART6_ROOT_DIV] = { 0xb200, 0, 0x3f, IMX7D_UART6_ROOT_PRE_DIV }, 266 [IMX7D_UART7_ROOT_DIV] = { 0xb280, 0, 0x3f, IMX7D_UART7_ROOT_PRE_DIV }, 267 }; 268 269 struct imxccm_mux imx7d_muxs[] = { 270 [IMX7D_ENET_AXI_ROOT_SRC] = { 0x8900, 24, 0x7 }, 271 [IMX7D_ENET1_TIME_ROOT_SRC] = { 0xa780, 24, 0x7 }, 272 [IMX7D_ENET2_TIME_ROOT_SRC] = { 0xa880, 24, 0x7 }, 273 [IMX7D_ENET_PHY_REF_ROOT_SRC] = { 0xa900, 24, 0x7 }, 274 [IMX7D_USDHC1_ROOT_SRC] = { 0xab00, 24, 0x7 }, 275 [IMX7D_USDHC2_ROOT_SRC] = { 0xab80, 24, 0x7 }, 276 [IMX7D_USDHC3_ROOT_SRC] = { 0xac00, 24, 0x7 }, 277 [IMX7D_I2C1_ROOT_SRC] = { 0xad80, 24, 0x7 }, 278 [IMX7D_I2C2_ROOT_SRC] = { 0xae00, 24, 0x7 }, 279 [IMX7D_I2C3_ROOT_SRC] = { 0xae80, 24, 0x7 }, 280 [IMX7D_I2C4_ROOT_SRC] = { 0xaf00, 24, 0x7 }, 281 [IMX7D_UART1_ROOT_SRC] = { 0xaf80, 24, 0x7 }, 282 [IMX7D_UART2_ROOT_SRC] = { 0xb000, 24, 0x7 }, 283 [IMX7D_UART3_ROOT_SRC] = { 0xb080, 24, 0x7 }, 284 [IMX7D_UART4_ROOT_SRC] = { 0xb100, 24, 0x7 }, 285 [IMX7D_UART5_ROOT_SRC] = { 0xb180, 24, 0x7 }, 286 [IMX7D_UART6_ROOT_SRC] = { 0xb200, 24, 0x7 }, 287 [IMX7D_UART7_ROOT_SRC] = { 0xb280, 24, 0x7 }, 288 }; 289 290 /* 291 * i.MX8MQ clocks. 292 */ 293 294 #define IMX8MQ_ARM_PLL 0x0a 295 #define IMX8MQ_ARM_PLL_OUT 0x0c 296 #define IMX8MQ_SYS1_PLL_100M 0x48 297 #define IMX8MQ_SYS1_PLL_266M 0x4c 298 #define IMX8MQ_SYS1_PLL_400M 0x4d 299 #define IMX8MQ_SYS1_PLL_800M 0x4e 300 #define IMX8MQ_SYS2_PLL_100M 0x50 301 #define IMX8MQ_SYS2_PLL_250M 0x54 302 #define IMX8MQ_SYS2_PLL_500M 0x56 303 #define IMX8MQ_CLK_A53_SRC 0x58 304 #define IMX8MQ_CLK_A53_CG 0x59 305 #define IMX8MQ_CLK_A53_DIV 0x5a 306 #define IMX8MQ_CLK_ENET_AXI_SRC 0x6b 307 #define IMX8MQ_CLK_ENET_AXI_CG 0x6c 308 #define IMX8MQ_CLK_ENET_AXI_PRE_DIV 0x6d 309 #define IMX8MQ_CLK_ENET_AXI_DIV 0x6e 310 #define IMX8MQ_CLK_USB_BUS_SRC 0x83 311 #define IMX8MQ_CLK_USB_BUS_CG 0x84 312 #define IMX8MQ_CLK_USB_BUS_PRE_DIV 0x85 313 #define IMX8MQ_CLK_PCIE1_CTRL_SRC 0xb7 314 #define IMX8MQ_CLK_PCIE1_CTRL_CG 0xb8 315 #define IMX8MQ_CLK_PCIE1_CTRL_PRE_DIV 0xb9 316 #define IMX8MQ_CLK_PCIE1_CTRL_DIV 0xba 317 #define IMX8MQ_CLK_PCIE1_PHY_SRC 0xbb 318 #define IMX8MQ_CLK_PCIE1_PHY_CG 0xbc 319 #define IMX8MQ_CLK_PCIE1_PHY_PRE_DIV 0xbd 320 #define IMX8MQ_CLK_PCIE1_PHY_DIV 0xbe 321 #define IMX8MQ_CLK_PCIE1_AUX_SRC 0xbf 322 #define IMX8MQ_CLK_PCIE1_AUX_CG 0xc0 323 #define IMX8MQ_CLK_PCIE1_AUX_PRE_DIV 0xc1 324 #define IMX8MQ_CLK_PCIE1_AUX_DIV 0xc2 325 #define IMX8MQ_CLK_USB_BUS_DIV 0x86 326 #define IMX8MQ_CLK_ENET_REF_SRC 0xeb 327 #define IMX8MQ_CLK_ENET_REF_CG 0xec 328 #define IMX8MQ_CLK_ENET_REF_PRE_DIV 0xed 329 #define IMX8MQ_CLK_ENET_REF_DIV 0xee 330 #define IMX8MQ_CLK_ENET_TIMER_SRC 0xef 331 #define IMX8MQ_CLK_ENET_TIMER_CG 0xf0 332 #define IMX8MQ_CLK_ENET_TIMER_PRE_DIV 0xf1 333 #define IMX8MQ_CLK_ENET_TIMER_DIV 0xf2 334 #define IMX8MQ_CLK_ENET_PHY_REF_SRC 0xf3 335 #define IMX8MQ_CLK_ENET_PHY_REF_CG 0xf4 336 #define IMX8MQ_CLK_ENET_PHY_REF_PRE_DIV 0xf5 337 #define IMX8MQ_CLK_ENET_PHY_REF_DIV 0xf6 338 #define IMX8MQ_CLK_USDHC1_SRC 0xff 339 #define IMX8MQ_CLK_USDHC1_CG 0x100 340 #define IMX8MQ_CLK_USDHC1_PRE_DIV 0x101 341 #define IMX8MQ_CLK_USDHC1_DIV 0x102 342 #define IMX8MQ_CLK_USDHC2_SRC 0x103 343 #define IMX8MQ_CLK_USDHC2_CG 0x104 344 #define IMX8MQ_CLK_USDHC2_PRE_DIV 0x105 345 #define IMX8MQ_CLK_USDHC2_DIV 0x106 346 #define IMX8MQ_CLK_I2C1_SRC 0x107 347 #define IMX8MQ_CLK_I2C1_CG 0x108 348 #define IMX8MQ_CLK_I2C1_PRE_DIV 0x109 349 #define IMX8MQ_CLK_I2C1_DIV 0x10a 350 #define IMX8MQ_CLK_I2C2_SRC 0x10b 351 #define IMX8MQ_CLK_I2C2_CG 0x10c 352 #define IMX8MQ_CLK_I2C2_PRE_DIV 0x10d 353 #define IMX8MQ_CLK_I2C2_DIV 0x10e 354 #define IMX8MQ_CLK_I2C3_SRC 0x10f 355 #define IMX8MQ_CLK_I2C3_CG 0x110 356 #define IMX8MQ_CLK_I2C3_PRE_DIV 0x111 357 #define IMX8MQ_CLK_I2C3_DIV 0x112 358 #define IMX8MQ_CLK_I2C4_SRC 0x113 359 #define IMX8MQ_CLK_I2C4_CG 0x114 360 #define IMX8MQ_CLK_I2C4_PRE_DIV 0x115 361 #define IMX8MQ_CLK_I2C4_DIV 0x116 362 #define IMX8MQ_CLK_UART1_SRC 0x117 363 #define IMX8MQ_CLK_UART1_CG 0x118 364 #define IMX8MQ_CLK_UART1_PRE_DIV 0x119 365 #define IMX8MQ_CLK_UART1_DIV 0x11a 366 #define IMX8MQ_CLK_UART2_SRC 0x11b 367 #define IMX8MQ_CLK_UART2_CG 0x11c 368 #define IMX8MQ_CLK_UART2_PRE_DIV 0x11d 369 #define IMX8MQ_CLK_UART2_DIV 0x11e 370 #define IMX8MQ_CLK_UART3_SRC 0x11f 371 #define IMX8MQ_CLK_UART3_CG 0x120 372 #define IMX8MQ_CLK_UART3_PRE_DIV 0x121 373 #define IMX8MQ_CLK_UART3_DIV 0x122 374 #define IMX8MQ_CLK_UART4_SRC 0x123 375 #define IMX8MQ_CLK_UART4_CG 0x124 376 #define IMX8MQ_CLK_UART4_PRE_DIV 0x125 377 #define IMX8MQ_CLK_UART4_DIV 0x126 378 #define IMX8MQ_CLK_USB_CORE_REF_SRC 0x127 379 #define IMX8MQ_CLK_USB_CORE_REF_CG 0x128 380 #define IMX8MQ_CLK_USB_CORE_REF_PRE_DIV 0x129 381 #define IMX8MQ_CLK_USB_CORE_REF_DIV 0x12a 382 #define IMX8MQ_CLK_USB_PHY_REF_SRC 0x12b 383 #define IMX8MQ_CLK_USB_PHY_REF_CG 0x12c 384 #define IMX8MQ_CLK_USB_PHY_REF_PRE_DIV 0x12d 385 #define IMX8MQ_CLK_USB_PHY_REF_DIV 0x12e 386 #define IMX8MQ_CLK_ECSPI1_SRC 0x12f 387 #define IMX8MQ_CLK_ECSPI1_CG 0x130 388 #define IMX8MQ_CLK_ECSPI1_PRE_DIV 0x131 389 #define IMX8MQ_CLK_ECSPI1_DIV 0x132 390 #define IMX8MQ_CLK_ECSPI2_SRC 0x133 391 #define IMX8MQ_CLK_ECSPI2_CG 0x134 392 #define IMX8MQ_CLK_ECSPI2_PRE_DIV 0x135 393 #define IMX8MQ_CLK_ECSPI2_DIV 0x136 394 #define IMX8MQ_CLK_PCIE2_CTRL_SRC 0x17b 395 #define IMX8MQ_CLK_PCIE2_CTRL_CG 0x17c 396 #define IMX8MQ_CLK_PCIE2_CTRL_PRE_DIV 0x17d 397 #define IMX8MQ_CLK_PCIE2_CTRL_DIV 0x17e 398 #define IMX8MQ_CLK_PCIE2_PHY_SRC 0x17f 399 #define IMX8MQ_CLK_PCIE2_PHY_CG 0x180 400 #define IMX8MQ_CLK_PCIE2_PHY_PRE_DIV 0x181 401 #define IMX8MQ_CLK_PCIE2_PHY_DIV 0x182 402 #define IMX8MQ_CLK_PCIE2_AUX_SRC 0x183 403 #define IMX8MQ_CLK_PCIE2_AUX_CG 0x184 404 #define IMX8MQ_CLK_PCIE2_AUX_PRE_DIV 0x185 405 #define IMX8MQ_CLK_PCIE2_AUX_DIV 0x186 406 #define IMX8MQ_CLK_ECSPI3_SRC 0x187 407 #define IMX8MQ_CLK_ECSPI3_CG 0x188 408 #define IMX8MQ_CLK_ECSPI3_PRE_DIV 0x189 409 #define IMX8MQ_CLK_ECSPI3_DIV 0x18a 410 #define IMX8MQ_CLK_ECSPI1_ROOT 0x18d 411 #define IMX8MQ_CLK_ECSPI2_ROOT 0x18e 412 #define IMX8MQ_CLK_ECSPI3_ROOT 0x18f 413 #define IMX8MQ_CLK_ENET1_ROOT 0x190 414 #define IMX8MQ_CLK_I2C1_ROOT 0x192 415 #define IMX8MQ_CLK_I2C2_ROOT 0x193 416 #define IMX8MQ_CLK_I2C3_ROOT 0x194 417 #define IMX8MQ_CLK_I2C4_ROOT 0x195 418 #define IMX8MQ_CLK_PCIE1_ROOT 0x197 419 #define IMX8MQ_CLK_PCIE2_ROOT 0x198 420 #define IMX8MQ_CLK_UART1_ROOT 0x1a4 421 #define IMX8MQ_CLK_UART2_ROOT 0x1a5 422 #define IMX8MQ_CLK_UART3_ROOT 0x1a6 423 #define IMX8MQ_CLK_UART4_ROOT 0x1a7 424 #define IMX8MQ_CLK_USB1_CTRL_ROOT 0x1a8 425 #define IMX8MQ_CLK_USB2_CTRL_ROOT 0x1a9 426 #define IMX8MQ_CLK_USB1_PHY_ROOT 0x1aa 427 #define IMX8MQ_CLK_USB2_PHY_ROOT 0x1ab 428 #define IMX8MQ_CLK_USDHC1_ROOT 0x1ac 429 #define IMX8MQ_CLK_USDHC2_ROOT 0x1ad 430 431 struct imxccm_gate imx8mq_gates[] = { 432 [IMX8MQ_CLK_A53_CG] = { 0x8000, 14, IMX8MQ_CLK_A53_SRC }, 433 [IMX8MQ_CLK_ENET_AXI_CG] = { 0x8880, 14, IMX8MQ_CLK_ENET_AXI_SRC }, 434 [IMX8MQ_CLK_USB_BUS_CG] = { 0x8b80, 14, IMX8MQ_CLK_USB_BUS_SRC }, 435 [IMX8MQ_CLK_PCIE1_CTRL_CG] = { 0xa300, 14, IMX8MQ_CLK_PCIE1_CTRL_SRC }, 436 [IMX8MQ_CLK_PCIE1_PHY_CG] = { 0xa380, 14, IMX8MQ_CLK_PCIE1_PHY_SRC }, 437 [IMX8MQ_CLK_PCIE1_AUX_CG] = { 0xa400, 14, IMX8MQ_CLK_PCIE1_AUX_SRC }, 438 [IMX8MQ_CLK_ENET_REF_CG] = { 0xa980, 14, IMX8MQ_CLK_ENET_REF_SRC }, 439 [IMX8MQ_CLK_ENET_TIMER_CG] = { 0xaa00, 14, IMX8MQ_CLK_ENET_TIMER_SRC }, 440 [IMX8MQ_CLK_ENET_PHY_REF_CG] = { 0xaa80, 14, IMX8MQ_CLK_ENET_PHY_REF_SRC }, 441 [IMX8MQ_CLK_USDHC1_CG] = { 0xac00, 14, IMX8MQ_CLK_USDHC1_SRC }, 442 [IMX8MQ_CLK_USDHC2_CG] = { 0xac80, 14, IMX8MQ_CLK_USDHC2_SRC }, 443 [IMX8MQ_CLK_I2C1_CG] = { 0xad00, 14, IMX8MQ_CLK_I2C1_SRC }, 444 [IMX8MQ_CLK_I2C2_CG] = { 0xad80, 14, IMX8MQ_CLK_I2C2_SRC }, 445 [IMX8MQ_CLK_I2C3_CG] = { 0xae00, 14, IMX8MQ_CLK_I2C3_SRC }, 446 [IMX8MQ_CLK_I2C4_CG] = { 0xae80, 14, IMX8MQ_CLK_I2C4_SRC }, 447 [IMX8MQ_CLK_UART1_CG] = { 0xaf00, 14, IMX8MQ_CLK_UART1_SRC }, 448 [IMX8MQ_CLK_UART2_CG] = { 0xaf80, 14, IMX8MQ_CLK_UART2_SRC }, 449 [IMX8MQ_CLK_UART3_CG] = { 0xb000, 14, IMX8MQ_CLK_UART3_SRC }, 450 [IMX8MQ_CLK_UART4_CG] = { 0xb080, 14, IMX8MQ_CLK_UART4_SRC }, 451 [IMX8MQ_CLK_USB_CORE_REF_CG] = { 0xb100, 14, IMX8MQ_CLK_USB_CORE_REF_SRC }, 452 [IMX8MQ_CLK_USB_PHY_REF_CG] = { 0xb180, 14, IMX8MQ_CLK_USB_PHY_REF_SRC }, 453 [IMX8MQ_CLK_ECSPI1_CG] = { 0xb280, 14, IMX8MQ_CLK_ECSPI1_SRC }, 454 [IMX8MQ_CLK_ECSPI2_CG] = { 0xb300, 14, IMX8MQ_CLK_ECSPI2_SRC }, 455 [IMX8MQ_CLK_PCIE2_CTRL_CG] = { 0xc000, 14, IMX8MQ_CLK_PCIE2_CTRL_SRC }, 456 [IMX8MQ_CLK_PCIE2_PHY_CG] = { 0xc080, 14, IMX8MQ_CLK_PCIE2_PHY_SRC }, 457 [IMX8MQ_CLK_PCIE2_AUX_CG] = { 0xc100, 14, IMX8MQ_CLK_PCIE2_AUX_SRC }, 458 [IMX8MQ_CLK_ECSPI3_CG] = { 0xc180, 14, IMX8MQ_CLK_ECSPI3_SRC }, 459 [IMX8MQ_CLK_ECSPI1_ROOT] = { 0x4070, 0, IMX8MQ_CLK_ECSPI1_DIV }, 460 [IMX8MQ_CLK_ECSPI2_ROOT] = { 0x4080, 0, IMX8MQ_CLK_ECSPI2_DIV }, 461 [IMX8MQ_CLK_ECSPI3_ROOT] = { 0x4090, 0, IMX8MQ_CLK_ECSPI3_DIV }, 462 [IMX8MQ_CLK_ENET1_ROOT] = { 0x40a0, 0, IMX8MQ_CLK_ENET_AXI_DIV }, 463 [IMX8MQ_CLK_I2C1_ROOT] = { 0x4170, 0, IMX8MQ_CLK_I2C1_DIV }, 464 [IMX8MQ_CLK_I2C2_ROOT] = { 0x4180, 0, IMX8MQ_CLK_I2C2_DIV }, 465 [IMX8MQ_CLK_I2C3_ROOT] = { 0x4190, 0, IMX8MQ_CLK_I2C3_DIV }, 466 [IMX8MQ_CLK_I2C4_ROOT] = { 0x41a0, 0, IMX8MQ_CLK_I2C4_DIV }, 467 [IMX8MQ_CLK_PCIE1_ROOT] = { 0x4250, 0, IMX8MQ_CLK_PCIE1_CTRL_DIV }, 468 [IMX8MQ_CLK_PCIE2_ROOT] = { 0x4640, 0, IMX8MQ_CLK_PCIE2_CTRL_DIV }, 469 [IMX8MQ_CLK_UART1_ROOT] = { 0x4490, 0, IMX8MQ_CLK_UART1_DIV }, 470 [IMX8MQ_CLK_UART2_ROOT] = { 0x44a0, 0, IMX8MQ_CLK_UART2_DIV }, 471 [IMX8MQ_CLK_UART3_ROOT] = { 0x44b0, 0, IMX8MQ_CLK_UART3_DIV }, 472 [IMX8MQ_CLK_UART4_ROOT] = { 0x44c0, 0, IMX8MQ_CLK_UART4_DIV }, 473 [IMX8MQ_CLK_USB1_CTRL_ROOT] = { 0x44d0, 0, IMX8MQ_CLK_USB_CORE_REF_DIV }, 474 [IMX8MQ_CLK_USB2_CTRL_ROOT] = { 0x44e0, 0, IMX8MQ_CLK_USB_CORE_REF_DIV }, 475 [IMX8MQ_CLK_USB1_PHY_ROOT] = { 0x44f0, 0, IMX8MQ_CLK_USB_PHY_REF_DIV }, 476 [IMX8MQ_CLK_USB2_PHY_ROOT] = { 0x4500, 0, IMX8MQ_CLK_USB_PHY_REF_DIV }, 477 [IMX8MQ_CLK_USDHC1_ROOT] = { 0x4510, 0, IMX8MQ_CLK_USDHC1_DIV }, 478 [IMX8MQ_CLK_USDHC2_ROOT] = { 0x4520, 0, IMX8MQ_CLK_USDHC2_DIV }, 479 }; 480 481 struct imxccm_divider imx8mq_divs[] = { 482 [IMX8MQ_CLK_A53_DIV] = { 0x8000, 0, 0x7, IMX8MQ_CLK_A53_CG }, 483 [IMX8MQ_CLK_ENET_AXI_PRE_DIV] = { 0x8880, 16, 0x7, IMX8MQ_CLK_ENET_AXI_CG }, 484 [IMX8MQ_CLK_ENET_AXI_DIV] = { 0x8880, 0, 0x3f, IMX8MQ_CLK_ENET_AXI_PRE_DIV }, 485 [IMX8MQ_CLK_USB_BUS_PRE_DIV] = { 0x8b80, 16, 0x7, IMX8MQ_CLK_USB_BUS_CG }, 486 [IMX8MQ_CLK_USB_BUS_DIV] = { 0x8b80, 0, 0x3f, IMX8MQ_CLK_USB_BUS_PRE_DIV }, 487 [IMX8MQ_CLK_PCIE1_CTRL_PRE_DIV] = { 0xa300, 16, 0x7, IMX8MQ_CLK_PCIE1_CTRL_CG }, 488 [IMX8MQ_CLK_PCIE1_CTRL_DIV] = { 0xa300, 0, 0x3f, IMX8MQ_CLK_PCIE1_CTRL_PRE_DIV }, 489 [IMX8MQ_CLK_PCIE1_PHY_PRE_DIV] = { 0xa380, 16, 0x7, IMX8MQ_CLK_PCIE1_PHY_CG }, 490 [IMX8MQ_CLK_PCIE1_PHY_DIV] = { 0xa380, 0, 0x3f, IMX8MQ_CLK_PCIE1_PHY_PRE_DIV }, 491 [IMX8MQ_CLK_PCIE1_AUX_PRE_DIV] = { 0xa400, 16, 0x7, IMX8MQ_CLK_PCIE1_AUX_CG }, 492 [IMX8MQ_CLK_PCIE1_AUX_DIV] = { 0xa400, 0, 0x3f, IMX8MQ_CLK_PCIE1_AUX_PRE_DIV }, 493 [IMX8MQ_CLK_ENET_REF_PRE_DIV] = { 0xa980, 16, 0x7, IMX8MQ_CLK_ENET_REF_CG }, 494 [IMX8MQ_CLK_ENET_REF_DIV] = { 0xa980, 0, 0x3f, IMX8MQ_CLK_ENET_REF_PRE_DIV }, 495 [IMX8MQ_CLK_ENET_TIMER_PRE_DIV] = { 0xaa00, 16, 0x7, IMX8MQ_CLK_ENET_TIMER_CG }, 496 [IMX8MQ_CLK_ENET_TIMER_DIV] = { 0xaa00, 0, 0x3f, IMX8MQ_CLK_ENET_TIMER_PRE_DIV }, 497 [IMX8MQ_CLK_ENET_PHY_REF_PRE_DIV] = { 0xaa80, 16, 0x7, IMX8MQ_CLK_ENET_PHY_REF_CG }, 498 [IMX8MQ_CLK_ENET_PHY_REF_DIV] = { 0xaa80, 0, 0x3f, IMX8MQ_CLK_ENET_PHY_REF_PRE_DIV }, 499 [IMX8MQ_CLK_USDHC1_PRE_DIV] = { 0xac00, 16, 0x7, IMX8MQ_CLK_USDHC1_CG }, 500 [IMX8MQ_CLK_USDHC1_DIV] = { 0xac00, 0, 0x3f, IMX8MQ_CLK_USDHC1_PRE_DIV }, 501 [IMX8MQ_CLK_USDHC2_PRE_DIV] = { 0xac80, 16, 0x7, IMX8MQ_CLK_USDHC2_CG }, 502 [IMX8MQ_CLK_USDHC2_DIV] = { 0xac80, 0, 0x3f, IMX8MQ_CLK_USDHC2_PRE_DIV }, 503 [IMX8MQ_CLK_I2C1_PRE_DIV] = { 0xad00, 16, 0x7, IMX8MQ_CLK_I2C1_CG }, 504 [IMX8MQ_CLK_I2C1_DIV] = { 0xad00, 0, 0x3f, IMX8MQ_CLK_I2C1_PRE_DIV }, 505 [IMX8MQ_CLK_I2C2_PRE_DIV] = { 0xad80, 16, 0x7, IMX8MQ_CLK_I2C2_CG }, 506 [IMX8MQ_CLK_I2C2_DIV] = { 0xad80, 0, 0x3f, IMX8MQ_CLK_I2C2_PRE_DIV }, 507 [IMX8MQ_CLK_I2C3_PRE_DIV] = { 0xae00, 16, 0x7, IMX8MQ_CLK_I2C3_CG }, 508 [IMX8MQ_CLK_I2C3_DIV] = { 0xae00, 0, 0x3f, IMX8MQ_CLK_I2C3_PRE_DIV }, 509 [IMX8MQ_CLK_I2C4_PRE_DIV] = { 0xae80, 16, 0x7, IMX8MQ_CLK_I2C4_CG }, 510 [IMX8MQ_CLK_I2C4_DIV] = { 0xae80, 0, 0x3f, IMX8MQ_CLK_I2C4_PRE_DIV }, 511 [IMX8MQ_CLK_UART1_PRE_DIV] = { 0xaf00, 16, 0x7, IMX8MQ_CLK_UART1_CG }, 512 [IMX8MQ_CLK_UART1_DIV] = { 0xaf00, 0, 0x3f, IMX8MQ_CLK_UART1_PRE_DIV }, 513 [IMX8MQ_CLK_UART2_PRE_DIV] = { 0xaf80, 16, 0x7, IMX8MQ_CLK_UART2_CG }, 514 [IMX8MQ_CLK_UART2_DIV] = { 0xaf80, 0, 0x3f, IMX8MQ_CLK_UART2_PRE_DIV }, 515 [IMX8MQ_CLK_UART3_PRE_DIV] = { 0xb000, 16, 0x7, IMX8MQ_CLK_UART3_CG }, 516 [IMX8MQ_CLK_UART3_DIV] = { 0xb000, 0, 0x3f, IMX8MQ_CLK_UART3_PRE_DIV }, 517 [IMX8MQ_CLK_UART4_PRE_DIV] = { 0xb080, 16, 0x7, IMX8MQ_CLK_UART4_CG }, 518 [IMX8MQ_CLK_UART4_DIV] = { 0xb080, 0, 0x3f, IMX8MQ_CLK_UART4_PRE_DIV }, 519 [IMX8MQ_CLK_USB_CORE_REF_PRE_DIV] = { 0xb100, 16, 0x7, IMX8MQ_CLK_USB_CORE_REF_CG }, 520 [IMX8MQ_CLK_USB_CORE_REF_DIV] = { 0xb100, 0, 0x3f, IMX8MQ_CLK_USB_CORE_REF_PRE_DIV }, 521 [IMX8MQ_CLK_USB_PHY_REF_PRE_DIV] = { 0xb180, 16, 0x7, IMX8MQ_CLK_USB_PHY_REF_CG }, 522 [IMX8MQ_CLK_USB_PHY_REF_DIV] = { 0xb180, 0, 0x3f, IMX8MQ_CLK_USB_PHY_REF_PRE_DIV }, 523 [IMX8MQ_CLK_ECSPI1_PRE_DIV] = { 0xb280, 16, 0x7, IMX8MQ_CLK_ECSPI1_CG }, 524 [IMX8MQ_CLK_ECSPI1_DIV] = { 0xb280, 0, 0x3f, IMX8MQ_CLK_ECSPI1_PRE_DIV }, 525 [IMX8MQ_CLK_ECSPI2_PRE_DIV] = { 0xb300, 16, 0x7, IMX8MQ_CLK_ECSPI2_CG }, 526 [IMX8MQ_CLK_ECSPI2_DIV] = { 0xb300, 0, 0x3f, IMX8MQ_CLK_ECSPI2_PRE_DIV }, 527 [IMX8MQ_CLK_PCIE2_CTRL_PRE_DIV] = { 0xc000, 16, 0x7, IMX8MQ_CLK_PCIE2_CTRL_CG }, 528 [IMX8MQ_CLK_PCIE2_CTRL_DIV] = { 0xc000, 0, 0x3f, IMX8MQ_CLK_PCIE2_CTRL_PRE_DIV }, 529 [IMX8MQ_CLK_PCIE2_PHY_PRE_DIV] = { 0xc080, 16, 0x7, IMX8MQ_CLK_PCIE2_PHY_CG }, 530 [IMX8MQ_CLK_PCIE2_PHY_DIV] = { 0xc080, 0, 0x3f, IMX8MQ_CLK_PCIE2_PHY_PRE_DIV }, 531 [IMX8MQ_CLK_PCIE2_AUX_PRE_DIV] = { 0xc100, 16, 0x7, IMX8MQ_CLK_PCIE2_AUX_CG }, 532 [IMX8MQ_CLK_PCIE2_AUX_DIV] = { 0xc100, 0, 0x3f, IMX8MQ_CLK_PCIE2_AUX_PRE_DIV }, 533 [IMX8MQ_CLK_ECSPI3_PRE_DIV] = { 0xc180, 16, 0x7, IMX8MQ_CLK_ECSPI3_CG }, 534 [IMX8MQ_CLK_ECSPI3_DIV] = { 0xc180, 0, 0x3f, IMX8MQ_CLK_ECSPI3_PRE_DIV }, 535 }; 536 537 struct imxccm_mux imx8mq_muxs[] = { 538 [IMX8MQ_CLK_A53_SRC] = { 0x8000, 24, 0x7 }, 539 [IMX8MQ_CLK_ENET_AXI_SRC] = { 0x8880, 24, 0x7 }, 540 [IMX8MQ_CLK_USB_BUS_SRC] = { 0x8b80, 24, 0x7 }, 541 [IMX8MQ_CLK_PCIE1_CTRL_SRC] = { 0xa300, 24, 0x7 }, 542 [IMX8MQ_CLK_PCIE1_PHY_SRC] = { 0xa380, 24, 0x7 }, 543 [IMX8MQ_CLK_PCIE1_AUX_SRC] = { 0xa400, 24, 0x7 }, 544 [IMX8MQ_CLK_ENET_REF_SRC] = { 0xa980, 24, 0x7 }, 545 [IMX8MQ_CLK_ENET_TIMER_SRC] = { 0xaa00, 24, 0x7 }, 546 [IMX8MQ_CLK_ENET_PHY_REF_SRC] = { 0xaa80, 24, 0x7 }, 547 [IMX8MQ_CLK_USDHC1_SRC] = { 0xac00, 24, 0x7 }, 548 [IMX8MQ_CLK_USDHC2_SRC] = { 0xac80, 24, 0x7 }, 549 [IMX8MQ_CLK_I2C1_SRC] = { 0xad00, 24, 0x7 }, 550 [IMX8MQ_CLK_I2C2_SRC] = { 0xad80, 24, 0x7 }, 551 [IMX8MQ_CLK_I2C3_SRC] = { 0xae00, 24, 0x7 }, 552 [IMX8MQ_CLK_I2C4_SRC] = { 0xae80, 24, 0x7 }, 553 [IMX8MQ_CLK_UART1_SRC] = { 0xaf00, 24, 0x7 }, 554 [IMX8MQ_CLK_UART2_SRC] = { 0xaf80, 24, 0x7 }, 555 [IMX8MQ_CLK_UART3_SRC] = { 0xb000, 24, 0x7 }, 556 [IMX8MQ_CLK_UART4_SRC] = { 0xb080, 24, 0x7 }, 557 [IMX8MQ_CLK_USB_CORE_REF_SRC] = { 0xb100, 24, 0x7 }, 558 [IMX8MQ_CLK_USB_PHY_REF_SRC] = { 0xb180, 24, 0x7 }, 559 [IMX8MQ_CLK_ECSPI1_SRC] = { 0xb280, 24, 0x7 }, 560 [IMX8MQ_CLK_ECSPI2_SRC] = { 0xb300, 24, 0x7 }, 561 [IMX8MQ_CLK_PCIE2_CTRL_SRC] = { 0xc000, 24, 0x7 }, 562 [IMX8MQ_CLK_PCIE2_PHY_SRC] = { 0xc080, 24, 0x7 }, 563 [IMX8MQ_CLK_PCIE2_AUX_SRC] = { 0xc100, 24, 0x7 }, 564 [IMX8MQ_CLK_ECSPI3_SRC] = { 0xc180, 24, 0x7 }, 565 }; 566