1 /* Public Domain */ 2 3 /* 4 * i.MX6Q clocks. 5 */ 6 7 #define IMX6_CLK_IPG 0x3e 8 #define IMX6_CLK_IPG_PER 0x3f 9 #define IMX6_CLK_ECSPI_ROOT 0x47 10 #define IMX6_CLK_ARM 0x68 11 #define IMX6_CLK_AHB 0x69 12 #define IMX6_CLK_ECSPI2 0x71 13 #define IMX6_CLK_ENET 0x75 14 #define IMX6_CLK_I2C1 0x7d 15 #define IMX6_CLK_I2C2 0x7e 16 #define IMX6_CLK_I2C3 0x7f 17 #define IMX6_CLK_SATA 0x9a 18 #define IMX6_CLK_UART_IPG 0xa0 19 #define IMX6_CLK_UART_SERIAL 0xa1 20 #define IMX6_CLK_USBOH3 0xa2 21 #define IMX6_CLK_USDHC1 0xa3 22 #define IMX6_CLK_USDHC2 0xa4 23 #define IMX6_CLK_USDHC3 0xa5 24 #define IMX6_CLK_USDHC4 0xa6 25 #define IMX6_CLK_PLL3_USB_OTG 0xac 26 #define IMX6_CLK_PLL7_USB_HOST 0xb0 27 #define IMX6_CLK_PLL6_ENET 0xb1 28 #define IMX6_CLK_USBPHY1 0xb6 29 #define IMX6_CLK_USBPHY2 0xb7 30 #define IMX6_CLK_SATA_REF 0xba 31 #define IMX6_CLK_SATA_REF_100 0xbb 32 #define IMX6_CLK_ENET_REF 0xbe 33 #define IMX6_CLK_PLL3 0xe1 34 #define IMX6_CLK_PLL6 0xe4 35 #define IMX6_CLK_PLL7 0xe5 36 37 struct imxccm_gate imx6_gates[] = { 38 [IMX6_CLK_ECSPI2] = { CCM_CCGR1, 1, IMX6_CLK_ECSPI_ROOT }, 39 [IMX6_CLK_ENET] = { CCM_CCGR1, 5, IMX6_CLK_IPG }, 40 [IMX6_CLK_I2C1] = { CCM_CCGR2, 3, IMX6_CLK_IPG_PER }, 41 [IMX6_CLK_I2C2] = { CCM_CCGR2, 4, IMX6_CLK_IPG_PER }, 42 [IMX6_CLK_I2C3] = { CCM_CCGR2, 5, IMX6_CLK_IPG_PER }, 43 [IMX6_CLK_SATA] = { CCM_CCGR5, 2 }, 44 [IMX6_CLK_UART_IPG] = { CCM_CCGR5, 12, IMX6_CLK_IPG }, 45 [IMX6_CLK_UART_SERIAL] = { CCM_CCGR5, 13 }, 46 [IMX6_CLK_USBOH3] = { CCM_CCGR6, 0 }, 47 [IMX6_CLK_USDHC1] = { CCM_CCGR6, 1 }, 48 [IMX6_CLK_USDHC2] = { CCM_CCGR6, 2 }, 49 [IMX6_CLK_USDHC3] = { CCM_CCGR6, 3 }, 50 [IMX6_CLK_USDHC4] = { CCM_CCGR6, 4 }, 51 }; 52 53 /* 54 * i.MX6UL clocks. 55 */ 56 57 #define IMX6UL_CLK_ARM 0x5d 58 #define IMX6UL_CLK_PERCLK 0x63 59 #define IMX6UL_CLK_IPG 0x64 60 #define IMX6UL_CLK_GPT1_BUS 0x98 61 #define IMX6UL_CLK_GPT1_SERIAL 0x99 62 #define IMX6UL_CLK_I2C1 0x9c 63 #define IMX6UL_CLK_I2C2 0x9d 64 #define IMX6UL_CLK_I2C3 0x9e 65 #define IMX6UL_CLK_I2C4 0x9f 66 #define IMX6UL_CLK_UART1_IPG 0xbd 67 #define IMX6UL_CLK_UART1_SERIAL 0xbe 68 #define IMX6UL_CLK_USBOH3 0xcd 69 #define IMX6UL_CLK_USDHC1 0xce 70 #define IMX6UL_CLK_USDHC2 0xcf 71 72 struct imxccm_gate imx6ul_gates[] = { 73 [IMX6UL_CLK_GPT1_BUS] = { CCM_CCGR1, 10, IMX6UL_CLK_PERCLK }, 74 [IMX6UL_CLK_GPT1_SERIAL] = { CCM_CCGR1, 11, IMX6UL_CLK_PERCLK }, 75 [IMX6UL_CLK_I2C1] = { CCM_CCGR2, 3, IMX6UL_CLK_PERCLK }, 76 [IMX6UL_CLK_I2C2] = { CCM_CCGR2, 4, IMX6UL_CLK_PERCLK }, 77 [IMX6UL_CLK_I2C3] = { CCM_CCGR2, 5, IMX6UL_CLK_PERCLK }, 78 [IMX6UL_CLK_I2C4] = { CCM_CCGR6, 12, IMX6UL_CLK_PERCLK }, 79 [IMX6UL_CLK_UART1_IPG] = { CCM_CCGR5, 12, IMX6UL_CLK_IPG }, 80 [IMX6UL_CLK_UART1_SERIAL] = { CCM_CCGR5, 12 }, 81 [IMX6UL_CLK_USBOH3] = { CCM_CCGR6, 0 }, 82 [IMX6UL_CLK_USDHC1] = { CCM_CCGR6, 1 }, 83 [IMX6UL_CLK_USDHC2] = { CCM_CCGR6, 2 }, 84 }; 85 86 /* 87 * i.MX7D clocks. 88 */ 89 90 #define IMX7D_PLL_ENET_MAIN_125M_CLK 0x2a 91 #define IMX7D_ENET_AXI_ROOT_CLK 0x52 92 #define IMX7D_ENET_AXI_ROOT_SRC 0x53 93 #define IMX7D_ENET_AXI_ROOT_CG 0x54 94 #define IMX7D_ENET_AXI_ROOT_DIV 0x55 95 #define IMX7D_ENET1_IPG_ROOT_CLK 0x9e 96 #define IMX7D_ENET1_TIME_ROOT_CLK 0xa2 97 #define IMX7D_ENET1_TIME_ROOT_SRC 0xa3 98 #define IMX7D_ENET1_TIME_ROOT_CG 0xa4 99 #define IMX7D_ENET1_TIME_ROOT_DIV 0xa5 100 #define IMX7D_ENET2_IPG_ROOT_CLK 0xa6 101 #define IMX7D_ENET2_TIME_ROOT_CLK 0xaa 102 #define IMX7D_ENET2_TIME_ROOT_SRC 0xab 103 #define IMX7D_ENET2_TIME_ROOT_CG 0xac 104 #define IMX7D_ENET2_TIME_ROOT_DIV 0xad 105 #define IMX7D_ENET_PHY_REF_ROOT_CLK 0xae 106 #define IMX7D_ENET_PHY_REF_ROOT_SRC 0xaf 107 #define IMX7D_ENET_PHY_REF_ROOT_CG 0xb0 108 #define IMX7D_ENET_PHY_REF_ROOT_DIV 0xb1 109 #define IMX7D_USDHC1_ROOT_CLK 0xbe 110 #define IMX7D_USDHC1_ROOT_SRC 0xbf 111 #define IMX7D_USDHC1_ROOT_CG 0xc0 112 #define IMX7D_USDHC1_ROOT_DIV 0xc1 113 #define IMX7D_USDHC2_ROOT_CLK 0xc2 114 #define IMX7D_USDHC2_ROOT_SRC 0xc3 115 #define IMX7D_USDHC2_ROOT_CG 0xc4 116 #define IMX7D_USDHC2_ROOT_DIV 0xc5 117 #define IMX7D_USDHC3_ROOT_CLK 0xc6 118 #define IMX7D_USDHC3_ROOT_SRC 0xc7 119 #define IMX7D_USDHC3_ROOT_CG 0xc8 120 #define IMX7D_USDHC3_ROOT_DIV 0xc9 121 #define IMX7D_I2C1_ROOT_CLK 0xd2 122 #define IMX7D_I2C1_ROOT_SRC 0xd3 123 #define IMX7D_I2C1_ROOT_CG 0xd4 124 #define IMX7D_I2C1_ROOT_DIV 0xd5 125 #define IMX7D_I2C2_ROOT_CLK 0xd6 126 #define IMX7D_I2C2_ROOT_SRC 0xd7 127 #define IMX7D_I2C2_ROOT_CG 0xd8 128 #define IMX7D_I2C2_ROOT_DIV 0xd9 129 #define IMX7D_I2C3_ROOT_CLK 0xda 130 #define IMX7D_I2C3_ROOT_SRC 0xdb 131 #define IMX7D_I2C3_ROOT_CG 0xdc 132 #define IMX7D_I2C3_ROOT_DIV 0xdd 133 #define IMX7D_I2C4_ROOT_CLK 0xde 134 #define IMX7D_I2C4_ROOT_SRC 0xdf 135 #define IMX7D_I2C4_ROOT_CG 0xe0 136 #define IMX7D_I2C4_ROOT_DIV 0xe1 137 #define IMX7D_UART1_ROOT_CLK 0xe2 138 #define IMX7D_UART1_ROOT_SRC 0xe3 139 #define IMX7D_UART1_ROOT_CG 0xe4 140 #define IMX7D_UART1_ROOT_DIV 0xe5 141 #define IMX7D_UART2_ROOT_CLK 0xe6 142 #define IMX7D_UART2_ROOT_SRC 0xe7 143 #define IMX7D_UART2_ROOT_CG 0xe8 144 #define IMX7D_UART2_ROOT_DIV 0xe9 145 #define IMX7D_UART3_ROOT_CLK 0xea 146 #define IMX7D_UART3_ROOT_SRC 0xeb 147 #define IMX7D_UART3_ROOT_CG 0xec 148 #define IMX7D_UART3_ROOT_DIV 0xed 149 #define IMX7D_UART4_ROOT_CLK 0xee 150 #define IMX7D_UART4_ROOT_SRC 0xef 151 #define IMX7D_UART4_ROOT_CG 0xf0 152 #define IMX7D_UART4_ROOT_DIV 0xf1 153 #define IMX7D_UART5_ROOT_CLK 0xf2 154 #define IMX7D_UART5_ROOT_SRC 0xf3 155 #define IMX7D_UART5_ROOT_CG 0xf4 156 #define IMX7D_UART5_ROOT_DIV 0xf5 157 #define IMX7D_UART6_ROOT_CLK 0xf6 158 #define IMX7D_UART6_ROOT_SRC 0xf7 159 #define IMX7D_UART6_ROOT_CG 0xf8 160 #define IMX7D_UART6_ROOT_DIV 0xf9 161 #define IMX7D_UART7_ROOT_CLK 0xfa 162 #define IMX7D_UART7_ROOT_SRC 0xfb 163 #define IMX7D_UART7_ROOT_CG 0xfc 164 #define IMX7D_UART7_ROOT_DIV 0xfd 165 #define IMX7D_ENET_AXI_ROOT_PRE_DIV 0x15a 166 #define IMX7D_ENET1_TIME_ROOT_PRE_DIV 0x16a 167 #define IMX7D_ENET2_TIME_ROOT_PRE_DIV 0x16c 168 #define IMX7D_ENET_PHY_REF_ROOT_PRE_DIV 0x16d 169 #define IMX7D_USDHC1_ROOT_PRE_DIV 0x171 170 #define IMX7D_USDHC2_ROOT_PRE_DIV 0x172 171 #define IMX7D_USDHC3_ROOT_PRE_DIV 0x173 172 #define IMX7D_I2C1_ROOT_PRE_DIV 0x176 173 #define IMX7D_I2C2_ROOT_PRE_DIV 0x177 174 #define IMX7D_I2C3_ROOT_PRE_DIV 0x178 175 #define IMX7D_I2C4_ROOT_PRE_DIV 0x179 176 #define IMX7D_UART1_ROOT_PRE_DIV 0x17a 177 #define IMX7D_UART2_ROOT_PRE_DIV 0x17b 178 #define IMX7D_UART3_ROOT_PRE_DIV 0x17c 179 #define IMX7D_UART4_ROOT_PRE_DIV 0x17d 180 #define IMX7D_UART5_ROOT_PRE_DIV 0x17e 181 #define IMX7D_UART6_ROOT_PRE_DIV 0x17f 182 #define IMX7D_UART7_ROOT_PRE_DIV 0x180 183 #define IMX7D_USB_CTRL_CLK 0x1a6 184 #define IMX7D_USB_PHY1_CLK 0x1a7 185 #define IMX7D_USB_PHY2_CLK 0x1a8 186 187 struct imxccm_gate imx7d_gates[] = { 188 [IMX7D_ENET_AXI_ROOT_CG] = { 0x8900, 28, IMX7D_ENET_AXI_ROOT_SRC }, 189 [IMX7D_ENET1_TIME_ROOT_CG] = { 0xa780, 28, IMX7D_ENET1_TIME_ROOT_SRC }, 190 [IMX7D_ENET2_TIME_ROOT_CG] = { 0xa880, 28, IMX7D_ENET2_TIME_ROOT_SRC }, 191 [IMX7D_ENET_PHY_REF_ROOT_CG] = { 0xa900, 28, IMX7D_ENET_PHY_REF_ROOT_SRC }, 192 [IMX7D_USDHC1_ROOT_CG] = { 0xab00, 28, IMX7D_USDHC1_ROOT_SRC }, 193 [IMX7D_USDHC2_ROOT_CG] = { 0xab80, 28, IMX7D_USDHC2_ROOT_SRC }, 194 [IMX7D_USDHC3_ROOT_CG] = { 0xabc0, 28, IMX7D_USDHC3_ROOT_SRC }, 195 [IMX7D_I2C1_ROOT_CG] = { 0xad80, 28, IMX7D_I2C1_ROOT_SRC }, 196 [IMX7D_I2C2_ROOT_CG] = { 0xae00, 28, IMX7D_I2C2_ROOT_SRC }, 197 [IMX7D_I2C3_ROOT_CG] = { 0xae80, 28, IMX7D_I2C3_ROOT_SRC }, 198 [IMX7D_I2C4_ROOT_CG] = { 0xaf00, 28, IMX7D_I2C4_ROOT_SRC }, 199 [IMX7D_UART1_ROOT_CG] = { 0xaf80, 28, IMX7D_UART1_ROOT_SRC }, 200 [IMX7D_UART2_ROOT_CG] = { 0xb000, 28, IMX7D_UART2_ROOT_SRC }, 201 [IMX7D_UART3_ROOT_CG] = { 0xb080, 28, IMX7D_UART3_ROOT_SRC }, 202 [IMX7D_UART4_ROOT_CG] = { 0xb100, 28, IMX7D_UART4_ROOT_SRC }, 203 [IMX7D_UART5_ROOT_CG] = { 0xb180, 28, IMX7D_UART5_ROOT_SRC }, 204 [IMX7D_UART6_ROOT_CG] = { 0xb200, 28, IMX7D_UART6_ROOT_SRC }, 205 [IMX7D_UART7_ROOT_CG] = { 0xb280, 28, IMX7D_UART7_ROOT_SRC }, 206 [IMX7D_ENET_AXI_ROOT_CLK] = { 0x4060, 0, IMX7D_ENET_AXI_ROOT_DIV }, 207 [IMX7D_USB_CTRL_CLK] = { 0x4680, 0 }, 208 [IMX7D_USB_PHY1_CLK] = { 0x46a0, 0 }, 209 [IMX7D_USB_PHY2_CLK] = { 0x46b0, 0 }, 210 [IMX7D_USDHC1_ROOT_CLK] = { 0x46c0, 0, IMX7D_USDHC1_ROOT_DIV }, 211 [IMX7D_USDHC2_ROOT_CLK] = { 0x46d0, 0, IMX7D_USDHC2_ROOT_DIV }, 212 [IMX7D_USDHC3_ROOT_CLK] = { 0x46e0, 0, IMX7D_USDHC3_ROOT_DIV }, 213 [IMX7D_ENET1_IPG_ROOT_CLK] = { 0x4700, 0, IMX7D_ENET_AXI_ROOT_DIV }, 214 [IMX7D_ENET1_TIME_ROOT_CLK] = { 0x4700, 0, IMX7D_ENET1_TIME_ROOT_DIV }, 215 [IMX7D_ENET2_IPG_ROOT_CLK] = { 0x4710, 0, IMX7D_ENET_AXI_ROOT_DIV }, 216 [IMX7D_ENET2_TIME_ROOT_CLK] = { 0x4710, 0, IMX7D_ENET1_TIME_ROOT_DIV }, 217 [IMX7D_I2C1_ROOT_CLK] = { 0x4880, 0, IMX7D_I2C1_ROOT_DIV }, 218 [IMX7D_I2C2_ROOT_CLK] = { 0x4890, 0, IMX7D_I2C2_ROOT_DIV }, 219 [IMX7D_I2C3_ROOT_CLK] = { 0x48a0, 0, IMX7D_I2C3_ROOT_DIV }, 220 [IMX7D_I2C4_ROOT_CLK] = { 0x48b0, 0, IMX7D_I2C4_ROOT_DIV }, 221 [IMX7D_UART1_ROOT_CLK] = { 0x4940, 0, IMX7D_UART1_ROOT_DIV }, 222 [IMX7D_UART2_ROOT_CLK] = { 0x4950, 0, IMX7D_UART2_ROOT_DIV }, 223 [IMX7D_UART3_ROOT_CLK] = { 0x4960, 0, IMX7D_UART3_ROOT_DIV }, 224 [IMX7D_UART4_ROOT_CLK] = { 0x4970, 0, IMX7D_UART4_ROOT_DIV }, 225 [IMX7D_UART5_ROOT_CLK] = { 0x4980, 0, IMX7D_UART5_ROOT_DIV }, 226 [IMX7D_UART6_ROOT_CLK] = { 0x4990, 0, IMX7D_UART6_ROOT_DIV }, 227 [IMX7D_UART7_ROOT_CLK] = { 0x49a0, 0, IMX7D_UART7_ROOT_DIV }, 228 }; 229 230 struct imxccm_divider imx7d_divs[] = { 231 [IMX7D_ENET_AXI_ROOT_PRE_DIV] = { 0x8900, 16, 0x7, IMX7D_ENET_AXI_ROOT_CG }, 232 [IMX7D_ENET1_TIME_ROOT_PRE_DIV] = { 0xa780, 16, 0x7, IMX7D_ENET1_TIME_ROOT_CG }, 233 [IMX7D_ENET2_TIME_ROOT_PRE_DIV] = { 0xa880, 16, 0x7, IMX7D_ENET2_TIME_ROOT_CG }, 234 [IMX7D_ENET_PHY_REF_ROOT_PRE_DIV] = { 0xa900, 16, 0x7, IMX7D_ENET_PHY_REF_ROOT_CG }, 235 [IMX7D_USDHC1_ROOT_PRE_DIV] = { 0xab00, 16, 0x7, IMX7D_USDHC1_ROOT_CG }, 236 [IMX7D_USDHC2_ROOT_PRE_DIV] = { 0xab80, 16, 0x7, IMX7D_USDHC2_ROOT_CG }, 237 [IMX7D_USDHC3_ROOT_PRE_DIV] = { 0xac00, 16, 0x7, IMX7D_USDHC3_ROOT_CG }, 238 [IMX7D_I2C1_ROOT_PRE_DIV] = { 0xad80, 16, 0x7, IMX7D_I2C1_ROOT_CG }, 239 [IMX7D_I2C2_ROOT_PRE_DIV] = { 0xae00, 16, 0x7, IMX7D_I2C2_ROOT_CG }, 240 [IMX7D_I2C3_ROOT_PRE_DIV] = { 0xae80, 16, 0x7, IMX7D_I2C3_ROOT_CG }, 241 [IMX7D_I2C4_ROOT_PRE_DIV] = { 0xaf00, 16, 0x7, IMX7D_I2C4_ROOT_CG }, 242 [IMX7D_UART1_ROOT_PRE_DIV] = { 0xaf80, 16, 0x7, IMX7D_UART1_ROOT_CG }, 243 [IMX7D_UART2_ROOT_PRE_DIV] = { 0xb000, 16, 0x7, IMX7D_UART2_ROOT_CG }, 244 [IMX7D_UART3_ROOT_PRE_DIV] = { 0xb080, 16, 0x7, IMX7D_UART3_ROOT_CG }, 245 [IMX7D_UART4_ROOT_PRE_DIV] = { 0xb100, 16, 0x7, IMX7D_UART4_ROOT_CG }, 246 [IMX7D_UART5_ROOT_PRE_DIV] = { 0xb180, 16, 0x7, IMX7D_UART5_ROOT_CG }, 247 [IMX7D_UART6_ROOT_PRE_DIV] = { 0xb200, 16, 0x7, IMX7D_UART6_ROOT_CG }, 248 [IMX7D_UART7_ROOT_PRE_DIV] = { 0xb280, 16, 0x7, IMX7D_UART7_ROOT_CG }, 249 [IMX7D_ENET_AXI_ROOT_DIV] = { 0x8900, 0, 0x3f, IMX7D_ENET_AXI_ROOT_PRE_DIV }, 250 [IMX7D_ENET1_TIME_ROOT_DIV] = { 0xa780, 0, 0x3f, IMX7D_ENET1_TIME_ROOT_PRE_DIV }, 251 [IMX7D_ENET2_TIME_ROOT_DIV] = { 0xa880, 0, 0x3f, IMX7D_ENET2_TIME_ROOT_PRE_DIV }, 252 [IMX7D_ENET_PHY_REF_ROOT_CLK] = { 0xa900, 0, 0x3f, IMX7D_ENET_PHY_REF_ROOT_PRE_DIV }, 253 [IMX7D_USDHC1_ROOT_DIV] = { 0xab00, 0, 0x3f, IMX7D_USDHC1_ROOT_PRE_DIV }, 254 [IMX7D_USDHC2_ROOT_DIV] = { 0xab80, 0, 0x3f, IMX7D_USDHC2_ROOT_PRE_DIV }, 255 [IMX7D_USDHC3_ROOT_DIV] = { 0xac00, 0, 0x3f, IMX7D_USDHC3_ROOT_PRE_DIV }, 256 [IMX7D_I2C1_ROOT_DIV] = { 0xad80, 0, 0x3f, IMX7D_I2C1_ROOT_PRE_DIV }, 257 [IMX7D_I2C2_ROOT_DIV] = { 0xae00, 0, 0x3f, IMX7D_I2C2_ROOT_PRE_DIV }, 258 [IMX7D_I2C3_ROOT_DIV] = { 0xae80, 0, 0x3f, IMX7D_I2C3_ROOT_PRE_DIV }, 259 [IMX7D_I2C4_ROOT_DIV] = { 0xaf00, 0, 0x3f, IMX7D_I2C4_ROOT_PRE_DIV }, 260 [IMX7D_UART1_ROOT_DIV] = { 0xaf80, 0, 0x3f, IMX7D_UART1_ROOT_PRE_DIV }, 261 [IMX7D_UART2_ROOT_DIV] = { 0xb000, 0, 0x3f, IMX7D_UART2_ROOT_PRE_DIV }, 262 [IMX7D_UART3_ROOT_DIV] = { 0xb080, 0, 0x3f, IMX7D_UART3_ROOT_PRE_DIV }, 263 [IMX7D_UART4_ROOT_DIV] = { 0xb100, 0, 0x3f, IMX7D_UART4_ROOT_PRE_DIV }, 264 [IMX7D_UART5_ROOT_DIV] = { 0xb180, 0, 0x3f, IMX7D_UART5_ROOT_PRE_DIV }, 265 [IMX7D_UART6_ROOT_DIV] = { 0xb200, 0, 0x3f, IMX7D_UART6_ROOT_PRE_DIV }, 266 [IMX7D_UART7_ROOT_DIV] = { 0xb280, 0, 0x3f, IMX7D_UART7_ROOT_PRE_DIV }, 267 }; 268 269 struct imxccm_mux imx7d_muxs[] = { 270 [IMX7D_ENET_AXI_ROOT_SRC] = { 0x8900, 24, 0x7 }, 271 [IMX7D_ENET1_TIME_ROOT_SRC] = { 0xa780, 24, 0x7 }, 272 [IMX7D_ENET2_TIME_ROOT_SRC] = { 0xa880, 24, 0x7 }, 273 [IMX7D_ENET_PHY_REF_ROOT_SRC] = { 0xa900, 24, 0x7 }, 274 [IMX7D_USDHC1_ROOT_SRC] = { 0xab00, 24, 0x7 }, 275 [IMX7D_USDHC2_ROOT_SRC] = { 0xab80, 24, 0x7 }, 276 [IMX7D_USDHC3_ROOT_SRC] = { 0xac00, 24, 0x7 }, 277 [IMX7D_I2C1_ROOT_SRC] = { 0xad80, 24, 0x7 }, 278 [IMX7D_I2C2_ROOT_SRC] = { 0xae00, 24, 0x7 }, 279 [IMX7D_I2C3_ROOT_SRC] = { 0xae80, 24, 0x7 }, 280 [IMX7D_I2C4_ROOT_SRC] = { 0xaf00, 24, 0x7 }, 281 [IMX7D_UART1_ROOT_SRC] = { 0xaf80, 24, 0x7 }, 282 [IMX7D_UART2_ROOT_SRC] = { 0xb000, 24, 0x7 }, 283 [IMX7D_UART3_ROOT_SRC] = { 0xb080, 24, 0x7 }, 284 [IMX7D_UART4_ROOT_SRC] = { 0xb100, 24, 0x7 }, 285 [IMX7D_UART5_ROOT_SRC] = { 0xb180, 24, 0x7 }, 286 [IMX7D_UART6_ROOT_SRC] = { 0xb200, 24, 0x7 }, 287 [IMX7D_UART7_ROOT_SRC] = { 0xb280, 24, 0x7 }, 288 }; 289 290 /* 291 * i.MX8MQ clocks. 292 */ 293 294 #define IMX8MQ_ARM_PLL 0x0a 295 #define IMX8MQ_ARM_PLL_OUT 0x0c 296 #define IMX8MQ_SYS1_PLL_100M 0x48 297 #define IMX8MQ_SYS1_PLL_266M 0x4c 298 #define IMX8MQ_SYS1_PLL_400M 0x4d 299 #define IMX8MQ_SYS1_PLL_800M 0x4e 300 #define IMX8MQ_SYS2_PLL_100M 0x50 301 #define IMX8MQ_SYS2_PLL_250M 0x54 302 #define IMX8MQ_SYS2_PLL_500M 0x56 303 #define IMX8MQ_CLK_A53_SRC 0x58 304 #define IMX8MQ_CLK_A53_CG 0x59 305 #define IMX8MQ_CLK_A53_DIV 0x5a 306 #define IMX8MQ_CLK_ENET_AXI 0x68 307 #define IMX8MQ_CLK_NAND_USDHC_BUS 0x69 308 #define IMX8MQ_CLK_USB_BUS 0x6e 309 #define IMX8MQ_CLK_PCIE1_CTRL 0x7c 310 #define IMX8MQ_CLK_PCIE1_PHY 0x7d 311 #define IMX8MQ_CLK_PCIE1_AUX 0x7e 312 #define IMX8MQ_CLK_ENET_REF 0x89 313 #define IMX8MQ_CLK_ENET_TIMER 0x8a 314 #define IMX8MQ_CLK_ENET_PHY_REF 0x8b 315 #define IMX8MQ_CLK_USDHC1 0x8e 316 #define IMX8MQ_CLK_USDHC2 0x8f 317 #define IMX8MQ_CLK_I2C1 0x90 318 #define IMX8MQ_CLK_I2C2 0x91 319 #define IMX8MQ_CLK_I2C3 0x92 320 #define IMX8MQ_CLK_I2C4 0x93 321 #define IMX8MQ_CLK_UART1 0x94 322 #define IMX8MQ_CLK_UART2 0x95 323 #define IMX8MQ_CLK_UART3 0x96 324 #define IMX8MQ_CLK_UART4 0x97 325 #define IMX8MQ_CLK_USB_CORE_REF 0x98 326 #define IMX8MQ_CLK_USB_PHY_REF 0x99 327 #define IMX8MQ_CLK_ECSPI1 0x9a 328 #define IMX8MQ_CLK_ECSPI2 0x9b 329 #define IMX8MQ_CLK_PWM1 0x9c 330 #define IMX8MQ_CLK_PWM2 0x9d 331 #define IMX8MQ_CLK_PWM3 0x9e 332 #define IMX8MQ_CLK_PWM4 0x9f 333 #define IMX8MQ_CLK_PCIE2_CTRL 0xad 334 #define IMX8MQ_CLK_PCIE2_PHY 0xae 335 #define IMX8MQ_CLK_PCIE2_AUX 0xaf 336 #define IMX8MQ_CLK_ECSPI3 0xb0 337 #define IMX8MQ_CLK_ECSPI1_ROOT 0xb3 338 #define IMX8MQ_CLK_ECSPI2_ROOT 0xb4 339 #define IMX8MQ_CLK_ECSPI3_ROOT 0xb5 340 #define IMX8MQ_CLK_ENET1_ROOT 0xb6 341 #define IMX8MQ_CLK_I2C1_ROOT 0xb8 342 #define IMX8MQ_CLK_I2C2_ROOT 0xb9 343 #define IMX8MQ_CLK_I2C3_ROOT 0xba 344 #define IMX8MQ_CLK_I2C4_ROOT 0xbb 345 #define IMX8MQ_CLK_PCIE1_ROOT 0xbd 346 #define IMX8MQ_CLK_PCIE2_ROOT 0xbe 347 #define IMX8MQ_CLK_PWM1_ROOT 0xbf 348 #define IMX8MQ_CLK_PWM2_ROOT 0xc0 349 #define IMX8MQ_CLK_PWM3_ROOT 0xc1 350 #define IMX8MQ_CLK_PWM4_ROOT 0xc2 351 #define IMX8MQ_CLK_UART1_ROOT 0xca 352 #define IMX8MQ_CLK_UART2_ROOT 0xcb 353 #define IMX8MQ_CLK_UART3_ROOT 0xcc 354 #define IMX8MQ_CLK_UART4_ROOT 0xcd 355 #define IMX8MQ_CLK_USB1_CTRL_ROOT 0xce 356 #define IMX8MQ_CLK_USB2_CTRL_ROOT 0xcf 357 #define IMX8MQ_CLK_USB1_PHY_ROOT 0xd0 358 #define IMX8MQ_CLK_USB2_PHY_ROOT 0xd1 359 #define IMX8MQ_CLK_USDHC1_ROOT 0xd2 360 #define IMX8MQ_CLK_USDHC2_ROOT 0xd3 361 #define IMX8MQ_CLK_ARM 0x102 362 363 struct imxccm_gate imx8mq_gates[] = { 364 [IMX8MQ_CLK_A53_CG] = { 0x8000, 14 }, 365 [IMX8MQ_CLK_ENET_AXI] = { 0x8880, 14 }, 366 [IMX8MQ_CLK_NAND_USDHC_BUS] = { 0x8900, 14 }, 367 [IMX8MQ_CLK_USB_BUS] = { 0x8b80, 14 }, 368 [IMX8MQ_CLK_PCIE1_CTRL] = { 0xa300, 14 }, 369 [IMX8MQ_CLK_PCIE1_PHY] = { 0xa380, 14 }, 370 [IMX8MQ_CLK_PCIE1_AUX] = { 0xa400, 14 }, 371 [IMX8MQ_CLK_ENET_REF] = { 0xa980, 14 }, 372 [IMX8MQ_CLK_ENET_TIMER] = { 0xaa00, 14 }, 373 [IMX8MQ_CLK_ENET_PHY_REF] = { 0xaa80, 14 }, 374 [IMX8MQ_CLK_USDHC1] = { 0xac00, 14 }, 375 [IMX8MQ_CLK_USDHC2] = { 0xac80, 14 }, 376 [IMX8MQ_CLK_I2C1] = { 0xad00, 14 }, 377 [IMX8MQ_CLK_I2C2] = { 0xad80, 14 }, 378 [IMX8MQ_CLK_I2C3] = { 0xae00, 14 }, 379 [IMX8MQ_CLK_I2C4] = { 0xae80, 14 }, 380 [IMX8MQ_CLK_UART1] = { 0xaf00, 14 }, 381 [IMX8MQ_CLK_UART2] = { 0xaf80, 14 }, 382 [IMX8MQ_CLK_UART3] = { 0xb000, 14 }, 383 [IMX8MQ_CLK_UART4] = { 0xb080, 14 }, 384 [IMX8MQ_CLK_USB_CORE_REF] = { 0xb100, 14 }, 385 [IMX8MQ_CLK_USB_PHY_REF] = { 0xb180, 14 }, 386 [IMX8MQ_CLK_ECSPI1] = { 0xb280, 14 }, 387 [IMX8MQ_CLK_ECSPI2] = { 0xb300, 14 }, 388 [IMX8MQ_CLK_PWM1] = { 0xb380, 14 }, 389 [IMX8MQ_CLK_PWM2] = { 0xb400, 14 }, 390 [IMX8MQ_CLK_PWM3] = { 0xb480, 14 }, 391 [IMX8MQ_CLK_PWM4] = { 0xb500, 14 }, 392 [IMX8MQ_CLK_PCIE2_CTRL] = { 0xc000, 14 }, 393 [IMX8MQ_CLK_PCIE2_PHY] = { 0xc080, 14 }, 394 [IMX8MQ_CLK_PCIE2_AUX] = { 0xc100, 14 }, 395 [IMX8MQ_CLK_ECSPI3] = { 0xc180, 14 }, 396 [IMX8MQ_CLK_ECSPI1_ROOT] = { 0x4070, 0, IMX8MQ_CLK_ECSPI1 }, 397 [IMX8MQ_CLK_ECSPI2_ROOT] = { 0x4080, 0, IMX8MQ_CLK_ECSPI2 }, 398 [IMX8MQ_CLK_ECSPI3_ROOT] = { 0x4090, 0, IMX8MQ_CLK_ECSPI3 }, 399 [IMX8MQ_CLK_ENET1_ROOT] = { 0x40a0, 0, IMX8MQ_CLK_ENET_AXI }, 400 [IMX8MQ_CLK_I2C1_ROOT] = { 0x4170, 0, IMX8MQ_CLK_I2C1 }, 401 [IMX8MQ_CLK_I2C2_ROOT] = { 0x4180, 0, IMX8MQ_CLK_I2C2 }, 402 [IMX8MQ_CLK_I2C3_ROOT] = { 0x4190, 0, IMX8MQ_CLK_I2C3 }, 403 [IMX8MQ_CLK_I2C4_ROOT] = { 0x41a0, 0, IMX8MQ_CLK_I2C4 }, 404 [IMX8MQ_CLK_PCIE1_ROOT] = { 0x4250, 0, IMX8MQ_CLK_PCIE1_CTRL }, 405 [IMX8MQ_CLK_PCIE2_ROOT] = { 0x4640, 0, IMX8MQ_CLK_PCIE2_CTRL }, 406 [IMX8MQ_CLK_PWM1_ROOT] = { 0x4280, 0, IMX8MQ_CLK_PWM1 }, 407 [IMX8MQ_CLK_PWM2_ROOT] = { 0x4290, 0, IMX8MQ_CLK_PWM2 }, 408 [IMX8MQ_CLK_PWM3_ROOT] = { 0x42a0, 0, IMX8MQ_CLK_PWM3 }, 409 [IMX8MQ_CLK_PWM4_ROOT] = { 0x42b0, 0, IMX8MQ_CLK_PWM4 }, 410 [IMX8MQ_CLK_UART1_ROOT] = { 0x4490, 0, IMX8MQ_CLK_UART1 }, 411 [IMX8MQ_CLK_UART2_ROOT] = { 0x44a0, 0, IMX8MQ_CLK_UART2 }, 412 [IMX8MQ_CLK_UART3_ROOT] = { 0x44b0, 0, IMX8MQ_CLK_UART3 }, 413 [IMX8MQ_CLK_UART4_ROOT] = { 0x44c0, 0, IMX8MQ_CLK_UART4 }, 414 [IMX8MQ_CLK_USB1_CTRL_ROOT] = { 0x44d0, 0, IMX8MQ_CLK_USB_CORE_REF }, 415 [IMX8MQ_CLK_USB2_CTRL_ROOT] = { 0x44e0, 0, IMX8MQ_CLK_USB_CORE_REF }, 416 [IMX8MQ_CLK_USB1_PHY_ROOT] = { 0x44f0, 0, IMX8MQ_CLK_USB_PHY_REF }, 417 [IMX8MQ_CLK_USB2_PHY_ROOT] = { 0x4500, 0, IMX8MQ_CLK_USB_PHY_REF }, 418 [IMX8MQ_CLK_USDHC1_ROOT] = { 0x4510, 0, IMX8MQ_CLK_USDHC1 }, 419 [IMX8MQ_CLK_USDHC2_ROOT] = { 0x4520, 0, IMX8MQ_CLK_USDHC2 }, 420 }; 421 422 struct imxccm_divider imx8mq_divs[] = { 423 [IMX8MQ_CLK_A53_DIV] = { 0x8000, 0, 0x7, IMX8MQ_CLK_A53_CG }, 424 [IMX8MQ_CLK_ENET_AXI] = { 0x8880, 0, 0x3f }, 425 [IMX8MQ_CLK_NAND_USDHC_BUS] = { 0x8900, 0, 0x3f }, 426 [IMX8MQ_CLK_USB_BUS] = { 0x8b80, 0, 0x3f }, 427 [IMX8MQ_CLK_PCIE1_CTRL] = { 0xa300, 0, 0x3f }, 428 [IMX8MQ_CLK_PCIE1_PHY] = { 0xa380, 0, 0x3f }, 429 [IMX8MQ_CLK_PCIE1_AUX] = { 0xa400, 0, 0x3f }, 430 [IMX8MQ_CLK_ENET_REF] = { 0xa980, 0, 0x3f }, 431 [IMX8MQ_CLK_ENET_TIMER] = { 0xaa00, 0, 0x3f }, 432 [IMX8MQ_CLK_ENET_PHY_REF] = { 0xaa80, 0, 0x3f }, 433 [IMX8MQ_CLK_USDHC1] = { 0xac00, 0, 0x3f }, 434 [IMX8MQ_CLK_USDHC2] = { 0xac80, 0, 0x3f }, 435 [IMX8MQ_CLK_I2C1] = { 0xad00, 0, 0x3f }, 436 [IMX8MQ_CLK_I2C2] = { 0xad80, 0, 0x3f }, 437 [IMX8MQ_CLK_I2C3] = { 0xae00, 0, 0x3f }, 438 [IMX8MQ_CLK_I2C4] = { 0xae80, 0, 0x3f }, 439 [IMX8MQ_CLK_UART1] = { 0xaf00, 0, 0x3f }, 440 [IMX8MQ_CLK_UART2] = { 0xaf80, 0, 0x3f }, 441 [IMX8MQ_CLK_UART3] = { 0xb000, 0, 0x3f }, 442 [IMX8MQ_CLK_UART4] = { 0xb080, 0, 0x3f }, 443 [IMX8MQ_CLK_USB_CORE_REF] = { 0xb100, 0, 0x3f }, 444 [IMX8MQ_CLK_USB_PHY_REF] = { 0xb180, 0, 0x3f }, 445 [IMX8MQ_CLK_ECSPI1] = { 0xb280, 0, 0x3f }, 446 [IMX8MQ_CLK_ECSPI2] = { 0xb300, 0, 0x3f }, 447 [IMX8MQ_CLK_PWM1] = { 0xb380, 0, 0x3f }, 448 [IMX8MQ_CLK_PWM2] = { 0xb400, 0, 0x3f }, 449 [IMX8MQ_CLK_PWM3] = { 0xb480, 0, 0x3f }, 450 [IMX8MQ_CLK_PWM4] = { 0xb500, 0, 0x3f }, 451 [IMX8MQ_CLK_PCIE2_CTRL] = { 0xc000, 0, 0x3f }, 452 [IMX8MQ_CLK_PCIE2_PHY] = { 0xc080, 0, 0x3f }, 453 [IMX8MQ_CLK_PCIE2_AUX] = { 0xc100, 0, 0x3f }, 454 [IMX8MQ_CLK_ECSPI3] = { 0xc180, 0, 0x3f }, 455 }; 456 457 struct imxccm_divider imx8mq_predivs[] = { 458 [IMX8MQ_CLK_ENET_AXI] = { 0x8880, 16, 0x7 }, 459 [IMX8MQ_CLK_NAND_USDHC_BUS] = { 0x8900, 16, 0x7 }, 460 [IMX8MQ_CLK_USB_BUS] = { 0x8b80, 16, 0x7 }, 461 [IMX8MQ_CLK_PCIE1_CTRL] = { 0xa300, 16, 0x7 }, 462 [IMX8MQ_CLK_PCIE1_PHY] = { 0xa380, 16, 0x7 }, 463 [IMX8MQ_CLK_PCIE1_AUX] = { 0xa400, 16, 0x7 }, 464 [IMX8MQ_CLK_ENET_REF] = { 0xa980, 16, 0x7 }, 465 [IMX8MQ_CLK_ENET_TIMER] = { 0xaa00, 16, 0x7 }, 466 [IMX8MQ_CLK_ENET_PHY_REF] = { 0xaa80, 16, 0x7 }, 467 [IMX8MQ_CLK_USDHC1] = { 0xac00, 16, 0x7 }, 468 [IMX8MQ_CLK_USDHC2] = { 0xac80, 16, 0x7 }, 469 [IMX8MQ_CLK_I2C1] = { 0xad00, 16, 0x7 }, 470 [IMX8MQ_CLK_I2C2] = { 0xad80, 16, 0x7 }, 471 [IMX8MQ_CLK_I2C3] = { 0xae00, 16, 0x7 }, 472 [IMX8MQ_CLK_I2C4] = { 0xae80, 16, 0x7 }, 473 [IMX8MQ_CLK_UART1] = { 0xaf00, 16, 0x7 }, 474 [IMX8MQ_CLK_UART2] = { 0xaf80, 16, 0x7 }, 475 [IMX8MQ_CLK_UART3] = { 0xb000, 16, 0x7 }, 476 [IMX8MQ_CLK_UART4] = { 0xb080, 16, 0x7 }, 477 [IMX8MQ_CLK_USB_CORE_REF] = { 0xb100, 16, 0x7 }, 478 [IMX8MQ_CLK_USB_PHY_REF] = { 0xb180, 16, 0x7 }, 479 [IMX8MQ_CLK_ECSPI1] = { 0xb280, 16, 0x7 }, 480 [IMX8MQ_CLK_ECSPI2] = { 0xb300, 16, 0x7 }, 481 [IMX8MQ_CLK_PWM1] = { 0xb380, 16, 0x7 }, 482 [IMX8MQ_CLK_PWM2] = { 0xb400, 16, 0x7 }, 483 [IMX8MQ_CLK_PWM3] = { 0xb480, 16, 0x7 }, 484 [IMX8MQ_CLK_PWM4] = { 0xb500, 16, 0x7 }, 485 [IMX8MQ_CLK_PCIE2_CTRL] = { 0xc000, 16, 0x7 }, 486 [IMX8MQ_CLK_PCIE2_PHY] = { 0xc080, 16, 0x7 }, 487 [IMX8MQ_CLK_PCIE2_AUX] = { 0xc100, 16, 0x7 }, 488 [IMX8MQ_CLK_ECSPI3] = { 0xc180, 16, 0x7 }, 489 }; 490 491 struct imxccm_mux imx8mq_muxs[] = { 492 [IMX8MQ_CLK_A53_SRC] = { 0x8000, 24, 0x7 }, 493 [IMX8MQ_CLK_ENET_AXI] = { 0x8880, 24, 0x7 }, 494 [IMX8MQ_CLK_NAND_USDHC_BUS] = { 0x8900, 24, 0x7 }, 495 [IMX8MQ_CLK_USB_BUS] = { 0x8b80, 24, 0x7 }, 496 [IMX8MQ_CLK_PCIE1_CTRL] = { 0xa300, 24, 0x7 }, 497 [IMX8MQ_CLK_PCIE1_PHY] = { 0xa380, 24, 0x7 }, 498 [IMX8MQ_CLK_PCIE1_AUX] = { 0xa400, 24, 0x7 }, 499 [IMX8MQ_CLK_ENET_REF] = { 0xa980, 24, 0x7 }, 500 [IMX8MQ_CLK_ENET_TIMER] = { 0xaa00, 24, 0x7 }, 501 [IMX8MQ_CLK_ENET_PHY_REF] = { 0xaa80, 24, 0x7 }, 502 [IMX8MQ_CLK_USDHC1] = { 0xac00, 24, 0x7 }, 503 [IMX8MQ_CLK_USDHC2] = { 0xac80, 24, 0x7 }, 504 [IMX8MQ_CLK_I2C1] = { 0xad00, 24, 0x7 }, 505 [IMX8MQ_CLK_I2C2] = { 0xad80, 24, 0x7 }, 506 [IMX8MQ_CLK_I2C3] = { 0xae00, 24, 0x7 }, 507 [IMX8MQ_CLK_I2C4] = { 0xae80, 24, 0x7 }, 508 [IMX8MQ_CLK_UART1] = { 0xaf00, 24, 0x7 }, 509 [IMX8MQ_CLK_UART2] = { 0xaf80, 24, 0x7 }, 510 [IMX8MQ_CLK_UART3] = { 0xb000, 24, 0x7 }, 511 [IMX8MQ_CLK_UART4] = { 0xb080, 24, 0x7 }, 512 [IMX8MQ_CLK_USB_CORE_REF] = { 0xb100, 24, 0x7 }, 513 [IMX8MQ_CLK_USB_PHY_REF] = { 0xb180, 24, 0x7 }, 514 [IMX8MQ_CLK_ECSPI1] = { 0xb280, 24, 0x7 }, 515 [IMX8MQ_CLK_ECSPI2] = { 0xb300, 24, 0x7 }, 516 [IMX8MQ_CLK_PWM1] = { 0xb380, 24, 0x7 }, 517 [IMX8MQ_CLK_PWM2] = { 0xb400, 24, 0x7 }, 518 [IMX8MQ_CLK_PWM3] = { 0xb480, 24, 0x7 }, 519 [IMX8MQ_CLK_PWM4] = { 0xb500, 24, 0x7 }, 520 [IMX8MQ_CLK_PCIE2_CTRL] = { 0xc000, 24, 0x7 }, 521 [IMX8MQ_CLK_PCIE2_PHY] = { 0xc080, 24, 0x7 }, 522 [IMX8MQ_CLK_PCIE2_AUX] = { 0xc100, 24, 0x7 }, 523 [IMX8MQ_CLK_ECSPI3] = { 0xc180, 24, 0x7 }, 524 }; 525