1 /* $OpenBSD: if_mvneta.c,v 1.11 2020/06/22 02:23:21 dlg Exp $ */ 2 /* $NetBSD: if_mvneta.c,v 1.41 2015/04/15 10:15:40 hsuenaga Exp $ */ 3 /* 4 * Copyright (c) 2007, 2008, 2013 KIYOHARA Takashi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 25 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include "bpfilter.h" 30 31 #include <sys/param.h> 32 #include <sys/device.h> 33 #include <sys/systm.h> 34 #include <sys/endian.h> 35 #include <sys/errno.h> 36 #include <sys/kernel.h> 37 #include <sys/mutex.h> 38 #include <sys/socket.h> 39 #include <sys/sockio.h> 40 #include <uvm/uvm_extern.h> 41 #include <sys/mbuf.h> 42 43 #include <machine/bus.h> 44 #include <machine/fdt.h> 45 46 #include <dev/ofw/openfirm.h> 47 #include <dev/ofw/ofw_clock.h> 48 #include <dev/ofw/ofw_misc.h> 49 #include <dev/ofw/ofw_pinctrl.h> 50 #include <dev/ofw/fdt.h> 51 52 #include <dev/fdt/if_mvnetareg.h> 53 #include <dev/fdt/mvmdiovar.h> 54 55 #ifdef __armv7__ 56 #include <armv7/marvell/mvmbusvar.h> 57 #endif 58 59 #include <net/if.h> 60 #include <net/if_media.h> 61 #include <net/if_types.h> 62 63 #include <net/bpf.h> 64 65 #include <netinet/in.h> 66 #include <netinet/if_ether.h> 67 68 #include <dev/mii/mii.h> 69 #include <dev/mii/miivar.h> 70 71 #if NBPFILTER > 0 72 #include <net/bpf.h> 73 #endif 74 75 #ifdef MVNETA_DEBUG 76 #define DPRINTF(x) if (mvneta_debug) printf x 77 #define DPRINTFN(n,x) if (mvneta_debug >= (n)) printf x 78 int mvneta_debug = MVNETA_DEBUG; 79 #else 80 #define DPRINTF(x) 81 #define DPRINTFN(n,x) 82 #endif 83 84 #define MVNETA_READ(sc, reg) \ 85 bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)) 86 #define MVNETA_WRITE(sc, reg, val) \ 87 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 88 #define MVNETA_READ_FILTER(sc, reg, val, c) \ 89 bus_space_read_region_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val), (c)) 90 #define MVNETA_WRITE_FILTER(sc, reg, val, c) \ 91 bus_space_write_region_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val), (c)) 92 93 #define MVNETA_LINKUP_READ(sc) \ 94 MVNETA_READ(sc, MVNETA_PS0) 95 #define MVNETA_IS_LINKUP(sc) (MVNETA_LINKUP_READ(sc) & MVNETA_PS0_LINKUP) 96 97 #define MVNETA_TX_RING_CNT 256 98 #define MVNETA_TX_RING_MSK (MVNETA_TX_RING_CNT - 1) 99 #define MVNETA_TX_RING_NEXT(x) (((x) + 1) & MVNETA_TX_RING_MSK) 100 #define MVNETA_TX_QUEUE_CNT 1 101 #define MVNETA_RX_RING_CNT 256 102 #define MVNETA_RX_RING_MSK (MVNETA_RX_RING_CNT - 1) 103 #define MVNETA_RX_RING_NEXT(x) (((x) + 1) & MVNETA_RX_RING_MSK) 104 #define MVNETA_RX_QUEUE_CNT 1 105 106 CTASSERT(MVNETA_TX_RING_CNT > 1 && MVNETA_TX_RING_NEXT(MVNETA_TX_RING_CNT) == 107 (MVNETA_TX_RING_CNT + 1) % MVNETA_TX_RING_CNT); 108 CTASSERT(MVNETA_RX_RING_CNT > 1 && MVNETA_RX_RING_NEXT(MVNETA_RX_RING_CNT) == 109 (MVNETA_RX_RING_CNT + 1) % MVNETA_RX_RING_CNT); 110 111 #define MVNETA_NTXSEG 30 112 113 struct mvneta_dmamem { 114 bus_dmamap_t mdm_map; 115 bus_dma_segment_t mdm_seg; 116 size_t mdm_size; 117 caddr_t mdm_kva; 118 }; 119 #define MVNETA_DMA_MAP(_mdm) ((_mdm)->mdm_map) 120 #define MVNETA_DMA_LEN(_mdm) ((_mdm)->mdm_size) 121 #define MVNETA_DMA_DVA(_mdm) ((_mdm)->mdm_map->dm_segs[0].ds_addr) 122 #define MVNETA_DMA_KVA(_mdm) ((void *)(_mdm)->mdm_kva) 123 124 struct mvneta_buf { 125 bus_dmamap_t tb_map; 126 struct mbuf *tb_m; 127 }; 128 129 struct mvneta_softc { 130 struct device sc_dev; 131 struct device *sc_mdio; 132 133 bus_space_tag_t sc_iot; 134 bus_space_handle_t sc_ioh; 135 bus_dma_tag_t sc_dmat; 136 137 struct arpcom sc_ac; 138 #define sc_enaddr sc_ac.ac_enaddr 139 struct mii_data sc_mii; 140 #define sc_media sc_mii.mii_media 141 142 struct timeout sc_tick_ch; 143 144 struct mvneta_dmamem *sc_txring; 145 struct mvneta_buf *sc_txbuf; 146 struct mvneta_tx_desc *sc_txdesc; 147 int sc_tx_prod; /* next free tx desc */ 148 int sc_tx_cnt; /* amount of tx sent */ 149 int sc_tx_cons; /* first tx desc sent */ 150 151 struct mvneta_dmamem *sc_rxring; 152 struct mvneta_buf *sc_rxbuf; 153 struct mvneta_rx_desc *sc_rxdesc; 154 int sc_rx_prod; /* next rx desc to fill */ 155 struct if_rxring sc_rx_ring; 156 int sc_rx_cons; /* next rx desc recvd */ 157 158 enum { 159 PHY_MODE_QSGMII, 160 PHY_MODE_SGMII, 161 PHY_MODE_RGMII, 162 PHY_MODE_RGMII_ID, 163 } sc_phy_mode; 164 int sc_fixed_link; 165 int sc_inband_status; 166 int sc_phy; 167 int sc_link; 168 int sc_sfp; 169 }; 170 171 172 int mvneta_miibus_readreg(struct device *, int, int); 173 void mvneta_miibus_writereg(struct device *, int, int, int); 174 void mvneta_miibus_statchg(struct device *); 175 176 void mvneta_wininit(struct mvneta_softc *); 177 178 /* Gigabit Ethernet Port part functions */ 179 int mvneta_match(struct device *, void *, void *); 180 void mvneta_attach(struct device *, struct device *, void *); 181 void mvneta_attach_deferred(struct device *); 182 183 void mvneta_tick(void *); 184 int mvneta_intr(void *); 185 186 void mvneta_start(struct ifnet *); 187 int mvneta_ioctl(struct ifnet *, u_long, caddr_t); 188 void mvneta_inband_statchg(struct mvneta_softc *); 189 void mvneta_port_change(struct mvneta_softc *); 190 void mvneta_port_up(struct mvneta_softc *); 191 int mvneta_up(struct mvneta_softc *); 192 void mvneta_down(struct mvneta_softc *); 193 void mvneta_watchdog(struct ifnet *); 194 195 int mvneta_mediachange(struct ifnet *); 196 void mvneta_mediastatus(struct ifnet *, struct ifmediareq *); 197 198 int mvneta_encap(struct mvneta_softc *, struct mbuf *, uint32_t *); 199 void mvneta_rx_proc(struct mvneta_softc *); 200 void mvneta_tx_proc(struct mvneta_softc *); 201 uint8_t mvneta_crc8(const uint8_t *, size_t); 202 void mvneta_iff(struct mvneta_softc *); 203 204 struct mvneta_dmamem *mvneta_dmamem_alloc(struct mvneta_softc *, 205 bus_size_t, bus_size_t); 206 void mvneta_dmamem_free(struct mvneta_softc *, struct mvneta_dmamem *); 207 void mvneta_fill_rx_ring(struct mvneta_softc *); 208 209 static struct rwlock mvneta_sff_lock = RWLOCK_INITIALIZER("mvnetasff"); 210 211 struct cfdriver mvneta_cd = { 212 NULL, "mvneta", DV_IFNET 213 }; 214 215 struct cfattach mvneta_ca = { 216 sizeof (struct mvneta_softc), mvneta_match, mvneta_attach, 217 }; 218 219 int 220 mvneta_miibus_readreg(struct device *dev, int phy, int reg) 221 { 222 struct mvneta_softc *sc = (struct mvneta_softc *) dev; 223 return mvmdio_miibus_readreg(sc->sc_mdio, phy, reg); 224 } 225 226 void 227 mvneta_miibus_writereg(struct device *dev, int phy, int reg, int val) 228 { 229 struct mvneta_softc *sc = (struct mvneta_softc *) dev; 230 return mvmdio_miibus_writereg(sc->sc_mdio, phy, reg, val); 231 } 232 233 void 234 mvneta_miibus_statchg(struct device *self) 235 { 236 struct mvneta_softc *sc = (struct mvneta_softc *)self; 237 238 if (sc->sc_mii.mii_media_status & IFM_ACTIVE) { 239 uint32_t panc = MVNETA_READ(sc, MVNETA_PANC); 240 241 panc &= ~(MVNETA_PANC_SETMIISPEED | 242 MVNETA_PANC_SETGMIISPEED | 243 MVNETA_PANC_SETFULLDX); 244 245 switch (IFM_SUBTYPE(sc->sc_mii.mii_media_active)) { 246 case IFM_1000_SX: 247 case IFM_1000_LX: 248 case IFM_1000_CX: 249 case IFM_1000_T: 250 panc |= MVNETA_PANC_SETGMIISPEED; 251 break; 252 case IFM_100_TX: 253 panc |= MVNETA_PANC_SETMIISPEED; 254 break; 255 case IFM_10_T: 256 break; 257 } 258 259 if ((sc->sc_mii.mii_media_active & IFM_GMASK) == IFM_FDX) 260 panc |= MVNETA_PANC_SETFULLDX; 261 262 MVNETA_WRITE(sc, MVNETA_PANC, panc); 263 } 264 265 mvneta_port_change(sc); 266 } 267 268 void 269 mvneta_inband_statchg(struct mvneta_softc *sc) 270 { 271 uint32_t reg; 272 273 sc->sc_mii.mii_media_status = IFM_AVALID; 274 sc->sc_mii.mii_media_active = IFM_ETHER; 275 276 reg = MVNETA_READ(sc, MVNETA_PS0); 277 if (reg & MVNETA_PS0_LINKUP) 278 sc->sc_mii.mii_media_status |= IFM_ACTIVE; 279 if (reg & MVNETA_PS0_GMIISPEED) 280 sc->sc_mii.mii_media_active |= IFM_1000_T; 281 else if (reg & MVNETA_PS0_MIISPEED) 282 sc->sc_mii.mii_media_active |= IFM_100_TX; 283 else 284 sc->sc_mii.mii_media_active |= IFM_10_T; 285 if (reg & MVNETA_PS0_FULLDX) 286 sc->sc_mii.mii_media_active |= IFM_FDX; 287 288 mvneta_port_change(sc); 289 } 290 291 void 292 mvneta_enaddr_write(struct mvneta_softc *sc) 293 { 294 uint32_t maddrh, maddrl; 295 maddrh = sc->sc_enaddr[0] << 24; 296 maddrh |= sc->sc_enaddr[1] << 16; 297 maddrh |= sc->sc_enaddr[2] << 8; 298 maddrh |= sc->sc_enaddr[3]; 299 maddrl = sc->sc_enaddr[4] << 8; 300 maddrl |= sc->sc_enaddr[5]; 301 MVNETA_WRITE(sc, MVNETA_MACAH, maddrh); 302 MVNETA_WRITE(sc, MVNETA_MACAL, maddrl); 303 } 304 305 void 306 mvneta_wininit(struct mvneta_softc *sc) 307 { 308 uint32_t en; 309 int i; 310 311 #ifdef __armv7__ 312 if (mvmbus_dram_info == NULL) 313 panic("%s: mbus dram information not set up", 314 sc->sc_dev.dv_xname); 315 #endif 316 317 for (i = 0; i < MVNETA_NWINDOW; i++) { 318 MVNETA_WRITE(sc, MVNETA_BASEADDR(i), 0); 319 MVNETA_WRITE(sc, MVNETA_S(i), 0); 320 321 if (i < MVNETA_NREMAP) 322 MVNETA_WRITE(sc, MVNETA_HA(i), 0); 323 } 324 325 en = MVNETA_BARE_EN_MASK; 326 327 #ifdef __armv7__ 328 for (i = 0; i < mvmbus_dram_info->numcs; i++) { 329 struct mbus_dram_window *win = &mvmbus_dram_info->cs[i]; 330 331 MVNETA_WRITE(sc, MVNETA_BASEADDR(i), 332 MVNETA_BASEADDR_TARGET(mvmbus_dram_info->targetid) | 333 MVNETA_BASEADDR_ATTR(win->attr) | 334 MVNETA_BASEADDR_BASE(win->base)); 335 MVNETA_WRITE(sc, MVNETA_S(i), MVNETA_S_SIZE(win->size)); 336 337 en &= ~(1 << i); 338 } 339 #else 340 MVNETA_WRITE(sc, MVNETA_S(0), MVNETA_S_SIZE(0)); 341 en &= ~(1 << 0); 342 #endif 343 344 MVNETA_WRITE(sc, MVNETA_BARE, en); 345 } 346 347 int 348 mvneta_match(struct device *parent, void *cfdata, void *aux) 349 { 350 struct fdt_attach_args *faa = aux; 351 352 return OF_is_compatible(faa->fa_node, "marvell,armada-370-neta") || 353 OF_is_compatible(faa->fa_node, "marvell,armada-3700-neta"); 354 } 355 356 void 357 mvneta_attach(struct device *parent, struct device *self, void *aux) 358 { 359 struct mvneta_softc *sc = (struct mvneta_softc *) self; 360 struct fdt_attach_args *faa = aux; 361 uint32_t ctl0, ctl2, panc; 362 struct ifnet *ifp; 363 int i, len, node; 364 char *phy_mode; 365 char *managed; 366 367 printf("\n"); 368 369 sc->sc_iot = faa->fa_iot; 370 timeout_set(&sc->sc_tick_ch, mvneta_tick, sc); 371 if (bus_space_map(sc->sc_iot, faa->fa_reg[0].addr, 372 faa->fa_reg[0].size, 0, &sc->sc_ioh)) { 373 printf("%s: cannot map registers\n", self->dv_xname); 374 return; 375 } 376 sc->sc_dmat = faa->fa_dmat; 377 378 clock_enable(faa->fa_node, NULL); 379 380 pinctrl_byname(faa->fa_node, "default"); 381 382 len = OF_getproplen(faa->fa_node, "phy-mode"); 383 if (len <= 0) { 384 printf("%s: cannot extract phy-mode\n", self->dv_xname); 385 return; 386 } 387 388 phy_mode = malloc(len, M_TEMP, M_WAITOK); 389 OF_getprop(faa->fa_node, "phy-mode", phy_mode, len); 390 if (!strncmp(phy_mode, "qsgmii", strlen("qsgmii"))) 391 sc->sc_phy_mode = PHY_MODE_QSGMII; 392 else if (!strncmp(phy_mode, "sgmii", strlen("sgmii"))) 393 sc->sc_phy_mode = PHY_MODE_SGMII; 394 else if (!strncmp(phy_mode, "rgmii-id", strlen("rgmii-id"))) 395 sc->sc_phy_mode = PHY_MODE_RGMII_ID; 396 else if (!strncmp(phy_mode, "rgmii", strlen("rgmii"))) 397 sc->sc_phy_mode = PHY_MODE_RGMII; 398 else { 399 printf("%s: cannot use phy-mode %s\n", self->dv_xname, 400 phy_mode); 401 return; 402 } 403 free(phy_mode, M_TEMP, len); 404 405 /* TODO: check child's name to be "fixed-link" */ 406 if (OF_getproplen(faa->fa_node, "fixed-link") >= 0 || 407 OF_child(faa->fa_node)) 408 sc->sc_fixed_link = 1; 409 410 if ((len = OF_getproplen(faa->fa_node, "managed")) >= 0) { 411 managed = malloc(len, M_TEMP, M_WAITOK); 412 OF_getprop(faa->fa_node, "managed", managed, len); 413 if (!strncmp(managed, "in-band-status", 414 strlen("in-band-status"))) { 415 sc->sc_fixed_link = 1; 416 sc->sc_inband_status = 1; 417 } 418 free(managed, M_TEMP, len); 419 } 420 421 if (!sc->sc_fixed_link) { 422 node = OF_getnodebyphandle(OF_getpropint(faa->fa_node, 423 "phy", 0)); 424 if (!node) { 425 printf("%s: cannot find phy in fdt\n", self->dv_xname); 426 return; 427 } 428 429 if ((sc->sc_phy = OF_getpropint(node, "reg", -1)) == -1) { 430 printf("%s: cannot extract phy addr\n", self->dv_xname); 431 return; 432 } 433 } 434 435 mvneta_wininit(sc); 436 437 if (OF_getproplen(faa->fa_node, "local-mac-address") == 438 ETHER_ADDR_LEN) { 439 OF_getprop(faa->fa_node, "local-mac-address", 440 sc->sc_enaddr, ETHER_ADDR_LEN); 441 mvneta_enaddr_write(sc); 442 } else { 443 uint32_t maddrh, maddrl; 444 maddrh = MVNETA_READ(sc, MVNETA_MACAH); 445 maddrl = MVNETA_READ(sc, MVNETA_MACAL); 446 if (maddrh || maddrl) { 447 sc->sc_enaddr[0] = maddrh >> 24; 448 sc->sc_enaddr[1] = maddrh >> 16; 449 sc->sc_enaddr[2] = maddrh >> 8; 450 sc->sc_enaddr[3] = maddrh >> 0; 451 sc->sc_enaddr[4] = maddrl >> 8; 452 sc->sc_enaddr[5] = maddrl >> 0; 453 } else 454 ether_fakeaddr(&sc->sc_ac.ac_if); 455 } 456 457 sc->sc_sfp = OF_getpropint(faa->fa_node, "sfp", 0); 458 459 printf("%s: Ethernet address %s\n", self->dv_xname, 460 ether_sprintf(sc->sc_enaddr)); 461 462 /* disable port */ 463 MVNETA_WRITE(sc, MVNETA_PMACC0, 464 MVNETA_READ(sc, MVNETA_PMACC0) & ~MVNETA_PMACC0_PORTEN); 465 delay(200); 466 467 /* clear all cause registers */ 468 MVNETA_WRITE(sc, MVNETA_PRXTXTIC, 0); 469 MVNETA_WRITE(sc, MVNETA_PRXTXIC, 0); 470 MVNETA_WRITE(sc, MVNETA_PMIC, 0); 471 472 /* mask all interrupts */ 473 MVNETA_WRITE(sc, MVNETA_PRXTXTIM, MVNETA_PRXTXTI_PMISCICSUMMARY); 474 MVNETA_WRITE(sc, MVNETA_PRXTXIM, 0); 475 MVNETA_WRITE(sc, MVNETA_PMIM, MVNETA_PMI_PHYSTATUSCHNG | 476 MVNETA_PMI_LINKCHANGE | MVNETA_PMI_PSCSYNCCHNG); 477 MVNETA_WRITE(sc, MVNETA_PIE, 0); 478 479 /* enable MBUS Retry bit16 */ 480 MVNETA_WRITE(sc, MVNETA_ERETRY, 0x20); 481 482 /* enable access for CPU0 */ 483 MVNETA_WRITE(sc, MVNETA_PCP2Q(0), 484 MVNETA_PCP2Q_RXQAE_ALL | MVNETA_PCP2Q_TXQAE_ALL); 485 486 /* reset RX and TX DMAs */ 487 MVNETA_WRITE(sc, MVNETA_PRXINIT, MVNETA_PRXINIT_RXDMAINIT); 488 MVNETA_WRITE(sc, MVNETA_PTXINIT, MVNETA_PTXINIT_TXDMAINIT); 489 490 /* disable legacy WRR, disable EJP, release from reset */ 491 MVNETA_WRITE(sc, MVNETA_TQC_1, 0); 492 for (i = 0; i < MVNETA_TX_QUEUE_CNT; i++) { 493 MVNETA_WRITE(sc, MVNETA_TQTBCOUNT(i), 0); 494 MVNETA_WRITE(sc, MVNETA_TQTBCONFIG(i), 0); 495 } 496 497 MVNETA_WRITE(sc, MVNETA_PRXINIT, 0); 498 MVNETA_WRITE(sc, MVNETA_PTXINIT, 0); 499 500 /* set port acceleration mode */ 501 MVNETA_WRITE(sc, MVNETA_PACC, MVGVE_PACC_ACCELERATIONMODE_EDM); 502 503 MVNETA_WRITE(sc, MVNETA_PXC, MVNETA_PXC_AMNOTXES | MVNETA_PXC_RXCS); 504 MVNETA_WRITE(sc, MVNETA_PXCX, 0); 505 MVNETA_WRITE(sc, MVNETA_PMFS, 64); 506 507 /* Set SDC register except IPGINT bits */ 508 MVNETA_WRITE(sc, MVNETA_SDC, 509 MVNETA_SDC_RXBSZ_16_64BITWORDS | 510 MVNETA_SDC_BLMR | /* Big/Little Endian Receive Mode: No swap */ 511 MVNETA_SDC_BLMT | /* Big/Little Endian Transmit Mode: No swap */ 512 MVNETA_SDC_TXBSZ_16_64BITWORDS); 513 514 /* XXX: Disable PHY polling in hardware */ 515 MVNETA_WRITE(sc, MVNETA_EUC, 516 MVNETA_READ(sc, MVNETA_EUC) & ~MVNETA_EUC_POLLING); 517 518 /* clear uni-/multicast tables */ 519 uint32_t dfut[MVNETA_NDFUT], dfsmt[MVNETA_NDFSMT], dfomt[MVNETA_NDFOMT]; 520 memset(dfut, 0, sizeof(dfut)); 521 memset(dfsmt, 0, sizeof(dfut)); 522 memset(dfomt, 0, sizeof(dfut)); 523 MVNETA_WRITE_FILTER(sc, MVNETA_DFUT, dfut, MVNETA_NDFUT); 524 MVNETA_WRITE_FILTER(sc, MVNETA_DFSMT, dfut, MVNETA_NDFSMT); 525 MVNETA_WRITE_FILTER(sc, MVNETA_DFOMT, dfut, MVNETA_NDFOMT); 526 527 MVNETA_WRITE(sc, MVNETA_PIE, 528 MVNETA_PIE_RXPKTINTRPTENB_ALL | MVNETA_PIE_TXPKTINTRPTENB_ALL); 529 530 MVNETA_WRITE(sc, MVNETA_EUIC, 0); 531 532 /* Setup phy. */ 533 ctl0 = MVNETA_READ(sc, MVNETA_PMACC0); 534 ctl2 = MVNETA_READ(sc, MVNETA_PMACC2); 535 panc = MVNETA_READ(sc, MVNETA_PANC); 536 537 /* Force link down to change in-band settings. */ 538 panc &= ~MVNETA_PANC_FORCELINKPASS; 539 panc |= MVNETA_PANC_FORCELINKFAIL; 540 MVNETA_WRITE(sc, MVNETA_PANC, panc); 541 542 ctl0 &= ~MVNETA_PMACC0_PORTTYPE; 543 ctl2 &= ~(MVNETA_PMACC2_PORTMACRESET | MVNETA_PMACC2_INBANDAN); 544 panc &= ~(MVNETA_PANC_INBANDANEN | MVNETA_PANC_INBANDRESTARTAN | 545 MVNETA_PANC_SETMIISPEED | MVNETA_PANC_SETGMIISPEED | 546 MVNETA_PANC_ANSPEEDEN | MVNETA_PANC_SETFCEN | 547 MVNETA_PANC_PAUSEADV | MVNETA_PANC_ANFCEN | 548 MVNETA_PANC_SETFULLDX | MVNETA_PANC_ANDUPLEXEN); 549 550 ctl2 |= MVNETA_PMACC2_RGMIIEN; 551 switch (sc->sc_phy_mode) { 552 case PHY_MODE_QSGMII: 553 MVNETA_WRITE(sc, MVNETA_SERDESCFG, 554 MVNETA_SERDESCFG_QSGMII_PROTO); 555 ctl2 |= MVNETA_PMACC2_PCSEN; 556 break; 557 case PHY_MODE_SGMII: 558 MVNETA_WRITE(sc, MVNETA_SERDESCFG, 559 MVNETA_SERDESCFG_SGMII_PROTO); 560 ctl2 |= MVNETA_PMACC2_PCSEN; 561 break; 562 default: 563 break; 564 } 565 566 /* Use Auto-Negotiation for Inband Status only */ 567 if (sc->sc_inband_status) { 568 panc &= ~(MVNETA_PANC_FORCELINKFAIL | 569 MVNETA_PANC_FORCELINKPASS); 570 /* TODO: read mode from SFP */ 571 if (1) { 572 /* 802.3z */ 573 ctl0 |= MVNETA_PMACC0_PORTTYPE; 574 panc |= (MVNETA_PANC_INBANDANEN | 575 MVNETA_PANC_SETGMIISPEED | 576 MVNETA_PANC_SETFULLDX); 577 } else { 578 /* SGMII */ 579 ctl2 |= MVNETA_PMACC2_INBANDAN; 580 panc |= (MVNETA_PANC_INBANDANEN | 581 MVNETA_PANC_ANSPEEDEN | 582 MVNETA_PANC_ANDUPLEXEN); 583 } 584 MVNETA_WRITE(sc, MVNETA_OMSCD, 585 MVNETA_READ(sc, MVNETA_OMSCD) | MVNETA_OMSCD_1MS_CLOCK_ENABLE); 586 } else { 587 MVNETA_WRITE(sc, MVNETA_OMSCD, 588 MVNETA_READ(sc, MVNETA_OMSCD) & ~MVNETA_OMSCD_1MS_CLOCK_ENABLE); 589 } 590 591 MVNETA_WRITE(sc, MVNETA_PMACC0, ctl0); 592 MVNETA_WRITE(sc, MVNETA_PMACC2, ctl2); 593 MVNETA_WRITE(sc, MVNETA_PANC, panc); 594 595 /* Port reset */ 596 while (MVNETA_READ(sc, MVNETA_PMACC2) & MVNETA_PMACC2_PORTMACRESET) 597 ; 598 599 fdt_intr_establish(faa->fa_node, IPL_NET, mvneta_intr, sc, 600 sc->sc_dev.dv_xname); 601 602 ifp = &sc->sc_ac.ac_if; 603 ifp->if_softc = sc; 604 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 605 ifp->if_start = mvneta_start; 606 ifp->if_ioctl = mvneta_ioctl; 607 ifp->if_watchdog = mvneta_watchdog; 608 ifp->if_capabilities = IFCAP_VLAN_MTU; 609 610 #if notyet 611 /* 612 * We can do IPv4/TCPv4/UDPv4 checksums in hardware. 613 */ 614 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 615 IFCAP_CSUM_UDPv4; 616 617 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 618 /* 619 * But, IPv6 packets in the stream can cause incorrect TCPv4 Tx sums. 620 */ 621 ifp->if_capabilities &= ~IFCAP_CSUM_TCPv4; 622 #endif 623 624 IFQ_SET_MAXLEN(&ifp->if_snd, max(MVNETA_TX_RING_CNT - 1, IFQ_MAXLEN)); 625 strlcpy(ifp->if_xname, sc->sc_dev.dv_xname, sizeof(ifp->if_xname)); 626 627 /* 628 * Do MII setup. 629 */ 630 sc->sc_mii.mii_ifp = ifp; 631 sc->sc_mii.mii_readreg = mvneta_miibus_readreg; 632 sc->sc_mii.mii_writereg = mvneta_miibus_writereg; 633 sc->sc_mii.mii_statchg = mvneta_miibus_statchg; 634 635 ifmedia_init(&sc->sc_mii.mii_media, 0, 636 mvneta_mediachange, mvneta_mediastatus); 637 638 config_defer(self, mvneta_attach_deferred); 639 } 640 641 void 642 mvneta_attach_deferred(struct device *self) 643 { 644 struct mvneta_softc *sc = (struct mvneta_softc *) self; 645 struct ifnet *ifp = &sc->sc_ac.ac_if; 646 647 if (!sc->sc_fixed_link) { 648 extern void *mvmdio_sc; 649 sc->sc_mdio = mvmdio_sc; 650 651 if (sc->sc_mdio == NULL) { 652 printf("%s: mdio bus not yet attached\n", self->dv_xname); 653 return; 654 } 655 656 mii_attach(self, &sc->sc_mii, 0xffffffff, sc->sc_phy, 657 MII_OFFSET_ANY, 0); 658 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 659 printf("%s: no PHY found!\n", self->dv_xname); 660 ifmedia_add(&sc->sc_mii.mii_media, 661 IFM_ETHER|IFM_MANUAL, 0, NULL); 662 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 663 } else 664 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 665 } else { 666 ifmedia_add(&sc->sc_mii.mii_media, 667 IFM_ETHER|IFM_MANUAL, 0, NULL); 668 ifmedia_set(&sc->sc_mii.mii_media, 669 IFM_ETHER|IFM_MANUAL); 670 671 if (sc->sc_inband_status) { 672 mvneta_inband_statchg(sc); 673 } else { 674 sc->sc_mii.mii_media_status = IFM_AVALID|IFM_ACTIVE; 675 sc->sc_mii.mii_media_active = IFM_ETHER|IFM_1000_T|IFM_FDX; 676 mvneta_miibus_statchg(self); 677 } 678 679 ifp->if_baudrate = ifmedia_baudrate(sc->sc_mii.mii_media_active); 680 ifp->if_link_state = LINK_STATE_FULL_DUPLEX; 681 } 682 683 /* 684 * Call MI attach routines. 685 */ 686 if_attach(ifp); 687 ether_ifattach(ifp); 688 } 689 690 void 691 mvneta_tick(void *arg) 692 { 693 struct mvneta_softc *sc = arg; 694 struct mii_data *mii = &sc->sc_mii; 695 int s; 696 697 s = splnet(); 698 mii_tick(mii); 699 splx(s); 700 701 timeout_add_sec(&sc->sc_tick_ch, 1); 702 } 703 704 int 705 mvneta_intr(void *arg) 706 { 707 struct mvneta_softc *sc = arg; 708 struct ifnet *ifp = &sc->sc_ac.ac_if; 709 uint32_t ic, misc; 710 711 ic = MVNETA_READ(sc, MVNETA_PRXTXTIC); 712 713 if (ic & MVNETA_PRXTXTI_PMISCICSUMMARY) { 714 misc = MVNETA_READ(sc, MVNETA_PMIC); 715 MVNETA_WRITE(sc, MVNETA_PMIC, 0); 716 if (sc->sc_inband_status && (misc & 717 (MVNETA_PMI_PHYSTATUSCHNG | 718 MVNETA_PMI_LINKCHANGE | 719 MVNETA_PMI_PSCSYNCCHNG))) { 720 mvneta_inband_statchg(sc); 721 } 722 } 723 724 if (!(ifp->if_flags & IFF_RUNNING)) 725 return 1; 726 727 if (ic & MVNETA_PRXTXTI_TBTCQ(0)) 728 mvneta_tx_proc(sc); 729 730 if (ic & MVNETA_PRXTXTI_RBICTAPQ(0)) 731 mvneta_rx_proc(sc); 732 733 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 734 mvneta_start(ifp); 735 736 return 1; 737 } 738 739 void 740 mvneta_start(struct ifnet *ifp) 741 { 742 struct mvneta_softc *sc = ifp->if_softc; 743 struct mbuf *m_head = NULL; 744 int idx; 745 746 DPRINTFN(3, ("mvneta_start (idx %d)\n", sc->sc_tx_prod)); 747 748 if (!(ifp->if_flags & IFF_RUNNING)) 749 return; 750 if (ifq_is_oactive(&ifp->if_snd)) 751 return; 752 if (IFQ_IS_EMPTY(&ifp->if_snd)) 753 return; 754 755 /* If Link is DOWN, can't start TX */ 756 if (!MVNETA_IS_LINKUP(sc)) 757 return; 758 759 bus_dmamap_sync(sc->sc_dmat, MVNETA_DMA_MAP(sc->sc_txring), 0, 760 MVNETA_DMA_LEN(sc->sc_txring), 761 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 762 763 idx = sc->sc_tx_prod; 764 while (sc->sc_tx_cnt < MVNETA_TX_RING_CNT) { 765 m_head = ifq_deq_begin(&ifp->if_snd); 766 if (m_head == NULL) 767 break; 768 769 /* 770 * Pack the data into the transmit ring. If we 771 * don't have room, set the OACTIVE flag and wait 772 * for the NIC to drain the ring. 773 */ 774 if (mvneta_encap(sc, m_head, &idx)) { 775 ifq_deq_rollback(&ifp->if_snd, m_head); 776 ifq_set_oactive(&ifp->if_snd); 777 break; 778 } 779 780 /* now we are committed to transmit the packet */ 781 ifq_deq_commit(&ifp->if_snd, m_head); 782 783 /* 784 * If there's a BPF listener, bounce a copy of this frame 785 * to him. 786 */ 787 #if NBPFILTER > 0 788 if (ifp->if_bpf) 789 bpf_mtap(ifp->if_bpf, m_head, BPF_DIRECTION_OUT); 790 #endif 791 } 792 793 if (sc->sc_tx_prod != idx) { 794 sc->sc_tx_prod = idx; 795 796 /* 797 * Set a timeout in case the chip goes out to lunch. 798 */ 799 ifp->if_timer = 5; 800 } 801 } 802 803 int 804 mvneta_ioctl(struct ifnet *ifp, u_long cmd, caddr_t addr) 805 { 806 struct mvneta_softc *sc = ifp->if_softc; 807 struct ifreq *ifr = (struct ifreq *)addr; 808 int s, error = 0; 809 810 s = splnet(); 811 812 switch (cmd) { 813 case SIOCSIFADDR: 814 ifp->if_flags |= IFF_UP; 815 /* FALLTHROUGH */ 816 case SIOCSIFFLAGS: 817 if (ifp->if_flags & IFF_UP) { 818 if (ifp->if_flags & IFF_RUNNING) 819 error = ENETRESET; 820 else 821 mvneta_up(sc); 822 } else { 823 if (ifp->if_flags & IFF_RUNNING) 824 mvneta_down(sc); 825 } 826 break; 827 case SIOCGIFMEDIA: 828 case SIOCSIFMEDIA: 829 DPRINTFN(2, ("mvneta_ioctl MEDIA\n")); 830 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 831 break; 832 case SIOCGIFRXR: 833 error = if_rxr_ioctl((struct if_rxrinfo *)ifr->ifr_data, 834 NULL, MCLBYTES, &sc->sc_rx_ring); 835 break; 836 case SIOCGIFSFFPAGE: 837 error = rw_enter(&mvneta_sff_lock, RW_WRITE|RW_INTR); 838 if (error != 0) 839 break; 840 841 error = sfp_get_sffpage(sc->sc_sfp, (struct if_sffpage *)addr); 842 rw_exit(&mvneta_sff_lock); 843 break; 844 default: 845 DPRINTFN(2, ("mvneta_ioctl ETHER\n")); 846 error = ether_ioctl(ifp, &sc->sc_ac, cmd, addr); 847 break; 848 } 849 850 if (error == ENETRESET) { 851 if (ifp->if_flags & IFF_RUNNING) 852 mvneta_iff(sc); 853 error = 0; 854 } 855 856 splx(s); 857 858 return error; 859 } 860 861 void 862 mvneta_port_change(struct mvneta_softc *sc) 863 { 864 if (!!(sc->sc_mii.mii_media_status & IFM_ACTIVE) != sc->sc_link) { 865 sc->sc_link = !sc->sc_link; 866 867 if (sc->sc_link) { 868 if (!sc->sc_inband_status) { 869 uint32_t panc = MVNETA_READ(sc, MVNETA_PANC); 870 panc &= ~MVNETA_PANC_FORCELINKFAIL; 871 panc |= MVNETA_PANC_FORCELINKPASS; 872 MVNETA_WRITE(sc, MVNETA_PANC, panc); 873 } 874 mvneta_port_up(sc); 875 } else { 876 if (!sc->sc_inband_status) { 877 uint32_t panc = MVNETA_READ(sc, MVNETA_PANC); 878 panc &= ~MVNETA_PANC_FORCELINKPASS; 879 panc |= MVNETA_PANC_FORCELINKFAIL; 880 MVNETA_WRITE(sc, MVNETA_PANC, panc); 881 } 882 } 883 } 884 } 885 886 void 887 mvneta_port_up(struct mvneta_softc *sc) 888 { 889 /* Enable port RX/TX. */ 890 MVNETA_WRITE(sc, MVNETA_RQC, MVNETA_RQC_ENQ(0)); 891 MVNETA_WRITE(sc, MVNETA_TQC, MVNETA_TQC_ENQ(0)); 892 } 893 894 int 895 mvneta_up(struct mvneta_softc *sc) 896 { 897 struct ifnet *ifp = &sc->sc_ac.ac_if; 898 struct mvneta_buf *txb, *rxb; 899 int i; 900 901 DPRINTFN(2, ("mvneta_up\n")); 902 903 /* Allocate Tx descriptor ring. */ 904 sc->sc_txring = mvneta_dmamem_alloc(sc, 905 MVNETA_TX_RING_CNT * sizeof(struct mvneta_tx_desc), 32); 906 sc->sc_txdesc = MVNETA_DMA_KVA(sc->sc_txring); 907 908 sc->sc_txbuf = malloc(sizeof(struct mvneta_buf) * MVNETA_TX_RING_CNT, 909 M_DEVBUF, M_WAITOK); 910 911 for (i = 0; i < MVNETA_TX_RING_CNT; i++) { 912 txb = &sc->sc_txbuf[i]; 913 bus_dmamap_create(sc->sc_dmat, MCLBYTES, MVNETA_NTXSEG, 914 MCLBYTES, 0, BUS_DMA_WAITOK, &txb->tb_map); 915 txb->tb_m = NULL; 916 } 917 918 sc->sc_tx_prod = sc->sc_tx_cons = 0; 919 sc->sc_tx_cnt = 0; 920 921 /* Allocate Rx descriptor ring. */ 922 sc->sc_rxring = mvneta_dmamem_alloc(sc, 923 MVNETA_RX_RING_CNT * sizeof(struct mvneta_rx_desc), 32); 924 sc->sc_rxdesc = MVNETA_DMA_KVA(sc->sc_rxring); 925 926 sc->sc_rxbuf = malloc(sizeof(struct mvneta_buf) * MVNETA_RX_RING_CNT, 927 M_DEVBUF, M_WAITOK); 928 929 for (i = 0; i < MVNETA_RX_RING_CNT; i++) { 930 rxb = &sc->sc_rxbuf[i]; 931 bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 932 MCLBYTES, 0, BUS_DMA_WAITOK, &rxb->tb_map); 933 rxb->tb_m = NULL; 934 } 935 936 /* Set Rx descriptor ring data. */ 937 MVNETA_WRITE(sc, MVNETA_PRXDQA(0), MVNETA_DMA_DVA(sc->sc_rxring)); 938 MVNETA_WRITE(sc, MVNETA_PRXDQS(0), MVNETA_RX_RING_CNT | 939 ((MCLBYTES >> 3) << 19)); 940 MVNETA_WRITE(sc, MVNETA_PRXDQTH(0), 0); 941 MVNETA_WRITE(sc, MVNETA_PRXC(0), 0); 942 943 /* Set Tx queue bandwidth. */ 944 MVNETA_WRITE(sc, MVNETA_TQTBCOUNT(0), 0x03ffffff); 945 MVNETA_WRITE(sc, MVNETA_TQTBCONFIG(0), 0x03ffffff); 946 947 /* Set Tx descriptor ring data. */ 948 MVNETA_WRITE(sc, MVNETA_PTXDQA(0), MVNETA_DMA_DVA(sc->sc_txring)); 949 MVNETA_WRITE(sc, MVNETA_PTXDQS(0), 950 MVNETA_PTXDQS_DQS(MVNETA_TX_RING_CNT)); 951 952 sc->sc_rx_prod = sc->sc_rx_cons = 0; 953 954 if_rxr_init(&sc->sc_rx_ring, 2, MVNETA_RX_RING_CNT); 955 mvneta_fill_rx_ring(sc); 956 957 /* TODO: correct frame size */ 958 MVNETA_WRITE(sc, MVNETA_PMACC0, 959 (MVNETA_READ(sc, MVNETA_PMACC0) & MVNETA_PMACC0_PORTTYPE) | 960 MVNETA_PMACC0_FRAMESIZELIMIT(MCLBYTES - MVNETA_HWHEADER_SIZE)); 961 962 /* set max MTU */ 963 MVNETA_WRITE(sc, MVNETA_TXMTU, MVNETA_TXMTU_MAX); 964 MVNETA_WRITE(sc, MVNETA_TXTKSIZE, 0xffffffff); 965 MVNETA_WRITE(sc, MVNETA_TXQTKSIZE(0), 0x7fffffff); 966 967 /* enable port */ 968 MVNETA_WRITE(sc, MVNETA_PMACC0, 969 MVNETA_READ(sc, MVNETA_PMACC0) | MVNETA_PMACC0_PORTEN); 970 971 mvneta_enaddr_write(sc); 972 973 /* Program promiscuous mode and multicast filters. */ 974 mvneta_iff(sc); 975 976 if (!sc->sc_fixed_link) 977 mii_mediachg(&sc->sc_mii); 978 979 if (sc->sc_link) 980 mvneta_port_up(sc); 981 982 /* Enable interrupt masks */ 983 MVNETA_WRITE(sc, MVNETA_PRXTXTIM, MVNETA_PRXTXTI_RBICTAPQ(0) | 984 MVNETA_PRXTXTI_TBTCQ(0) | MVNETA_PRXTXTI_PMISCICSUMMARY); 985 MVNETA_WRITE(sc, MVNETA_PMIM, MVNETA_PMI_PHYSTATUSCHNG | 986 MVNETA_PMI_LINKCHANGE | MVNETA_PMI_PSCSYNCCHNG); 987 988 timeout_add_sec(&sc->sc_tick_ch, 1); 989 990 ifp->if_flags |= IFF_RUNNING; 991 ifq_clr_oactive(&ifp->if_snd); 992 993 return 0; 994 } 995 996 void 997 mvneta_down(struct mvneta_softc *sc) 998 { 999 struct ifnet *ifp = &sc->sc_ac.ac_if; 1000 uint32_t reg, txinprog, txfifoemp; 1001 struct mvneta_buf *txb, *rxb; 1002 int i, cnt; 1003 1004 DPRINTFN(2, ("mvneta_down\n")); 1005 1006 timeout_del(&sc->sc_tick_ch); 1007 1008 /* Stop Rx port activity. Check port Rx activity. */ 1009 reg = MVNETA_READ(sc, MVNETA_RQC); 1010 if (reg & MVNETA_RQC_ENQ_MASK) 1011 /* Issue stop command for active channels only */ 1012 MVNETA_WRITE(sc, MVNETA_RQC, MVNETA_RQC_DISQ_DISABLE(reg)); 1013 1014 /* Stop Tx port activity. Check port Tx activity. */ 1015 if (MVNETA_READ(sc, MVNETA_TQC) & MVNETA_TQC_ENQ(0)) 1016 MVNETA_WRITE(sc, MVNETA_TQC, MVNETA_TQC_DISQ(0)); 1017 1018 txinprog = MVNETA_PS_TXINPROG_(0); 1019 txfifoemp = MVNETA_PS_TXFIFOEMP_(0); 1020 1021 #define RX_DISABLE_TIMEOUT 0x1000000 1022 #define TX_FIFO_EMPTY_TIMEOUT 0x1000000 1023 /* Wait for all Rx activity to terminate. */ 1024 cnt = 0; 1025 do { 1026 if (cnt >= RX_DISABLE_TIMEOUT) { 1027 printf("%s: timeout for RX stopped. rqc 0x%x\n", 1028 sc->sc_dev.dv_xname, reg); 1029 break; 1030 } 1031 cnt++; 1032 1033 /* 1034 * Check Receive Queue Command register that all Rx queues 1035 * are stopped 1036 */ 1037 reg = MVNETA_READ(sc, MVNETA_RQC); 1038 } while (reg & 0xff); 1039 1040 /* Double check to verify that TX FIFO is empty */ 1041 cnt = 0; 1042 while (1) { 1043 do { 1044 if (cnt >= TX_FIFO_EMPTY_TIMEOUT) { 1045 printf("%s: timeout for TX FIFO empty. status " 1046 "0x%x\n", sc->sc_dev.dv_xname, reg); 1047 break; 1048 } 1049 cnt++; 1050 1051 reg = MVNETA_READ(sc, MVNETA_PS); 1052 } while (!(reg & txfifoemp) || reg & txinprog); 1053 1054 if (cnt >= TX_FIFO_EMPTY_TIMEOUT) 1055 break; 1056 1057 /* Double check */ 1058 reg = MVNETA_READ(sc, MVNETA_PS); 1059 if (reg & txfifoemp && !(reg & txinprog)) 1060 break; 1061 else 1062 printf("%s: TX FIFO empty double check failed." 1063 " %d loops, status 0x%x\n", sc->sc_dev.dv_xname, 1064 cnt, reg); 1065 } 1066 1067 delay(200); 1068 1069 /* disable port */ 1070 MVNETA_WRITE(sc, MVNETA_PMACC0, 1071 MVNETA_READ(sc, MVNETA_PMACC0) & ~MVNETA_PMACC0_PORTEN); 1072 delay(200); 1073 1074 /* mask all interrupts */ 1075 MVNETA_WRITE(sc, MVNETA_PRXTXTIM, MVNETA_PRXTXTI_PMISCICSUMMARY); 1076 MVNETA_WRITE(sc, MVNETA_PRXTXIM, 0); 1077 1078 /* clear all cause registers */ 1079 MVNETA_WRITE(sc, MVNETA_PRXTXTIC, 0); 1080 MVNETA_WRITE(sc, MVNETA_PRXTXIC, 0); 1081 1082 /* Free RX and TX mbufs still in the queues. */ 1083 for (i = 0; i < MVNETA_TX_RING_CNT; i++) { 1084 txb = &sc->sc_txbuf[i]; 1085 if (txb->tb_m) { 1086 bus_dmamap_sync(sc->sc_dmat, txb->tb_map, 0, 1087 txb->tb_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1088 bus_dmamap_unload(sc->sc_dmat, txb->tb_map); 1089 m_freem(txb->tb_m); 1090 } 1091 bus_dmamap_destroy(sc->sc_dmat, txb->tb_map); 1092 } 1093 1094 mvneta_dmamem_free(sc, sc->sc_txring); 1095 free(sc->sc_txbuf, M_DEVBUF, 0); 1096 1097 for (i = 0; i < MVNETA_RX_RING_CNT; i++) { 1098 rxb = &sc->sc_rxbuf[i]; 1099 if (rxb->tb_m) { 1100 bus_dmamap_sync(sc->sc_dmat, rxb->tb_map, 0, 1101 rxb->tb_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1102 bus_dmamap_unload(sc->sc_dmat, rxb->tb_map); 1103 m_freem(rxb->tb_m); 1104 } 1105 bus_dmamap_destroy(sc->sc_dmat, rxb->tb_map); 1106 } 1107 1108 mvneta_dmamem_free(sc, sc->sc_rxring); 1109 free(sc->sc_rxbuf, M_DEVBUF, 0); 1110 1111 /* reset RX and TX DMAs */ 1112 MVNETA_WRITE(sc, MVNETA_PRXINIT, MVNETA_PRXINIT_RXDMAINIT); 1113 MVNETA_WRITE(sc, MVNETA_PTXINIT, MVNETA_PTXINIT_TXDMAINIT); 1114 MVNETA_WRITE(sc, MVNETA_PRXINIT, 0); 1115 MVNETA_WRITE(sc, MVNETA_PTXINIT, 0); 1116 1117 ifp->if_flags &= ~IFF_RUNNING; 1118 ifq_clr_oactive(&ifp->if_snd); 1119 } 1120 1121 void 1122 mvneta_watchdog(struct ifnet *ifp) 1123 { 1124 struct mvneta_softc *sc = ifp->if_softc; 1125 1126 /* 1127 * Reclaim first as there is a possibility of losing Tx completion 1128 * interrupts. 1129 */ 1130 mvneta_tx_proc(sc); 1131 if (sc->sc_tx_cnt != 0) { 1132 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 1133 1134 ifp->if_oerrors++; 1135 } 1136 } 1137 1138 /* 1139 * Set media options. 1140 */ 1141 int 1142 mvneta_mediachange(struct ifnet *ifp) 1143 { 1144 struct mvneta_softc *sc = ifp->if_softc; 1145 1146 if (LIST_FIRST(&sc->sc_mii.mii_phys)) 1147 mii_mediachg(&sc->sc_mii); 1148 1149 return (0); 1150 } 1151 1152 /* 1153 * Report current media status. 1154 */ 1155 void 1156 mvneta_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1157 { 1158 struct mvneta_softc *sc = ifp->if_softc; 1159 1160 if (LIST_FIRST(&sc->sc_mii.mii_phys)) { 1161 mii_pollstat(&sc->sc_mii); 1162 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1163 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1164 } 1165 1166 if (sc->sc_fixed_link) { 1167 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1168 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1169 } 1170 } 1171 1172 int 1173 mvneta_encap(struct mvneta_softc *sc, struct mbuf *m, uint32_t *idx) 1174 { 1175 struct mvneta_tx_desc *txd; 1176 bus_dmamap_t map; 1177 uint32_t cmdsts; 1178 int i, current, first, last; 1179 1180 DPRINTFN(3, ("mvneta_encap\n")); 1181 1182 first = last = current = *idx; 1183 map = sc->sc_txbuf[current].tb_map; 1184 1185 if (bus_dmamap_load_mbuf(sc->sc_dmat, map, m, BUS_DMA_NOWAIT)) 1186 return (ENOBUFS); 1187 1188 if (map->dm_nsegs > (MVNETA_TX_RING_CNT - sc->sc_tx_cnt - 2)) { 1189 bus_dmamap_unload(sc->sc_dmat, map); 1190 return (ENOBUFS); 1191 } 1192 1193 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1194 BUS_DMASYNC_PREWRITE); 1195 1196 DPRINTFN(2, ("mvneta_encap: dm_nsegs=%d\n", map->dm_nsegs)); 1197 1198 cmdsts = MVNETA_TX_L4_CSUM_NOT; 1199 #if notyet 1200 int m_csumflags; 1201 if (m_csumflags & M_CSUM_IPv4) 1202 cmdsts |= MVNETA_TX_GENERATE_IP_CHKSUM; 1203 if (m_csumflags & M_CSUM_TCPv4) 1204 cmdsts |= 1205 MVNETA_TX_GENERATE_L4_CHKSUM | MVNETA_TX_L4_TYPE_TCP; 1206 if (m_csumflags & M_CSUM_UDPv4) 1207 cmdsts |= 1208 MVNETA_TX_GENERATE_L4_CHKSUM | MVNETA_TX_L4_TYPE_UDP; 1209 if (m_csumflags & (M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 1210 const int iphdr_unitlen = sizeof(struct ip) / sizeof(uint32_t); 1211 1212 cmdsts |= MVNETA_TX_IP_NO_FRAG | 1213 MVNETA_TX_IP_HEADER_LEN(iphdr_unitlen); /* unit is 4B */ 1214 } 1215 #endif 1216 1217 for (i = 0; i < map->dm_nsegs; i++) { 1218 txd = &sc->sc_txdesc[current]; 1219 memset(txd, 0, sizeof(*txd)); 1220 txd->bufptr = map->dm_segs[i].ds_addr; 1221 txd->bytecnt = map->dm_segs[i].ds_len; 1222 txd->cmdsts = cmdsts | 1223 MVNETA_TX_ZERO_PADDING; 1224 if (i == 0) 1225 txd->cmdsts |= MVNETA_TX_FIRST_DESC; 1226 if (i == (map->dm_nsegs - 1)) 1227 txd->cmdsts |= MVNETA_TX_LAST_DESC; 1228 1229 bus_dmamap_sync(sc->sc_dmat, MVNETA_DMA_MAP(sc->sc_txring), 1230 current * sizeof(*txd), sizeof(*txd), 1231 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1232 1233 last = current; 1234 current = MVNETA_TX_RING_NEXT(current); 1235 KASSERT(current != sc->sc_tx_cons); 1236 } 1237 1238 KASSERT(sc->sc_txbuf[last].tb_m == NULL); 1239 sc->sc_txbuf[first].tb_map = sc->sc_txbuf[last].tb_map; 1240 sc->sc_txbuf[last].tb_map = map; 1241 sc->sc_txbuf[last].tb_m = m; 1242 1243 sc->sc_tx_cnt += map->dm_nsegs; 1244 *idx = current; 1245 1246 /* Let him know we sent another packet. */ 1247 MVNETA_WRITE(sc, MVNETA_PTXSU(0), map->dm_nsegs); 1248 1249 DPRINTFN(3, ("mvneta_encap: completed successfully\n")); 1250 1251 return 0; 1252 } 1253 1254 void 1255 mvneta_rx_proc(struct mvneta_softc *sc) 1256 { 1257 struct ifnet *ifp = &sc->sc_ac.ac_if; 1258 struct mvneta_rx_desc *rxd; 1259 struct mvneta_buf *rxb; 1260 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 1261 struct mbuf *m; 1262 uint32_t rxstat; 1263 int i, idx, len, ready; 1264 1265 DPRINTFN(3, ("%s: %d\n", __func__, sc->sc_rx_cons)); 1266 1267 if (!(ifp->if_flags & IFF_RUNNING)) 1268 return; 1269 1270 bus_dmamap_sync(sc->sc_dmat, MVNETA_DMA_MAP(sc->sc_rxring), 0, 1271 MVNETA_DMA_LEN(sc->sc_rxring), 1272 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1273 1274 ready = MVNETA_PRXS_ODC(MVNETA_READ(sc, MVNETA_PRXS(0))); 1275 MVNETA_WRITE(sc, MVNETA_PRXSU(0), ready); 1276 1277 for (i = 0; i < ready; i++) { 1278 idx = sc->sc_rx_cons; 1279 KASSERT(idx < MVNETA_RX_RING_CNT); 1280 1281 rxd = &sc->sc_rxdesc[idx]; 1282 1283 #ifdef DIAGNOSTIC 1284 if ((rxd->cmdsts & 1285 (MVNETA_RX_LAST_DESC | MVNETA_RX_FIRST_DESC)) != 1286 (MVNETA_RX_LAST_DESC | MVNETA_RX_FIRST_DESC)) 1287 panic("%s: buffer size is smaller than packet", 1288 __func__); 1289 #endif 1290 1291 len = rxd->bytecnt; 1292 rxb = &sc->sc_rxbuf[idx]; 1293 KASSERT(rxb->tb_m); 1294 1295 bus_dmamap_sync(sc->sc_dmat, rxb->tb_map, 0, 1296 len, BUS_DMASYNC_POSTREAD); 1297 bus_dmamap_unload(sc->sc_dmat, rxb->tb_map); 1298 1299 m = rxb->tb_m; 1300 rxb->tb_m = NULL; 1301 m->m_pkthdr.len = m->m_len = len; 1302 1303 rxstat = rxd->cmdsts; 1304 if (rxstat & MVNETA_ERROR_SUMMARY) { 1305 #if 0 1306 int err = rxstat & MVNETA_RX_ERROR_CODE_MASK; 1307 1308 if (err == MVNETA_RX_CRC_ERROR) 1309 ifp->if_ierrors++; 1310 if (err == MVNETA_RX_OVERRUN_ERROR) 1311 ifp->if_ierrors++; 1312 if (err == MVNETA_RX_MAX_FRAME_LEN_ERROR) 1313 ifp->if_ierrors++; 1314 if (err == MVNETA_RX_RESOURCE_ERROR) 1315 ifp->if_ierrors++; 1316 #else 1317 ifp->if_ierrors++; 1318 #endif 1319 panic("%s: handle input errors", __func__); 1320 continue; 1321 } 1322 1323 #if notyet 1324 if (rxstat & MVNETA_RX_IP_FRAME_TYPE) { 1325 int flgs = 0; 1326 1327 /* Check IPv4 header checksum */ 1328 flgs |= M_CSUM_IPv4; 1329 if (!(rxstat & MVNETA_RX_IP_HEADER_OK)) 1330 flgs |= M_CSUM_IPv4_BAD; 1331 else if ((bufsize & MVNETA_RX_IP_FRAGMENT) == 0) { 1332 /* 1333 * Check TCPv4/UDPv4 checksum for 1334 * non-fragmented packet only. 1335 * 1336 * It seemd that sometimes 1337 * MVNETA_RX_L4_CHECKSUM_OK bit was set to 0 1338 * even if the checksum is correct and the 1339 * packet was not fragmented. So we don't set 1340 * M_CSUM_TCP_UDP_BAD even if csum bit is 0. 1341 */ 1342 1343 if (((rxstat & MVNETA_RX_L4_TYPE_MASK) == 1344 MVNETA_RX_L4_TYPE_TCP) && 1345 ((rxstat & MVNETA_RX_L4_CHECKSUM_OK) != 0)) 1346 flgs |= M_CSUM_TCPv4; 1347 else if (((rxstat & MVNETA_RX_L4_TYPE_MASK) == 1348 MVNETA_RX_L4_TYPE_UDP) && 1349 ((rxstat & MVNETA_RX_L4_CHECKSUM_OK) != 0)) 1350 flgs |= M_CSUM_UDPv4; 1351 } 1352 m->m_pkthdr.csum_flags = flgs; 1353 } 1354 #endif 1355 1356 /* Skip on first 2byte (HW header) */ 1357 m_adj(m, MVNETA_HWHEADER_SIZE); 1358 1359 ml_enqueue(&ml, m); 1360 1361 if_rxr_put(&sc->sc_rx_ring, 1); 1362 1363 sc->sc_rx_cons = MVNETA_RX_RING_NEXT(idx); 1364 } 1365 1366 if (ifiq_input(&ifp->if_rcv, &ml)) 1367 if_rxr_livelocked(&sc->sc_rx_ring); 1368 1369 mvneta_fill_rx_ring(sc); 1370 } 1371 1372 void 1373 mvneta_tx_proc(struct mvneta_softc *sc) 1374 { 1375 struct ifnet *ifp = &sc->sc_ac.ac_if; 1376 struct mvneta_tx_desc *txd; 1377 struct mvneta_buf *txb; 1378 int i, idx, sent; 1379 1380 DPRINTFN(3, ("%s\n", __func__)); 1381 1382 if (!(ifp->if_flags & IFF_RUNNING)) 1383 return; 1384 1385 bus_dmamap_sync(sc->sc_dmat, MVNETA_DMA_MAP(sc->sc_txring), 0, 1386 MVNETA_DMA_LEN(sc->sc_txring), 1387 BUS_DMASYNC_POSTREAD); 1388 1389 sent = MVNETA_PTXS_TBC(MVNETA_READ(sc, MVNETA_PTXS(0))); 1390 MVNETA_WRITE(sc, MVNETA_PTXSU(0), MVNETA_PTXSU_NORB(sent)); 1391 1392 for (i = 0; i < sent; i++) { 1393 idx = sc->sc_tx_cons; 1394 KASSERT(idx < MVNETA_TX_RING_CNT); 1395 1396 txd = &sc->sc_txdesc[idx]; 1397 txb = &sc->sc_txbuf[idx]; 1398 if (txb->tb_m) { 1399 bus_dmamap_sync(sc->sc_dmat, txb->tb_map, 0, 1400 txb->tb_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1401 bus_dmamap_unload(sc->sc_dmat, txb->tb_map); 1402 1403 m_freem(txb->tb_m); 1404 txb->tb_m = NULL; 1405 } 1406 1407 ifq_clr_oactive(&ifp->if_snd); 1408 1409 sc->sc_tx_cnt--; 1410 1411 if (txd->cmdsts & MVNETA_ERROR_SUMMARY) { 1412 int err = txd->cmdsts & MVNETA_TX_ERROR_CODE_MASK; 1413 1414 if (err == MVNETA_TX_LATE_COLLISION_ERROR) 1415 ifp->if_collisions++; 1416 if (err == MVNETA_TX_UNDERRUN_ERROR) 1417 ifp->if_oerrors++; 1418 if (err == MVNETA_TX_EXCESSIVE_COLLISION_ERRO) 1419 ifp->if_collisions++; 1420 } 1421 1422 sc->sc_tx_cons = MVNETA_TX_RING_NEXT(sc->sc_tx_cons); 1423 } 1424 1425 if (sc->sc_tx_cnt == 0) 1426 ifp->if_timer = 0; 1427 } 1428 1429 uint8_t 1430 mvneta_crc8(const uint8_t *data, size_t size) 1431 { 1432 int bit; 1433 uint8_t byte; 1434 uint8_t crc = 0; 1435 const uint8_t poly = 0x07; 1436 1437 while(size--) 1438 for (byte = *data++, bit = NBBY-1; bit >= 0; bit--) 1439 crc = (crc << 1) ^ ((((crc >> 7) ^ (byte >> bit)) & 1) ? poly : 0); 1440 1441 return crc; 1442 } 1443 1444 CTASSERT(MVNETA_NDFSMT == MVNETA_NDFOMT); 1445 1446 void 1447 mvneta_iff(struct mvneta_softc *sc) 1448 { 1449 struct arpcom *ac = &sc->sc_ac; 1450 struct ifnet *ifp = &sc->sc_ac.ac_if; 1451 struct ether_multi *enm; 1452 struct ether_multistep step; 1453 uint32_t dfut[MVNETA_NDFUT], dfsmt[MVNETA_NDFSMT], dfomt[MVNETA_NDFOMT]; 1454 uint32_t pxc; 1455 int i; 1456 const uint8_t special[ETHER_ADDR_LEN] = {0x01,0x00,0x5e,0x00,0x00,0x00}; 1457 1458 pxc = MVNETA_READ(sc, MVNETA_PXC); 1459 pxc &= ~(MVNETA_PXC_RB | MVNETA_PXC_RBIP | MVNETA_PXC_RBARP | MVNETA_PXC_UPM); 1460 ifp->if_flags &= ~IFF_ALLMULTI; 1461 memset(dfut, 0, sizeof(dfut)); 1462 memset(dfsmt, 0, sizeof(dfsmt)); 1463 memset(dfomt, 0, sizeof(dfomt)); 1464 1465 if (ifp->if_flags & IFF_PROMISC || ac->ac_multirangecnt > 0) { 1466 ifp->if_flags |= IFF_ALLMULTI; 1467 if (ifp->if_flags & IFF_PROMISC) 1468 pxc |= MVNETA_PXC_UPM; 1469 for (i = 0; i < MVNETA_NDFSMT; i++) { 1470 dfsmt[i] = dfomt[i] = 1471 MVNETA_DF(0, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS) | 1472 MVNETA_DF(1, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS) | 1473 MVNETA_DF(2, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS) | 1474 MVNETA_DF(3, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS); 1475 } 1476 } else { 1477 ETHER_FIRST_MULTI(step, ac, enm); 1478 while (enm != NULL) { 1479 /* chip handles some IPv4 multicast specially */ 1480 if (memcmp(enm->enm_addrlo, special, 5) == 0) { 1481 i = enm->enm_addrlo[5]; 1482 dfsmt[i>>2] |= 1483 MVNETA_DF(i&3, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS); 1484 } else { 1485 i = mvneta_crc8(enm->enm_addrlo, ETHER_ADDR_LEN); 1486 dfomt[i>>2] |= 1487 MVNETA_DF(i&3, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS); 1488 } 1489 1490 ETHER_NEXT_MULTI(step, enm); 1491 } 1492 } 1493 1494 MVNETA_WRITE(sc, MVNETA_PXC, pxc); 1495 1496 /* Set Destination Address Filter Unicast Table */ 1497 i = sc->sc_enaddr[5] & 0xf; /* last nibble */ 1498 dfut[i>>2] = MVNETA_DF(i&3, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS); 1499 MVNETA_WRITE_FILTER(sc, MVNETA_DFUT, dfut, MVNETA_NDFUT); 1500 1501 /* Set Destination Address Filter Multicast Tables */ 1502 MVNETA_WRITE_FILTER(sc, MVNETA_DFSMT, dfsmt, MVNETA_NDFSMT); 1503 MVNETA_WRITE_FILTER(sc, MVNETA_DFOMT, dfomt, MVNETA_NDFOMT); 1504 } 1505 1506 struct mvneta_dmamem * 1507 mvneta_dmamem_alloc(struct mvneta_softc *sc, bus_size_t size, bus_size_t align) 1508 { 1509 struct mvneta_dmamem *mdm; 1510 int nsegs; 1511 1512 mdm = malloc(sizeof(*mdm), M_DEVBUF, M_WAITOK | M_ZERO); 1513 mdm->mdm_size = size; 1514 1515 if (bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 1516 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, &mdm->mdm_map) != 0) 1517 goto mdmfree; 1518 1519 if (bus_dmamem_alloc(sc->sc_dmat, size, align, 0, &mdm->mdm_seg, 1, 1520 &nsegs, BUS_DMA_WAITOK) != 0) 1521 goto destroy; 1522 1523 if (bus_dmamem_map(sc->sc_dmat, &mdm->mdm_seg, nsegs, size, 1524 &mdm->mdm_kva, BUS_DMA_WAITOK|BUS_DMA_COHERENT) != 0) 1525 goto free; 1526 1527 if (bus_dmamap_load(sc->sc_dmat, mdm->mdm_map, mdm->mdm_kva, size, 1528 NULL, BUS_DMA_WAITOK) != 0) 1529 goto unmap; 1530 1531 bzero(mdm->mdm_kva, size); 1532 1533 return (mdm); 1534 1535 unmap: 1536 bus_dmamem_unmap(sc->sc_dmat, mdm->mdm_kva, size); 1537 free: 1538 bus_dmamem_free(sc->sc_dmat, &mdm->mdm_seg, 1); 1539 destroy: 1540 bus_dmamap_destroy(sc->sc_dmat, mdm->mdm_map); 1541 mdmfree: 1542 free(mdm, M_DEVBUF, 0); 1543 1544 return (NULL); 1545 } 1546 1547 void 1548 mvneta_dmamem_free(struct mvneta_softc *sc, struct mvneta_dmamem *mdm) 1549 { 1550 bus_dmamem_unmap(sc->sc_dmat, mdm->mdm_kva, mdm->mdm_size); 1551 bus_dmamem_free(sc->sc_dmat, &mdm->mdm_seg, 1); 1552 bus_dmamap_destroy(sc->sc_dmat, mdm->mdm_map); 1553 free(mdm, M_DEVBUF, 0); 1554 } 1555 1556 struct mbuf * 1557 mvneta_alloc_mbuf(struct mvneta_softc *sc, bus_dmamap_t map) 1558 { 1559 struct mbuf *m = NULL; 1560 1561 m = MCLGETI(NULL, M_DONTWAIT, NULL, MCLBYTES); 1562 if (!m) 1563 return (NULL); 1564 m->m_len = m->m_pkthdr.len = MCLBYTES; 1565 1566 if (bus_dmamap_load_mbuf(sc->sc_dmat, map, m, BUS_DMA_NOWAIT) != 0) { 1567 printf("%s: could not load mbuf DMA map", sc->sc_dev.dv_xname); 1568 m_freem(m); 1569 return (NULL); 1570 } 1571 1572 bus_dmamap_sync(sc->sc_dmat, map, 0, 1573 m->m_pkthdr.len, BUS_DMASYNC_PREREAD); 1574 1575 return (m); 1576 } 1577 1578 void 1579 mvneta_fill_rx_ring(struct mvneta_softc *sc) 1580 { 1581 struct mvneta_rx_desc *rxd; 1582 struct mvneta_buf *rxb; 1583 u_int slots; 1584 1585 for (slots = if_rxr_get(&sc->sc_rx_ring, MVNETA_RX_RING_CNT); 1586 slots > 0; slots--) { 1587 rxb = &sc->sc_rxbuf[sc->sc_rx_prod]; 1588 rxb->tb_m = mvneta_alloc_mbuf(sc, rxb->tb_map); 1589 if (rxb->tb_m == NULL) 1590 break; 1591 1592 rxd = &sc->sc_rxdesc[sc->sc_rx_prod]; 1593 memset(rxd, 0, sizeof(*rxd)); 1594 rxd->bufptr = rxb->tb_map->dm_segs[0].ds_addr; 1595 1596 bus_dmamap_sync(sc->sc_dmat, MVNETA_DMA_MAP(sc->sc_rxring), 1597 sc->sc_rx_prod * sizeof(*rxd), sizeof(*rxd), 1598 BUS_DMASYNC_PREWRITE); 1599 1600 sc->sc_rx_prod = MVNETA_RX_RING_NEXT(sc->sc_rx_prod); 1601 1602 /* Tell him that there's a new free desc. */ 1603 MVNETA_WRITE(sc, MVNETA_PRXSU(0), 1604 MVNETA_PRXSU_NOOFNEWDESCRIPTORS(1)); 1605 } 1606 1607 if_rxr_put(&sc->sc_rx_ring, slots); 1608 } 1609