1 /* $OpenBSD: if_mvneta.c,v 1.6 2018/08/06 10:52:30 patrick Exp $ */ 2 /* $NetBSD: if_mvneta.c,v 1.41 2015/04/15 10:15:40 hsuenaga Exp $ */ 3 /* 4 * Copyright (c) 2007, 2008, 2013 KIYOHARA Takashi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 25 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include "bpfilter.h" 30 31 #include <sys/param.h> 32 #include <sys/device.h> 33 #include <sys/systm.h> 34 #include <sys/endian.h> 35 #include <sys/errno.h> 36 #include <sys/kernel.h> 37 #include <sys/mutex.h> 38 #include <sys/socket.h> 39 #include <sys/sockio.h> 40 #include <uvm/uvm_extern.h> 41 #include <sys/mbuf.h> 42 43 #include <machine/bus.h> 44 #include <machine/fdt.h> 45 46 #include <dev/ofw/openfirm.h> 47 #include <dev/ofw/ofw_clock.h> 48 #include <dev/ofw/ofw_pinctrl.h> 49 #include <dev/ofw/fdt.h> 50 51 #include <dev/fdt/if_mvnetareg.h> 52 #include <dev/fdt/mvmdiovar.h> 53 54 #ifdef __armv7__ 55 #include <armv7/marvell/mvmbusvar.h> 56 #endif 57 58 #include <net/if.h> 59 #include <net/if_media.h> 60 #include <net/if_types.h> 61 62 #include <net/bpf.h> 63 64 #include <netinet/in.h> 65 #include <netinet/if_ether.h> 66 67 #include <dev/mii/mii.h> 68 #include <dev/mii/miivar.h> 69 70 #if NBPFILTER > 0 71 #include <net/bpf.h> 72 #endif 73 74 #ifdef MVNETA_DEBUG 75 #define DPRINTF(x) if (mvneta_debug) printf x 76 #define DPRINTFN(n,x) if (mvneta_debug >= (n)) printf x 77 int mvneta_debug = MVNETA_DEBUG; 78 #else 79 #define DPRINTF(x) 80 #define DPRINTFN(n,x) 81 #endif 82 83 #define MVNETA_READ(sc, reg) \ 84 bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)) 85 #define MVNETA_WRITE(sc, reg, val) \ 86 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 87 #define MVNETA_READ_FILTER(sc, reg, val, c) \ 88 bus_space_read_region_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val), (c)) 89 #define MVNETA_WRITE_FILTER(sc, reg, val, c) \ 90 bus_space_write_region_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val), (c)) 91 92 #define MVNETA_LINKUP_READ(sc) \ 93 MVNETA_READ(sc, MVNETA_PS0) 94 #define MVNETA_IS_LINKUP(sc) (MVNETA_LINKUP_READ(sc) & MVNETA_PS0_LINKUP) 95 96 #define MVNETA_TX_RING_CNT 256 97 #define MVNETA_TX_RING_MSK (MVNETA_TX_RING_CNT - 1) 98 #define MVNETA_TX_RING_NEXT(x) (((x) + 1) & MVNETA_TX_RING_MSK) 99 #define MVNETA_TX_QUEUE_CNT 1 100 #define MVNETA_RX_RING_CNT 256 101 #define MVNETA_RX_RING_MSK (MVNETA_RX_RING_CNT - 1) 102 #define MVNETA_RX_RING_NEXT(x) (((x) + 1) & MVNETA_RX_RING_MSK) 103 #define MVNETA_RX_QUEUE_CNT 1 104 105 CTASSERT(MVNETA_TX_RING_CNT > 1 && MVNETA_TX_RING_NEXT(MVNETA_TX_RING_CNT) == 106 (MVNETA_TX_RING_CNT + 1) % MVNETA_TX_RING_CNT); 107 CTASSERT(MVNETA_RX_RING_CNT > 1 && MVNETA_RX_RING_NEXT(MVNETA_RX_RING_CNT) == 108 (MVNETA_RX_RING_CNT + 1) % MVNETA_RX_RING_CNT); 109 110 #define MVNETA_NTXSEG 30 111 112 struct mvneta_dmamem { 113 bus_dmamap_t mdm_map; 114 bus_dma_segment_t mdm_seg; 115 size_t mdm_size; 116 caddr_t mdm_kva; 117 }; 118 #define MVNETA_DMA_MAP(_mdm) ((_mdm)->mdm_map) 119 #define MVNETA_DMA_LEN(_mdm) ((_mdm)->mdm_size) 120 #define MVNETA_DMA_DVA(_mdm) ((_mdm)->mdm_map->dm_segs[0].ds_addr) 121 #define MVNETA_DMA_KVA(_mdm) ((void *)(_mdm)->mdm_kva) 122 123 struct mvneta_buf { 124 bus_dmamap_t tb_map; 125 struct mbuf *tb_m; 126 }; 127 128 struct mvneta_softc { 129 struct device sc_dev; 130 struct device *sc_mdio; 131 132 bus_space_tag_t sc_iot; 133 bus_space_handle_t sc_ioh; 134 bus_dma_tag_t sc_dmat; 135 136 struct arpcom sc_ac; 137 #define sc_enaddr sc_ac.ac_enaddr 138 struct mii_data sc_mii; 139 #define sc_media sc_mii.mii_media 140 141 struct timeout sc_tick_ch; 142 143 struct mvneta_dmamem *sc_txring; 144 struct mvneta_buf *sc_txbuf; 145 struct mvneta_tx_desc *sc_txdesc; 146 int sc_tx_prod; /* next free tx desc */ 147 int sc_tx_cnt; /* amount of tx sent */ 148 int sc_tx_cons; /* first tx desc sent */ 149 150 struct mvneta_dmamem *sc_rxring; 151 struct mvneta_buf *sc_rxbuf; 152 struct mvneta_rx_desc *sc_rxdesc; 153 int sc_rx_prod; /* next rx desc to fill */ 154 struct if_rxring sc_rx_ring; 155 int sc_rx_cons; /* next rx desc recvd */ 156 157 enum { 158 PHY_MODE_QSGMII, 159 PHY_MODE_SGMII, 160 PHY_MODE_RGMII, 161 PHY_MODE_RGMII_ID, 162 } sc_phy_mode; 163 int sc_fixed_link; 164 int sc_inband_status; 165 int sc_phy; 166 int sc_link; 167 }; 168 169 170 int mvneta_miibus_readreg(struct device *, int, int); 171 void mvneta_miibus_writereg(struct device *, int, int, int); 172 void mvneta_miibus_statchg(struct device *); 173 174 void mvneta_wininit(struct mvneta_softc *); 175 176 /* Gigabit Ethernet Port part functions */ 177 int mvneta_match(struct device *, void *, void *); 178 void mvneta_attach(struct device *, struct device *, void *); 179 void mvneta_attach_deferred(struct device *); 180 181 void mvneta_tick(void *); 182 int mvneta_intr(void *); 183 184 void mvneta_start(struct ifnet *); 185 int mvneta_ioctl(struct ifnet *, u_long, caddr_t); 186 void mvneta_inband_statchg(struct mvneta_softc *); 187 void mvneta_port_change(struct mvneta_softc *); 188 void mvneta_port_up(struct mvneta_softc *); 189 int mvneta_up(struct mvneta_softc *); 190 void mvneta_down(struct mvneta_softc *); 191 void mvneta_watchdog(struct ifnet *); 192 193 int mvneta_mediachange(struct ifnet *); 194 void mvneta_mediastatus(struct ifnet *, struct ifmediareq *); 195 196 int mvneta_encap(struct mvneta_softc *, struct mbuf *, uint32_t *); 197 void mvneta_rx_proc(struct mvneta_softc *); 198 void mvneta_tx_proc(struct mvneta_softc *); 199 uint8_t mvneta_crc8(const uint8_t *, size_t); 200 void mvneta_iff(struct mvneta_softc *); 201 202 struct mvneta_dmamem *mvneta_dmamem_alloc(struct mvneta_softc *, 203 bus_size_t, bus_size_t); 204 void mvneta_dmamem_free(struct mvneta_softc *, struct mvneta_dmamem *); 205 void mvneta_fill_rx_ring(struct mvneta_softc *); 206 207 struct cfdriver mvneta_cd = { 208 NULL, "mvneta", DV_IFNET 209 }; 210 211 struct cfattach mvneta_ca = { 212 sizeof (struct mvneta_softc), mvneta_match, mvneta_attach, 213 }; 214 215 int 216 mvneta_miibus_readreg(struct device *dev, int phy, int reg) 217 { 218 struct mvneta_softc *sc = (struct mvneta_softc *) dev; 219 return mvmdio_miibus_readreg(sc->sc_mdio, phy, reg); 220 } 221 222 void 223 mvneta_miibus_writereg(struct device *dev, int phy, int reg, int val) 224 { 225 struct mvneta_softc *sc = (struct mvneta_softc *) dev; 226 return mvmdio_miibus_writereg(sc->sc_mdio, phy, reg, val); 227 } 228 229 void 230 mvneta_miibus_statchg(struct device *self) 231 { 232 struct mvneta_softc *sc = (struct mvneta_softc *)self; 233 234 if (sc->sc_mii.mii_media_status & IFM_ACTIVE) { 235 uint32_t panc = MVNETA_READ(sc, MVNETA_PANC); 236 237 panc &= ~(MVNETA_PANC_SETMIISPEED | 238 MVNETA_PANC_SETGMIISPEED | 239 MVNETA_PANC_SETFULLDX); 240 241 switch (IFM_SUBTYPE(sc->sc_mii.mii_media_active)) { 242 case IFM_1000_SX: 243 case IFM_1000_LX: 244 case IFM_1000_CX: 245 case IFM_1000_T: 246 panc |= MVNETA_PANC_SETGMIISPEED; 247 break; 248 case IFM_100_TX: 249 panc |= MVNETA_PANC_SETMIISPEED; 250 break; 251 case IFM_10_T: 252 break; 253 } 254 255 if ((sc->sc_mii.mii_media_active & IFM_GMASK) == IFM_FDX) 256 panc |= MVNETA_PANC_SETFULLDX; 257 258 MVNETA_WRITE(sc, MVNETA_PANC, panc); 259 } 260 261 mvneta_port_change(sc); 262 } 263 264 void 265 mvneta_inband_statchg(struct mvneta_softc *sc) 266 { 267 uint32_t reg; 268 269 sc->sc_mii.mii_media_status = IFM_AVALID; 270 sc->sc_mii.mii_media_active = IFM_ETHER; 271 272 reg = MVNETA_READ(sc, MVNETA_PS0); 273 if (reg & MVNETA_PS0_LINKUP) 274 sc->sc_mii.mii_media_status |= IFM_ACTIVE; 275 if (reg & MVNETA_PS0_GMIISPEED) 276 sc->sc_mii.mii_media_active |= IFM_1000_T; 277 else if (reg & MVNETA_PS0_MIISPEED) 278 sc->sc_mii.mii_media_active |= IFM_100_TX; 279 else 280 sc->sc_mii.mii_media_active |= IFM_10_T; 281 if (reg & MVNETA_PS0_FULLDX) 282 sc->sc_mii.mii_media_active |= IFM_FDX; 283 284 mvneta_port_change(sc); 285 } 286 287 void 288 mvneta_enaddr_write(struct mvneta_softc *sc) 289 { 290 uint32_t maddrh, maddrl; 291 maddrh = sc->sc_enaddr[0] << 24; 292 maddrh |= sc->sc_enaddr[1] << 16; 293 maddrh |= sc->sc_enaddr[2] << 8; 294 maddrh |= sc->sc_enaddr[3]; 295 maddrl = sc->sc_enaddr[4] << 8; 296 maddrl |= sc->sc_enaddr[5]; 297 MVNETA_WRITE(sc, MVNETA_MACAH, maddrh); 298 MVNETA_WRITE(sc, MVNETA_MACAL, maddrl); 299 } 300 301 void 302 mvneta_wininit(struct mvneta_softc *sc) 303 { 304 #ifdef __armv7__ 305 uint32_t en; 306 int i; 307 308 if (mvmbus_dram_info == NULL) 309 panic("%s: mbus dram information not set up", 310 sc->sc_dev.dv_xname); 311 312 for (i = 0; i < MVNETA_NWINDOW; i++) { 313 MVNETA_WRITE(sc, MVNETA_BASEADDR(i), 0); 314 MVNETA_WRITE(sc, MVNETA_S(i), 0); 315 316 if (i < MVNETA_NREMAP) 317 MVNETA_WRITE(sc, MVNETA_HA(i), 0); 318 } 319 320 en = MVNETA_BARE_EN_MASK; 321 322 for (i = 0; i < mvmbus_dram_info->numcs; i++) { 323 struct mbus_dram_window *win = &mvmbus_dram_info->cs[i]; 324 325 MVNETA_WRITE(sc, MVNETA_BASEADDR(i), 326 MVNETA_BASEADDR_TARGET(mvmbus_dram_info->targetid) | 327 MVNETA_BASEADDR_ATTR(win->attr) | 328 MVNETA_BASEADDR_BASE(win->base)); 329 MVNETA_WRITE(sc, MVNETA_S(i), MVNETA_S_SIZE(win->size)); 330 331 en &= ~(1 << i); 332 } 333 334 MVNETA_WRITE(sc, MVNETA_BARE, en); 335 #endif 336 } 337 338 int 339 mvneta_match(struct device *parent, void *cfdata, void *aux) 340 { 341 struct fdt_attach_args *faa = aux; 342 343 return OF_is_compatible(faa->fa_node, "marvell,armada-370-neta"); 344 } 345 346 void 347 mvneta_attach(struct device *parent, struct device *self, void *aux) 348 { 349 struct mvneta_softc *sc = (struct mvneta_softc *) self; 350 struct fdt_attach_args *faa = aux; 351 uint32_t ctl0, ctl2, panc; 352 struct ifnet *ifp; 353 int i, len, node; 354 char *phy_mode; 355 char *managed; 356 357 printf("\n"); 358 359 sc->sc_iot = faa->fa_iot; 360 timeout_set(&sc->sc_tick_ch, mvneta_tick, sc); 361 if (bus_space_map(sc->sc_iot, faa->fa_reg[0].addr, 362 faa->fa_reg[0].size, 0, &sc->sc_ioh)) { 363 printf("%s: cannot map registers\n", self->dv_xname); 364 return; 365 } 366 sc->sc_dmat = faa->fa_dmat; 367 368 clock_enable(faa->fa_node, NULL); 369 370 pinctrl_byname(faa->fa_node, "default"); 371 372 len = OF_getproplen(faa->fa_node, "phy-mode"); 373 if (len <= 0) { 374 printf("%s: cannot extract phy-mode\n", self->dv_xname); 375 return; 376 } 377 378 phy_mode = malloc(len, M_TEMP, M_WAITOK); 379 OF_getprop(faa->fa_node, "phy-mode", phy_mode, len); 380 if (!strncmp(phy_mode, "qsgmii", strlen("qsgmii"))) 381 sc->sc_phy_mode = PHY_MODE_QSGMII; 382 else if (!strncmp(phy_mode, "sgmii", strlen("sgmii"))) 383 sc->sc_phy_mode = PHY_MODE_SGMII; 384 else if (!strncmp(phy_mode, "rgmii-id", strlen("rgmii-id"))) 385 sc->sc_phy_mode = PHY_MODE_RGMII_ID; 386 else if (!strncmp(phy_mode, "rgmii", strlen("rgmii"))) 387 sc->sc_phy_mode = PHY_MODE_RGMII; 388 else { 389 printf("%s: cannot use phy-mode %s\n", self->dv_xname, 390 phy_mode); 391 return; 392 } 393 free(phy_mode, M_TEMP, len); 394 395 /* TODO: check child's name to be "fixed-link" */ 396 if (OF_getproplen(faa->fa_node, "fixed-link") >= 0 || 397 OF_child(faa->fa_node)) 398 sc->sc_fixed_link = 1; 399 400 if ((len = OF_getproplen(faa->fa_node, "managed")) >= 0) { 401 managed = malloc(len, M_TEMP, M_WAITOK); 402 OF_getprop(faa->fa_node, "managed", managed, len); 403 if (!strncmp(managed, "in-band-status", 404 strlen("in-band-status"))) { 405 sc->sc_fixed_link = 1; 406 sc->sc_inband_status = 1; 407 } 408 free(managed, M_TEMP, len); 409 } 410 411 if (!sc->sc_fixed_link) { 412 node = OF_getnodebyphandle(OF_getpropint(faa->fa_node, 413 "phy", 0)); 414 if (!node) { 415 printf("%s: cannot find phy in fdt\n", self->dv_xname); 416 return; 417 } 418 419 if ((sc->sc_phy = OF_getpropint(node, "reg", -1)) == -1) { 420 printf("%s: cannot extract phy addr\n", self->dv_xname); 421 return; 422 } 423 } 424 425 mvneta_wininit(sc); 426 427 if (OF_getproplen(faa->fa_node, "local-mac-address") == 428 ETHER_ADDR_LEN) { 429 OF_getprop(faa->fa_node, "local-mac-address", 430 sc->sc_enaddr, ETHER_ADDR_LEN); 431 mvneta_enaddr_write(sc); 432 } else { 433 uint32_t maddrh, maddrl; 434 maddrh = MVNETA_READ(sc, MVNETA_MACAH); 435 maddrl = MVNETA_READ(sc, MVNETA_MACAL); 436 if (maddrh || maddrl) { 437 sc->sc_enaddr[0] = maddrh >> 24; 438 sc->sc_enaddr[1] = maddrh >> 16; 439 sc->sc_enaddr[2] = maddrh >> 8; 440 sc->sc_enaddr[3] = maddrh >> 0; 441 sc->sc_enaddr[4] = maddrl >> 8; 442 sc->sc_enaddr[5] = maddrl >> 0; 443 } else 444 ether_fakeaddr(&sc->sc_ac.ac_if); 445 } 446 447 printf("%s: Ethernet address %s\n", self->dv_xname, 448 ether_sprintf(sc->sc_enaddr)); 449 450 /* disable port */ 451 MVNETA_WRITE(sc, MVNETA_PMACC0, 452 MVNETA_READ(sc, MVNETA_PMACC0) & ~MVNETA_PMACC0_PORTEN); 453 delay(200); 454 455 /* clear all cause registers */ 456 MVNETA_WRITE(sc, MVNETA_PRXTXTIC, 0); 457 MVNETA_WRITE(sc, MVNETA_PRXTXIC, 0); 458 MVNETA_WRITE(sc, MVNETA_PMIC, 0); 459 460 /* mask all interrupts */ 461 MVNETA_WRITE(sc, MVNETA_PRXTXTIM, MVNETA_PRXTXTI_PMISCICSUMMARY); 462 MVNETA_WRITE(sc, MVNETA_PRXTXIM, 0); 463 MVNETA_WRITE(sc, MVNETA_PMIM, MVNETA_PMI_PHYSTATUSCHNG | 464 MVNETA_PMI_LINKCHANGE | MVNETA_PMI_PSCSYNCCHNG); 465 MVNETA_WRITE(sc, MVNETA_PIE, 0); 466 467 /* enable MBUS Retry bit16 */ 468 MVNETA_WRITE(sc, MVNETA_ERETRY, 0x20); 469 470 /* enable access for CPU0 */ 471 MVNETA_WRITE(sc, MVNETA_PCP2Q(0), 472 MVNETA_PCP2Q_RXQAE_ALL | MVNETA_PCP2Q_TXQAE_ALL); 473 474 /* reset RX and TX DMAs */ 475 MVNETA_WRITE(sc, MVNETA_PRXINIT, MVNETA_PRXINIT_RXDMAINIT); 476 MVNETA_WRITE(sc, MVNETA_PTXINIT, MVNETA_PTXINIT_TXDMAINIT); 477 478 /* disable legacy WRR, disable EJP, release from reset */ 479 MVNETA_WRITE(sc, MVNETA_TQC_1, 0); 480 for (i = 0; i < MVNETA_TX_QUEUE_CNT; i++) { 481 MVNETA_WRITE(sc, MVNETA_TQTBCOUNT(i), 0); 482 MVNETA_WRITE(sc, MVNETA_TQTBCONFIG(i), 0); 483 } 484 485 MVNETA_WRITE(sc, MVNETA_PRXINIT, 0); 486 MVNETA_WRITE(sc, MVNETA_PTXINIT, 0); 487 488 /* set port acceleration mode */ 489 MVNETA_WRITE(sc, MVNETA_PACC, MVGVE_PACC_ACCELERATIONMODE_EDM); 490 491 MVNETA_WRITE(sc, MVNETA_PXC, MVNETA_PXC_AMNOTXES | MVNETA_PXC_RXCS); 492 MVNETA_WRITE(sc, MVNETA_PXCX, 0); 493 MVNETA_WRITE(sc, MVNETA_PMFS, 64); 494 495 /* Set SDC register except IPGINT bits */ 496 MVNETA_WRITE(sc, MVNETA_SDC, 497 MVNETA_SDC_RXBSZ_16_64BITWORDS | 498 MVNETA_SDC_BLMR | /* Big/Little Endian Receive Mode: No swap */ 499 MVNETA_SDC_BLMT | /* Big/Little Endian Transmit Mode: No swap */ 500 MVNETA_SDC_TXBSZ_16_64BITWORDS); 501 502 /* XXX: Disable PHY polling in hardware */ 503 MVNETA_WRITE(sc, MVNETA_EUC, 504 MVNETA_READ(sc, MVNETA_EUC) & ~MVNETA_EUC_POLLING); 505 506 /* clear uni-/multicast tables */ 507 uint32_t dfut[MVNETA_NDFUT], dfsmt[MVNETA_NDFSMT], dfomt[MVNETA_NDFOMT]; 508 memset(dfut, 0, sizeof(dfut)); 509 memset(dfsmt, 0, sizeof(dfut)); 510 memset(dfomt, 0, sizeof(dfut)); 511 MVNETA_WRITE_FILTER(sc, MVNETA_DFUT, dfut, MVNETA_NDFUT); 512 MVNETA_WRITE_FILTER(sc, MVNETA_DFSMT, dfut, MVNETA_NDFSMT); 513 MVNETA_WRITE_FILTER(sc, MVNETA_DFOMT, dfut, MVNETA_NDFOMT); 514 515 MVNETA_WRITE(sc, MVNETA_PIE, 516 MVNETA_PIE_RXPKTINTRPTENB_ALL | MVNETA_PIE_TXPKTINTRPTENB_ALL); 517 518 MVNETA_WRITE(sc, MVNETA_EUIC, 0); 519 520 /* Setup phy. */ 521 ctl0 = MVNETA_READ(sc, MVNETA_PMACC0); 522 ctl2 = MVNETA_READ(sc, MVNETA_PMACC2); 523 panc = MVNETA_READ(sc, MVNETA_PANC); 524 525 /* Force link down to change in-band settings. */ 526 panc &= ~MVNETA_PANC_FORCELINKPASS; 527 panc |= MVNETA_PANC_FORCELINKFAIL; 528 MVNETA_WRITE(sc, MVNETA_PANC, panc); 529 530 ctl0 &= ~MVNETA_PMACC0_PORTTYPE; 531 ctl2 &= ~(MVNETA_PMACC2_PORTMACRESET | MVNETA_PMACC2_INBANDAN); 532 panc &= ~(MVNETA_PANC_INBANDANEN | MVNETA_PANC_INBANDRESTARTAN | 533 MVNETA_PANC_SETMIISPEED | MVNETA_PANC_SETGMIISPEED | 534 MVNETA_PANC_ANSPEEDEN | MVNETA_PANC_SETFCEN | 535 MVNETA_PANC_PAUSEADV | MVNETA_PANC_ANFCEN | 536 MVNETA_PANC_SETFULLDX | MVNETA_PANC_ANDUPLEXEN); 537 538 ctl2 |= MVNETA_PMACC2_RGMIIEN; 539 switch (sc->sc_phy_mode) { 540 case PHY_MODE_QSGMII: 541 MVNETA_WRITE(sc, MVNETA_SERDESCFG, 542 MVNETA_SERDESCFG_QSGMII_PROTO); 543 ctl2 |= MVNETA_PMACC2_PCSEN; 544 break; 545 case PHY_MODE_SGMII: 546 MVNETA_WRITE(sc, MVNETA_SERDESCFG, 547 MVNETA_SERDESCFG_SGMII_PROTO); 548 ctl2 |= MVNETA_PMACC2_PCSEN; 549 break; 550 default: 551 break; 552 } 553 554 /* Use Auto-Negotiation for Inband Status only */ 555 if (sc->sc_inband_status) { 556 panc &= ~(MVNETA_PANC_FORCELINKFAIL | 557 MVNETA_PANC_FORCELINKPASS); 558 /* TODO: read mode from SFP */ 559 if (1) { 560 /* 802.3z */ 561 ctl0 |= MVNETA_PMACC0_PORTTYPE; 562 panc |= (MVNETA_PANC_INBANDANEN | 563 MVNETA_PANC_SETGMIISPEED | 564 MVNETA_PANC_SETFULLDX); 565 } else { 566 /* SGMII */ 567 ctl2 |= MVNETA_PMACC2_INBANDAN; 568 panc |= (MVNETA_PANC_INBANDANEN | 569 MVNETA_PANC_ANSPEEDEN | 570 MVNETA_PANC_ANDUPLEXEN); 571 } 572 MVNETA_WRITE(sc, MVNETA_OMSCD, 573 MVNETA_READ(sc, MVNETA_OMSCD) | MVNETA_OMSCD_1MS_CLOCK_ENABLE); 574 } else { 575 MVNETA_WRITE(sc, MVNETA_OMSCD, 576 MVNETA_READ(sc, MVNETA_OMSCD) & ~MVNETA_OMSCD_1MS_CLOCK_ENABLE); 577 } 578 579 MVNETA_WRITE(sc, MVNETA_PMACC0, ctl0); 580 MVNETA_WRITE(sc, MVNETA_PMACC2, ctl2); 581 MVNETA_WRITE(sc, MVNETA_PANC, panc); 582 583 /* Port reset */ 584 while (MVNETA_READ(sc, MVNETA_PMACC2) & MVNETA_PMACC2_PORTMACRESET) 585 ; 586 587 fdt_intr_establish(faa->fa_node, IPL_NET, mvneta_intr, sc, 588 sc->sc_dev.dv_xname); 589 590 ifp = &sc->sc_ac.ac_if; 591 ifp->if_softc = sc; 592 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 593 ifp->if_start = mvneta_start; 594 ifp->if_ioctl = mvneta_ioctl; 595 ifp->if_watchdog = mvneta_watchdog; 596 ifp->if_capabilities = IFCAP_VLAN_MTU; 597 598 #if notyet 599 /* 600 * We can do IPv4/TCPv4/UDPv4 checksums in hardware. 601 */ 602 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 603 IFCAP_CSUM_UDPv4; 604 605 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 606 /* 607 * But, IPv6 packets in the stream can cause incorrect TCPv4 Tx sums. 608 */ 609 ifp->if_capabilities &= ~IFCAP_CSUM_TCPv4; 610 #endif 611 612 IFQ_SET_MAXLEN(&ifp->if_snd, max(MVNETA_TX_RING_CNT - 1, IFQ_MAXLEN)); 613 strlcpy(ifp->if_xname, sc->sc_dev.dv_xname, sizeof(ifp->if_xname)); 614 615 /* 616 * Do MII setup. 617 */ 618 sc->sc_mii.mii_ifp = ifp; 619 sc->sc_mii.mii_readreg = mvneta_miibus_readreg; 620 sc->sc_mii.mii_writereg = mvneta_miibus_writereg; 621 sc->sc_mii.mii_statchg = mvneta_miibus_statchg; 622 623 ifmedia_init(&sc->sc_mii.mii_media, 0, 624 mvneta_mediachange, mvneta_mediastatus); 625 626 if (!sc->sc_fixed_link) { 627 extern void *mvmdio_sc; 628 sc->sc_mdio = mvmdio_sc; 629 630 if (sc->sc_mdio == NULL) { 631 config_defer(self, mvneta_attach_deferred); 632 return; 633 } 634 635 mii_attach(self, &sc->sc_mii, 0xffffffff, sc->sc_phy, 636 MII_OFFSET_ANY, 0); 637 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 638 printf("%s: no PHY found!\n", self->dv_xname); 639 ifmedia_add(&sc->sc_mii.mii_media, 640 IFM_ETHER|IFM_MANUAL, 0, NULL); 641 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 642 } else 643 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 644 } else { 645 ifmedia_add(&sc->sc_mii.mii_media, 646 IFM_ETHER|IFM_MANUAL, 0, NULL); 647 ifmedia_set(&sc->sc_mii.mii_media, 648 IFM_ETHER|IFM_MANUAL); 649 650 if (sc->sc_inband_status) { 651 mvneta_inband_statchg(sc); 652 } else { 653 sc->sc_mii.mii_media_status = IFM_AVALID|IFM_ACTIVE; 654 sc->sc_mii.mii_media_active = IFM_ETHER|IFM_1000_T|IFM_FDX; 655 mvneta_miibus_statchg(self); 656 } 657 658 ifp->if_baudrate = ifmedia_baudrate(sc->sc_mii.mii_media_active); 659 ifp->if_link_state = LINK_STATE_FULL_DUPLEX; 660 } 661 662 /* 663 * Call MI attach routines. 664 */ 665 if_attach(ifp); 666 ether_ifattach(ifp); 667 668 return; 669 } 670 671 void 672 mvneta_attach_deferred(struct device *self) 673 { 674 struct mvneta_softc *sc = (struct mvneta_softc *) self; 675 struct ifnet *ifp = &sc->sc_ac.ac_if; 676 677 extern void *mvmdio_sc; 678 sc->sc_mdio = mvmdio_sc; 679 if (sc->sc_mdio == NULL) { 680 printf("%s: mdio bus not yet attached\n", self->dv_xname); 681 return; 682 } 683 684 mii_attach(self, &sc->sc_mii, 0xffffffff, sc->sc_phy, 685 MII_OFFSET_ANY, 0); 686 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 687 printf("%s: no PHY found!\n", self->dv_xname); 688 ifmedia_add(&sc->sc_mii.mii_media, 689 IFM_ETHER|IFM_MANUAL, 0, NULL); 690 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 691 } else 692 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 693 694 /* 695 * Call MI attach routines. 696 */ 697 if_attach(ifp); 698 ether_ifattach(ifp); 699 700 return; 701 } 702 703 void 704 mvneta_tick(void *arg) 705 { 706 struct mvneta_softc *sc = arg; 707 struct mii_data *mii = &sc->sc_mii; 708 int s; 709 710 s = splnet(); 711 mii_tick(mii); 712 splx(s); 713 714 timeout_add_sec(&sc->sc_tick_ch, 1); 715 } 716 717 int 718 mvneta_intr(void *arg) 719 { 720 struct mvneta_softc *sc = arg; 721 struct ifnet *ifp = &sc->sc_ac.ac_if; 722 uint32_t ic, misc; 723 724 ic = MVNETA_READ(sc, MVNETA_PRXTXTIC); 725 726 if (ic & MVNETA_PRXTXTI_PMISCICSUMMARY) { 727 misc = MVNETA_READ(sc, MVNETA_PMIC); 728 MVNETA_WRITE(sc, MVNETA_PMIC, 0); 729 if (sc->sc_inband_status && (misc & 730 (MVNETA_PMI_PHYSTATUSCHNG | 731 MVNETA_PMI_LINKCHANGE | 732 MVNETA_PMI_PSCSYNCCHNG))) { 733 mvneta_inband_statchg(sc); 734 } 735 } 736 737 if (!(ifp->if_flags & IFF_RUNNING)) 738 return 1; 739 740 if (ic & MVNETA_PRXTXTI_TBTCQ(0)) 741 mvneta_tx_proc(sc); 742 743 if (ic & MVNETA_PRXTXTI_RBICTAPQ(0)) 744 mvneta_rx_proc(sc); 745 746 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 747 mvneta_start(ifp); 748 749 return 1; 750 } 751 752 void 753 mvneta_start(struct ifnet *ifp) 754 { 755 struct mvneta_softc *sc = ifp->if_softc; 756 struct mbuf *m_head = NULL; 757 int idx; 758 759 DPRINTFN(3, ("mvneta_start (idx %d)\n", sc->sc_tx_prod)); 760 761 if (!(ifp->if_flags & IFF_RUNNING)) 762 return; 763 if (ifq_is_oactive(&ifp->if_snd)) 764 return; 765 if (IFQ_IS_EMPTY(&ifp->if_snd)) 766 return; 767 768 /* If Link is DOWN, can't start TX */ 769 if (!MVNETA_IS_LINKUP(sc)) 770 return; 771 772 bus_dmamap_sync(sc->sc_dmat, MVNETA_DMA_MAP(sc->sc_txring), 0, 773 MVNETA_DMA_LEN(sc->sc_txring), 774 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 775 776 idx = sc->sc_tx_prod; 777 while (sc->sc_tx_cnt < MVNETA_TX_RING_CNT) { 778 m_head = ifq_deq_begin(&ifp->if_snd); 779 if (m_head == NULL) 780 break; 781 782 /* 783 * Pack the data into the transmit ring. If we 784 * don't have room, set the OACTIVE flag and wait 785 * for the NIC to drain the ring. 786 */ 787 if (mvneta_encap(sc, m_head, &idx)) { 788 ifq_deq_rollback(&ifp->if_snd, m_head); 789 ifq_set_oactive(&ifp->if_snd); 790 break; 791 } 792 793 /* now we are committed to transmit the packet */ 794 ifq_deq_commit(&ifp->if_snd, m_head); 795 796 /* 797 * If there's a BPF listener, bounce a copy of this frame 798 * to him. 799 */ 800 #if NBPFILTER > 0 801 if (ifp->if_bpf) 802 bpf_mtap(ifp->if_bpf, m_head, BPF_DIRECTION_OUT); 803 #endif 804 } 805 806 if (sc->sc_tx_prod != idx) { 807 sc->sc_tx_prod = idx; 808 809 /* 810 * Set a timeout in case the chip goes out to lunch. 811 */ 812 ifp->if_timer = 5; 813 } 814 } 815 816 int 817 mvneta_ioctl(struct ifnet *ifp, u_long cmd, caddr_t addr) 818 { 819 struct mvneta_softc *sc = ifp->if_softc; 820 struct ifreq *ifr = (struct ifreq *)addr; 821 int s, error = 0; 822 823 s = splnet(); 824 825 switch (cmd) { 826 case SIOCSIFADDR: 827 ifp->if_flags |= IFF_UP; 828 /* FALLTHROUGH */ 829 case SIOCSIFFLAGS: 830 if (ifp->if_flags & IFF_UP) { 831 if (ifp->if_flags & IFF_RUNNING) 832 error = ENETRESET; 833 else 834 mvneta_up(sc); 835 } else { 836 if (ifp->if_flags & IFF_RUNNING) 837 mvneta_down(sc); 838 } 839 break; 840 case SIOCGIFMEDIA: 841 case SIOCSIFMEDIA: 842 DPRINTFN(2, ("mvneta_ioctl MEDIA\n")); 843 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 844 break; 845 case SIOCGIFRXR: 846 error = if_rxr_ioctl((struct if_rxrinfo *)ifr->ifr_data, 847 NULL, MCLBYTES, &sc->sc_rx_ring); 848 break; 849 default: 850 DPRINTFN(2, ("mvneta_ioctl ETHER\n")); 851 error = ether_ioctl(ifp, &sc->sc_ac, cmd, addr); 852 break; 853 } 854 855 if (error == ENETRESET) { 856 if (ifp->if_flags & IFF_RUNNING) 857 mvneta_iff(sc); 858 error = 0; 859 } 860 861 splx(s); 862 863 return error; 864 } 865 866 void 867 mvneta_port_change(struct mvneta_softc *sc) 868 { 869 if (!!(sc->sc_mii.mii_media_status & IFM_ACTIVE) != sc->sc_link) { 870 sc->sc_link = !sc->sc_link; 871 872 if (sc->sc_link) { 873 if (!sc->sc_inband_status) { 874 uint32_t panc = MVNETA_READ(sc, MVNETA_PANC); 875 panc &= ~MVNETA_PANC_FORCELINKFAIL; 876 panc |= MVNETA_PANC_FORCELINKPASS; 877 MVNETA_WRITE(sc, MVNETA_PANC, panc); 878 } 879 mvneta_port_up(sc); 880 } else { 881 if (!sc->sc_inband_status) { 882 uint32_t panc = MVNETA_READ(sc, MVNETA_PANC); 883 panc &= ~MVNETA_PANC_FORCELINKPASS; 884 panc |= MVNETA_PANC_FORCELINKFAIL; 885 MVNETA_WRITE(sc, MVNETA_PANC, panc); 886 } 887 } 888 } 889 } 890 891 void 892 mvneta_port_up(struct mvneta_softc *sc) 893 { 894 /* Enable port RX/TX. */ 895 MVNETA_WRITE(sc, MVNETA_RQC, MVNETA_RQC_ENQ(0)); 896 MVNETA_WRITE(sc, MVNETA_TQC, MVNETA_TQC_ENQ(0)); 897 } 898 899 int 900 mvneta_up(struct mvneta_softc *sc) 901 { 902 struct ifnet *ifp = &sc->sc_ac.ac_if; 903 struct mvneta_buf *txb, *rxb; 904 int i; 905 906 DPRINTFN(2, ("mvneta_up\n")); 907 908 /* Allocate Tx descriptor ring. */ 909 sc->sc_txring = mvneta_dmamem_alloc(sc, 910 MVNETA_TX_RING_CNT * sizeof(struct mvneta_tx_desc), 32); 911 sc->sc_txdesc = MVNETA_DMA_KVA(sc->sc_txring); 912 913 sc->sc_txbuf = malloc(sizeof(struct mvneta_buf) * MVNETA_TX_RING_CNT, 914 M_DEVBUF, M_WAITOK); 915 916 for (i = 0; i < MVNETA_TX_RING_CNT; i++) { 917 txb = &sc->sc_txbuf[i]; 918 bus_dmamap_create(sc->sc_dmat, MCLBYTES, MVNETA_NTXSEG, 919 MCLBYTES, 0, BUS_DMA_WAITOK, &txb->tb_map); 920 txb->tb_m = NULL; 921 } 922 923 sc->sc_tx_prod = sc->sc_tx_cons = 0; 924 sc->sc_tx_cnt = 0; 925 926 /* Allocate Rx descriptor ring. */ 927 sc->sc_rxring = mvneta_dmamem_alloc(sc, 928 MVNETA_RX_RING_CNT * sizeof(struct mvneta_rx_desc), 32); 929 sc->sc_rxdesc = MVNETA_DMA_KVA(sc->sc_rxring); 930 931 sc->sc_rxbuf = malloc(sizeof(struct mvneta_buf) * MVNETA_RX_RING_CNT, 932 M_DEVBUF, M_WAITOK); 933 934 for (i = 0; i < MVNETA_RX_RING_CNT; i++) { 935 rxb = &sc->sc_rxbuf[i]; 936 bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 937 MCLBYTES, 0, BUS_DMA_WAITOK, &rxb->tb_map); 938 rxb->tb_m = NULL; 939 } 940 941 /* Set Rx descriptor ring data. */ 942 MVNETA_WRITE(sc, MVNETA_PRXDQA(0), MVNETA_DMA_DVA(sc->sc_rxring)); 943 MVNETA_WRITE(sc, MVNETA_PRXDQS(0), MVNETA_RX_RING_CNT | 944 ((MCLBYTES >> 3) << 19)); 945 MVNETA_WRITE(sc, MVNETA_PRXDQTH(0), 0); 946 MVNETA_WRITE(sc, MVNETA_PRXC(0), 0); 947 948 /* Set Tx queue bandwidth. */ 949 MVNETA_WRITE(sc, MVNETA_TQTBCOUNT(0), 0x03ffffff); 950 MVNETA_WRITE(sc, MVNETA_TQTBCONFIG(0), 0x03ffffff); 951 952 /* Set Tx descriptor ring data. */ 953 MVNETA_WRITE(sc, MVNETA_PTXDQA(0), MVNETA_DMA_DVA(sc->sc_txring)); 954 MVNETA_WRITE(sc, MVNETA_PTXDQS(0), 955 MVNETA_PTXDQS_DQS(MVNETA_TX_RING_CNT)); 956 957 sc->sc_rx_prod = sc->sc_rx_cons = 0; 958 959 if_rxr_init(&sc->sc_rx_ring, 2, MVNETA_RX_RING_CNT); 960 mvneta_fill_rx_ring(sc); 961 962 /* TODO: correct frame size */ 963 MVNETA_WRITE(sc, MVNETA_PMACC0, 964 (MVNETA_READ(sc, MVNETA_PMACC0) & MVNETA_PMACC0_PORTTYPE) | 965 MVNETA_PMACC0_FRAMESIZELIMIT(MCLBYTES - MVNETA_HWHEADER_SIZE)); 966 967 /* set max MTU */ 968 MVNETA_WRITE(sc, MVNETA_TXMTU, MVNETA_TXMTU_MAX); 969 MVNETA_WRITE(sc, MVNETA_TXTKSIZE, 0xffffffff); 970 MVNETA_WRITE(sc, MVNETA_TXQTKSIZE(0), 0x7fffffff); 971 972 /* enable port */ 973 MVNETA_WRITE(sc, MVNETA_PMACC0, 974 MVNETA_READ(sc, MVNETA_PMACC0) | MVNETA_PMACC0_PORTEN); 975 976 mvneta_enaddr_write(sc); 977 978 /* Program promiscuous mode and multicast filters. */ 979 mvneta_iff(sc); 980 981 if (!sc->sc_fixed_link) 982 mii_mediachg(&sc->sc_mii); 983 984 if (sc->sc_link) 985 mvneta_port_up(sc); 986 987 /* Enable interrupt masks */ 988 MVNETA_WRITE(sc, MVNETA_PRXTXTIM, MVNETA_PRXTXTI_RBICTAPQ(0) | 989 MVNETA_PRXTXTI_TBTCQ(0) | MVNETA_PRXTXTI_PMISCICSUMMARY); 990 MVNETA_WRITE(sc, MVNETA_PMIM, MVNETA_PMI_PHYSTATUSCHNG | 991 MVNETA_PMI_LINKCHANGE | MVNETA_PMI_PSCSYNCCHNG); 992 993 timeout_add_sec(&sc->sc_tick_ch, 1); 994 995 ifp->if_flags |= IFF_RUNNING; 996 ifq_clr_oactive(&ifp->if_snd); 997 998 return 0; 999 } 1000 1001 void 1002 mvneta_down(struct mvneta_softc *sc) 1003 { 1004 struct ifnet *ifp = &sc->sc_ac.ac_if; 1005 uint32_t reg, txinprog, txfifoemp; 1006 struct mvneta_buf *txb, *rxb; 1007 int i, cnt; 1008 1009 DPRINTFN(2, ("mvneta_down\n")); 1010 1011 timeout_del(&sc->sc_tick_ch); 1012 1013 /* Stop Rx port activity. Check port Rx activity. */ 1014 reg = MVNETA_READ(sc, MVNETA_RQC); 1015 if (reg & MVNETA_RQC_ENQ_MASK) 1016 /* Issue stop command for active channels only */ 1017 MVNETA_WRITE(sc, MVNETA_RQC, MVNETA_RQC_DISQ_DISABLE(reg)); 1018 1019 /* Stop Tx port activity. Check port Tx activity. */ 1020 if (MVNETA_READ(sc, MVNETA_TQC) & MVNETA_TQC_ENQ(0)) 1021 MVNETA_WRITE(sc, MVNETA_TQC, MVNETA_TQC_DISQ(0)); 1022 1023 txinprog = MVNETA_PS_TXINPROG_(0); 1024 txfifoemp = MVNETA_PS_TXFIFOEMP_(0); 1025 1026 #define RX_DISABLE_TIMEOUT 0x1000000 1027 #define TX_FIFO_EMPTY_TIMEOUT 0x1000000 1028 /* Wait for all Rx activity to terminate. */ 1029 cnt = 0; 1030 do { 1031 if (cnt >= RX_DISABLE_TIMEOUT) { 1032 printf("%s: timeout for RX stopped. rqc 0x%x\n", 1033 sc->sc_dev.dv_xname, reg); 1034 break; 1035 } 1036 cnt++; 1037 1038 /* 1039 * Check Receive Queue Command register that all Rx queues 1040 * are stopped 1041 */ 1042 reg = MVNETA_READ(sc, MVNETA_RQC); 1043 } while (reg & 0xff); 1044 1045 /* Double check to verify that TX FIFO is empty */ 1046 cnt = 0; 1047 while (1) { 1048 do { 1049 if (cnt >= TX_FIFO_EMPTY_TIMEOUT) { 1050 printf("%s: timeout for TX FIFO empty. status " 1051 "0x%x\n", sc->sc_dev.dv_xname, reg); 1052 break; 1053 } 1054 cnt++; 1055 1056 reg = MVNETA_READ(sc, MVNETA_PS); 1057 } while (!(reg & txfifoemp) || reg & txinprog); 1058 1059 if (cnt >= TX_FIFO_EMPTY_TIMEOUT) 1060 break; 1061 1062 /* Double check */ 1063 reg = MVNETA_READ(sc, MVNETA_PS); 1064 if (reg & txfifoemp && !(reg & txinprog)) 1065 break; 1066 else 1067 printf("%s: TX FIFO empty double check failed." 1068 " %d loops, status 0x%x\n", sc->sc_dev.dv_xname, 1069 cnt, reg); 1070 } 1071 1072 delay(200); 1073 1074 /* disable port */ 1075 MVNETA_WRITE(sc, MVNETA_PMACC0, 1076 MVNETA_READ(sc, MVNETA_PMACC0) & ~MVNETA_PMACC0_PORTEN); 1077 delay(200); 1078 1079 /* mask all interrupts */ 1080 MVNETA_WRITE(sc, MVNETA_PRXTXTIM, MVNETA_PRXTXTI_PMISCICSUMMARY); 1081 MVNETA_WRITE(sc, MVNETA_PRXTXIM, 0); 1082 1083 /* clear all cause registers */ 1084 MVNETA_WRITE(sc, MVNETA_PRXTXTIC, 0); 1085 MVNETA_WRITE(sc, MVNETA_PRXTXIC, 0); 1086 1087 /* Free RX and TX mbufs still in the queues. */ 1088 for (i = 0; i < MVNETA_TX_RING_CNT; i++) { 1089 txb = &sc->sc_txbuf[i]; 1090 if (txb->tb_m) { 1091 bus_dmamap_sync(sc->sc_dmat, txb->tb_map, 0, 1092 txb->tb_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1093 bus_dmamap_unload(sc->sc_dmat, txb->tb_map); 1094 m_freem(txb->tb_m); 1095 } 1096 bus_dmamap_destroy(sc->sc_dmat, txb->tb_map); 1097 } 1098 1099 mvneta_dmamem_free(sc, sc->sc_txring); 1100 free(sc->sc_txbuf, M_DEVBUF, 0); 1101 1102 for (i = 0; i < MVNETA_RX_RING_CNT; i++) { 1103 rxb = &sc->sc_rxbuf[i]; 1104 if (rxb->tb_m) { 1105 bus_dmamap_sync(sc->sc_dmat, rxb->tb_map, 0, 1106 rxb->tb_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1107 bus_dmamap_unload(sc->sc_dmat, rxb->tb_map); 1108 m_freem(rxb->tb_m); 1109 } 1110 bus_dmamap_destroy(sc->sc_dmat, rxb->tb_map); 1111 } 1112 1113 mvneta_dmamem_free(sc, sc->sc_rxring); 1114 free(sc->sc_rxbuf, M_DEVBUF, 0); 1115 1116 /* reset RX and TX DMAs */ 1117 MVNETA_WRITE(sc, MVNETA_PRXINIT, MVNETA_PRXINIT_RXDMAINIT); 1118 MVNETA_WRITE(sc, MVNETA_PTXINIT, MVNETA_PTXINIT_TXDMAINIT); 1119 MVNETA_WRITE(sc, MVNETA_PRXINIT, 0); 1120 MVNETA_WRITE(sc, MVNETA_PTXINIT, 0); 1121 1122 ifp->if_flags &= ~IFF_RUNNING; 1123 ifq_clr_oactive(&ifp->if_snd); 1124 } 1125 1126 void 1127 mvneta_watchdog(struct ifnet *ifp) 1128 { 1129 struct mvneta_softc *sc = ifp->if_softc; 1130 1131 /* 1132 * Reclaim first as there is a possibility of losing Tx completion 1133 * interrupts. 1134 */ 1135 mvneta_tx_proc(sc); 1136 if (sc->sc_tx_cnt != 0) { 1137 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 1138 1139 ifp->if_oerrors++; 1140 } 1141 } 1142 1143 /* 1144 * Set media options. 1145 */ 1146 int 1147 mvneta_mediachange(struct ifnet *ifp) 1148 { 1149 struct mvneta_softc *sc = ifp->if_softc; 1150 1151 if (LIST_FIRST(&sc->sc_mii.mii_phys)) 1152 mii_mediachg(&sc->sc_mii); 1153 1154 return (0); 1155 } 1156 1157 /* 1158 * Report current media status. 1159 */ 1160 void 1161 mvneta_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1162 { 1163 struct mvneta_softc *sc = ifp->if_softc; 1164 1165 if (LIST_FIRST(&sc->sc_mii.mii_phys)) { 1166 mii_pollstat(&sc->sc_mii); 1167 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1168 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1169 } 1170 1171 if (sc->sc_fixed_link) { 1172 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1173 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1174 } 1175 } 1176 1177 int 1178 mvneta_encap(struct mvneta_softc *sc, struct mbuf *m, uint32_t *idx) 1179 { 1180 struct mvneta_tx_desc *txd; 1181 bus_dmamap_t map; 1182 uint32_t cmdsts; 1183 int i, current, first, last; 1184 1185 DPRINTFN(3, ("mvneta_encap\n")); 1186 1187 first = last = current = *idx; 1188 map = sc->sc_txbuf[current].tb_map; 1189 1190 if (bus_dmamap_load_mbuf(sc->sc_dmat, map, m, BUS_DMA_NOWAIT)) 1191 return (ENOBUFS); 1192 1193 if (map->dm_nsegs > (MVNETA_TX_RING_CNT - sc->sc_tx_cnt - 2)) { 1194 bus_dmamap_unload(sc->sc_dmat, map); 1195 return (ENOBUFS); 1196 } 1197 1198 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1199 BUS_DMASYNC_PREWRITE); 1200 1201 DPRINTFN(2, ("mvneta_encap: dm_nsegs=%d\n", map->dm_nsegs)); 1202 1203 cmdsts = MVNETA_TX_L4_CSUM_NOT; 1204 #if notyet 1205 int m_csumflags; 1206 if (m_csumflags & M_CSUM_IPv4) 1207 cmdsts |= MVNETA_TX_GENERATE_IP_CHKSUM; 1208 if (m_csumflags & M_CSUM_TCPv4) 1209 cmdsts |= 1210 MVNETA_TX_GENERATE_L4_CHKSUM | MVNETA_TX_L4_TYPE_TCP; 1211 if (m_csumflags & M_CSUM_UDPv4) 1212 cmdsts |= 1213 MVNETA_TX_GENERATE_L4_CHKSUM | MVNETA_TX_L4_TYPE_UDP; 1214 if (m_csumflags & (M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 1215 const int iphdr_unitlen = sizeof(struct ip) / sizeof(uint32_t); 1216 1217 cmdsts |= MVNETA_TX_IP_NO_FRAG | 1218 MVNETA_TX_IP_HEADER_LEN(iphdr_unitlen); /* unit is 4B */ 1219 } 1220 #endif 1221 1222 for (i = 0; i < map->dm_nsegs; i++) { 1223 txd = &sc->sc_txdesc[current]; 1224 memset(txd, 0, sizeof(*txd)); 1225 txd->bufptr = map->dm_segs[i].ds_addr; 1226 txd->bytecnt = map->dm_segs[i].ds_len; 1227 txd->cmdsts = cmdsts | 1228 MVNETA_TX_ZERO_PADDING; 1229 if (i == 0) 1230 txd->cmdsts |= MVNETA_TX_FIRST_DESC; 1231 if (i == (map->dm_nsegs - 1)) 1232 txd->cmdsts |= MVNETA_TX_LAST_DESC; 1233 1234 bus_dmamap_sync(sc->sc_dmat, MVNETA_DMA_MAP(sc->sc_txring), 1235 current * sizeof(*txd), sizeof(*txd), 1236 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1237 1238 last = current; 1239 current = MVNETA_TX_RING_NEXT(current); 1240 KASSERT(current != sc->sc_tx_cons); 1241 } 1242 1243 KASSERT(sc->sc_txbuf[last].tb_m == NULL); 1244 sc->sc_txbuf[first].tb_map = sc->sc_txbuf[last].tb_map; 1245 sc->sc_txbuf[last].tb_map = map; 1246 sc->sc_txbuf[last].tb_m = m; 1247 1248 sc->sc_tx_cnt += map->dm_nsegs; 1249 *idx = current; 1250 1251 /* Let him know we sent another packet. */ 1252 MVNETA_WRITE(sc, MVNETA_PTXSU(0), map->dm_nsegs); 1253 1254 DPRINTFN(3, ("mvneta_encap: completed successfully\n")); 1255 1256 return 0; 1257 } 1258 1259 void 1260 mvneta_rx_proc(struct mvneta_softc *sc) 1261 { 1262 struct ifnet *ifp = &sc->sc_ac.ac_if; 1263 struct mvneta_rx_desc *rxd; 1264 struct mvneta_buf *rxb; 1265 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 1266 struct mbuf *m; 1267 uint32_t rxstat; 1268 int i, idx, len, ready; 1269 1270 DPRINTFN(3, ("%s: %d\n", __func__, sc->sc_rx_cons)); 1271 1272 if (!(ifp->if_flags & IFF_RUNNING)) 1273 return; 1274 1275 bus_dmamap_sync(sc->sc_dmat, MVNETA_DMA_MAP(sc->sc_rxring), 0, 1276 MVNETA_DMA_LEN(sc->sc_rxring), 1277 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1278 1279 ready = MVNETA_PRXS_ODC(MVNETA_READ(sc, MVNETA_PRXS(0))); 1280 MVNETA_WRITE(sc, MVNETA_PRXSU(0), ready); 1281 1282 for (i = 0; i < ready; i++) { 1283 idx = sc->sc_rx_cons; 1284 KASSERT(idx < MVNETA_RX_RING_CNT); 1285 1286 rxd = &sc->sc_rxdesc[idx]; 1287 1288 #ifdef DIAGNOSTIC 1289 if ((rxd->cmdsts & 1290 (MVNETA_RX_LAST_DESC | MVNETA_RX_FIRST_DESC)) != 1291 (MVNETA_RX_LAST_DESC | MVNETA_RX_FIRST_DESC)) 1292 panic("%s: buffer size is smaller than packet", 1293 __func__); 1294 #endif 1295 1296 len = rxd->bytecnt; 1297 rxb = &sc->sc_rxbuf[idx]; 1298 KASSERT(rxb->tb_m); 1299 1300 bus_dmamap_sync(sc->sc_dmat, rxb->tb_map, 0, 1301 len, BUS_DMASYNC_POSTREAD); 1302 bus_dmamap_unload(sc->sc_dmat, rxb->tb_map); 1303 1304 m = rxb->tb_m; 1305 rxb->tb_m = NULL; 1306 m->m_pkthdr.len = m->m_len = len; 1307 1308 rxstat = rxd->cmdsts; 1309 if (rxstat & MVNETA_ERROR_SUMMARY) { 1310 #if 0 1311 int err = rxstat & MVNETA_RX_ERROR_CODE_MASK; 1312 1313 if (err == MVNETA_RX_CRC_ERROR) 1314 ifp->if_ierrors++; 1315 if (err == MVNETA_RX_OVERRUN_ERROR) 1316 ifp->if_ierrors++; 1317 if (err == MVNETA_RX_MAX_FRAME_LEN_ERROR) 1318 ifp->if_ierrors++; 1319 if (err == MVNETA_RX_RESOURCE_ERROR) 1320 ifp->if_ierrors++; 1321 #else 1322 ifp->if_ierrors++; 1323 #endif 1324 panic("%s: handle input errors", __func__); 1325 continue; 1326 } 1327 1328 #if notyet 1329 if (rxstat & MVNETA_RX_IP_FRAME_TYPE) { 1330 int flgs = 0; 1331 1332 /* Check IPv4 header checksum */ 1333 flgs |= M_CSUM_IPv4; 1334 if (!(rxstat & MVNETA_RX_IP_HEADER_OK)) 1335 flgs |= M_CSUM_IPv4_BAD; 1336 else if ((bufsize & MVNETA_RX_IP_FRAGMENT) == 0) { 1337 /* 1338 * Check TCPv4/UDPv4 checksum for 1339 * non-fragmented packet only. 1340 * 1341 * It seemd that sometimes 1342 * MVNETA_RX_L4_CHECKSUM_OK bit was set to 0 1343 * even if the checksum is correct and the 1344 * packet was not fragmented. So we don't set 1345 * M_CSUM_TCP_UDP_BAD even if csum bit is 0. 1346 */ 1347 1348 if (((rxstat & MVNETA_RX_L4_TYPE_MASK) == 1349 MVNETA_RX_L4_TYPE_TCP) && 1350 ((rxstat & MVNETA_RX_L4_CHECKSUM_OK) != 0)) 1351 flgs |= M_CSUM_TCPv4; 1352 else if (((rxstat & MVNETA_RX_L4_TYPE_MASK) == 1353 MVNETA_RX_L4_TYPE_UDP) && 1354 ((rxstat & MVNETA_RX_L4_CHECKSUM_OK) != 0)) 1355 flgs |= M_CSUM_UDPv4; 1356 } 1357 m->m_pkthdr.csum_flags = flgs; 1358 } 1359 #endif 1360 1361 /* Skip on first 2byte (HW header) */ 1362 m_adj(m, MVNETA_HWHEADER_SIZE); 1363 1364 ml_enqueue(&ml, m); 1365 1366 if_rxr_put(&sc->sc_rx_ring, 1); 1367 1368 sc->sc_rx_cons = MVNETA_RX_RING_NEXT(idx); 1369 } 1370 1371 mvneta_fill_rx_ring(sc); 1372 1373 if_input(ifp, &ml); 1374 } 1375 1376 void 1377 mvneta_tx_proc(struct mvneta_softc *sc) 1378 { 1379 struct ifnet *ifp = &sc->sc_ac.ac_if; 1380 struct mvneta_tx_desc *txd; 1381 struct mvneta_buf *txb; 1382 int i, idx, sent; 1383 1384 DPRINTFN(3, ("%s\n", __func__)); 1385 1386 if (!(ifp->if_flags & IFF_RUNNING)) 1387 return; 1388 1389 bus_dmamap_sync(sc->sc_dmat, MVNETA_DMA_MAP(sc->sc_txring), 0, 1390 MVNETA_DMA_LEN(sc->sc_txring), 1391 BUS_DMASYNC_POSTREAD); 1392 1393 sent = MVNETA_PTXS_TBC(MVNETA_READ(sc, MVNETA_PTXS(0))); 1394 MVNETA_WRITE(sc, MVNETA_PTXSU(0), MVNETA_PTXSU_NORB(sent)); 1395 1396 for (i = 0; i < sent; i++) { 1397 idx = sc->sc_tx_cons; 1398 KASSERT(idx < MVNETA_TX_RING_CNT); 1399 1400 txd = &sc->sc_txdesc[idx]; 1401 txb = &sc->sc_txbuf[idx]; 1402 if (txb->tb_m) { 1403 bus_dmamap_sync(sc->sc_dmat, txb->tb_map, 0, 1404 txb->tb_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1405 bus_dmamap_unload(sc->sc_dmat, txb->tb_map); 1406 1407 m_freem(txb->tb_m); 1408 txb->tb_m = NULL; 1409 } 1410 1411 ifq_clr_oactive(&ifp->if_snd); 1412 1413 sc->sc_tx_cnt--; 1414 1415 if (txd->cmdsts & MVNETA_ERROR_SUMMARY) { 1416 int err = txd->cmdsts & MVNETA_TX_ERROR_CODE_MASK; 1417 1418 if (err == MVNETA_TX_LATE_COLLISION_ERROR) 1419 ifp->if_collisions++; 1420 if (err == MVNETA_TX_UNDERRUN_ERROR) 1421 ifp->if_oerrors++; 1422 if (err == MVNETA_TX_EXCESSIVE_COLLISION_ERRO) 1423 ifp->if_collisions++; 1424 } 1425 1426 sc->sc_tx_cons = MVNETA_TX_RING_NEXT(sc->sc_tx_cons); 1427 } 1428 1429 if (sc->sc_tx_cnt == 0) 1430 ifp->if_timer = 0; 1431 } 1432 1433 uint8_t 1434 mvneta_crc8(const uint8_t *data, size_t size) 1435 { 1436 int bit; 1437 uint8_t byte; 1438 uint8_t crc = 0; 1439 const uint8_t poly = 0x07; 1440 1441 while(size--) 1442 for (byte = *data++, bit = NBBY-1; bit >= 0; bit--) 1443 crc = (crc << 1) ^ ((((crc >> 7) ^ (byte >> bit)) & 1) ? poly : 0); 1444 1445 return crc; 1446 } 1447 1448 CTASSERT(MVNETA_NDFSMT == MVNETA_NDFOMT); 1449 1450 void 1451 mvneta_iff(struct mvneta_softc *sc) 1452 { 1453 struct arpcom *ac = &sc->sc_ac; 1454 struct ifnet *ifp = &sc->sc_ac.ac_if; 1455 struct ether_multi *enm; 1456 struct ether_multistep step; 1457 uint32_t dfut[MVNETA_NDFUT], dfsmt[MVNETA_NDFSMT], dfomt[MVNETA_NDFOMT]; 1458 uint32_t pxc; 1459 int i; 1460 const uint8_t special[ETHER_ADDR_LEN] = {0x01,0x00,0x5e,0x00,0x00,0x00}; 1461 1462 pxc = MVNETA_READ(sc, MVNETA_PXC); 1463 pxc &= ~(MVNETA_PXC_RB | MVNETA_PXC_RBIP | MVNETA_PXC_RBARP | MVNETA_PXC_UPM); 1464 ifp->if_flags &= ~IFF_ALLMULTI; 1465 memset(dfut, 0, sizeof(dfut)); 1466 memset(dfsmt, 0, sizeof(dfsmt)); 1467 memset(dfomt, 0, sizeof(dfomt)); 1468 1469 if (ifp->if_flags & IFF_PROMISC || ac->ac_multirangecnt > 0) { 1470 ifp->if_flags |= IFF_ALLMULTI; 1471 if (ifp->if_flags & IFF_PROMISC) 1472 pxc |= MVNETA_PXC_UPM; 1473 for (i = 0; i < MVNETA_NDFSMT; i++) { 1474 dfsmt[i] = dfomt[i] = 1475 MVNETA_DF(0, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS) | 1476 MVNETA_DF(1, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS) | 1477 MVNETA_DF(2, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS) | 1478 MVNETA_DF(3, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS); 1479 } 1480 } else { 1481 ETHER_FIRST_MULTI(step, ac, enm); 1482 while (enm != NULL) { 1483 /* chip handles some IPv4 multicast specially */ 1484 if (memcmp(enm->enm_addrlo, special, 5) == 0) { 1485 i = enm->enm_addrlo[5]; 1486 dfsmt[i>>2] |= 1487 MVNETA_DF(i&3, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS); 1488 } else { 1489 i = mvneta_crc8(enm->enm_addrlo, ETHER_ADDR_LEN); 1490 dfomt[i>>2] |= 1491 MVNETA_DF(i&3, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS); 1492 } 1493 1494 ETHER_NEXT_MULTI(step, enm); 1495 } 1496 } 1497 1498 MVNETA_WRITE(sc, MVNETA_PXC, pxc); 1499 1500 /* Set Destination Address Filter Unicast Table */ 1501 i = sc->sc_enaddr[5] & 0xf; /* last nibble */ 1502 dfut[i>>2] = MVNETA_DF(i&3, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS); 1503 MVNETA_WRITE_FILTER(sc, MVNETA_DFUT, dfut, MVNETA_NDFUT); 1504 1505 /* Set Destination Address Filter Multicast Tables */ 1506 MVNETA_WRITE_FILTER(sc, MVNETA_DFSMT, dfsmt, MVNETA_NDFSMT); 1507 MVNETA_WRITE_FILTER(sc, MVNETA_DFOMT, dfomt, MVNETA_NDFOMT); 1508 } 1509 1510 struct mvneta_dmamem * 1511 mvneta_dmamem_alloc(struct mvneta_softc *sc, bus_size_t size, bus_size_t align) 1512 { 1513 struct mvneta_dmamem *mdm; 1514 int nsegs; 1515 1516 mdm = malloc(sizeof(*mdm), M_DEVBUF, M_WAITOK | M_ZERO); 1517 mdm->mdm_size = size; 1518 1519 if (bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 1520 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, &mdm->mdm_map) != 0) 1521 goto mdmfree; 1522 1523 if (bus_dmamem_alloc(sc->sc_dmat, size, align, 0, &mdm->mdm_seg, 1, 1524 &nsegs, BUS_DMA_WAITOK) != 0) 1525 goto destroy; 1526 1527 if (bus_dmamem_map(sc->sc_dmat, &mdm->mdm_seg, nsegs, size, 1528 &mdm->mdm_kva, BUS_DMA_WAITOK|BUS_DMA_COHERENT) != 0) 1529 goto free; 1530 1531 if (bus_dmamap_load(sc->sc_dmat, mdm->mdm_map, mdm->mdm_kva, size, 1532 NULL, BUS_DMA_WAITOK) != 0) 1533 goto unmap; 1534 1535 bzero(mdm->mdm_kva, size); 1536 1537 return (mdm); 1538 1539 unmap: 1540 bus_dmamem_unmap(sc->sc_dmat, mdm->mdm_kva, size); 1541 free: 1542 bus_dmamem_free(sc->sc_dmat, &mdm->mdm_seg, 1); 1543 destroy: 1544 bus_dmamap_destroy(sc->sc_dmat, mdm->mdm_map); 1545 mdmfree: 1546 free(mdm, M_DEVBUF, 0); 1547 1548 return (NULL); 1549 } 1550 1551 void 1552 mvneta_dmamem_free(struct mvneta_softc *sc, struct mvneta_dmamem *mdm) 1553 { 1554 bus_dmamem_unmap(sc->sc_dmat, mdm->mdm_kva, mdm->mdm_size); 1555 bus_dmamem_free(sc->sc_dmat, &mdm->mdm_seg, 1); 1556 bus_dmamap_destroy(sc->sc_dmat, mdm->mdm_map); 1557 free(mdm, M_DEVBUF, 0); 1558 } 1559 1560 struct mbuf * 1561 mvneta_alloc_mbuf(struct mvneta_softc *sc, bus_dmamap_t map) 1562 { 1563 struct mbuf *m = NULL; 1564 1565 m = MCLGETI(NULL, M_DONTWAIT, NULL, MCLBYTES); 1566 if (!m) 1567 return (NULL); 1568 m->m_len = m->m_pkthdr.len = MCLBYTES; 1569 1570 if (bus_dmamap_load_mbuf(sc->sc_dmat, map, m, BUS_DMA_NOWAIT) != 0) { 1571 printf("%s: could not load mbuf DMA map", sc->sc_dev.dv_xname); 1572 m_freem(m); 1573 return (NULL); 1574 } 1575 1576 bus_dmamap_sync(sc->sc_dmat, map, 0, 1577 m->m_pkthdr.len, BUS_DMASYNC_PREREAD); 1578 1579 return (m); 1580 } 1581 1582 void 1583 mvneta_fill_rx_ring(struct mvneta_softc *sc) 1584 { 1585 struct mvneta_rx_desc *rxd; 1586 struct mvneta_buf *rxb; 1587 u_int slots; 1588 1589 for (slots = if_rxr_get(&sc->sc_rx_ring, MVNETA_RX_RING_CNT); 1590 slots > 0; slots--) { 1591 rxb = &sc->sc_rxbuf[sc->sc_rx_prod]; 1592 rxb->tb_m = mvneta_alloc_mbuf(sc, rxb->tb_map); 1593 if (rxb->tb_m == NULL) 1594 break; 1595 1596 rxd = &sc->sc_rxdesc[sc->sc_rx_prod]; 1597 memset(rxd, 0, sizeof(*rxd)); 1598 rxd->bufptr = rxb->tb_map->dm_segs[0].ds_addr; 1599 1600 bus_dmamap_sync(sc->sc_dmat, MVNETA_DMA_MAP(sc->sc_rxring), 1601 sc->sc_rx_prod * sizeof(*rxd), sizeof(*rxd), 1602 BUS_DMASYNC_PREWRITE); 1603 1604 sc->sc_rx_prod = MVNETA_RX_RING_NEXT(sc->sc_rx_prod); 1605 1606 /* Tell him that there's a new free desc. */ 1607 MVNETA_WRITE(sc, MVNETA_PRXSU(0), 1608 MVNETA_PRXSU_NOOFNEWDESCRIPTORS(1)); 1609 } 1610 1611 if_rxr_put(&sc->sc_rx_ring, slots); 1612 } 1613