1 /* $OpenBSD: if_dwge.c,v 1.9 2021/05/07 19:03:01 kettenis Exp $ */ 2 /* 3 * Copyright (c) 2008, 2019 Mark Kettenis <kettenis@openbsd.org> 4 * Copyright (c) 2017 Patrick Wildt <patrick@blueri.se> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * Driver for the Synopsys Designware ethernet controller. 21 */ 22 23 #include "bpfilter.h" 24 25 #include <sys/param.h> 26 #include <sys/systm.h> 27 #include <sys/device.h> 28 #include <sys/kernel.h> 29 #include <sys/malloc.h> 30 #include <sys/mbuf.h> 31 #include <sys/queue.h> 32 #include <sys/socket.h> 33 #include <sys/sockio.h> 34 #include <sys/timeout.h> 35 36 #include <machine/bus.h> 37 #include <machine/fdt.h> 38 39 #include <net/if.h> 40 #include <net/if_media.h> 41 42 #include <dev/ofw/openfirm.h> 43 #include <dev/ofw/ofw_clock.h> 44 #include <dev/ofw/ofw_gpio.h> 45 #include <dev/ofw/ofw_misc.h> 46 #include <dev/ofw/ofw_pinctrl.h> 47 #include <dev/ofw/ofw_regulator.h> 48 #include <dev/ofw/fdt.h> 49 50 #include <dev/mii/mii.h> 51 #include <dev/mii/miivar.h> 52 53 #if NBPFILTER > 0 54 #include <net/bpf.h> 55 #endif 56 57 #include <netinet/in.h> 58 #include <netinet/if_ether.h> 59 60 /* Registers */ 61 62 #define GMAC_MAC_CONF 0x0000 63 #define GMAC_MAC_CONF_JD (1 << 22) 64 #define GMAC_MAC_CONF_BE (1 << 21) 65 #define GMAC_MAC_CONF_DCRS (1 << 16) 66 #define GMAC_MAC_CONF_PS (1 << 15) 67 #define GMAC_MAC_CONF_FES (1 << 14) 68 #define GMAC_MAC_CONF_LM (1 << 12) 69 #define GMAC_MAC_CONF_DM (1 << 11) 70 #define GMAC_MAC_CONF_TE (1 << 3) 71 #define GMAC_MAC_CONF_RE (1 << 2) 72 #define GMAC_MAC_FRM_FILT 0x0004 73 #define GMAC_MAC_FRM_FILT_PM (1 << 4) 74 #define GMAC_MAC_FRM_FILT_HMC (1 << 2) 75 #define GMAC_MAC_FRM_FILT_PR (1 << 0) 76 #define GMAC_HASH_TAB_HI 0x0008 77 #define GMAC_HASH_TAB_LO 0x000c 78 #define GMAC_GMII_ADDR 0x0010 79 #define GMAC_GMII_ADDR_PA_SHIFT 11 80 #define GMAC_GMII_ADDR_GR_SHIFT 6 81 #define GMAC_GMII_ADDR_CR_SHIFT 2 82 #define GMAC_GMII_ADDR_CR_MASK 0xf 83 #define GMAC_GMII_ADDR_CR_DIV_42 0 84 #define GMAC_GMII_ADDR_CR_DIV_62 1 85 #define GMAC_GMII_ADDR_CR_DIV_16 2 86 #define GMAC_GMII_ADDR_CR_DIV_26 3 87 #define GMAC_GMII_ADDR_CR_DIV_102 4 88 #define GMAC_GMII_ADDR_CR_DIV_124 5 89 #define GMAC_GMII_ADDR_GW (1 << 1) 90 #define GMAC_GMII_ADDR_GB (1 << 0) 91 #define GMAC_GMII_DATA 0x0014 92 #define GMAC_VERSION 0x0020 93 #define GMAC_VERSION_SNPS_MASK 0xff 94 #define GMAC_INT_MASK 0x003c 95 #define GMAC_INT_MASK_PIM (1 << 3) 96 #define GMAC_INT_MASK_RIM (1 << 0) 97 #define GMAC_MAC_ADDR0_HI 0x0040 98 #define GMAC_MAC_ADDR0_LO 0x0044 99 #define GMAC_MMC_RX_INT_MSK 0x010c 100 #define GMAC_MMC_TX_INT_MSK 0x0110 101 #define GMAC_MMC_IPC_INT_MSK 0x0200 102 #define GMAC_BUS_MODE 0x1000 103 #define GMAC_BUS_MODE_8XPBL (1 << 24) 104 #define GMAC_BUS_MODE_USP (1 << 23) 105 #define GMAC_BUS_MODE_RPBL_MASK (0x3f << 17) 106 #define GMAC_BUS_MODE_RPBL_SHIFT 17 107 #define GMAC_BUS_MODE_FB (1 << 16) 108 #define GMAC_BUS_MODE_PBL_MASK (0x3f << 8) 109 #define GMAC_BUS_MODE_PBL_SHIFT 8 110 #define GMAC_BUS_MODE_SWR (1 << 0) 111 #define GMAC_TX_POLL_DEMAND 0x1004 112 #define GMAC_RX_DESC_LIST_ADDR 0x100c 113 #define GMAC_TX_DESC_LIST_ADDR 0x1010 114 #define GMAC_STATUS 0x1014 115 #define GMAC_STATUS_RI (1 << 6) 116 #define GMAC_STATUS_TU (1 << 2) 117 #define GMAC_STATUS_TI (1 << 0) 118 #define GMAC_OP_MODE 0x1018 119 #define GMAC_OP_MODE_RSF (1 << 25) 120 #define GMAC_OP_MODE_TSF (1 << 21) 121 #define GMAC_OP_MODE_FTF (1 << 20) 122 #define GMAC_OP_MODE_TTC_MASK (0x7 << 14) 123 #define GMAC_OP_MODE_TTC_64 (0x0 << 14) 124 #define GMAC_OP_MODE_TTC_128 (0x1 << 14) 125 #define GMAC_OP_MODE_ST (1 << 13) 126 #define GMAC_OP_MODE_RTC_MASK (0x3 << 3) 127 #define GMAC_OP_MODE_RTC_64 (0x0 << 3) 128 #define GMAC_OP_MODE_RTC_128 (0x3 << 3) 129 #define GMAC_OP_MODE_OSF (1 << 2) 130 #define GMAC_OP_MODE_SR (1 << 1) 131 #define GMAC_INT_ENA 0x101c 132 #define GMAC_INT_ENA_NIE (1 << 16) 133 #define GMAC_INT_ENA_RIE (1 << 6) 134 #define GMAC_INT_ENA_TUE (1 << 2) 135 #define GMAC_INT_ENA_TIE (1 << 0) 136 #define GMAC_AXI_BUS_MODE 0x1028 137 #define GMAC_AXI_BUS_MODE_WR_OSR_LMT_MASK (0xf << 20) 138 #define GMAC_AXI_BUS_MODE_WR_OSR_LMT_SHIFT 20 139 #define GMAC_AXI_BUS_MODE_RD_OSR_LMT_MASK (0xf << 16) 140 #define GMAC_AXI_BUS_MODE_RD_OSR_LMT_SHIFT 16 141 #define GMAC_AXI_BUS_MODE_BLEN_256 (1 << 7) 142 #define GMAC_AXI_BUS_MODE_BLEN_128 (1 << 6) 143 #define GMAC_AXI_BUS_MODE_BLEN_64 (1 << 5) 144 #define GMAC_AXI_BUS_MODE_BLEN_32 (1 << 4) 145 #define GMAC_AXI_BUS_MODE_BLEN_16 (1 << 3) 146 #define GMAC_AXI_BUS_MODE_BLEN_8 (1 << 2) 147 #define GMAC_AXI_BUS_MODE_BLEN_4 (1 << 1) 148 149 /* 150 * DWGE descriptors. 151 */ 152 153 struct dwge_desc { 154 uint32_t sd_status; 155 uint32_t sd_len; 156 uint32_t sd_addr; 157 uint32_t sd_next; 158 }; 159 160 /* Tx status bits. */ 161 #define TDES0_DB (1 << 0) 162 #define TDES0_UF (1 << 1) 163 #define TDES0_ED (1 << 2) 164 #define TDES0_CC_MASK (0xf << 3) 165 #define TDES0_CC_SHIFT 3 166 #define TDES0_EC (1 << 8) 167 #define TDES0_LC (1 << 9) 168 #define TDES0_NC (1 << 10) 169 #define TDES0_PCE (1 << 12) 170 #define TDES0_JT (1 << 14) 171 #define TDES0_IHE (1 << 16) 172 #define TDES0_OWN (1 << 31) 173 174 /* Rx status bits */ 175 #define RDES0_PE (1 << 0) 176 #define RDES0_CE (1 << 1) 177 #define RDES0_RE (1 << 3) 178 #define RDES0_RWT (1 << 4) 179 #define RDES0_FT (1 << 5) 180 #define RDES0_LC (1 << 6) 181 #define RDES0_IPC (1 << 7) 182 #define RDES0_LS (1 << 8) 183 #define RDES0_FS (1 << 9) 184 #define RDES0_OE (1 << 11) 185 #define RDES0_SAF (1 << 13) 186 #define RDES0_DE (1 << 14) 187 #define RDES0_FL_MASK 0x3fff 188 #define RDES0_FL_SHIFT 16 189 #define RDES0_AFM (1 << 30) 190 #define RDES0_OWN (1 << 31) 191 192 /* Tx size bits */ 193 #define TDES1_TBS1 (0xfff << 0) 194 #define TDES1_TCH (1 << 24) 195 #define TDES1_DC (1 << 26) 196 #define TDES1_CIC_MASK (0x3 << 27) 197 #define TDES1_CIC_IP (1 << 27) 198 #define TDES1_CIC_NO_PSE (2 << 27) 199 #define TDES1_CIC_FULL (3 << 27) 200 #define TDES1_FS (1 << 29) 201 #define TDES1_LS (1 << 30) 202 #define TDES1_IC (1 << 31) 203 204 /* Rx size bits */ 205 #define RDES1_RBS1 (0xfff << 0) 206 #define RDES1_RCH (1 << 24) 207 #define RDES1_DIC (1 << 31) 208 209 struct dwge_buf { 210 bus_dmamap_t tb_map; 211 struct mbuf *tb_m; 212 }; 213 214 #define DWGE_NTXDESC 512 215 #define DWGE_NTXSEGS 16 216 217 #define DWGE_NRXDESC 512 218 219 struct dwge_dmamem { 220 bus_dmamap_t tdm_map; 221 bus_dma_segment_t tdm_seg; 222 size_t tdm_size; 223 caddr_t tdm_kva; 224 }; 225 #define DWGE_DMA_MAP(_tdm) ((_tdm)->tdm_map) 226 #define DWGE_DMA_LEN(_tdm) ((_tdm)->tdm_size) 227 #define DWGE_DMA_DVA(_tdm) ((_tdm)->tdm_map->dm_segs[0].ds_addr) 228 #define DWGE_DMA_KVA(_tdm) ((void *)(_tdm)->tdm_kva) 229 230 struct dwge_softc { 231 struct device sc_dev; 232 int sc_node; 233 bus_space_tag_t sc_iot; 234 bus_space_handle_t sc_ioh; 235 bus_dma_tag_t sc_dmat; 236 237 struct arpcom sc_ac; 238 #define sc_lladdr sc_ac.ac_enaddr 239 struct mii_data sc_mii; 240 #define sc_media sc_mii.mii_media 241 int sc_link; 242 int sc_phyloc; 243 int sc_force_thresh_dma_mode; 244 245 struct dwge_dmamem *sc_txring; 246 struct dwge_buf *sc_txbuf; 247 struct dwge_desc *sc_txdesc; 248 int sc_tx_prod; 249 int sc_tx_cnt; 250 int sc_tx_cons; 251 252 struct dwge_dmamem *sc_rxring; 253 struct dwge_buf *sc_rxbuf; 254 struct dwge_desc *sc_rxdesc; 255 int sc_rx_prod; 256 struct if_rxring sc_rx_ring; 257 int sc_rx_cons; 258 259 struct timeout sc_tick; 260 struct timeout sc_rxto; 261 262 uint32_t sc_clk; 263 264 bus_size_t sc_clk_sel; 265 uint32_t sc_clk_sel_125; 266 uint32_t sc_clk_sel_25; 267 uint32_t sc_clk_sel_2_5; 268 }; 269 270 #define DEVNAME(_s) ((_s)->sc_dev.dv_xname) 271 272 int dwge_match(struct device *, void *, void *); 273 void dwge_attach(struct device *, struct device *, void *); 274 void dwge_setup_allwinner(struct dwge_softc *); 275 void dwge_setup_rockchip(struct dwge_softc *); 276 277 struct cfattach dwge_ca = { 278 sizeof(struct dwge_softc), dwge_match, dwge_attach 279 }; 280 281 struct cfdriver dwge_cd = { 282 NULL, "dwge", DV_IFNET 283 }; 284 285 void dwge_reset_phy(struct dwge_softc *); 286 287 uint32_t dwge_read(struct dwge_softc *, bus_addr_t); 288 void dwge_write(struct dwge_softc *, bus_addr_t, uint32_t); 289 290 int dwge_ioctl(struct ifnet *, u_long, caddr_t); 291 void dwge_start(struct ifnet *); 292 void dwge_watchdog(struct ifnet *); 293 294 int dwge_media_change(struct ifnet *); 295 void dwge_media_status(struct ifnet *, struct ifmediareq *); 296 297 int dwge_mii_readreg(struct device *, int, int); 298 void dwge_mii_writereg(struct device *, int, int, int); 299 void dwge_mii_statchg(struct device *); 300 301 void dwge_lladdr_read(struct dwge_softc *, uint8_t *); 302 void dwge_lladdr_write(struct dwge_softc *); 303 304 void dwge_tick(void *); 305 void dwge_rxtick(void *); 306 307 int dwge_intr(void *); 308 void dwge_tx_proc(struct dwge_softc *); 309 void dwge_rx_proc(struct dwge_softc *); 310 311 void dwge_up(struct dwge_softc *); 312 void dwge_down(struct dwge_softc *); 313 void dwge_iff(struct dwge_softc *); 314 int dwge_encap(struct dwge_softc *, struct mbuf *, int *); 315 316 void dwge_reset(struct dwge_softc *); 317 void dwge_stop_dma(struct dwge_softc *); 318 319 struct dwge_dmamem * 320 dwge_dmamem_alloc(struct dwge_softc *, bus_size_t, bus_size_t); 321 void dwge_dmamem_free(struct dwge_softc *, struct dwge_dmamem *); 322 struct mbuf *dwge_alloc_mbuf(struct dwge_softc *, bus_dmamap_t); 323 void dwge_fill_rx_ring(struct dwge_softc *); 324 325 int 326 dwge_match(struct device *parent, void *cfdata, void *aux) 327 { 328 struct fdt_attach_args *faa = aux; 329 330 return (OF_is_compatible(faa->fa_node, "allwinner,sun7i-a20-gmac") || 331 OF_is_compatible(faa->fa_node, "amlogic,meson-axg-dwmac") || 332 OF_is_compatible(faa->fa_node, "amlogic,meson-g12a-dwmac") || 333 OF_is_compatible(faa->fa_node, "rockchip,rk3288-gmac") || 334 OF_is_compatible(faa->fa_node, "rockchip,rk3308-mac") || 335 OF_is_compatible(faa->fa_node, "rockchip,rk3328-gmac") || 336 OF_is_compatible(faa->fa_node, "rockchip,rk3399-gmac") || 337 OF_is_compatible(faa->fa_node, "snps,dwmac")); 338 } 339 340 void 341 dwge_attach(struct device *parent, struct device *self, void *aux) 342 { 343 struct dwge_softc *sc = (void *)self; 344 struct fdt_attach_args *faa = aux; 345 struct ifnet *ifp; 346 uint32_t phy, phy_supply; 347 uint32_t axi_config; 348 uint32_t mode, pbl; 349 uint32_t version; 350 int node; 351 352 sc->sc_node = faa->fa_node; 353 sc->sc_iot = faa->fa_iot; 354 if (bus_space_map(sc->sc_iot, faa->fa_reg[0].addr, 355 faa->fa_reg[0].size, 0, &sc->sc_ioh)) { 356 printf("%s: cannot map registers\n", self->dv_xname); 357 return; 358 } 359 sc->sc_dmat = faa->fa_dmat; 360 361 /* Lookup PHY. */ 362 phy = OF_getpropint(faa->fa_node, "phy", 0); 363 if (phy == 0) 364 phy = OF_getpropint(faa->fa_node, "phy-handle", 0); 365 node = OF_getnodebyphandle(phy); 366 if (node) 367 sc->sc_phyloc = OF_getpropint(node, "reg", MII_PHY_ANY); 368 else 369 sc->sc_phyloc = MII_PHY_ANY; 370 371 pinctrl_byname(faa->fa_node, "default"); 372 373 /* Enable clock. */ 374 clock_enable(faa->fa_node, "stmmaceth"); 375 reset_deassert(faa->fa_node, "stmmaceth"); 376 delay(5000); 377 378 version = dwge_read(sc, GMAC_VERSION); 379 printf(": rev 0x%02x", version & GMAC_VERSION_SNPS_MASK); 380 381 /* Power up PHY. */ 382 phy_supply = OF_getpropint(faa->fa_node, "phy-supply", 0); 383 if (phy_supply) 384 regulator_enable(phy_supply); 385 386 /* Reset PHY */ 387 dwge_reset_phy(sc); 388 389 sc->sc_clk = clock_get_frequency(faa->fa_node, "stmmaceth"); 390 if (sc->sc_clk > 250000000) 391 sc->sc_clk = GMAC_GMII_ADDR_CR_DIV_124; 392 else if (sc->sc_clk > 150000000) 393 sc->sc_clk = GMAC_GMII_ADDR_CR_DIV_102; 394 else if (sc->sc_clk > 100000000) 395 sc->sc_clk = GMAC_GMII_ADDR_CR_DIV_62; 396 else if (sc->sc_clk > 60000000) 397 sc->sc_clk = GMAC_GMII_ADDR_CR_DIV_42; 398 else if (sc->sc_clk > 35000000) 399 sc->sc_clk = GMAC_GMII_ADDR_CR_DIV_26; 400 else 401 sc->sc_clk = GMAC_GMII_ADDR_CR_DIV_16; 402 403 if (OF_getprop(faa->fa_node, "local-mac-address", 404 &sc->sc_lladdr, ETHER_ADDR_LEN) != ETHER_ADDR_LEN) 405 dwge_lladdr_read(sc, sc->sc_lladdr); 406 printf(", address %s\n", ether_sprintf(sc->sc_lladdr)); 407 408 timeout_set(&sc->sc_tick, dwge_tick, sc); 409 timeout_set(&sc->sc_rxto, dwge_rxtick, sc); 410 411 ifp = &sc->sc_ac.ac_if; 412 ifp->if_softc = sc; 413 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 414 ifp->if_ioctl = dwge_ioctl; 415 ifp->if_start = dwge_start; 416 ifp->if_watchdog = dwge_watchdog; 417 ifq_set_maxlen(&ifp->if_snd, DWGE_NTXDESC - 1); 418 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 419 420 ifp->if_capabilities = IFCAP_VLAN_MTU; 421 422 sc->sc_mii.mii_ifp = ifp; 423 sc->sc_mii.mii_readreg = dwge_mii_readreg; 424 sc->sc_mii.mii_writereg = dwge_mii_writereg; 425 sc->sc_mii.mii_statchg = dwge_mii_statchg; 426 427 ifmedia_init(&sc->sc_media, 0, dwge_media_change, dwge_media_status); 428 429 /* Do hardware specific initializations. */ 430 if (OF_is_compatible(faa->fa_node, "allwinner,sun7i-a20-gmac")) 431 dwge_setup_allwinner(sc); 432 else if (OF_is_compatible(faa->fa_node, "rockchip,rk3288-gmac")) 433 dwge_setup_rockchip(sc); 434 else if (OF_is_compatible(faa->fa_node, "rockchip,rk3308-mac")) 435 dwge_setup_rockchip(sc); 436 else if (OF_is_compatible(faa->fa_node, "rockchip,rk3328-gmac")) 437 dwge_setup_rockchip(sc); 438 else if (OF_is_compatible(faa->fa_node, "rockchip,rk3399-gmac")) 439 dwge_setup_rockchip(sc); 440 441 if (OF_getpropbool(faa->fa_node, "snps,force_thresh_dma_mode")) 442 sc->sc_force_thresh_dma_mode = 1; 443 444 dwge_reset(sc); 445 446 /* Configure MAC. */ 447 dwge_write(sc, GMAC_MAC_CONF, dwge_read(sc, GMAC_MAC_CONF) | 448 GMAC_MAC_CONF_JD | GMAC_MAC_CONF_BE | GMAC_MAC_CONF_DCRS); 449 450 /* Configure DMA engine. */ 451 mode = dwge_read(sc, GMAC_BUS_MODE); 452 mode |= GMAC_BUS_MODE_USP; 453 if (!OF_getpropbool(faa->fa_node, "snps,no-pbl-x8")) 454 mode |= GMAC_BUS_MODE_8XPBL; 455 mode &= ~(GMAC_BUS_MODE_RPBL_MASK | GMAC_BUS_MODE_PBL_MASK); 456 pbl = OF_getpropint(faa->fa_node, "snps,pbl", 8); 457 mode |= pbl << GMAC_BUS_MODE_RPBL_SHIFT; 458 mode |= pbl << GMAC_BUS_MODE_PBL_SHIFT; 459 if (OF_getpropbool(faa->fa_node, "snps,fixed-burst")) 460 mode |= GMAC_BUS_MODE_FB; 461 dwge_write(sc, GMAC_BUS_MODE, mode); 462 463 /* Configure AXI master. */ 464 axi_config = OF_getpropint(faa->fa_node, "snps,axi-config", 0); 465 node = OF_getnodebyphandle(axi_config); 466 if (node) { 467 uint32_t blen[7] = { 0 }; 468 uint32_t osr_lmt; 469 int i; 470 471 mode = dwge_read(sc, GMAC_AXI_BUS_MODE); 472 473 osr_lmt = OF_getpropint(node, "snps,wr_osr_lmt", 1); 474 mode &= ~GMAC_AXI_BUS_MODE_WR_OSR_LMT_MASK; 475 mode |= (osr_lmt << GMAC_AXI_BUS_MODE_WR_OSR_LMT_SHIFT); 476 osr_lmt = OF_getpropint(node, "snps,rd_osr_lmt", 1); 477 mode &= ~GMAC_AXI_BUS_MODE_RD_OSR_LMT_MASK; 478 mode |= (osr_lmt << GMAC_AXI_BUS_MODE_RD_OSR_LMT_SHIFT); 479 480 OF_getpropintarray(node, "snps,blen", blen, sizeof(blen)); 481 for (i = 0; i < nitems(blen); i++) { 482 switch (blen[i]) { 483 case 256: 484 mode |= GMAC_AXI_BUS_MODE_BLEN_256; 485 break; 486 case 128: 487 mode |= GMAC_AXI_BUS_MODE_BLEN_128; 488 break; 489 case 64: 490 mode |= GMAC_AXI_BUS_MODE_BLEN_64; 491 break; 492 case 32: 493 mode |= GMAC_AXI_BUS_MODE_BLEN_32; 494 break; 495 case 16: 496 mode |= GMAC_AXI_BUS_MODE_BLEN_16; 497 break; 498 case 8: 499 mode |= GMAC_AXI_BUS_MODE_BLEN_8; 500 break; 501 case 4: 502 mode |= GMAC_AXI_BUS_MODE_BLEN_4; 503 break; 504 } 505 } 506 507 dwge_write(sc, GMAC_AXI_BUS_MODE, mode); 508 } 509 510 mii_attach(self, &sc->sc_mii, 0xffffffff, sc->sc_phyloc, 511 (sc->sc_phyloc == MII_PHY_ANY) ? 0 : MII_OFFSET_ANY, 0); 512 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 513 printf("%s: no PHY found!\n", sc->sc_dev.dv_xname); 514 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 515 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 516 } else 517 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_AUTO); 518 519 if_attach(ifp); 520 ether_ifattach(ifp); 521 522 /* Disable interrupts. */ 523 dwge_write(sc, GMAC_INT_ENA, 0); 524 dwge_write(sc, GMAC_INT_MASK, GMAC_INT_MASK_PIM | GMAC_INT_MASK_RIM); 525 dwge_write(sc, GMAC_MMC_RX_INT_MSK, 0xffffffff); 526 dwge_write(sc, GMAC_MMC_TX_INT_MSK, 0xffffffff); 527 dwge_write(sc, GMAC_MMC_IPC_INT_MSK, 0xffffffff); 528 529 fdt_intr_establish(faa->fa_node, IPL_NET, dwge_intr, sc, 530 sc->sc_dev.dv_xname); 531 } 532 533 void 534 dwge_reset_phy(struct dwge_softc *sc) 535 { 536 uint32_t *gpio; 537 uint32_t delays[3]; 538 int active = 1; 539 int len; 540 541 len = OF_getproplen(sc->sc_node, "snps,reset-gpio"); 542 if (len <= 0) 543 return; 544 545 gpio = malloc(len, M_TEMP, M_WAITOK); 546 547 /* Gather information. */ 548 OF_getpropintarray(sc->sc_node, "snps,reset-gpio", gpio, len); 549 if (OF_getpropbool(sc->sc_node, "snps-reset-active-low")) 550 active = 0; 551 delays[0] = delays[1] = delays[2] = 0; 552 OF_getpropintarray(sc->sc_node, "snps,reset-delays-us", delays, 553 sizeof(delays)); 554 555 /* Perform reset sequence. */ 556 gpio_controller_config_pin(gpio, GPIO_CONFIG_OUTPUT); 557 gpio_controller_set_pin(gpio, !active); 558 delay(delays[0]); 559 gpio_controller_set_pin(gpio, active); 560 delay(delays[1]); 561 gpio_controller_set_pin(gpio, !active); 562 delay(delays[2]); 563 564 free(gpio, M_TEMP, len); 565 } 566 567 uint32_t 568 dwge_read(struct dwge_softc *sc, bus_addr_t addr) 569 { 570 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, addr); 571 } 572 573 void 574 dwge_write(struct dwge_softc *sc, bus_addr_t addr, uint32_t data) 575 { 576 bus_space_write_4(sc->sc_iot, sc->sc_ioh, addr, data); 577 } 578 579 void 580 dwge_lladdr_read(struct dwge_softc *sc, uint8_t *lladdr) 581 { 582 uint32_t machi, maclo; 583 584 machi = dwge_read(sc, GMAC_MAC_ADDR0_HI); 585 maclo = dwge_read(sc, GMAC_MAC_ADDR0_LO); 586 587 lladdr[0] = (maclo >> 0) & 0xff; 588 lladdr[1] = (maclo >> 8) & 0xff; 589 lladdr[2] = (maclo >> 16) & 0xff; 590 lladdr[3] = (maclo >> 24) & 0xff; 591 lladdr[4] = (machi >> 0) & 0xff; 592 lladdr[5] = (machi >> 8) & 0xff; 593 } 594 595 void 596 dwge_lladdr_write(struct dwge_softc *sc) 597 { 598 dwge_write(sc, GMAC_MAC_ADDR0_HI, 599 sc->sc_lladdr[5] << 8 | sc->sc_lladdr[4] << 0); 600 dwge_write(sc, GMAC_MAC_ADDR0_LO, 601 sc->sc_lladdr[3] << 24 | sc->sc_lladdr[2] << 16 | 602 sc->sc_lladdr[1] << 8 | sc->sc_lladdr[0] << 0); 603 } 604 605 void 606 dwge_start(struct ifnet *ifp) 607 { 608 struct dwge_softc *sc = ifp->if_softc; 609 struct mbuf *m; 610 int error, idx; 611 612 if (!(ifp->if_flags & IFF_RUNNING)) 613 return; 614 if (ifq_is_oactive(&ifp->if_snd)) 615 return; 616 if (ifq_empty(&ifp->if_snd)) 617 return; 618 if (!sc->sc_link) 619 return; 620 621 idx = sc->sc_tx_prod; 622 while ((sc->sc_txdesc[idx].sd_status & TDES0_OWN) == 0) { 623 m = ifq_deq_begin(&ifp->if_snd); 624 if (m == NULL) 625 break; 626 627 error = dwge_encap(sc, m, &idx); 628 if (error == ENOBUFS) { 629 ifq_deq_rollback(&ifp->if_snd, m); 630 ifq_set_oactive(&ifp->if_snd); 631 break; 632 } 633 if (error == EFBIG) { 634 ifq_deq_commit(&ifp->if_snd, m); 635 m_freem(m); /* give up: drop it */ 636 ifp->if_oerrors++; 637 continue; 638 } 639 640 /* Now we are committed to transmit the packet. */ 641 ifq_deq_commit(&ifp->if_snd, m); 642 643 #if NBPFILTER > 0 644 if (ifp->if_bpf) 645 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); 646 #endif 647 } 648 649 if (sc->sc_tx_prod != idx) { 650 sc->sc_tx_prod = idx; 651 652 /* Set a timeout in case the chip goes out to lunch. */ 653 ifp->if_timer = 5; 654 } 655 } 656 657 int 658 dwge_ioctl(struct ifnet *ifp, u_long cmd, caddr_t addr) 659 { 660 struct dwge_softc *sc = ifp->if_softc; 661 struct ifreq *ifr = (struct ifreq *)addr; 662 int error = 0, s; 663 664 s = splnet(); 665 666 switch (cmd) { 667 case SIOCSIFADDR: 668 ifp->if_flags |= IFF_UP; 669 /* FALLTHROUGH */ 670 case SIOCSIFFLAGS: 671 if (ifp->if_flags & IFF_UP) { 672 if (ifp->if_flags & IFF_RUNNING) 673 error = ENETRESET; 674 else 675 dwge_up(sc); 676 } else { 677 if (ifp->if_flags & IFF_RUNNING) 678 dwge_down(sc); 679 } 680 break; 681 682 case SIOCGIFMEDIA: 683 case SIOCSIFMEDIA: 684 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 685 break; 686 687 case SIOCGIFRXR: 688 error = if_rxr_ioctl((struct if_rxrinfo *)ifr->ifr_data, 689 NULL, MCLBYTES, &sc->sc_rx_ring); 690 break; 691 692 default: 693 error = ether_ioctl(ifp, &sc->sc_ac, cmd, addr); 694 break; 695 } 696 697 if (error == ENETRESET) { 698 if (ifp->if_flags & IFF_RUNNING) 699 dwge_iff(sc); 700 error = 0; 701 } 702 703 splx(s); 704 return (error); 705 } 706 707 void 708 dwge_watchdog(struct ifnet *ifp) 709 { 710 printf("%s\n", __func__); 711 } 712 713 int 714 dwge_media_change(struct ifnet *ifp) 715 { 716 struct dwge_softc *sc = ifp->if_softc; 717 718 if (LIST_FIRST(&sc->sc_mii.mii_phys)) 719 mii_mediachg(&sc->sc_mii); 720 721 return (0); 722 } 723 724 void 725 dwge_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 726 { 727 struct dwge_softc *sc = ifp->if_softc; 728 729 if (LIST_FIRST(&sc->sc_mii.mii_phys)) { 730 mii_pollstat(&sc->sc_mii); 731 ifmr->ifm_active = sc->sc_mii.mii_media_active; 732 ifmr->ifm_status = sc->sc_mii.mii_media_status; 733 } 734 } 735 736 int 737 dwge_mii_readreg(struct device *self, int phy, int reg) 738 { 739 struct dwge_softc *sc = (void *)self; 740 int n; 741 742 dwge_write(sc, GMAC_GMII_ADDR, 743 sc->sc_clk << GMAC_GMII_ADDR_CR_SHIFT | 744 phy << GMAC_GMII_ADDR_PA_SHIFT | 745 reg << GMAC_GMII_ADDR_GR_SHIFT | 746 GMAC_GMII_ADDR_GB); 747 for (n = 0; n < 1000; n++) { 748 if ((dwge_read(sc, GMAC_GMII_ADDR) & GMAC_GMII_ADDR_GB) == 0) 749 return dwge_read(sc, GMAC_GMII_DATA); 750 delay(10); 751 } 752 753 printf("%s: mii_read timeout\n", sc->sc_dev.dv_xname); 754 return (0); 755 } 756 757 void 758 dwge_mii_writereg(struct device *self, int phy, int reg, int val) 759 { 760 struct dwge_softc *sc = (void *)self; 761 int n; 762 763 dwge_write(sc, GMAC_GMII_DATA, val); 764 dwge_write(sc, GMAC_GMII_ADDR, 765 sc->sc_clk << GMAC_GMII_ADDR_CR_SHIFT | 766 phy << GMAC_GMII_ADDR_PA_SHIFT | 767 reg << GMAC_GMII_ADDR_GR_SHIFT | 768 GMAC_GMII_ADDR_GW | GMAC_GMII_ADDR_GB); 769 for (n = 0; n < 1000; n++) { 770 if ((dwge_read(sc, GMAC_GMII_ADDR) & GMAC_GMII_ADDR_GB) == 0) 771 return; 772 delay(10); 773 } 774 775 printf("%s: mii_write timeout\n", sc->sc_dev.dv_xname); 776 } 777 778 void 779 dwge_mii_statchg(struct device *self) 780 { 781 struct dwge_softc *sc = (void *)self; 782 uint32_t conf; 783 784 conf = dwge_read(sc, GMAC_MAC_CONF); 785 conf &= ~(GMAC_MAC_CONF_PS | GMAC_MAC_CONF_FES); 786 787 switch (IFM_SUBTYPE(sc->sc_mii.mii_media_active)) { 788 case IFM_1000_SX: 789 case IFM_1000_LX: 790 case IFM_1000_CX: 791 case IFM_1000_T: 792 sc->sc_link = 1; 793 break; 794 case IFM_100_TX: 795 conf |= GMAC_MAC_CONF_PS | GMAC_MAC_CONF_FES; 796 sc->sc_link = 1; 797 break; 798 case IFM_10_T: 799 conf |= GMAC_MAC_CONF_PS; 800 sc->sc_link = 1; 801 break; 802 default: 803 sc->sc_link = 0; 804 return; 805 } 806 807 if (sc->sc_link == 0) 808 return; 809 810 conf &= ~GMAC_MAC_CONF_DM; 811 if ((sc->sc_mii.mii_media_active & IFM_GMASK) == IFM_FDX) 812 conf |= GMAC_MAC_CONF_DM; 813 814 /* XXX: RX/TX flow control? */ 815 816 dwge_write(sc, GMAC_MAC_CONF, conf); 817 } 818 819 void 820 dwge_tick(void *arg) 821 { 822 struct dwge_softc *sc = arg; 823 int s; 824 825 s = splnet(); 826 mii_tick(&sc->sc_mii); 827 splx(s); 828 829 timeout_add_sec(&sc->sc_tick, 1); 830 } 831 832 void 833 dwge_rxtick(void *arg) 834 { 835 struct dwge_softc *sc = arg; 836 uint32_t mode; 837 int s; 838 839 s = splnet(); 840 841 mode = dwge_read(sc, GMAC_OP_MODE); 842 dwge_write(sc, GMAC_OP_MODE, mode & ~GMAC_OP_MODE_SR); 843 844 bus_dmamap_sync(sc->sc_dmat, DWGE_DMA_MAP(sc->sc_rxring), 845 0, DWGE_DMA_LEN(sc->sc_rxring), 846 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 847 848 dwge_write(sc, GMAC_RX_DESC_LIST_ADDR, 0); 849 850 sc->sc_rx_prod = sc->sc_rx_cons = 0; 851 dwge_fill_rx_ring(sc); 852 853 bus_dmamap_sync(sc->sc_dmat, DWGE_DMA_MAP(sc->sc_rxring), 854 0, DWGE_DMA_LEN(sc->sc_rxring), 855 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 856 857 dwge_write(sc, GMAC_RX_DESC_LIST_ADDR, DWGE_DMA_DVA(sc->sc_rxring)); 858 dwge_write(sc, GMAC_OP_MODE, mode); 859 860 splx(s); 861 } 862 863 int 864 dwge_intr(void *arg) 865 { 866 struct dwge_softc *sc = arg; 867 uint32_t reg; 868 869 reg = dwge_read(sc, GMAC_STATUS); 870 dwge_write(sc, GMAC_STATUS, reg); 871 872 if (reg & GMAC_STATUS_RI) 873 dwge_rx_proc(sc); 874 875 if (reg & GMAC_STATUS_TI || 876 reg & GMAC_STATUS_TU) 877 dwge_tx_proc(sc); 878 879 return (1); 880 } 881 882 void 883 dwge_tx_proc(struct dwge_softc *sc) 884 { 885 struct ifnet *ifp = &sc->sc_ac.ac_if; 886 struct dwge_desc *txd; 887 struct dwge_buf *txb; 888 int idx, txfree; 889 890 bus_dmamap_sync(sc->sc_dmat, DWGE_DMA_MAP(sc->sc_txring), 0, 891 DWGE_DMA_LEN(sc->sc_txring), 892 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 893 894 txfree = 0; 895 while (sc->sc_tx_cnt > 0) { 896 idx = sc->sc_tx_cons; 897 KASSERT(idx < DWGE_NTXDESC); 898 899 txd = &sc->sc_txdesc[idx]; 900 if (txd->sd_status & TDES0_OWN) 901 break; 902 903 txb = &sc->sc_txbuf[idx]; 904 if (txb->tb_m) { 905 bus_dmamap_sync(sc->sc_dmat, txb->tb_map, 0, 906 txb->tb_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 907 bus_dmamap_unload(sc->sc_dmat, txb->tb_map); 908 909 m_freem(txb->tb_m); 910 txb->tb_m = NULL; 911 } 912 913 txfree++; 914 sc->sc_tx_cnt--; 915 916 if (sc->sc_tx_cons == (DWGE_NTXDESC - 1)) 917 sc->sc_tx_cons = 0; 918 else 919 sc->sc_tx_cons++; 920 921 txd->sd_status = 0; 922 } 923 924 if (sc->sc_tx_cnt == 0) 925 ifp->if_timer = 0; 926 927 if (txfree) { 928 if (ifq_is_oactive(&ifp->if_snd)) 929 ifq_restart(&ifp->if_snd); 930 } 931 } 932 933 void 934 dwge_rx_proc(struct dwge_softc *sc) 935 { 936 struct ifnet *ifp = &sc->sc_ac.ac_if; 937 struct dwge_desc *rxd; 938 struct dwge_buf *rxb; 939 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 940 struct mbuf *m; 941 int idx, len; 942 943 if ((ifp->if_flags & IFF_RUNNING) == 0) 944 return; 945 946 bus_dmamap_sync(sc->sc_dmat, DWGE_DMA_MAP(sc->sc_rxring), 0, 947 DWGE_DMA_LEN(sc->sc_rxring), 948 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 949 950 while (if_rxr_inuse(&sc->sc_rx_ring) > 0) { 951 idx = sc->sc_rx_cons; 952 KASSERT(idx < DWGE_NRXDESC); 953 954 rxd = &sc->sc_rxdesc[idx]; 955 if (rxd->sd_status & RDES0_OWN) 956 break; 957 958 len = (rxd->sd_status >> RDES0_FL_SHIFT) & RDES0_FL_MASK; 959 rxb = &sc->sc_rxbuf[idx]; 960 KASSERT(rxb->tb_m); 961 962 bus_dmamap_sync(sc->sc_dmat, rxb->tb_map, 0, 963 len, BUS_DMASYNC_POSTREAD); 964 bus_dmamap_unload(sc->sc_dmat, rxb->tb_map); 965 966 /* Strip off CRC. */ 967 len -= ETHER_CRC_LEN; 968 KASSERT(len > 0); 969 970 m = rxb->tb_m; 971 rxb->tb_m = NULL; 972 m->m_pkthdr.len = m->m_len = len; 973 974 ml_enqueue(&ml, m); 975 976 if_rxr_put(&sc->sc_rx_ring, 1); 977 if (sc->sc_rx_cons == (DWGE_NRXDESC - 1)) 978 sc->sc_rx_cons = 0; 979 else 980 sc->sc_rx_cons++; 981 } 982 983 if (ifiq_input(&ifp->if_rcv, &ml)) 984 if_rxr_livelocked(&sc->sc_rx_ring); 985 986 dwge_fill_rx_ring(sc); 987 988 bus_dmamap_sync(sc->sc_dmat, DWGE_DMA_MAP(sc->sc_rxring), 0, 989 DWGE_DMA_LEN(sc->sc_rxring), 990 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 991 992 } 993 994 void 995 dwge_up(struct dwge_softc *sc) 996 { 997 struct ifnet *ifp = &sc->sc_ac.ac_if; 998 struct dwge_buf *txb, *rxb; 999 uint32_t mode; 1000 int i; 1001 1002 /* Allocate Tx descriptor ring. */ 1003 sc->sc_txring = dwge_dmamem_alloc(sc, 1004 DWGE_NTXDESC * sizeof(struct dwge_desc), 8); 1005 sc->sc_txdesc = DWGE_DMA_KVA(sc->sc_txring); 1006 1007 sc->sc_txbuf = malloc(sizeof(struct dwge_buf) * DWGE_NTXDESC, 1008 M_DEVBUF, M_WAITOK); 1009 for (i = 0; i < DWGE_NTXDESC; i++) { 1010 txb = &sc->sc_txbuf[i]; 1011 bus_dmamap_create(sc->sc_dmat, MCLBYTES, DWGE_NTXSEGS, 1012 MCLBYTES, 0, BUS_DMA_WAITOK, &txb->tb_map); 1013 txb->tb_m = NULL; 1014 1015 sc->sc_txdesc[i].sd_next = 1016 DWGE_DMA_DVA(sc->sc_txring) + 1017 ((i+1) % DWGE_NTXDESC) * sizeof(struct dwge_desc); 1018 } 1019 1020 bus_dmamap_sync(sc->sc_dmat, DWGE_DMA_MAP(sc->sc_txring), 1021 0, DWGE_DMA_LEN(sc->sc_txring), BUS_DMASYNC_PREWRITE); 1022 1023 sc->sc_tx_prod = sc->sc_tx_cons = 0; 1024 sc->sc_tx_cnt = 0; 1025 1026 dwge_write(sc, GMAC_TX_DESC_LIST_ADDR, DWGE_DMA_DVA(sc->sc_txring)); 1027 1028 /* Allocate descriptor ring. */ 1029 sc->sc_rxring = dwge_dmamem_alloc(sc, 1030 DWGE_NRXDESC * sizeof(struct dwge_desc), 8); 1031 sc->sc_rxdesc = DWGE_DMA_KVA(sc->sc_rxring); 1032 1033 sc->sc_rxbuf = malloc(sizeof(struct dwge_buf) * DWGE_NRXDESC, 1034 M_DEVBUF, M_WAITOK); 1035 1036 for (i = 0; i < DWGE_NRXDESC; i++) { 1037 rxb = &sc->sc_rxbuf[i]; 1038 bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1039 MCLBYTES, 0, BUS_DMA_WAITOK, &rxb->tb_map); 1040 rxb->tb_m = NULL; 1041 1042 sc->sc_rxdesc[i].sd_next = 1043 DWGE_DMA_DVA(sc->sc_rxring) + 1044 ((i+1) % DWGE_NRXDESC) * sizeof(struct dwge_desc); 1045 } 1046 1047 if_rxr_init(&sc->sc_rx_ring, 2, DWGE_NRXDESC); 1048 1049 sc->sc_rx_prod = sc->sc_rx_cons = 0; 1050 dwge_fill_rx_ring(sc); 1051 1052 bus_dmamap_sync(sc->sc_dmat, DWGE_DMA_MAP(sc->sc_rxring), 1053 0, DWGE_DMA_LEN(sc->sc_rxring), 1054 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1055 1056 dwge_write(sc, GMAC_RX_DESC_LIST_ADDR, DWGE_DMA_DVA(sc->sc_rxring)); 1057 1058 dwge_lladdr_write(sc); 1059 1060 /* Configure media. */ 1061 if (LIST_FIRST(&sc->sc_mii.mii_phys)) 1062 mii_mediachg(&sc->sc_mii); 1063 1064 /* Program promiscuous mode and multicast filters. */ 1065 dwge_iff(sc); 1066 1067 ifp->if_flags |= IFF_RUNNING; 1068 ifq_clr_oactive(&ifp->if_snd); 1069 1070 dwge_write(sc, GMAC_INT_ENA, GMAC_INT_ENA_NIE | 1071 GMAC_INT_ENA_RIE | GMAC_INT_ENA_TIE | GMAC_INT_ENA_TUE); 1072 1073 mode = dwge_read(sc, GMAC_OP_MODE); 1074 if (sc->sc_force_thresh_dma_mode) { 1075 mode &= ~(GMAC_OP_MODE_TSF | GMAC_OP_MODE_TTC_MASK); 1076 mode |= GMAC_OP_MODE_TTC_128; 1077 mode &= ~(GMAC_OP_MODE_RSF | GMAC_OP_MODE_RTC_MASK); 1078 mode |= GMAC_OP_MODE_RTC_128; 1079 } else { 1080 mode |= GMAC_OP_MODE_TSF | GMAC_OP_MODE_OSF; 1081 mode |= GMAC_OP_MODE_RSF; 1082 } 1083 dwge_write(sc, GMAC_OP_MODE, mode | GMAC_OP_MODE_ST | GMAC_OP_MODE_SR); 1084 1085 dwge_write(sc, GMAC_MAC_CONF, dwge_read(sc, GMAC_MAC_CONF) | 1086 GMAC_MAC_CONF_TE | GMAC_MAC_CONF_RE); 1087 1088 timeout_add_sec(&sc->sc_tick, 1); 1089 } 1090 1091 void 1092 dwge_down(struct dwge_softc *sc) 1093 { 1094 struct ifnet *ifp = &sc->sc_ac.ac_if; 1095 struct dwge_buf *txb, *rxb; 1096 uint32_t dmactrl; 1097 int i; 1098 1099 timeout_del(&sc->sc_rxto); 1100 timeout_del(&sc->sc_tick); 1101 1102 ifp->if_flags &= ~IFF_RUNNING; 1103 ifq_clr_oactive(&ifp->if_snd); 1104 ifp->if_timer = 0; 1105 1106 dwge_stop_dma(sc); 1107 1108 dwge_write(sc, GMAC_MAC_CONF, dwge_read(sc, 1109 GMAC_MAC_CONF) & ~(GMAC_MAC_CONF_TE | GMAC_MAC_CONF_RE)); 1110 1111 dmactrl = dwge_read(sc, GMAC_OP_MODE); 1112 dmactrl &= ~(GMAC_OP_MODE_ST | GMAC_OP_MODE_SR); 1113 dwge_write(sc, GMAC_OP_MODE, dmactrl); 1114 1115 dwge_write(sc, GMAC_INT_ENA, 0); 1116 1117 for (i = 0; i < DWGE_NTXDESC; i++) { 1118 txb = &sc->sc_txbuf[i]; 1119 if (txb->tb_m) { 1120 bus_dmamap_sync(sc->sc_dmat, txb->tb_map, 0, 1121 txb->tb_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1122 bus_dmamap_unload(sc->sc_dmat, txb->tb_map); 1123 m_freem(txb->tb_m); 1124 } 1125 bus_dmamap_destroy(sc->sc_dmat, txb->tb_map); 1126 } 1127 1128 dwge_dmamem_free(sc, sc->sc_txring); 1129 free(sc->sc_txbuf, M_DEVBUF, 0); 1130 1131 for (i = 0; i < DWGE_NRXDESC; i++) { 1132 rxb = &sc->sc_rxbuf[i]; 1133 if (rxb->tb_m) { 1134 bus_dmamap_sync(sc->sc_dmat, rxb->tb_map, 0, 1135 rxb->tb_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1136 bus_dmamap_unload(sc->sc_dmat, rxb->tb_map); 1137 m_freem(rxb->tb_m); 1138 } 1139 bus_dmamap_destroy(sc->sc_dmat, rxb->tb_map); 1140 } 1141 1142 dwge_dmamem_free(sc, sc->sc_rxring); 1143 free(sc->sc_rxbuf, M_DEVBUF, 0); 1144 } 1145 1146 /* Bit Reversal - http://aggregate.org/MAGIC/#Bit%20Reversal */ 1147 static uint32_t 1148 bitrev32(uint32_t x) 1149 { 1150 x = (((x & 0xaaaaaaaa) >> 1) | ((x & 0x55555555) << 1)); 1151 x = (((x & 0xcccccccc) >> 2) | ((x & 0x33333333) << 2)); 1152 x = (((x & 0xf0f0f0f0) >> 4) | ((x & 0x0f0f0f0f) << 4)); 1153 x = (((x & 0xff00ff00) >> 8) | ((x & 0x00ff00ff) << 8)); 1154 1155 return (x >> 16) | (x << 16); 1156 } 1157 1158 void 1159 dwge_iff(struct dwge_softc *sc) 1160 { 1161 struct arpcom *ac = &sc->sc_ac; 1162 struct ifnet *ifp = &sc->sc_ac.ac_if; 1163 struct ether_multi *enm; 1164 struct ether_multistep step; 1165 uint32_t crc, hash[2], hashbit, hashreg; 1166 uint32_t reg; 1167 1168 reg = 0; 1169 1170 ifp->if_flags &= ~IFF_ALLMULTI; 1171 bzero(hash, sizeof(hash)); 1172 if (ifp->if_flags & IFF_PROMISC || ac->ac_multirangecnt > 0) { 1173 ifp->if_flags |= IFF_ALLMULTI; 1174 reg |= GMAC_MAC_FRM_FILT_PM; 1175 if (ifp->if_flags & IFF_PROMISC) 1176 reg |= GMAC_MAC_FRM_FILT_PR; 1177 } else { 1178 reg |= GMAC_MAC_FRM_FILT_HMC; 1179 ETHER_FIRST_MULTI(step, ac, enm); 1180 while (enm != NULL) { 1181 crc = ether_crc32_le(enm->enm_addrlo, 1182 ETHER_ADDR_LEN) & 0x7f; 1183 1184 crc = bitrev32(~crc) >> 26; 1185 hashreg = (crc >> 5); 1186 hashbit = (crc & 0x1f); 1187 hash[hashreg] |= (1 << hashbit); 1188 1189 ETHER_NEXT_MULTI(step, enm); 1190 } 1191 } 1192 1193 dwge_lladdr_write(sc); 1194 1195 dwge_write(sc, GMAC_HASH_TAB_HI, hash[1]); 1196 dwge_write(sc, GMAC_HASH_TAB_LO, hash[0]); 1197 1198 dwge_write(sc, GMAC_MAC_FRM_FILT, reg); 1199 } 1200 1201 int 1202 dwge_encap(struct dwge_softc *sc, struct mbuf *m, int *idx) 1203 { 1204 struct dwge_desc *txd, *txd_start; 1205 bus_dmamap_t map; 1206 int cur, frag, i; 1207 1208 cur = frag = *idx; 1209 map = sc->sc_txbuf[cur].tb_map; 1210 1211 if (bus_dmamap_load_mbuf(sc->sc_dmat, map, m, BUS_DMA_NOWAIT)) { 1212 if (m_defrag(m, M_DONTWAIT)) 1213 return (EFBIG); 1214 if (bus_dmamap_load_mbuf(sc->sc_dmat, map, m, BUS_DMA_NOWAIT)) 1215 return (EFBIG); 1216 } 1217 1218 if (map->dm_nsegs > (DWGE_NTXDESC - sc->sc_tx_cnt - 2)) { 1219 bus_dmamap_unload(sc->sc_dmat, map); 1220 return (ENOBUFS); 1221 } 1222 1223 /* Sync the DMA map. */ 1224 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1225 BUS_DMASYNC_PREWRITE); 1226 1227 txd = txd_start = &sc->sc_txdesc[frag]; 1228 for (i = 0; i < map->dm_nsegs; i++) { 1229 txd->sd_addr = map->dm_segs[i].ds_addr; 1230 txd->sd_len = map->dm_segs[i].ds_len | TDES1_TCH; 1231 if (i == 0) 1232 txd->sd_len |= TDES1_FS; 1233 if (i == (map->dm_nsegs - 1)) 1234 txd->sd_len |= TDES1_LS | TDES1_IC; 1235 if (i != 0) 1236 txd->sd_status = TDES0_OWN; 1237 1238 bus_dmamap_sync(sc->sc_dmat, DWGE_DMA_MAP(sc->sc_txring), 1239 frag * sizeof(*txd), sizeof(*txd), BUS_DMASYNC_PREWRITE); 1240 1241 cur = frag; 1242 if (frag == (DWGE_NTXDESC - 1)) { 1243 txd = &sc->sc_txdesc[0]; 1244 frag = 0; 1245 } else { 1246 txd++; 1247 frag++; 1248 } 1249 KASSERT(frag != sc->sc_tx_cons); 1250 } 1251 1252 txd_start->sd_status = TDES0_OWN; 1253 bus_dmamap_sync(sc->sc_dmat, DWGE_DMA_MAP(sc->sc_txring), 1254 *idx * sizeof(*txd), sizeof(*txd), BUS_DMASYNC_PREWRITE); 1255 1256 dwge_write(sc, GMAC_TX_POLL_DEMAND, 0xffffffff); 1257 1258 KASSERT(sc->sc_txbuf[cur].tb_m == NULL); 1259 sc->sc_txbuf[*idx].tb_map = sc->sc_txbuf[cur].tb_map; 1260 sc->sc_txbuf[cur].tb_map = map; 1261 sc->sc_txbuf[cur].tb_m = m; 1262 1263 sc->sc_tx_cnt += map->dm_nsegs; 1264 *idx = frag; 1265 1266 return (0); 1267 } 1268 1269 void 1270 dwge_reset(struct dwge_softc *sc) 1271 { 1272 int n; 1273 1274 dwge_stop_dma(sc); 1275 1276 dwge_write(sc, GMAC_BUS_MODE, dwge_read(sc, GMAC_BUS_MODE) | 1277 GMAC_BUS_MODE_SWR); 1278 1279 for (n = 0; n < 30000; n++) { 1280 if ((dwge_read(sc, GMAC_BUS_MODE) & 1281 GMAC_BUS_MODE_SWR) == 0) 1282 return; 1283 delay(10); 1284 } 1285 1286 printf("%s: reset timeout\n", sc->sc_dev.dv_xname); 1287 } 1288 1289 void 1290 dwge_stop_dma(struct dwge_softc *sc) 1291 { 1292 uint32_t dmactrl; 1293 1294 /* Stop DMA. */ 1295 dmactrl = dwge_read(sc, GMAC_OP_MODE); 1296 dmactrl &= ~GMAC_OP_MODE_ST; 1297 dmactrl |= GMAC_OP_MODE_FTF; 1298 dwge_write(sc, GMAC_OP_MODE, dmactrl); 1299 } 1300 1301 struct dwge_dmamem * 1302 dwge_dmamem_alloc(struct dwge_softc *sc, bus_size_t size, bus_size_t align) 1303 { 1304 struct dwge_dmamem *tdm; 1305 int nsegs; 1306 1307 tdm = malloc(sizeof(*tdm), M_DEVBUF, M_WAITOK | M_ZERO); 1308 tdm->tdm_size = size; 1309 1310 if (bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 1311 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, &tdm->tdm_map) != 0) 1312 goto tdmfree; 1313 1314 if (bus_dmamem_alloc(sc->sc_dmat, size, align, 0, &tdm->tdm_seg, 1, 1315 &nsegs, BUS_DMA_WAITOK) != 0) 1316 goto destroy; 1317 1318 if (bus_dmamem_map(sc->sc_dmat, &tdm->tdm_seg, nsegs, size, 1319 &tdm->tdm_kva, BUS_DMA_WAITOK | BUS_DMA_COHERENT) != 0) 1320 goto free; 1321 1322 if (bus_dmamap_load(sc->sc_dmat, tdm->tdm_map, tdm->tdm_kva, size, 1323 NULL, BUS_DMA_WAITOK) != 0) 1324 goto unmap; 1325 1326 bzero(tdm->tdm_kva, size); 1327 1328 return (tdm); 1329 1330 unmap: 1331 bus_dmamem_unmap(sc->sc_dmat, tdm->tdm_kva, size); 1332 free: 1333 bus_dmamem_free(sc->sc_dmat, &tdm->tdm_seg, 1); 1334 destroy: 1335 bus_dmamap_destroy(sc->sc_dmat, tdm->tdm_map); 1336 tdmfree: 1337 free(tdm, M_DEVBUF, 0); 1338 1339 return (NULL); 1340 } 1341 1342 void 1343 dwge_dmamem_free(struct dwge_softc *sc, struct dwge_dmamem *tdm) 1344 { 1345 bus_dmamem_unmap(sc->sc_dmat, tdm->tdm_kva, tdm->tdm_size); 1346 bus_dmamem_free(sc->sc_dmat, &tdm->tdm_seg, 1); 1347 bus_dmamap_destroy(sc->sc_dmat, tdm->tdm_map); 1348 free(tdm, M_DEVBUF, 0); 1349 } 1350 1351 struct mbuf * 1352 dwge_alloc_mbuf(struct dwge_softc *sc, bus_dmamap_t map) 1353 { 1354 struct mbuf *m = NULL; 1355 1356 m = MCLGETL(NULL, M_DONTWAIT, MCLBYTES); 1357 if (!m) 1358 return (NULL); 1359 m->m_len = m->m_pkthdr.len = MCLBYTES; 1360 m_adj(m, ETHER_ALIGN); 1361 1362 if (bus_dmamap_load_mbuf(sc->sc_dmat, map, m, BUS_DMA_NOWAIT) != 0) { 1363 printf("%s: could not load mbuf DMA map", DEVNAME(sc)); 1364 m_freem(m); 1365 return (NULL); 1366 } 1367 1368 bus_dmamap_sync(sc->sc_dmat, map, 0, 1369 m->m_pkthdr.len, BUS_DMASYNC_PREREAD); 1370 1371 return (m); 1372 } 1373 1374 void 1375 dwge_fill_rx_ring(struct dwge_softc *sc) 1376 { 1377 struct dwge_desc *rxd; 1378 struct dwge_buf *rxb; 1379 u_int slots; 1380 1381 for (slots = if_rxr_get(&sc->sc_rx_ring, DWGE_NRXDESC); 1382 slots > 0; slots--) { 1383 rxb = &sc->sc_rxbuf[sc->sc_rx_prod]; 1384 rxb->tb_m = dwge_alloc_mbuf(sc, rxb->tb_map); 1385 if (rxb->tb_m == NULL) 1386 break; 1387 1388 rxd = &sc->sc_rxdesc[sc->sc_rx_prod]; 1389 rxd->sd_len = rxb->tb_map->dm_segs[0].ds_len | RDES1_RCH; 1390 rxd->sd_addr = rxb->tb_map->dm_segs[0].ds_addr; 1391 rxd->sd_status = RDES0_OWN; 1392 1393 if (sc->sc_rx_prod == (DWGE_NRXDESC - 1)) 1394 sc->sc_rx_prod = 0; 1395 else 1396 sc->sc_rx_prod++; 1397 } 1398 if_rxr_put(&sc->sc_rx_ring, slots); 1399 1400 if (if_rxr_inuse(&sc->sc_rx_ring) == 0) 1401 timeout_add(&sc->sc_rxto, 1); 1402 } 1403 1404 /* 1405 * Allwinner A20/A31. 1406 */ 1407 1408 void 1409 dwge_setup_allwinner(struct dwge_softc *sc) 1410 { 1411 char phy_mode[8]; 1412 uint32_t freq; 1413 1414 /* default to RGMII */ 1415 OF_getprop(sc->sc_node, "phy-mode", phy_mode, sizeof(phy_mode)); 1416 if (strcmp(phy_mode, "mii") == 0) 1417 freq = 25000000; 1418 else 1419 freq = 125000000; 1420 clock_set_frequency(sc->sc_node, "allwinner_gmac_tx", freq); 1421 } 1422 1423 /* 1424 * Rockchip RK3288/RK3399. 1425 */ 1426 1427 /* RK3308 registers */ 1428 #define RK3308_GRF_MAC_CON0 0x04a0 1429 #define RK3308_MAC_SPEED_100M ((0x1 << 0) << 16 | (0x1 << 0)) 1430 #define RK3308_MAC_SPEED_10M ((0x1 << 0) << 16 | (0x0 << 0)) 1431 #define RK3308_INTF_SEL_RMII ((0x1 << 4) << 16 | (0x1 << 4)) 1432 1433 /* RK3288 registers */ 1434 #define RK3288_GRF_SOC_CON1 0x0248 1435 #define RK3288_GMAC_PHY_INTF_SEL_RGMII ((0x7 << 6) << 16 | (0x1 << 6)) 1436 #define RK3288_GMAC_PHY_INTF_SEL_RMII ((0x7 << 6) << 16 | (0x4 << 6)) 1437 #define RK3288_RMII_MODE_RMII ((1 << 14) << 16 | (1 << 14)) 1438 #define RK3288_RMII_MODE_MII ((1 << 14) << 16 | (0 << 14)) 1439 #define RK3288_GMAC_CLK_SEL_125 ((0x3 << 12) << 16 | (0x0 << 12)) 1440 #define RK3288_GMAC_CLK_SEL_25 ((0x3 << 12) << 16 | (0x3 << 12)) 1441 #define RK3288_GMAC_CLK_SEL_2_5 ((0x3 << 12) << 16 | (0x2 << 12)) 1442 1443 #define RK3288_GRF_SOC_CON3 0x0250 1444 #define RK3288_GMAC_RXCLK_DLY_ENA ((1 << 15) << 16 | (1 << 15)) 1445 #define RK3288_GMAC_CLK_RX_DL_CFG(val) ((0x7f << 7) << 16 | ((val) << 7)) 1446 #define RK3288_GMAC_TXCLK_DLY_ENA ((1 << 14) << 16 | (1 << 14)) 1447 #define RK3288_GMAC_CLK_TX_DL_CFG(val) ((0x7f << 0) << 16 | ((val) << 0)) 1448 1449 /* RK3328 registers */ 1450 #define RK3328_GRF_MAC_CON0 0x0900 1451 #define RK3328_GMAC_CLK_RX_DL_CFG(val) ((0x7f << 7) << 16 | ((val) << 7)) 1452 #define RK3328_GMAC_CLK_TX_DL_CFG(val) ((0x7f << 0) << 16 | ((val) << 0)) 1453 1454 #define RK3328_GRF_MAC_CON1 0x0904 1455 #define RK3328_GMAC_PHY_INTF_SEL_RGMII ((0x7 << 4) << 16 | (0x1 << 4)) 1456 #define RK3328_GMAC_PHY_INTF_SEL_RMII ((0x7 << 4) << 16 | (0x4 << 4)) 1457 #define RK3328_RMII_MODE_RMII ((1 << 9) << 16 | (1 << 9)) 1458 #define RK3328_RMII_MODE_MII ((1 << 9) << 16 | (0 << 9)) 1459 #define RK3328_GMAC_CLK_SEL_125 ((0x3 << 11) << 16 | (0x0 << 11)) 1460 #define RK3328_GMAC_CLK_SEL_25 ((0x3 << 11) << 16 | (0x3 << 11)) 1461 #define RK3328_GMAC_CLK_SEL_2_5 ((0x3 << 11) << 16 | (0x2 << 11)) 1462 #define RK3328_GMAC_RXCLK_DLY_ENA ((1 << 1) << 16 | (1 << 1)) 1463 #define RK3328_GMAC_TXCLK_DLY_ENA ((1 << 0) << 16 | (1 << 0)) 1464 1465 /* RK3399 registers */ 1466 #define RK3399_GRF_SOC_CON5 0xc214 1467 #define RK3399_GMAC_PHY_INTF_SEL_RGMII ((0x7 << 9) << 16 | (0x1 << 9)) 1468 #define RK3399_GMAC_PHY_INTF_SEL_RMII ((0x7 << 9) << 16 | (0x4 << 9)) 1469 #define RK3399_RMII_MODE_RMII ((1 << 6) << 16 | (1 << 6)) 1470 #define RK3399_RMII_MODE_MII ((1 << 6) << 16 | (0 << 6)) 1471 #define RK3399_GMAC_CLK_SEL_125 ((0x3 << 4) << 16 | (0x0 << 4)) 1472 #define RK3399_GMAC_CLK_SEL_25 ((0x3 << 4) << 16 | (0x3 << 4)) 1473 #define RK3399_GMAC_CLK_SEL_2_5 ((0x3 << 4) << 16 | (0x2 << 4)) 1474 #define RK3399_GRF_SOC_CON6 0xc218 1475 #define RK3399_GMAC_RXCLK_DLY_ENA ((1 << 15) << 16 | (1 << 15)) 1476 #define RK3399_GMAC_CLK_RX_DL_CFG(val) ((0x7f << 8) << 16 | ((val) << 8)) 1477 #define RK3399_GMAC_TXCLK_DLY_ENA ((1 << 7) << 16 | (1 << 7)) 1478 #define RK3399_GMAC_CLK_TX_DL_CFG(val) ((0x7f << 0) << 16 | ((val) << 0)) 1479 1480 void dwge_mii_statchg_rockchip(struct device *); 1481 1482 void 1483 dwge_setup_rockchip(struct dwge_softc *sc) 1484 { 1485 struct regmap *rm; 1486 uint32_t grf; 1487 int tx_delay, rx_delay; 1488 char clock_mode[8]; 1489 1490 grf = OF_getpropint(sc->sc_node, "rockchip,grf", 0); 1491 rm = regmap_byphandle(grf); 1492 if (rm == NULL) 1493 return; 1494 1495 clock_set_assigned(sc->sc_node); 1496 clock_enable(sc->sc_node, "mac_clk_rx"); 1497 clock_enable(sc->sc_node, "mac_clk_tx"); 1498 clock_enable(sc->sc_node, "aclk_mac"); 1499 clock_enable(sc->sc_node, "pclk_mac"); 1500 1501 tx_delay = OF_getpropint(sc->sc_node, "tx_delay", 0x30); 1502 rx_delay = OF_getpropint(sc->sc_node, "rx_delay", 0x10); 1503 1504 if (OF_is_compatible(sc->sc_node, "rockchip,rk3288-gmac")) { 1505 /* Use RGMII interface. */ 1506 regmap_write_4(rm, RK3288_GRF_SOC_CON1, 1507 RK3288_GMAC_PHY_INTF_SEL_RGMII | RK3288_RMII_MODE_MII); 1508 1509 /* Program clock delay lines. */ 1510 regmap_write_4(rm, RK3288_GRF_SOC_CON3, 1511 RK3288_GMAC_TXCLK_DLY_ENA | RK3288_GMAC_RXCLK_DLY_ENA | 1512 RK3288_GMAC_CLK_TX_DL_CFG(tx_delay) | 1513 RK3288_GMAC_CLK_RX_DL_CFG(rx_delay)); 1514 1515 /* Clock speed bits. */ 1516 sc->sc_clk_sel = RK3288_GRF_SOC_CON1; 1517 sc->sc_clk_sel_2_5 = RK3288_GMAC_CLK_SEL_2_5; 1518 sc->sc_clk_sel_25 = RK3288_GMAC_CLK_SEL_25; 1519 sc->sc_clk_sel_125 = RK3288_GMAC_CLK_SEL_125; 1520 } else if (OF_is_compatible(sc->sc_node, "rockchip,rk3308-mac")) { 1521 /* Use RMII interface. */ 1522 regmap_write_4(rm, RK3308_GRF_MAC_CON0, 1523 RK3308_INTF_SEL_RMII | RK3308_MAC_SPEED_100M); 1524 1525 /* Adjust MAC clock if necessary. */ 1526 OF_getprop(sc->sc_node, "clock_in_out", clock_mode, 1527 sizeof(clock_mode)); 1528 if (strcmp(clock_mode, "output") == 0) { 1529 clock_set_frequency(sc->sc_node, "stmmaceth", 1530 50000000); 1531 sc->sc_clk = GMAC_GMII_ADDR_CR_DIV_26; 1532 } 1533 1534 /* Clock speed bits. */ 1535 sc->sc_clk_sel = RK3308_GRF_MAC_CON0; 1536 sc->sc_clk_sel_2_5 = RK3308_MAC_SPEED_10M; 1537 sc->sc_clk_sel_25 = RK3308_MAC_SPEED_100M; 1538 } else if (OF_is_compatible(sc->sc_node, "rockchip,rk3328-gmac")) { 1539 /* Use RGMII interface. */ 1540 regmap_write_4(rm, RK3328_GRF_MAC_CON1, 1541 RK3328_GMAC_PHY_INTF_SEL_RGMII | RK3328_RMII_MODE_MII); 1542 1543 /* Program clock delay lines. */ 1544 regmap_write_4(rm, RK3328_GRF_MAC_CON0, 1545 RK3328_GMAC_CLK_TX_DL_CFG(tx_delay) | 1546 RK3328_GMAC_CLK_RX_DL_CFG(rx_delay)); 1547 regmap_write_4(rm, RK3328_GRF_MAC_CON1, 1548 RK3328_GMAC_TXCLK_DLY_ENA | RK3328_GMAC_RXCLK_DLY_ENA); 1549 1550 /* Clock speed bits. */ 1551 sc->sc_clk_sel = RK3328_GRF_MAC_CON1; 1552 sc->sc_clk_sel_2_5 = RK3328_GMAC_CLK_SEL_2_5; 1553 sc->sc_clk_sel_25 = RK3328_GMAC_CLK_SEL_25; 1554 sc->sc_clk_sel_125 = RK3328_GMAC_CLK_SEL_125; 1555 } else { 1556 /* Use RGMII interface. */ 1557 regmap_write_4(rm, RK3399_GRF_SOC_CON5, 1558 RK3399_GMAC_PHY_INTF_SEL_RGMII | RK3399_RMII_MODE_MII); 1559 1560 /* Program clock delay lines. */ 1561 regmap_write_4(rm, RK3399_GRF_SOC_CON6, 1562 RK3399_GMAC_TXCLK_DLY_ENA | RK3399_GMAC_RXCLK_DLY_ENA | 1563 RK3399_GMAC_CLK_TX_DL_CFG(tx_delay) | 1564 RK3399_GMAC_CLK_RX_DL_CFG(rx_delay)); 1565 1566 /* Clock speed bits. */ 1567 sc->sc_clk_sel = RK3399_GRF_SOC_CON5; 1568 sc->sc_clk_sel_2_5 = RK3399_GMAC_CLK_SEL_2_5; 1569 sc->sc_clk_sel_25 = RK3399_GMAC_CLK_SEL_25; 1570 sc->sc_clk_sel_125 = RK3399_GMAC_CLK_SEL_125; 1571 } 1572 1573 sc->sc_mii.mii_statchg = dwge_mii_statchg_rockchip; 1574 } 1575 1576 void 1577 dwge_mii_statchg_rockchip(struct device *self) 1578 { 1579 struct dwge_softc *sc = (void *)self; 1580 struct regmap *rm; 1581 uint32_t grf; 1582 uint32_t gmac_clk_sel = 0; 1583 1584 dwge_mii_statchg(self); 1585 1586 grf = OF_getpropint(sc->sc_node, "rockchip,grf", 0); 1587 rm = regmap_byphandle(grf); 1588 if (rm == NULL) 1589 return; 1590 1591 switch (IFM_SUBTYPE(sc->sc_mii.mii_media_active)) { 1592 case IFM_10_T: 1593 gmac_clk_sel = sc->sc_clk_sel_2_5; 1594 break; 1595 case IFM_100_TX: 1596 gmac_clk_sel = sc->sc_clk_sel_25; 1597 break; 1598 case IFM_1000_T: 1599 gmac_clk_sel = sc->sc_clk_sel_125; 1600 break; 1601 } 1602 1603 regmap_write_4(rm, sc->sc_clk_sel, gmac_clk_sel); 1604 } 1605