1 /* $OpenBSD: if_dwge.c,v 1.11 2021/10/22 14:28:54 kettenis Exp $ */ 2 /* 3 * Copyright (c) 2008, 2019 Mark Kettenis <kettenis@openbsd.org> 4 * Copyright (c) 2017 Patrick Wildt <patrick@blueri.se> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * Driver for the Synopsys Designware ethernet controller. 21 */ 22 23 #include "bpfilter.h" 24 25 #include <sys/param.h> 26 #include <sys/systm.h> 27 #include <sys/device.h> 28 #include <sys/kernel.h> 29 #include <sys/malloc.h> 30 #include <sys/mbuf.h> 31 #include <sys/queue.h> 32 #include <sys/socket.h> 33 #include <sys/sockio.h> 34 #include <sys/timeout.h> 35 36 #include <machine/bus.h> 37 #include <machine/fdt.h> 38 39 #include <net/if.h> 40 #include <net/if_media.h> 41 42 #include <dev/ofw/openfirm.h> 43 #include <dev/ofw/ofw_clock.h> 44 #include <dev/ofw/ofw_gpio.h> 45 #include <dev/ofw/ofw_misc.h> 46 #include <dev/ofw/ofw_pinctrl.h> 47 #include <dev/ofw/ofw_regulator.h> 48 #include <dev/ofw/fdt.h> 49 50 #include <dev/mii/mii.h> 51 #include <dev/mii/miivar.h> 52 53 #if NBPFILTER > 0 54 #include <net/bpf.h> 55 #endif 56 57 #include <netinet/in.h> 58 #include <netinet/if_ether.h> 59 60 /* Registers */ 61 62 #define GMAC_MAC_CONF 0x0000 63 #define GMAC_MAC_CONF_JD (1 << 22) 64 #define GMAC_MAC_CONF_BE (1 << 21) 65 #define GMAC_MAC_CONF_DCRS (1 << 16) 66 #define GMAC_MAC_CONF_PS (1 << 15) 67 #define GMAC_MAC_CONF_FES (1 << 14) 68 #define GMAC_MAC_CONF_LM (1 << 12) 69 #define GMAC_MAC_CONF_DM (1 << 11) 70 #define GMAC_MAC_CONF_TE (1 << 3) 71 #define GMAC_MAC_CONF_RE (1 << 2) 72 #define GMAC_MAC_FRM_FILT 0x0004 73 #define GMAC_MAC_FRM_FILT_PM (1 << 4) 74 #define GMAC_MAC_FRM_FILT_HMC (1 << 2) 75 #define GMAC_MAC_FRM_FILT_PR (1 << 0) 76 #define GMAC_HASH_TAB_HI 0x0008 77 #define GMAC_HASH_TAB_LO 0x000c 78 #define GMAC_GMII_ADDR 0x0010 79 #define GMAC_GMII_ADDR_PA_SHIFT 11 80 #define GMAC_GMII_ADDR_GR_SHIFT 6 81 #define GMAC_GMII_ADDR_CR_SHIFT 2 82 #define GMAC_GMII_ADDR_CR_MASK 0xf 83 #define GMAC_GMII_ADDR_CR_DIV_42 0 84 #define GMAC_GMII_ADDR_CR_DIV_62 1 85 #define GMAC_GMII_ADDR_CR_DIV_16 2 86 #define GMAC_GMII_ADDR_CR_DIV_26 3 87 #define GMAC_GMII_ADDR_CR_DIV_102 4 88 #define GMAC_GMII_ADDR_CR_DIV_124 5 89 #define GMAC_GMII_ADDR_GW (1 << 1) 90 #define GMAC_GMII_ADDR_GB (1 << 0) 91 #define GMAC_GMII_DATA 0x0014 92 #define GMAC_VERSION 0x0020 93 #define GMAC_VERSION_SNPS_MASK 0xff 94 #define GMAC_INT_MASK 0x003c 95 #define GMAC_INT_MASK_LPIIM (1 << 10) 96 #define GMAC_INT_MASK_PIM (1 << 3) 97 #define GMAC_INT_MASK_RIM (1 << 0) 98 #define GMAC_MAC_ADDR0_HI 0x0040 99 #define GMAC_MAC_ADDR0_LO 0x0044 100 #define GMAC_MMC_RX_INT_MSK 0x010c 101 #define GMAC_MMC_TX_INT_MSK 0x0110 102 #define GMAC_MMC_IPC_INT_MSK 0x0200 103 #define GMAC_BUS_MODE 0x1000 104 #define GMAC_BUS_MODE_8XPBL (1 << 24) 105 #define GMAC_BUS_MODE_USP (1 << 23) 106 #define GMAC_BUS_MODE_RPBL_MASK (0x3f << 17) 107 #define GMAC_BUS_MODE_RPBL_SHIFT 17 108 #define GMAC_BUS_MODE_FB (1 << 16) 109 #define GMAC_BUS_MODE_PBL_MASK (0x3f << 8) 110 #define GMAC_BUS_MODE_PBL_SHIFT 8 111 #define GMAC_BUS_MODE_SWR (1 << 0) 112 #define GMAC_TX_POLL_DEMAND 0x1004 113 #define GMAC_RX_DESC_LIST_ADDR 0x100c 114 #define GMAC_TX_DESC_LIST_ADDR 0x1010 115 #define GMAC_STATUS 0x1014 116 #define GMAC_STATUS_RI (1 << 6) 117 #define GMAC_STATUS_TU (1 << 2) 118 #define GMAC_STATUS_TI (1 << 0) 119 #define GMAC_OP_MODE 0x1018 120 #define GMAC_OP_MODE_RSF (1 << 25) 121 #define GMAC_OP_MODE_TSF (1 << 21) 122 #define GMAC_OP_MODE_FTF (1 << 20) 123 #define GMAC_OP_MODE_TTC_MASK (0x7 << 14) 124 #define GMAC_OP_MODE_TTC_64 (0x0 << 14) 125 #define GMAC_OP_MODE_TTC_128 (0x1 << 14) 126 #define GMAC_OP_MODE_ST (1 << 13) 127 #define GMAC_OP_MODE_RTC_MASK (0x3 << 3) 128 #define GMAC_OP_MODE_RTC_64 (0x0 << 3) 129 #define GMAC_OP_MODE_RTC_128 (0x3 << 3) 130 #define GMAC_OP_MODE_OSF (1 << 2) 131 #define GMAC_OP_MODE_SR (1 << 1) 132 #define GMAC_INT_ENA 0x101c 133 #define GMAC_INT_ENA_NIE (1 << 16) 134 #define GMAC_INT_ENA_RIE (1 << 6) 135 #define GMAC_INT_ENA_TUE (1 << 2) 136 #define GMAC_INT_ENA_TIE (1 << 0) 137 #define GMAC_AXI_BUS_MODE 0x1028 138 #define GMAC_AXI_BUS_MODE_WR_OSR_LMT_MASK (0xf << 20) 139 #define GMAC_AXI_BUS_MODE_WR_OSR_LMT_SHIFT 20 140 #define GMAC_AXI_BUS_MODE_RD_OSR_LMT_MASK (0xf << 16) 141 #define GMAC_AXI_BUS_MODE_RD_OSR_LMT_SHIFT 16 142 #define GMAC_AXI_BUS_MODE_BLEN_256 (1 << 7) 143 #define GMAC_AXI_BUS_MODE_BLEN_128 (1 << 6) 144 #define GMAC_AXI_BUS_MODE_BLEN_64 (1 << 5) 145 #define GMAC_AXI_BUS_MODE_BLEN_32 (1 << 4) 146 #define GMAC_AXI_BUS_MODE_BLEN_16 (1 << 3) 147 #define GMAC_AXI_BUS_MODE_BLEN_8 (1 << 2) 148 #define GMAC_AXI_BUS_MODE_BLEN_4 (1 << 1) 149 150 /* 151 * DWGE descriptors. 152 */ 153 154 struct dwge_desc { 155 uint32_t sd_status; 156 uint32_t sd_len; 157 uint32_t sd_addr; 158 uint32_t sd_next; 159 }; 160 161 /* Tx status bits. */ 162 #define TDES0_DB (1 << 0) 163 #define TDES0_UF (1 << 1) 164 #define TDES0_ED (1 << 2) 165 #define TDES0_CC_MASK (0xf << 3) 166 #define TDES0_CC_SHIFT 3 167 #define TDES0_EC (1 << 8) 168 #define TDES0_LC (1 << 9) 169 #define TDES0_NC (1 << 10) 170 #define TDES0_PCE (1 << 12) 171 #define TDES0_JT (1 << 14) 172 #define TDES0_IHE (1 << 16) 173 #define TDES0_OWN (1 << 31) 174 175 /* Rx status bits */ 176 #define RDES0_PE (1 << 0) 177 #define RDES0_CE (1 << 1) 178 #define RDES0_RE (1 << 3) 179 #define RDES0_RWT (1 << 4) 180 #define RDES0_FT (1 << 5) 181 #define RDES0_LC (1 << 6) 182 #define RDES0_IPC (1 << 7) 183 #define RDES0_LS (1 << 8) 184 #define RDES0_FS (1 << 9) 185 #define RDES0_OE (1 << 11) 186 #define RDES0_SAF (1 << 13) 187 #define RDES0_DE (1 << 14) 188 #define RDES0_FL_MASK 0x3fff 189 #define RDES0_FL_SHIFT 16 190 #define RDES0_AFM (1 << 30) 191 #define RDES0_OWN (1 << 31) 192 193 /* Tx size bits */ 194 #define TDES1_TBS1 (0xfff << 0) 195 #define TDES1_TCH (1 << 24) 196 #define TDES1_DC (1 << 26) 197 #define TDES1_CIC_MASK (0x3 << 27) 198 #define TDES1_CIC_IP (1 << 27) 199 #define TDES1_CIC_NO_PSE (2 << 27) 200 #define TDES1_CIC_FULL (3 << 27) 201 #define TDES1_FS (1 << 29) 202 #define TDES1_LS (1 << 30) 203 #define TDES1_IC (1 << 31) 204 205 /* Rx size bits */ 206 #define RDES1_RBS1 (0xfff << 0) 207 #define RDES1_RCH (1 << 24) 208 #define RDES1_DIC (1 << 31) 209 210 struct dwge_buf { 211 bus_dmamap_t tb_map; 212 struct mbuf *tb_m; 213 }; 214 215 #define DWGE_NTXDESC 512 216 #define DWGE_NTXSEGS 16 217 218 #define DWGE_NRXDESC 512 219 220 struct dwge_dmamem { 221 bus_dmamap_t tdm_map; 222 bus_dma_segment_t tdm_seg; 223 size_t tdm_size; 224 caddr_t tdm_kva; 225 }; 226 #define DWGE_DMA_MAP(_tdm) ((_tdm)->tdm_map) 227 #define DWGE_DMA_LEN(_tdm) ((_tdm)->tdm_size) 228 #define DWGE_DMA_DVA(_tdm) ((_tdm)->tdm_map->dm_segs[0].ds_addr) 229 #define DWGE_DMA_KVA(_tdm) ((void *)(_tdm)->tdm_kva) 230 231 struct dwge_softc { 232 struct device sc_dev; 233 int sc_node; 234 bus_space_tag_t sc_iot; 235 bus_space_handle_t sc_ioh; 236 bus_dma_tag_t sc_dmat; 237 238 struct arpcom sc_ac; 239 #define sc_lladdr sc_ac.ac_enaddr 240 struct mii_data sc_mii; 241 #define sc_media sc_mii.mii_media 242 int sc_link; 243 int sc_phyloc; 244 int sc_force_thresh_dma_mode; 245 246 struct dwge_dmamem *sc_txring; 247 struct dwge_buf *sc_txbuf; 248 struct dwge_desc *sc_txdesc; 249 int sc_tx_prod; 250 int sc_tx_cnt; 251 int sc_tx_cons; 252 253 struct dwge_dmamem *sc_rxring; 254 struct dwge_buf *sc_rxbuf; 255 struct dwge_desc *sc_rxdesc; 256 int sc_rx_prod; 257 struct if_rxring sc_rx_ring; 258 int sc_rx_cons; 259 260 struct timeout sc_tick; 261 struct timeout sc_rxto; 262 263 uint32_t sc_clk; 264 265 bus_size_t sc_clk_sel; 266 uint32_t sc_clk_sel_125; 267 uint32_t sc_clk_sel_25; 268 uint32_t sc_clk_sel_2_5; 269 }; 270 271 #define DEVNAME(_s) ((_s)->sc_dev.dv_xname) 272 273 int dwge_match(struct device *, void *, void *); 274 void dwge_attach(struct device *, struct device *, void *); 275 void dwge_setup_allwinner(struct dwge_softc *); 276 void dwge_setup_rockchip(struct dwge_softc *); 277 278 struct cfattach dwge_ca = { 279 sizeof(struct dwge_softc), dwge_match, dwge_attach 280 }; 281 282 struct cfdriver dwge_cd = { 283 NULL, "dwge", DV_IFNET 284 }; 285 286 void dwge_reset_phy(struct dwge_softc *); 287 288 uint32_t dwge_read(struct dwge_softc *, bus_addr_t); 289 void dwge_write(struct dwge_softc *, bus_addr_t, uint32_t); 290 291 int dwge_ioctl(struct ifnet *, u_long, caddr_t); 292 void dwge_start(struct ifnet *); 293 void dwge_watchdog(struct ifnet *); 294 295 int dwge_media_change(struct ifnet *); 296 void dwge_media_status(struct ifnet *, struct ifmediareq *); 297 298 int dwge_mii_readreg(struct device *, int, int); 299 void dwge_mii_writereg(struct device *, int, int, int); 300 void dwge_mii_statchg(struct device *); 301 302 void dwge_lladdr_read(struct dwge_softc *, uint8_t *); 303 void dwge_lladdr_write(struct dwge_softc *); 304 305 void dwge_tick(void *); 306 void dwge_rxtick(void *); 307 308 int dwge_intr(void *); 309 void dwge_tx_proc(struct dwge_softc *); 310 void dwge_rx_proc(struct dwge_softc *); 311 312 void dwge_up(struct dwge_softc *); 313 void dwge_down(struct dwge_softc *); 314 void dwge_iff(struct dwge_softc *); 315 int dwge_encap(struct dwge_softc *, struct mbuf *, int *); 316 317 void dwge_reset(struct dwge_softc *); 318 void dwge_stop_dma(struct dwge_softc *); 319 320 struct dwge_dmamem * 321 dwge_dmamem_alloc(struct dwge_softc *, bus_size_t, bus_size_t); 322 void dwge_dmamem_free(struct dwge_softc *, struct dwge_dmamem *); 323 struct mbuf *dwge_alloc_mbuf(struct dwge_softc *, bus_dmamap_t); 324 void dwge_fill_rx_ring(struct dwge_softc *); 325 326 int 327 dwge_match(struct device *parent, void *cfdata, void *aux) 328 { 329 struct fdt_attach_args *faa = aux; 330 331 return (OF_is_compatible(faa->fa_node, "allwinner,sun7i-a20-gmac") || 332 OF_is_compatible(faa->fa_node, "amlogic,meson-axg-dwmac") || 333 OF_is_compatible(faa->fa_node, "amlogic,meson-g12a-dwmac") || 334 OF_is_compatible(faa->fa_node, "rockchip,rk3288-gmac") || 335 OF_is_compatible(faa->fa_node, "rockchip,rk3308-mac") || 336 OF_is_compatible(faa->fa_node, "rockchip,rk3328-gmac") || 337 OF_is_compatible(faa->fa_node, "rockchip,rk3399-gmac") || 338 OF_is_compatible(faa->fa_node, "snps,dwmac")); 339 } 340 341 void 342 dwge_attach(struct device *parent, struct device *self, void *aux) 343 { 344 struct dwge_softc *sc = (void *)self; 345 struct fdt_attach_args *faa = aux; 346 struct ifnet *ifp; 347 uint32_t phy, phy_supply; 348 uint32_t axi_config; 349 uint32_t mode, pbl; 350 uint32_t version; 351 int node; 352 353 sc->sc_node = faa->fa_node; 354 sc->sc_iot = faa->fa_iot; 355 if (bus_space_map(sc->sc_iot, faa->fa_reg[0].addr, 356 faa->fa_reg[0].size, 0, &sc->sc_ioh)) { 357 printf("%s: cannot map registers\n", self->dv_xname); 358 return; 359 } 360 sc->sc_dmat = faa->fa_dmat; 361 362 /* Lookup PHY. */ 363 phy = OF_getpropint(faa->fa_node, "phy", 0); 364 if (phy == 0) 365 phy = OF_getpropint(faa->fa_node, "phy-handle", 0); 366 node = OF_getnodebyphandle(phy); 367 if (node) 368 sc->sc_phyloc = OF_getpropint(node, "reg", MII_PHY_ANY); 369 else 370 sc->sc_phyloc = MII_PHY_ANY; 371 372 pinctrl_byname(faa->fa_node, "default"); 373 374 /* Enable clocks. */ 375 clock_set_assigned(faa->fa_node); 376 clock_enable(faa->fa_node, "stmmaceth"); 377 reset_deassert(faa->fa_node, "stmmaceth"); 378 if (OF_is_compatible(faa->fa_node, "rockchip,rk3288-gmac") || 379 OF_is_compatible(faa->fa_node, "rockchip,rk3308-mac") || 380 OF_is_compatible(faa->fa_node, "rockchip,rk3328-gmac") || 381 OF_is_compatible(faa->fa_node, "rockchip,rk3399-gmac")) { 382 clock_enable(faa->fa_node, "mac_clk_rx"); 383 clock_enable(faa->fa_node, "mac_clk_tx"); 384 clock_enable(faa->fa_node, "aclk_mac"); 385 clock_enable(faa->fa_node, "pclk_mac"); 386 } 387 delay(5000); 388 389 version = dwge_read(sc, GMAC_VERSION); 390 printf(": rev 0x%02x", version & GMAC_VERSION_SNPS_MASK); 391 392 /* Power up PHY. */ 393 phy_supply = OF_getpropint(faa->fa_node, "phy-supply", 0); 394 if (phy_supply) 395 regulator_enable(phy_supply); 396 397 /* Reset PHY */ 398 dwge_reset_phy(sc); 399 400 sc->sc_clk = clock_get_frequency(faa->fa_node, "stmmaceth"); 401 if (sc->sc_clk > 250000000) 402 sc->sc_clk = GMAC_GMII_ADDR_CR_DIV_124; 403 else if (sc->sc_clk > 150000000) 404 sc->sc_clk = GMAC_GMII_ADDR_CR_DIV_102; 405 else if (sc->sc_clk > 100000000) 406 sc->sc_clk = GMAC_GMII_ADDR_CR_DIV_62; 407 else if (sc->sc_clk > 60000000) 408 sc->sc_clk = GMAC_GMII_ADDR_CR_DIV_42; 409 else if (sc->sc_clk > 35000000) 410 sc->sc_clk = GMAC_GMII_ADDR_CR_DIV_26; 411 else 412 sc->sc_clk = GMAC_GMII_ADDR_CR_DIV_16; 413 414 if (OF_getprop(faa->fa_node, "local-mac-address", 415 &sc->sc_lladdr, ETHER_ADDR_LEN) != ETHER_ADDR_LEN) 416 dwge_lladdr_read(sc, sc->sc_lladdr); 417 printf(", address %s\n", ether_sprintf(sc->sc_lladdr)); 418 419 timeout_set(&sc->sc_tick, dwge_tick, sc); 420 timeout_set(&sc->sc_rxto, dwge_rxtick, sc); 421 422 ifp = &sc->sc_ac.ac_if; 423 ifp->if_softc = sc; 424 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 425 ifp->if_ioctl = dwge_ioctl; 426 ifp->if_start = dwge_start; 427 ifp->if_watchdog = dwge_watchdog; 428 ifq_set_maxlen(&ifp->if_snd, DWGE_NTXDESC - 1); 429 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 430 431 ifp->if_capabilities = IFCAP_VLAN_MTU; 432 433 sc->sc_mii.mii_ifp = ifp; 434 sc->sc_mii.mii_readreg = dwge_mii_readreg; 435 sc->sc_mii.mii_writereg = dwge_mii_writereg; 436 sc->sc_mii.mii_statchg = dwge_mii_statchg; 437 438 ifmedia_init(&sc->sc_media, 0, dwge_media_change, dwge_media_status); 439 440 /* Do hardware specific initializations. */ 441 if (OF_is_compatible(faa->fa_node, "allwinner,sun7i-a20-gmac")) 442 dwge_setup_allwinner(sc); 443 if (OF_is_compatible(faa->fa_node, "rockchip,rk3288-gmac") || 444 OF_is_compatible(faa->fa_node, "rockchip,rk3308-mac") || 445 OF_is_compatible(faa->fa_node, "rockchip,rk3328-gmac") || 446 OF_is_compatible(faa->fa_node, "rockchip,rk3399-gmac")) 447 dwge_setup_rockchip(sc); 448 449 if (OF_getpropbool(faa->fa_node, "snps,force_thresh_dma_mode")) 450 sc->sc_force_thresh_dma_mode = 1; 451 452 dwge_reset(sc); 453 454 /* Configure MAC. */ 455 dwge_write(sc, GMAC_MAC_CONF, dwge_read(sc, GMAC_MAC_CONF) | 456 GMAC_MAC_CONF_JD | GMAC_MAC_CONF_BE | GMAC_MAC_CONF_DCRS); 457 458 /* Configure DMA engine. */ 459 mode = dwge_read(sc, GMAC_BUS_MODE); 460 mode |= GMAC_BUS_MODE_USP; 461 if (!OF_getpropbool(faa->fa_node, "snps,no-pbl-x8")) 462 mode |= GMAC_BUS_MODE_8XPBL; 463 mode &= ~(GMAC_BUS_MODE_RPBL_MASK | GMAC_BUS_MODE_PBL_MASK); 464 pbl = OF_getpropint(faa->fa_node, "snps,pbl", 8); 465 mode |= pbl << GMAC_BUS_MODE_RPBL_SHIFT; 466 mode |= pbl << GMAC_BUS_MODE_PBL_SHIFT; 467 if (OF_getpropbool(faa->fa_node, "snps,fixed-burst")) 468 mode |= GMAC_BUS_MODE_FB; 469 dwge_write(sc, GMAC_BUS_MODE, mode); 470 471 /* Configure AXI master. */ 472 axi_config = OF_getpropint(faa->fa_node, "snps,axi-config", 0); 473 node = OF_getnodebyphandle(axi_config); 474 if (node) { 475 uint32_t blen[7] = { 0 }; 476 uint32_t osr_lmt; 477 int i; 478 479 mode = dwge_read(sc, GMAC_AXI_BUS_MODE); 480 481 osr_lmt = OF_getpropint(node, "snps,wr_osr_lmt", 1); 482 mode &= ~GMAC_AXI_BUS_MODE_WR_OSR_LMT_MASK; 483 mode |= (osr_lmt << GMAC_AXI_BUS_MODE_WR_OSR_LMT_SHIFT); 484 osr_lmt = OF_getpropint(node, "snps,rd_osr_lmt", 1); 485 mode &= ~GMAC_AXI_BUS_MODE_RD_OSR_LMT_MASK; 486 mode |= (osr_lmt << GMAC_AXI_BUS_MODE_RD_OSR_LMT_SHIFT); 487 488 OF_getpropintarray(node, "snps,blen", blen, sizeof(blen)); 489 for (i = 0; i < nitems(blen); i++) { 490 switch (blen[i]) { 491 case 256: 492 mode |= GMAC_AXI_BUS_MODE_BLEN_256; 493 break; 494 case 128: 495 mode |= GMAC_AXI_BUS_MODE_BLEN_128; 496 break; 497 case 64: 498 mode |= GMAC_AXI_BUS_MODE_BLEN_64; 499 break; 500 case 32: 501 mode |= GMAC_AXI_BUS_MODE_BLEN_32; 502 break; 503 case 16: 504 mode |= GMAC_AXI_BUS_MODE_BLEN_16; 505 break; 506 case 8: 507 mode |= GMAC_AXI_BUS_MODE_BLEN_8; 508 break; 509 case 4: 510 mode |= GMAC_AXI_BUS_MODE_BLEN_4; 511 break; 512 } 513 } 514 515 dwge_write(sc, GMAC_AXI_BUS_MODE, mode); 516 } 517 518 mii_attach(self, &sc->sc_mii, 0xffffffff, sc->sc_phyloc, 519 (sc->sc_phyloc == MII_PHY_ANY) ? 0 : MII_OFFSET_ANY, 0); 520 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 521 printf("%s: no PHY found!\n", sc->sc_dev.dv_xname); 522 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 523 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 524 } else 525 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_AUTO); 526 527 if_attach(ifp); 528 ether_ifattach(ifp); 529 530 /* Disable interrupts. */ 531 dwge_write(sc, GMAC_INT_ENA, 0); 532 dwge_write(sc, GMAC_INT_MASK, 533 GMAC_INT_MASK_LPIIM | GMAC_INT_MASK_PIM | GMAC_INT_MASK_RIM); 534 dwge_write(sc, GMAC_MMC_RX_INT_MSK, 0xffffffff); 535 dwge_write(sc, GMAC_MMC_TX_INT_MSK, 0xffffffff); 536 dwge_write(sc, GMAC_MMC_IPC_INT_MSK, 0xffffffff); 537 538 fdt_intr_establish(faa->fa_node, IPL_NET, dwge_intr, sc, 539 sc->sc_dev.dv_xname); 540 } 541 542 void 543 dwge_reset_phy(struct dwge_softc *sc) 544 { 545 uint32_t *gpio; 546 uint32_t delays[3]; 547 int active = 1; 548 int len; 549 550 len = OF_getproplen(sc->sc_node, "snps,reset-gpio"); 551 if (len <= 0) 552 return; 553 554 gpio = malloc(len, M_TEMP, M_WAITOK); 555 556 /* Gather information. */ 557 OF_getpropintarray(sc->sc_node, "snps,reset-gpio", gpio, len); 558 if (OF_getpropbool(sc->sc_node, "snps-reset-active-low")) 559 active = 0; 560 delays[0] = delays[1] = delays[2] = 0; 561 OF_getpropintarray(sc->sc_node, "snps,reset-delays-us", delays, 562 sizeof(delays)); 563 564 /* Perform reset sequence. */ 565 gpio_controller_config_pin(gpio, GPIO_CONFIG_OUTPUT); 566 gpio_controller_set_pin(gpio, !active); 567 delay(delays[0]); 568 gpio_controller_set_pin(gpio, active); 569 delay(delays[1]); 570 gpio_controller_set_pin(gpio, !active); 571 delay(delays[2]); 572 573 free(gpio, M_TEMP, len); 574 } 575 576 uint32_t 577 dwge_read(struct dwge_softc *sc, bus_addr_t addr) 578 { 579 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, addr); 580 } 581 582 void 583 dwge_write(struct dwge_softc *sc, bus_addr_t addr, uint32_t data) 584 { 585 bus_space_write_4(sc->sc_iot, sc->sc_ioh, addr, data); 586 } 587 588 void 589 dwge_lladdr_read(struct dwge_softc *sc, uint8_t *lladdr) 590 { 591 uint32_t machi, maclo; 592 593 machi = dwge_read(sc, GMAC_MAC_ADDR0_HI); 594 maclo = dwge_read(sc, GMAC_MAC_ADDR0_LO); 595 596 lladdr[0] = (maclo >> 0) & 0xff; 597 lladdr[1] = (maclo >> 8) & 0xff; 598 lladdr[2] = (maclo >> 16) & 0xff; 599 lladdr[3] = (maclo >> 24) & 0xff; 600 lladdr[4] = (machi >> 0) & 0xff; 601 lladdr[5] = (machi >> 8) & 0xff; 602 } 603 604 void 605 dwge_lladdr_write(struct dwge_softc *sc) 606 { 607 dwge_write(sc, GMAC_MAC_ADDR0_HI, 608 sc->sc_lladdr[5] << 8 | sc->sc_lladdr[4] << 0); 609 dwge_write(sc, GMAC_MAC_ADDR0_LO, 610 sc->sc_lladdr[3] << 24 | sc->sc_lladdr[2] << 16 | 611 sc->sc_lladdr[1] << 8 | sc->sc_lladdr[0] << 0); 612 } 613 614 void 615 dwge_start(struct ifnet *ifp) 616 { 617 struct dwge_softc *sc = ifp->if_softc; 618 struct mbuf *m; 619 int error, idx; 620 621 if (!(ifp->if_flags & IFF_RUNNING)) 622 return; 623 if (ifq_is_oactive(&ifp->if_snd)) 624 return; 625 if (ifq_empty(&ifp->if_snd)) 626 return; 627 if (!sc->sc_link) 628 return; 629 630 idx = sc->sc_tx_prod; 631 while ((sc->sc_txdesc[idx].sd_status & TDES0_OWN) == 0) { 632 m = ifq_deq_begin(&ifp->if_snd); 633 if (m == NULL) 634 break; 635 636 error = dwge_encap(sc, m, &idx); 637 if (error == ENOBUFS) { 638 ifq_deq_rollback(&ifp->if_snd, m); 639 ifq_set_oactive(&ifp->if_snd); 640 break; 641 } 642 if (error == EFBIG) { 643 ifq_deq_commit(&ifp->if_snd, m); 644 m_freem(m); /* give up: drop it */ 645 ifp->if_oerrors++; 646 continue; 647 } 648 649 /* Now we are committed to transmit the packet. */ 650 ifq_deq_commit(&ifp->if_snd, m); 651 652 #if NBPFILTER > 0 653 if (ifp->if_bpf) 654 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); 655 #endif 656 } 657 658 if (sc->sc_tx_prod != idx) { 659 sc->sc_tx_prod = idx; 660 661 /* Set a timeout in case the chip goes out to lunch. */ 662 ifp->if_timer = 5; 663 } 664 } 665 666 int 667 dwge_ioctl(struct ifnet *ifp, u_long cmd, caddr_t addr) 668 { 669 struct dwge_softc *sc = ifp->if_softc; 670 struct ifreq *ifr = (struct ifreq *)addr; 671 int error = 0, s; 672 673 s = splnet(); 674 675 switch (cmd) { 676 case SIOCSIFADDR: 677 ifp->if_flags |= IFF_UP; 678 /* FALLTHROUGH */ 679 case SIOCSIFFLAGS: 680 if (ifp->if_flags & IFF_UP) { 681 if (ifp->if_flags & IFF_RUNNING) 682 error = ENETRESET; 683 else 684 dwge_up(sc); 685 } else { 686 if (ifp->if_flags & IFF_RUNNING) 687 dwge_down(sc); 688 } 689 break; 690 691 case SIOCGIFMEDIA: 692 case SIOCSIFMEDIA: 693 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 694 break; 695 696 case SIOCGIFRXR: 697 error = if_rxr_ioctl((struct if_rxrinfo *)ifr->ifr_data, 698 NULL, MCLBYTES, &sc->sc_rx_ring); 699 break; 700 701 default: 702 error = ether_ioctl(ifp, &sc->sc_ac, cmd, addr); 703 break; 704 } 705 706 if (error == ENETRESET) { 707 if (ifp->if_flags & IFF_RUNNING) 708 dwge_iff(sc); 709 error = 0; 710 } 711 712 splx(s); 713 return (error); 714 } 715 716 void 717 dwge_watchdog(struct ifnet *ifp) 718 { 719 printf("%s\n", __func__); 720 } 721 722 int 723 dwge_media_change(struct ifnet *ifp) 724 { 725 struct dwge_softc *sc = ifp->if_softc; 726 727 if (LIST_FIRST(&sc->sc_mii.mii_phys)) 728 mii_mediachg(&sc->sc_mii); 729 730 return (0); 731 } 732 733 void 734 dwge_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 735 { 736 struct dwge_softc *sc = ifp->if_softc; 737 738 if (LIST_FIRST(&sc->sc_mii.mii_phys)) { 739 mii_pollstat(&sc->sc_mii); 740 ifmr->ifm_active = sc->sc_mii.mii_media_active; 741 ifmr->ifm_status = sc->sc_mii.mii_media_status; 742 } 743 } 744 745 int 746 dwge_mii_readreg(struct device *self, int phy, int reg) 747 { 748 struct dwge_softc *sc = (void *)self; 749 int n; 750 751 dwge_write(sc, GMAC_GMII_ADDR, 752 sc->sc_clk << GMAC_GMII_ADDR_CR_SHIFT | 753 phy << GMAC_GMII_ADDR_PA_SHIFT | 754 reg << GMAC_GMII_ADDR_GR_SHIFT | 755 GMAC_GMII_ADDR_GB); 756 for (n = 0; n < 1000; n++) { 757 if ((dwge_read(sc, GMAC_GMII_ADDR) & GMAC_GMII_ADDR_GB) == 0) 758 return dwge_read(sc, GMAC_GMII_DATA); 759 delay(10); 760 } 761 762 printf("%s: mii_read timeout\n", sc->sc_dev.dv_xname); 763 return (0); 764 } 765 766 void 767 dwge_mii_writereg(struct device *self, int phy, int reg, int val) 768 { 769 struct dwge_softc *sc = (void *)self; 770 int n; 771 772 dwge_write(sc, GMAC_GMII_DATA, val); 773 dwge_write(sc, GMAC_GMII_ADDR, 774 sc->sc_clk << GMAC_GMII_ADDR_CR_SHIFT | 775 phy << GMAC_GMII_ADDR_PA_SHIFT | 776 reg << GMAC_GMII_ADDR_GR_SHIFT | 777 GMAC_GMII_ADDR_GW | GMAC_GMII_ADDR_GB); 778 for (n = 0; n < 1000; n++) { 779 if ((dwge_read(sc, GMAC_GMII_ADDR) & GMAC_GMII_ADDR_GB) == 0) 780 return; 781 delay(10); 782 } 783 784 printf("%s: mii_write timeout\n", sc->sc_dev.dv_xname); 785 } 786 787 void 788 dwge_mii_statchg(struct device *self) 789 { 790 struct dwge_softc *sc = (void *)self; 791 uint32_t conf; 792 793 conf = dwge_read(sc, GMAC_MAC_CONF); 794 conf &= ~(GMAC_MAC_CONF_PS | GMAC_MAC_CONF_FES); 795 796 switch (IFM_SUBTYPE(sc->sc_mii.mii_media_active)) { 797 case IFM_1000_SX: 798 case IFM_1000_LX: 799 case IFM_1000_CX: 800 case IFM_1000_T: 801 sc->sc_link = 1; 802 break; 803 case IFM_100_TX: 804 conf |= GMAC_MAC_CONF_PS | GMAC_MAC_CONF_FES; 805 sc->sc_link = 1; 806 break; 807 case IFM_10_T: 808 conf |= GMAC_MAC_CONF_PS; 809 sc->sc_link = 1; 810 break; 811 default: 812 sc->sc_link = 0; 813 return; 814 } 815 816 if (sc->sc_link == 0) 817 return; 818 819 conf &= ~GMAC_MAC_CONF_DM; 820 if ((sc->sc_mii.mii_media_active & IFM_GMASK) == IFM_FDX) 821 conf |= GMAC_MAC_CONF_DM; 822 823 /* XXX: RX/TX flow control? */ 824 825 dwge_write(sc, GMAC_MAC_CONF, conf); 826 } 827 828 void 829 dwge_tick(void *arg) 830 { 831 struct dwge_softc *sc = arg; 832 int s; 833 834 s = splnet(); 835 mii_tick(&sc->sc_mii); 836 splx(s); 837 838 timeout_add_sec(&sc->sc_tick, 1); 839 } 840 841 void 842 dwge_rxtick(void *arg) 843 { 844 struct dwge_softc *sc = arg; 845 uint32_t mode; 846 int s; 847 848 s = splnet(); 849 850 mode = dwge_read(sc, GMAC_OP_MODE); 851 dwge_write(sc, GMAC_OP_MODE, mode & ~GMAC_OP_MODE_SR); 852 853 bus_dmamap_sync(sc->sc_dmat, DWGE_DMA_MAP(sc->sc_rxring), 854 0, DWGE_DMA_LEN(sc->sc_rxring), 855 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 856 857 dwge_write(sc, GMAC_RX_DESC_LIST_ADDR, 0); 858 859 sc->sc_rx_prod = sc->sc_rx_cons = 0; 860 dwge_fill_rx_ring(sc); 861 862 bus_dmamap_sync(sc->sc_dmat, DWGE_DMA_MAP(sc->sc_rxring), 863 0, DWGE_DMA_LEN(sc->sc_rxring), 864 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 865 866 dwge_write(sc, GMAC_RX_DESC_LIST_ADDR, DWGE_DMA_DVA(sc->sc_rxring)); 867 dwge_write(sc, GMAC_OP_MODE, mode); 868 869 splx(s); 870 } 871 872 int 873 dwge_intr(void *arg) 874 { 875 struct dwge_softc *sc = arg; 876 uint32_t reg; 877 878 reg = dwge_read(sc, GMAC_STATUS); 879 dwge_write(sc, GMAC_STATUS, reg); 880 881 if (reg & GMAC_STATUS_RI) 882 dwge_rx_proc(sc); 883 884 if (reg & GMAC_STATUS_TI || 885 reg & GMAC_STATUS_TU) 886 dwge_tx_proc(sc); 887 888 return (1); 889 } 890 891 void 892 dwge_tx_proc(struct dwge_softc *sc) 893 { 894 struct ifnet *ifp = &sc->sc_ac.ac_if; 895 struct dwge_desc *txd; 896 struct dwge_buf *txb; 897 int idx, txfree; 898 899 bus_dmamap_sync(sc->sc_dmat, DWGE_DMA_MAP(sc->sc_txring), 0, 900 DWGE_DMA_LEN(sc->sc_txring), 901 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 902 903 txfree = 0; 904 while (sc->sc_tx_cnt > 0) { 905 idx = sc->sc_tx_cons; 906 KASSERT(idx < DWGE_NTXDESC); 907 908 txd = &sc->sc_txdesc[idx]; 909 if (txd->sd_status & TDES0_OWN) 910 break; 911 912 txb = &sc->sc_txbuf[idx]; 913 if (txb->tb_m) { 914 bus_dmamap_sync(sc->sc_dmat, txb->tb_map, 0, 915 txb->tb_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 916 bus_dmamap_unload(sc->sc_dmat, txb->tb_map); 917 918 m_freem(txb->tb_m); 919 txb->tb_m = NULL; 920 } 921 922 txfree++; 923 sc->sc_tx_cnt--; 924 925 if (sc->sc_tx_cons == (DWGE_NTXDESC - 1)) 926 sc->sc_tx_cons = 0; 927 else 928 sc->sc_tx_cons++; 929 930 txd->sd_status = 0; 931 } 932 933 if (sc->sc_tx_cnt == 0) 934 ifp->if_timer = 0; 935 936 if (txfree) { 937 if (ifq_is_oactive(&ifp->if_snd)) 938 ifq_restart(&ifp->if_snd); 939 } 940 } 941 942 void 943 dwge_rx_proc(struct dwge_softc *sc) 944 { 945 struct ifnet *ifp = &sc->sc_ac.ac_if; 946 struct dwge_desc *rxd; 947 struct dwge_buf *rxb; 948 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 949 struct mbuf *m; 950 int idx, len; 951 952 if ((ifp->if_flags & IFF_RUNNING) == 0) 953 return; 954 955 bus_dmamap_sync(sc->sc_dmat, DWGE_DMA_MAP(sc->sc_rxring), 0, 956 DWGE_DMA_LEN(sc->sc_rxring), 957 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 958 959 while (if_rxr_inuse(&sc->sc_rx_ring) > 0) { 960 idx = sc->sc_rx_cons; 961 KASSERT(idx < DWGE_NRXDESC); 962 963 rxd = &sc->sc_rxdesc[idx]; 964 if (rxd->sd_status & RDES0_OWN) 965 break; 966 967 len = (rxd->sd_status >> RDES0_FL_SHIFT) & RDES0_FL_MASK; 968 rxb = &sc->sc_rxbuf[idx]; 969 KASSERT(rxb->tb_m); 970 971 bus_dmamap_sync(sc->sc_dmat, rxb->tb_map, 0, 972 len, BUS_DMASYNC_POSTREAD); 973 bus_dmamap_unload(sc->sc_dmat, rxb->tb_map); 974 975 /* Strip off CRC. */ 976 len -= ETHER_CRC_LEN; 977 KASSERT(len > 0); 978 979 m = rxb->tb_m; 980 rxb->tb_m = NULL; 981 m->m_pkthdr.len = m->m_len = len; 982 983 ml_enqueue(&ml, m); 984 985 if_rxr_put(&sc->sc_rx_ring, 1); 986 if (sc->sc_rx_cons == (DWGE_NRXDESC - 1)) 987 sc->sc_rx_cons = 0; 988 else 989 sc->sc_rx_cons++; 990 } 991 992 if (ifiq_input(&ifp->if_rcv, &ml)) 993 if_rxr_livelocked(&sc->sc_rx_ring); 994 995 dwge_fill_rx_ring(sc); 996 997 bus_dmamap_sync(sc->sc_dmat, DWGE_DMA_MAP(sc->sc_rxring), 0, 998 DWGE_DMA_LEN(sc->sc_rxring), 999 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1000 1001 } 1002 1003 void 1004 dwge_up(struct dwge_softc *sc) 1005 { 1006 struct ifnet *ifp = &sc->sc_ac.ac_if; 1007 struct dwge_buf *txb, *rxb; 1008 uint32_t mode; 1009 int i; 1010 1011 /* Allocate Tx descriptor ring. */ 1012 sc->sc_txring = dwge_dmamem_alloc(sc, 1013 DWGE_NTXDESC * sizeof(struct dwge_desc), 8); 1014 sc->sc_txdesc = DWGE_DMA_KVA(sc->sc_txring); 1015 1016 sc->sc_txbuf = malloc(sizeof(struct dwge_buf) * DWGE_NTXDESC, 1017 M_DEVBUF, M_WAITOK); 1018 for (i = 0; i < DWGE_NTXDESC; i++) { 1019 txb = &sc->sc_txbuf[i]; 1020 bus_dmamap_create(sc->sc_dmat, MCLBYTES, DWGE_NTXSEGS, 1021 MCLBYTES, 0, BUS_DMA_WAITOK, &txb->tb_map); 1022 txb->tb_m = NULL; 1023 1024 sc->sc_txdesc[i].sd_next = 1025 DWGE_DMA_DVA(sc->sc_txring) + 1026 ((i+1) % DWGE_NTXDESC) * sizeof(struct dwge_desc); 1027 } 1028 1029 bus_dmamap_sync(sc->sc_dmat, DWGE_DMA_MAP(sc->sc_txring), 1030 0, DWGE_DMA_LEN(sc->sc_txring), BUS_DMASYNC_PREWRITE); 1031 1032 sc->sc_tx_prod = sc->sc_tx_cons = 0; 1033 sc->sc_tx_cnt = 0; 1034 1035 dwge_write(sc, GMAC_TX_DESC_LIST_ADDR, DWGE_DMA_DVA(sc->sc_txring)); 1036 1037 /* Allocate descriptor ring. */ 1038 sc->sc_rxring = dwge_dmamem_alloc(sc, 1039 DWGE_NRXDESC * sizeof(struct dwge_desc), 8); 1040 sc->sc_rxdesc = DWGE_DMA_KVA(sc->sc_rxring); 1041 1042 sc->sc_rxbuf = malloc(sizeof(struct dwge_buf) * DWGE_NRXDESC, 1043 M_DEVBUF, M_WAITOK); 1044 1045 for (i = 0; i < DWGE_NRXDESC; i++) { 1046 rxb = &sc->sc_rxbuf[i]; 1047 bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1048 MCLBYTES, 0, BUS_DMA_WAITOK, &rxb->tb_map); 1049 rxb->tb_m = NULL; 1050 1051 sc->sc_rxdesc[i].sd_next = 1052 DWGE_DMA_DVA(sc->sc_rxring) + 1053 ((i+1) % DWGE_NRXDESC) * sizeof(struct dwge_desc); 1054 } 1055 1056 if_rxr_init(&sc->sc_rx_ring, 2, DWGE_NRXDESC); 1057 1058 sc->sc_rx_prod = sc->sc_rx_cons = 0; 1059 dwge_fill_rx_ring(sc); 1060 1061 bus_dmamap_sync(sc->sc_dmat, DWGE_DMA_MAP(sc->sc_rxring), 1062 0, DWGE_DMA_LEN(sc->sc_rxring), 1063 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1064 1065 dwge_write(sc, GMAC_RX_DESC_LIST_ADDR, DWGE_DMA_DVA(sc->sc_rxring)); 1066 1067 dwge_lladdr_write(sc); 1068 1069 /* Configure media. */ 1070 if (LIST_FIRST(&sc->sc_mii.mii_phys)) 1071 mii_mediachg(&sc->sc_mii); 1072 1073 /* Program promiscuous mode and multicast filters. */ 1074 dwge_iff(sc); 1075 1076 ifp->if_flags |= IFF_RUNNING; 1077 ifq_clr_oactive(&ifp->if_snd); 1078 1079 dwge_write(sc, GMAC_INT_ENA, GMAC_INT_ENA_NIE | 1080 GMAC_INT_ENA_RIE | GMAC_INT_ENA_TIE | GMAC_INT_ENA_TUE); 1081 1082 mode = dwge_read(sc, GMAC_OP_MODE); 1083 if (sc->sc_force_thresh_dma_mode) { 1084 mode &= ~(GMAC_OP_MODE_TSF | GMAC_OP_MODE_TTC_MASK); 1085 mode |= GMAC_OP_MODE_TTC_128; 1086 mode &= ~(GMAC_OP_MODE_RSF | GMAC_OP_MODE_RTC_MASK); 1087 mode |= GMAC_OP_MODE_RTC_128; 1088 } else { 1089 mode |= GMAC_OP_MODE_TSF | GMAC_OP_MODE_OSF; 1090 mode |= GMAC_OP_MODE_RSF; 1091 } 1092 dwge_write(sc, GMAC_OP_MODE, mode | GMAC_OP_MODE_ST | GMAC_OP_MODE_SR); 1093 1094 dwge_write(sc, GMAC_MAC_CONF, dwge_read(sc, GMAC_MAC_CONF) | 1095 GMAC_MAC_CONF_TE | GMAC_MAC_CONF_RE); 1096 1097 timeout_add_sec(&sc->sc_tick, 1); 1098 } 1099 1100 void 1101 dwge_down(struct dwge_softc *sc) 1102 { 1103 struct ifnet *ifp = &sc->sc_ac.ac_if; 1104 struct dwge_buf *txb, *rxb; 1105 uint32_t dmactrl; 1106 int i; 1107 1108 timeout_del(&sc->sc_rxto); 1109 timeout_del(&sc->sc_tick); 1110 1111 ifp->if_flags &= ~IFF_RUNNING; 1112 ifq_clr_oactive(&ifp->if_snd); 1113 ifp->if_timer = 0; 1114 1115 dwge_stop_dma(sc); 1116 1117 dwge_write(sc, GMAC_MAC_CONF, dwge_read(sc, 1118 GMAC_MAC_CONF) & ~(GMAC_MAC_CONF_TE | GMAC_MAC_CONF_RE)); 1119 1120 dmactrl = dwge_read(sc, GMAC_OP_MODE); 1121 dmactrl &= ~(GMAC_OP_MODE_ST | GMAC_OP_MODE_SR); 1122 dwge_write(sc, GMAC_OP_MODE, dmactrl); 1123 1124 dwge_write(sc, GMAC_INT_ENA, 0); 1125 1126 for (i = 0; i < DWGE_NTXDESC; i++) { 1127 txb = &sc->sc_txbuf[i]; 1128 if (txb->tb_m) { 1129 bus_dmamap_sync(sc->sc_dmat, txb->tb_map, 0, 1130 txb->tb_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1131 bus_dmamap_unload(sc->sc_dmat, txb->tb_map); 1132 m_freem(txb->tb_m); 1133 } 1134 bus_dmamap_destroy(sc->sc_dmat, txb->tb_map); 1135 } 1136 1137 dwge_dmamem_free(sc, sc->sc_txring); 1138 free(sc->sc_txbuf, M_DEVBUF, 0); 1139 1140 for (i = 0; i < DWGE_NRXDESC; i++) { 1141 rxb = &sc->sc_rxbuf[i]; 1142 if (rxb->tb_m) { 1143 bus_dmamap_sync(sc->sc_dmat, rxb->tb_map, 0, 1144 rxb->tb_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1145 bus_dmamap_unload(sc->sc_dmat, rxb->tb_map); 1146 m_freem(rxb->tb_m); 1147 } 1148 bus_dmamap_destroy(sc->sc_dmat, rxb->tb_map); 1149 } 1150 1151 dwge_dmamem_free(sc, sc->sc_rxring); 1152 free(sc->sc_rxbuf, M_DEVBUF, 0); 1153 } 1154 1155 /* Bit Reversal - http://aggregate.org/MAGIC/#Bit%20Reversal */ 1156 static uint32_t 1157 bitrev32(uint32_t x) 1158 { 1159 x = (((x & 0xaaaaaaaa) >> 1) | ((x & 0x55555555) << 1)); 1160 x = (((x & 0xcccccccc) >> 2) | ((x & 0x33333333) << 2)); 1161 x = (((x & 0xf0f0f0f0) >> 4) | ((x & 0x0f0f0f0f) << 4)); 1162 x = (((x & 0xff00ff00) >> 8) | ((x & 0x00ff00ff) << 8)); 1163 1164 return (x >> 16) | (x << 16); 1165 } 1166 1167 void 1168 dwge_iff(struct dwge_softc *sc) 1169 { 1170 struct arpcom *ac = &sc->sc_ac; 1171 struct ifnet *ifp = &sc->sc_ac.ac_if; 1172 struct ether_multi *enm; 1173 struct ether_multistep step; 1174 uint32_t crc, hash[2], hashbit, hashreg; 1175 uint32_t reg; 1176 1177 reg = 0; 1178 1179 ifp->if_flags &= ~IFF_ALLMULTI; 1180 bzero(hash, sizeof(hash)); 1181 if (ifp->if_flags & IFF_PROMISC || ac->ac_multirangecnt > 0) { 1182 ifp->if_flags |= IFF_ALLMULTI; 1183 reg |= GMAC_MAC_FRM_FILT_PM; 1184 if (ifp->if_flags & IFF_PROMISC) 1185 reg |= GMAC_MAC_FRM_FILT_PR; 1186 } else { 1187 reg |= GMAC_MAC_FRM_FILT_HMC; 1188 ETHER_FIRST_MULTI(step, ac, enm); 1189 while (enm != NULL) { 1190 crc = ether_crc32_le(enm->enm_addrlo, 1191 ETHER_ADDR_LEN) & 0x7f; 1192 1193 crc = bitrev32(~crc) >> 26; 1194 hashreg = (crc >> 5); 1195 hashbit = (crc & 0x1f); 1196 hash[hashreg] |= (1 << hashbit); 1197 1198 ETHER_NEXT_MULTI(step, enm); 1199 } 1200 } 1201 1202 dwge_lladdr_write(sc); 1203 1204 dwge_write(sc, GMAC_HASH_TAB_HI, hash[1]); 1205 dwge_write(sc, GMAC_HASH_TAB_LO, hash[0]); 1206 1207 dwge_write(sc, GMAC_MAC_FRM_FILT, reg); 1208 } 1209 1210 int 1211 dwge_encap(struct dwge_softc *sc, struct mbuf *m, int *idx) 1212 { 1213 struct dwge_desc *txd, *txd_start; 1214 bus_dmamap_t map; 1215 int cur, frag, i; 1216 1217 cur = frag = *idx; 1218 map = sc->sc_txbuf[cur].tb_map; 1219 1220 if (bus_dmamap_load_mbuf(sc->sc_dmat, map, m, BUS_DMA_NOWAIT)) { 1221 if (m_defrag(m, M_DONTWAIT)) 1222 return (EFBIG); 1223 if (bus_dmamap_load_mbuf(sc->sc_dmat, map, m, BUS_DMA_NOWAIT)) 1224 return (EFBIG); 1225 } 1226 1227 if (map->dm_nsegs > (DWGE_NTXDESC - sc->sc_tx_cnt - 2)) { 1228 bus_dmamap_unload(sc->sc_dmat, map); 1229 return (ENOBUFS); 1230 } 1231 1232 /* Sync the DMA map. */ 1233 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1234 BUS_DMASYNC_PREWRITE); 1235 1236 txd = txd_start = &sc->sc_txdesc[frag]; 1237 for (i = 0; i < map->dm_nsegs; i++) { 1238 txd->sd_addr = map->dm_segs[i].ds_addr; 1239 txd->sd_len = map->dm_segs[i].ds_len | TDES1_TCH; 1240 if (i == 0) 1241 txd->sd_len |= TDES1_FS; 1242 if (i == (map->dm_nsegs - 1)) 1243 txd->sd_len |= TDES1_LS | TDES1_IC; 1244 if (i != 0) 1245 txd->sd_status = TDES0_OWN; 1246 1247 bus_dmamap_sync(sc->sc_dmat, DWGE_DMA_MAP(sc->sc_txring), 1248 frag * sizeof(*txd), sizeof(*txd), BUS_DMASYNC_PREWRITE); 1249 1250 cur = frag; 1251 if (frag == (DWGE_NTXDESC - 1)) { 1252 txd = &sc->sc_txdesc[0]; 1253 frag = 0; 1254 } else { 1255 txd++; 1256 frag++; 1257 } 1258 KASSERT(frag != sc->sc_tx_cons); 1259 } 1260 1261 txd_start->sd_status = TDES0_OWN; 1262 bus_dmamap_sync(sc->sc_dmat, DWGE_DMA_MAP(sc->sc_txring), 1263 *idx * sizeof(*txd), sizeof(*txd), BUS_DMASYNC_PREWRITE); 1264 1265 dwge_write(sc, GMAC_TX_POLL_DEMAND, 0xffffffff); 1266 1267 KASSERT(sc->sc_txbuf[cur].tb_m == NULL); 1268 sc->sc_txbuf[*idx].tb_map = sc->sc_txbuf[cur].tb_map; 1269 sc->sc_txbuf[cur].tb_map = map; 1270 sc->sc_txbuf[cur].tb_m = m; 1271 1272 sc->sc_tx_cnt += map->dm_nsegs; 1273 *idx = frag; 1274 1275 return (0); 1276 } 1277 1278 void 1279 dwge_reset(struct dwge_softc *sc) 1280 { 1281 int n; 1282 1283 dwge_stop_dma(sc); 1284 1285 dwge_write(sc, GMAC_BUS_MODE, dwge_read(sc, GMAC_BUS_MODE) | 1286 GMAC_BUS_MODE_SWR); 1287 1288 for (n = 0; n < 30000; n++) { 1289 if ((dwge_read(sc, GMAC_BUS_MODE) & 1290 GMAC_BUS_MODE_SWR) == 0) 1291 return; 1292 delay(10); 1293 } 1294 1295 printf("%s: reset timeout\n", sc->sc_dev.dv_xname); 1296 } 1297 1298 void 1299 dwge_stop_dma(struct dwge_softc *sc) 1300 { 1301 uint32_t dmactrl; 1302 1303 /* Stop DMA. */ 1304 dmactrl = dwge_read(sc, GMAC_OP_MODE); 1305 dmactrl &= ~GMAC_OP_MODE_ST; 1306 dmactrl |= GMAC_OP_MODE_FTF; 1307 dwge_write(sc, GMAC_OP_MODE, dmactrl); 1308 } 1309 1310 struct dwge_dmamem * 1311 dwge_dmamem_alloc(struct dwge_softc *sc, bus_size_t size, bus_size_t align) 1312 { 1313 struct dwge_dmamem *tdm; 1314 int nsegs; 1315 1316 tdm = malloc(sizeof(*tdm), M_DEVBUF, M_WAITOK | M_ZERO); 1317 tdm->tdm_size = size; 1318 1319 if (bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 1320 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, &tdm->tdm_map) != 0) 1321 goto tdmfree; 1322 1323 if (bus_dmamem_alloc(sc->sc_dmat, size, align, 0, &tdm->tdm_seg, 1, 1324 &nsegs, BUS_DMA_WAITOK) != 0) 1325 goto destroy; 1326 1327 if (bus_dmamem_map(sc->sc_dmat, &tdm->tdm_seg, nsegs, size, 1328 &tdm->tdm_kva, BUS_DMA_WAITOK | BUS_DMA_COHERENT) != 0) 1329 goto free; 1330 1331 if (bus_dmamap_load(sc->sc_dmat, tdm->tdm_map, tdm->tdm_kva, size, 1332 NULL, BUS_DMA_WAITOK) != 0) 1333 goto unmap; 1334 1335 bzero(tdm->tdm_kva, size); 1336 1337 return (tdm); 1338 1339 unmap: 1340 bus_dmamem_unmap(sc->sc_dmat, tdm->tdm_kva, size); 1341 free: 1342 bus_dmamem_free(sc->sc_dmat, &tdm->tdm_seg, 1); 1343 destroy: 1344 bus_dmamap_destroy(sc->sc_dmat, tdm->tdm_map); 1345 tdmfree: 1346 free(tdm, M_DEVBUF, 0); 1347 1348 return (NULL); 1349 } 1350 1351 void 1352 dwge_dmamem_free(struct dwge_softc *sc, struct dwge_dmamem *tdm) 1353 { 1354 bus_dmamem_unmap(sc->sc_dmat, tdm->tdm_kva, tdm->tdm_size); 1355 bus_dmamem_free(sc->sc_dmat, &tdm->tdm_seg, 1); 1356 bus_dmamap_destroy(sc->sc_dmat, tdm->tdm_map); 1357 free(tdm, M_DEVBUF, 0); 1358 } 1359 1360 struct mbuf * 1361 dwge_alloc_mbuf(struct dwge_softc *sc, bus_dmamap_t map) 1362 { 1363 struct mbuf *m = NULL; 1364 1365 m = MCLGETL(NULL, M_DONTWAIT, MCLBYTES); 1366 if (!m) 1367 return (NULL); 1368 m->m_len = m->m_pkthdr.len = MCLBYTES; 1369 m_adj(m, ETHER_ALIGN); 1370 1371 if (bus_dmamap_load_mbuf(sc->sc_dmat, map, m, BUS_DMA_NOWAIT) != 0) { 1372 printf("%s: could not load mbuf DMA map", DEVNAME(sc)); 1373 m_freem(m); 1374 return (NULL); 1375 } 1376 1377 bus_dmamap_sync(sc->sc_dmat, map, 0, 1378 m->m_pkthdr.len, BUS_DMASYNC_PREREAD); 1379 1380 return (m); 1381 } 1382 1383 void 1384 dwge_fill_rx_ring(struct dwge_softc *sc) 1385 { 1386 struct dwge_desc *rxd; 1387 struct dwge_buf *rxb; 1388 u_int slots; 1389 1390 for (slots = if_rxr_get(&sc->sc_rx_ring, DWGE_NRXDESC); 1391 slots > 0; slots--) { 1392 rxb = &sc->sc_rxbuf[sc->sc_rx_prod]; 1393 rxb->tb_m = dwge_alloc_mbuf(sc, rxb->tb_map); 1394 if (rxb->tb_m == NULL) 1395 break; 1396 1397 rxd = &sc->sc_rxdesc[sc->sc_rx_prod]; 1398 rxd->sd_len = rxb->tb_map->dm_segs[0].ds_len | RDES1_RCH; 1399 rxd->sd_addr = rxb->tb_map->dm_segs[0].ds_addr; 1400 rxd->sd_status = RDES0_OWN; 1401 1402 if (sc->sc_rx_prod == (DWGE_NRXDESC - 1)) 1403 sc->sc_rx_prod = 0; 1404 else 1405 sc->sc_rx_prod++; 1406 } 1407 if_rxr_put(&sc->sc_rx_ring, slots); 1408 1409 if (if_rxr_inuse(&sc->sc_rx_ring) == 0) 1410 timeout_add(&sc->sc_rxto, 1); 1411 } 1412 1413 /* 1414 * Allwinner A20/A31. 1415 */ 1416 1417 void 1418 dwge_setup_allwinner(struct dwge_softc *sc) 1419 { 1420 char phy_mode[8]; 1421 uint32_t freq; 1422 1423 /* default to RGMII */ 1424 OF_getprop(sc->sc_node, "phy-mode", phy_mode, sizeof(phy_mode)); 1425 if (strcmp(phy_mode, "mii") == 0) 1426 freq = 25000000; 1427 else 1428 freq = 125000000; 1429 clock_set_frequency(sc->sc_node, "allwinner_gmac_tx", freq); 1430 } 1431 1432 /* 1433 * Rockchip RK3288/RK3399. 1434 */ 1435 1436 /* RK3308 registers */ 1437 #define RK3308_GRF_MAC_CON0 0x04a0 1438 #define RK3308_MAC_SPEED_100M ((0x1 << 0) << 16 | (0x1 << 0)) 1439 #define RK3308_MAC_SPEED_10M ((0x1 << 0) << 16 | (0x0 << 0)) 1440 #define RK3308_INTF_SEL_RMII ((0x1 << 4) << 16 | (0x1 << 4)) 1441 1442 /* RK3288 registers */ 1443 #define RK3288_GRF_SOC_CON1 0x0248 1444 #define RK3288_GMAC_PHY_INTF_SEL_RGMII ((0x7 << 6) << 16 | (0x1 << 6)) 1445 #define RK3288_GMAC_PHY_INTF_SEL_RMII ((0x7 << 6) << 16 | (0x4 << 6)) 1446 #define RK3288_RMII_MODE_RMII ((1 << 14) << 16 | (1 << 14)) 1447 #define RK3288_RMII_MODE_MII ((1 << 14) << 16 | (0 << 14)) 1448 #define RK3288_GMAC_CLK_SEL_125 ((0x3 << 12) << 16 | (0x0 << 12)) 1449 #define RK3288_GMAC_CLK_SEL_25 ((0x3 << 12) << 16 | (0x3 << 12)) 1450 #define RK3288_GMAC_CLK_SEL_2_5 ((0x3 << 12) << 16 | (0x2 << 12)) 1451 1452 #define RK3288_GRF_SOC_CON3 0x0250 1453 #define RK3288_GMAC_RXCLK_DLY_ENA ((1 << 15) << 16 | (1 << 15)) 1454 #define RK3288_GMAC_CLK_RX_DL_CFG(val) ((0x7f << 7) << 16 | ((val) << 7)) 1455 #define RK3288_GMAC_TXCLK_DLY_ENA ((1 << 14) << 16 | (1 << 14)) 1456 #define RK3288_GMAC_CLK_TX_DL_CFG(val) ((0x7f << 0) << 16 | ((val) << 0)) 1457 1458 /* RK3328 registers */ 1459 #define RK3328_GRF_MAC_CON0 0x0900 1460 #define RK3328_GMAC_CLK_RX_DL_CFG(val) ((0x7f << 7) << 16 | ((val) << 7)) 1461 #define RK3328_GMAC_CLK_TX_DL_CFG(val) ((0x7f << 0) << 16 | ((val) << 0)) 1462 1463 #define RK3328_GRF_MAC_CON1 0x0904 1464 #define RK3328_GMAC_PHY_INTF_SEL_RGMII ((0x7 << 4) << 16 | (0x1 << 4)) 1465 #define RK3328_GMAC_PHY_INTF_SEL_RMII ((0x7 << 4) << 16 | (0x4 << 4)) 1466 #define RK3328_RMII_MODE_RMII ((1 << 9) << 16 | (1 << 9)) 1467 #define RK3328_RMII_MODE_MII ((1 << 9) << 16 | (0 << 9)) 1468 #define RK3328_GMAC_CLK_SEL_125 ((0x3 << 11) << 16 | (0x0 << 11)) 1469 #define RK3328_GMAC_CLK_SEL_25 ((0x3 << 11) << 16 | (0x3 << 11)) 1470 #define RK3328_GMAC_CLK_SEL_2_5 ((0x3 << 11) << 16 | (0x2 << 11)) 1471 #define RK3328_GMAC_RXCLK_DLY_ENA ((1 << 1) << 16 | (1 << 1)) 1472 #define RK3328_GMAC_TXCLK_DLY_ENA ((1 << 0) << 16 | (1 << 0)) 1473 1474 /* RK3399 registers */ 1475 #define RK3399_GRF_SOC_CON5 0xc214 1476 #define RK3399_GMAC_PHY_INTF_SEL_RGMII ((0x7 << 9) << 16 | (0x1 << 9)) 1477 #define RK3399_GMAC_PHY_INTF_SEL_RMII ((0x7 << 9) << 16 | (0x4 << 9)) 1478 #define RK3399_RMII_MODE_RMII ((1 << 6) << 16 | (1 << 6)) 1479 #define RK3399_RMII_MODE_MII ((1 << 6) << 16 | (0 << 6)) 1480 #define RK3399_GMAC_CLK_SEL_125 ((0x3 << 4) << 16 | (0x0 << 4)) 1481 #define RK3399_GMAC_CLK_SEL_25 ((0x3 << 4) << 16 | (0x3 << 4)) 1482 #define RK3399_GMAC_CLK_SEL_2_5 ((0x3 << 4) << 16 | (0x2 << 4)) 1483 #define RK3399_GRF_SOC_CON6 0xc218 1484 #define RK3399_GMAC_RXCLK_DLY_ENA ((1 << 15) << 16 | (1 << 15)) 1485 #define RK3399_GMAC_CLK_RX_DL_CFG(val) ((0x7f << 8) << 16 | ((val) << 8)) 1486 #define RK3399_GMAC_TXCLK_DLY_ENA ((1 << 7) << 16 | (1 << 7)) 1487 #define RK3399_GMAC_CLK_TX_DL_CFG(val) ((0x7f << 0) << 16 | ((val) << 0)) 1488 1489 void dwge_mii_statchg_rockchip(struct device *); 1490 1491 void 1492 dwge_setup_rockchip(struct dwge_softc *sc) 1493 { 1494 struct regmap *rm; 1495 uint32_t grf; 1496 int tx_delay, rx_delay; 1497 char clock_mode[8]; 1498 1499 grf = OF_getpropint(sc->sc_node, "rockchip,grf", 0); 1500 rm = regmap_byphandle(grf); 1501 if (rm == NULL) 1502 return; 1503 1504 tx_delay = OF_getpropint(sc->sc_node, "tx_delay", 0x30); 1505 rx_delay = OF_getpropint(sc->sc_node, "rx_delay", 0x10); 1506 1507 if (OF_is_compatible(sc->sc_node, "rockchip,rk3288-gmac")) { 1508 /* Use RGMII interface. */ 1509 regmap_write_4(rm, RK3288_GRF_SOC_CON1, 1510 RK3288_GMAC_PHY_INTF_SEL_RGMII | RK3288_RMII_MODE_MII); 1511 1512 /* Program clock delay lines. */ 1513 regmap_write_4(rm, RK3288_GRF_SOC_CON3, 1514 RK3288_GMAC_TXCLK_DLY_ENA | RK3288_GMAC_RXCLK_DLY_ENA | 1515 RK3288_GMAC_CLK_TX_DL_CFG(tx_delay) | 1516 RK3288_GMAC_CLK_RX_DL_CFG(rx_delay)); 1517 1518 /* Clock speed bits. */ 1519 sc->sc_clk_sel = RK3288_GRF_SOC_CON1; 1520 sc->sc_clk_sel_2_5 = RK3288_GMAC_CLK_SEL_2_5; 1521 sc->sc_clk_sel_25 = RK3288_GMAC_CLK_SEL_25; 1522 sc->sc_clk_sel_125 = RK3288_GMAC_CLK_SEL_125; 1523 } else if (OF_is_compatible(sc->sc_node, "rockchip,rk3308-mac")) { 1524 /* Use RMII interface. */ 1525 regmap_write_4(rm, RK3308_GRF_MAC_CON0, 1526 RK3308_INTF_SEL_RMII | RK3308_MAC_SPEED_100M); 1527 1528 /* Adjust MAC clock if necessary. */ 1529 OF_getprop(sc->sc_node, "clock_in_out", clock_mode, 1530 sizeof(clock_mode)); 1531 if (strcmp(clock_mode, "output") == 0) { 1532 clock_set_frequency(sc->sc_node, "stmmaceth", 1533 50000000); 1534 sc->sc_clk = GMAC_GMII_ADDR_CR_DIV_26; 1535 } 1536 1537 /* Clock speed bits. */ 1538 sc->sc_clk_sel = RK3308_GRF_MAC_CON0; 1539 sc->sc_clk_sel_2_5 = RK3308_MAC_SPEED_10M; 1540 sc->sc_clk_sel_25 = RK3308_MAC_SPEED_100M; 1541 } else if (OF_is_compatible(sc->sc_node, "rockchip,rk3328-gmac")) { 1542 /* Use RGMII interface. */ 1543 regmap_write_4(rm, RK3328_GRF_MAC_CON1, 1544 RK3328_GMAC_PHY_INTF_SEL_RGMII | RK3328_RMII_MODE_MII); 1545 1546 /* Program clock delay lines. */ 1547 regmap_write_4(rm, RK3328_GRF_MAC_CON0, 1548 RK3328_GMAC_CLK_TX_DL_CFG(tx_delay) | 1549 RK3328_GMAC_CLK_RX_DL_CFG(rx_delay)); 1550 regmap_write_4(rm, RK3328_GRF_MAC_CON1, 1551 RK3328_GMAC_TXCLK_DLY_ENA | RK3328_GMAC_RXCLK_DLY_ENA); 1552 1553 /* Clock speed bits. */ 1554 sc->sc_clk_sel = RK3328_GRF_MAC_CON1; 1555 sc->sc_clk_sel_2_5 = RK3328_GMAC_CLK_SEL_2_5; 1556 sc->sc_clk_sel_25 = RK3328_GMAC_CLK_SEL_25; 1557 sc->sc_clk_sel_125 = RK3328_GMAC_CLK_SEL_125; 1558 } else { 1559 /* Use RGMII interface. */ 1560 regmap_write_4(rm, RK3399_GRF_SOC_CON5, 1561 RK3399_GMAC_PHY_INTF_SEL_RGMII | RK3399_RMII_MODE_MII); 1562 1563 /* Program clock delay lines. */ 1564 regmap_write_4(rm, RK3399_GRF_SOC_CON6, 1565 RK3399_GMAC_TXCLK_DLY_ENA | RK3399_GMAC_RXCLK_DLY_ENA | 1566 RK3399_GMAC_CLK_TX_DL_CFG(tx_delay) | 1567 RK3399_GMAC_CLK_RX_DL_CFG(rx_delay)); 1568 1569 /* Clock speed bits. */ 1570 sc->sc_clk_sel = RK3399_GRF_SOC_CON5; 1571 sc->sc_clk_sel_2_5 = RK3399_GMAC_CLK_SEL_2_5; 1572 sc->sc_clk_sel_25 = RK3399_GMAC_CLK_SEL_25; 1573 sc->sc_clk_sel_125 = RK3399_GMAC_CLK_SEL_125; 1574 } 1575 1576 sc->sc_mii.mii_statchg = dwge_mii_statchg_rockchip; 1577 } 1578 1579 void 1580 dwge_mii_statchg_rockchip(struct device *self) 1581 { 1582 struct dwge_softc *sc = (void *)self; 1583 struct regmap *rm; 1584 uint32_t grf; 1585 uint32_t gmac_clk_sel = 0; 1586 1587 dwge_mii_statchg(self); 1588 1589 grf = OF_getpropint(sc->sc_node, "rockchip,grf", 0); 1590 rm = regmap_byphandle(grf); 1591 if (rm == NULL) 1592 return; 1593 1594 switch (IFM_SUBTYPE(sc->sc_mii.mii_media_active)) { 1595 case IFM_10_T: 1596 gmac_clk_sel = sc->sc_clk_sel_2_5; 1597 break; 1598 case IFM_100_TX: 1599 gmac_clk_sel = sc->sc_clk_sel_25; 1600 break; 1601 case IFM_1000_T: 1602 gmac_clk_sel = sc->sc_clk_sel_125; 1603 break; 1604 } 1605 1606 regmap_write_4(rm, sc->sc_clk_sel, gmac_clk_sel); 1607 } 1608