1 /* $OpenBSD: if_cad.c,v 1.11 2022/03/08 16:13:08 visa Exp $ */ 2 3 /* 4 * Copyright (c) 2021-2022 Visa Hankala 5 * 6 * Permission to use, copy, modify, and/or distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * Driver for Cadence 10/100/Gigabit Ethernet device. 21 */ 22 23 #include "bpfilter.h" 24 #include "kstat.h" 25 26 #include <sys/param.h> 27 #include <sys/systm.h> 28 #include <sys/atomic.h> 29 #include <sys/device.h> 30 #include <sys/ioctl.h> 31 #include <sys/mutex.h> 32 #include <sys/kstat.h> 33 #include <sys/rwlock.h> 34 #include <sys/task.h> 35 #include <sys/timeout.h> 36 37 #include <net/if.h> 38 #include <net/if_media.h> 39 #include <netinet/in.h> 40 #include <netinet/ip.h> 41 #include <netinet/if_ether.h> 42 43 #if NBPFILTER > 0 44 #include <net/bpf.h> 45 #endif 46 47 #include <dev/mii/mii.h> 48 #include <dev/mii/miivar.h> 49 #include <dev/mii/miidevs.h> 50 51 #include <machine/bus.h> 52 #include <machine/fdt.h> 53 54 #include <dev/ofw/fdt.h> 55 #include <dev/ofw/openfirm.h> 56 #include <dev/ofw/ofw_clock.h> 57 58 #define GEM_NETCTL 0x0000 59 #define GEM_NETCTL_DPRAM (1 << 18) 60 #define GEM_NETCTL_STARTTX (1 << 9) 61 #define GEM_NETCTL_STATCLR (1 << 5) 62 #define GEM_NETCTL_MDEN (1 << 4) 63 #define GEM_NETCTL_TXEN (1 << 3) 64 #define GEM_NETCTL_RXEN (1 << 2) 65 #define GEM_NETCFG 0x0004 66 #define GEM_NETCFG_SGMIIEN (1 << 27) 67 #define GEM_NETCFG_RXCSUMEN (1 << 24) 68 #define GEM_NETCFG_MDCCLKDIV_MASK (0x7 << 18) 69 #define GEM_NETCFG_MDCCLKDIV_SHIFT 18 70 #define GEM_NETCFG_FCSREM (1 << 17) 71 #define GEM_NETCFG_RXOFFS_MASK (0x3 << 14) 72 #define GEM_NETCFG_RXOFFS_SHIFT 14 73 #define GEM_NETCFG_PCSSEL (1 << 11) 74 #define GEM_NETCFG_1000 (1 << 10) 75 #define GEM_NETCFG_1536RXEN (1 << 8) 76 #define GEM_NETCFG_UCASTHASHEN (1 << 7) 77 #define GEM_NETCFG_MCASTHASHEN (1 << 6) 78 #define GEM_NETCFG_BCASTDI (1 << 5) 79 #define GEM_NETCFG_COPYALL (1 << 4) 80 #define GEM_NETCFG_FDEN (1 << 1) 81 #define GEM_NETCFG_100 (1 << 0) 82 #define GEM_NETSR 0x0008 83 #define GEM_NETSR_PHY_MGMT_IDLE (1 << 2) 84 #define GEM_DMACR 0x0010 85 #define GEM_DMACR_DMA64 (1 << 30) 86 #define GEM_DMACR_AHBDISC (1 << 24) 87 #define GEM_DMACR_RXBUF_MASK (0xff << 16) 88 #define GEM_DMACR_RXBUF_SHIFT 16 89 #define GEM_DMACR_TXCSUMEN (1 << 11) 90 #define GEM_DMACR_TXSIZE (1 << 10) 91 #define GEM_DMACR_RXSIZE_MASK (0x3 << 8) 92 #define GEM_DMACR_RXSIZE_8K (0x3 << 8) 93 #define GEM_DMACR_ES_PDATA (1 << 7) 94 #define GEM_DMACR_ES_DESCR (1 << 6) 95 #define GEM_DMACR_BLEN_MASK (0x1f << 0) 96 #define GEM_DMACR_BLEN_16 (0x10 << 0) 97 #define GEM_TXSR 0x0014 98 #define GEM_TXSR_TXGO (1 << 3) 99 #define GEM_RXQBASE 0x0018 100 #define GEM_TXQBASE 0x001c 101 #define GEM_RXSR 0x0020 102 #define GEM_RXSR_RXOVR (1 << 2) 103 #define GEM_ISR 0x0024 104 #define GEM_IER 0x0028 105 #define GEM_IDR 0x002c 106 #define GEM_IXR_HRESP (1 << 11) 107 #define GEM_IXR_RXOVR (1 << 10) 108 #define GEM_IXR_TXDONE (1 << 7) 109 #define GEM_IXR_TXURUN (1 << 6) 110 #define GEM_IXR_RETRY (1 << 5) 111 #define GEM_IXR_TXUSED (1 << 3) 112 #define GEM_IXR_RXUSED (1 << 2) 113 #define GEM_IXR_RXDONE (1 << 1) 114 #define GEM_PHYMNTNC 0x0034 115 #define GEM_PHYMNTNC_CLAUSE_22 (1 << 30) 116 #define GEM_PHYMNTNC_OP_READ (0x2 << 28) 117 #define GEM_PHYMNTNC_OP_WRITE (0x1 << 28) 118 #define GEM_PHYMNTNC_ADDR_MASK (0x1f << 23) 119 #define GEM_PHYMNTNC_ADDR_SHIFT 23 120 #define GEM_PHYMNTNC_REG_MASK (0x1f << 18) 121 #define GEM_PHYMNTNC_REG_SHIFT 18 122 #define GEM_PHYMNTNC_MUST_10 (0x2 << 16) 123 #define GEM_PHYMNTNC_DATA_MASK 0xffff 124 #define GEM_HASHL 0x0080 125 #define GEM_HASHH 0x0084 126 #define GEM_LADDRL(i) (0x0088 + (i) * 8) 127 #define GEM_LADDRH(i) (0x008c + (i) * 8) 128 #define GEM_LADDRNUM 4 129 #define GEM_MID 0x00fc 130 #define GEM_MID_VERSION_MASK (0xfff << 16) 131 #define GEM_MID_VERSION_SHIFT 16 132 #define GEM_OCTTXL 0x0100 133 #define GEM_OCTTXH 0x0104 134 #define GEM_TXCNT 0x0108 135 #define GEM_TXBCCNT 0x010c 136 #define GEM_TXMCCNT 0x0110 137 #define GEM_TXPAUSECNT 0x0114 138 #define GEM_TX64CNT 0x0118 139 #define GEM_TX65CNT 0x011c 140 #define GEM_TX128CNT 0x0120 141 #define GEM_TX256CNT 0x0124 142 #define GEM_TX512CNT 0x0128 143 #define GEM_TX1024CNT 0x012c 144 #define GEM_TXURUNCNT 0x0134 145 #define GEM_SNGLCOLLCNT 0x0138 146 #define GEM_MULTICOLLCNT 0x013c 147 #define GEM_EXCESSCOLLCNT 0x0140 148 #define GEM_LATECOLLCNT 0x0144 149 #define GEM_TXDEFERCNT 0x0148 150 #define GEM_TXCSENSECNT 0x014c 151 #define GEM_OCTRXL 0x0150 152 #define GEM_OCTRXH 0x0154 153 #define GEM_RXCNT 0x0158 154 #define GEM_RXBROADCNT 0x015c 155 #define GEM_RXMULTICNT 0x0160 156 #define GEM_RXPAUSECNT 0x0164 157 #define GEM_RX64CNT 0x0168 158 #define GEM_RX65CNT 0x016c 159 #define GEM_RX128CNT 0x0170 160 #define GEM_RX256CNT 0x0174 161 #define GEM_RX512CNT 0x0178 162 #define GEM_RX1024CNT 0x017c 163 #define GEM_RXUNDRCNT 0x0184 164 #define GEM_RXOVRCNT 0x0188 165 #define GEM_RXJABCNT 0x018c 166 #define GEM_RXFCSCNT 0x0190 167 #define GEM_RXLENGTHCNT 0x0194 168 #define GEM_RXSYMBCNT 0x0198 169 #define GEM_RXALIGNCNT 0x019c 170 #define GEM_RXRESERRCNT 0x01a0 171 #define GEM_RXORCNT 0x01a4 172 #define GEM_RXIPCCNT 0x01a8 173 #define GEM_RXTCPCCNT 0x01ac 174 #define GEM_RXUDPCCNT 0x01b0 175 #define GEM_CFG6 0x0294 176 #define GEM_CFG6_DMA64 (1 << 23) 177 #define GEM_CFG6_PRIQ_MASK(x) ((x) & 0xffff) 178 #define GEM_CFG8 0x029c 179 #define GEM_CFG8_NUM_TYPE1_SCR(x) (((x) >> 24) & 0xff) 180 #define GEM_CFG8_NUM_TYPE2_SCR(x) (((x) >> 16) & 0xff) 181 #define GEM_TXQ1BASE(i) (0x0440 + (i) * 4) 182 #define GEM_TXQ1BASE_DISABLE (1 << 0) 183 #define GEM_RXQ1BASE(i) (0x0480 + (i) * 4) 184 #define GEM_RXQ1BASE_DISABLE (1 << 0) 185 #define GEM_TXQBASEHI 0x04c8 186 #define GEM_RXQBASEHI 0x04d4 187 #define GEM_SCR_TYPE1(i) (0x0500 + (i) * 4) 188 #define GEM_SCR_TYPE2(i) (0x0540 + (i) * 4) 189 #define GEM_RXQ8BASE(i) (0x05c0 + (i) * 4) 190 #define GEM_RXQ8BASE_DISABLE (1 << 0) 191 192 #define GEM_MAX_PRIQ 16 193 194 #define GEM_CLK_TX "tx_clk" 195 196 struct cad_buf { 197 bus_dmamap_t bf_map; 198 struct mbuf *bf_m; 199 }; 200 201 struct cad_dmamem { 202 bus_dmamap_t cdm_map; 203 bus_dma_segment_t cdm_seg; 204 size_t cdm_size; 205 caddr_t cdm_kva; 206 }; 207 208 struct cad_desc32 { 209 uint32_t d_addr; 210 uint32_t d_status; 211 }; 212 213 struct cad_desc64 { 214 uint32_t d_addrlo; 215 uint32_t d_status; 216 uint32_t d_addrhi; 217 uint32_t d_unused; 218 }; 219 220 #define GEM_RXD_ADDR_WRAP (1 << 1) 221 #define GEM_RXD_ADDR_USED (1 << 0) 222 223 #define GEM_RXD_BCAST (1 << 31) 224 #define GEM_RXD_MCAST (1 << 30) 225 #define GEM_RXD_UCAST (1 << 29) 226 #define GEM_RXD_SPEC (1 << 27) 227 #define GEM_RXD_SPEC_MASK (0x3 << 25) 228 #define GEM_RXD_CSUM_MASK (0x3 << 22) 229 #define GEM_RXD_CSUM_UDP_OK (0x3 << 22) 230 #define GEM_RXD_CSUM_TCP_OK (0x2 << 22) 231 #define GEM_RXD_CSUM_IP_OK (0x1 << 22) 232 #define GEM_RXD_VLANTAG (1 << 21) 233 #define GEM_RXD_PRIOTAG (1 << 20) 234 #define GEM_RXD_CFI (1 << 16) 235 #define GEM_RXD_EOF (1 << 15) 236 #define GEM_RXD_SOF (1 << 14) 237 #define GEM_RXD_BADFCS (1 << 13) 238 #define GEM_RXD_LEN_MASK 0x1fff 239 240 #define GEM_TXD_USED (1 << 31) 241 #define GEM_TXD_WRAP (1 << 30) 242 #define GEM_TXD_RLIMIT (1 << 29) 243 #define GEM_TXD_CORRUPT (1 << 27) 244 #define GEM_TXD_LCOLL (1 << 26) 245 #define GEM_TXD_CSUMERR_MASK (0x7 << 20) 246 #define GEM_TXD_NOFCS (1 << 16) 247 #define GEM_TXD_LAST (1 << 15) 248 #define GEM_TXD_LEN_MASK 0x3fff 249 250 #define CAD_NRXDESC 256 251 252 #define CAD_NTXDESC 256 253 #define CAD_NTXSEGS 16 254 255 enum cad_phy_mode { 256 CAD_PHY_MODE_GMII, 257 CAD_PHY_MODE_RGMII, 258 CAD_PHY_MODE_RGMII_ID, 259 CAD_PHY_MODE_RGMII_RXID, 260 CAD_PHY_MODE_RGMII_TXID, 261 CAD_PHY_MODE_SGMII, 262 }; 263 264 struct cad_softc { 265 struct device sc_dev; 266 struct arpcom sc_ac; 267 268 bus_dma_tag_t sc_dmat; 269 bus_space_tag_t sc_iot; 270 bus_space_handle_t sc_ioh; 271 void *sc_ih; 272 int sc_node; 273 int sc_phy_loc; 274 enum cad_phy_mode sc_phy_mode; 275 unsigned char sc_rxhang_erratum; 276 unsigned char sc_rxdone; 277 unsigned char sc_dma64; 278 size_t sc_descsize; 279 uint32_t sc_qmask; 280 uint8_t sc_ntype1scr; 281 uint8_t sc_ntype2scr; 282 283 struct mii_data sc_mii; 284 #define sc_media sc_mii.mii_media 285 struct timeout sc_tick; 286 287 struct cad_dmamem *sc_txring; 288 struct cad_buf *sc_txbuf; 289 caddr_t sc_txdesc; 290 unsigned int sc_tx_prod; 291 unsigned int sc_tx_cons; 292 293 struct if_rxring sc_rx_ring; 294 struct cad_dmamem *sc_rxring; 295 struct cad_buf *sc_rxbuf; 296 caddr_t sc_rxdesc; 297 unsigned int sc_rx_prod; 298 unsigned int sc_rx_cons; 299 uint32_t sc_netctl; 300 301 struct rwlock sc_cfg_lock; 302 struct task sc_statchg_task; 303 uint32_t sc_tx_freq; 304 305 struct mutex sc_kstat_mtx; 306 struct kstat *sc_kstat; 307 }; 308 309 #define HREAD4(sc, reg) \ 310 (bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg))) 311 #define HWRITE4(sc, reg, val) \ 312 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 313 314 int cad_match(struct device *, void *, void *); 315 void cad_attach(struct device *, struct device *, void *); 316 317 int cad_ioctl(struct ifnet *, u_long, caddr_t); 318 void cad_start(struct ifqueue *); 319 void cad_watchdog(struct ifnet *); 320 321 void cad_reset(struct cad_softc *); 322 int cad_up(struct cad_softc *); 323 void cad_down(struct cad_softc *); 324 void cad_iff(struct cad_softc *); 325 int cad_intr(void *); 326 void cad_tick(void *); 327 void cad_statchg_task(void *); 328 329 int cad_media_change(struct ifnet *); 330 void cad_media_status(struct ifnet *, struct ifmediareq *); 331 int cad_mii_readreg(struct device *, int, int); 332 void cad_mii_writereg(struct device *, int, int, int); 333 void cad_mii_statchg(struct device *); 334 335 struct cad_dmamem *cad_dmamem_alloc(struct cad_softc *, bus_size_t, bus_size_t); 336 void cad_dmamem_free(struct cad_softc *, struct cad_dmamem *); 337 void cad_rxfill(struct cad_softc *); 338 void cad_rxeof(struct cad_softc *); 339 void cad_txeof(struct cad_softc *); 340 unsigned int cad_encap(struct cad_softc *, struct mbuf *); 341 struct mbuf *cad_alloc_mbuf(struct cad_softc *, bus_dmamap_t); 342 343 #if NKSTAT > 0 344 void cad_kstat_attach(struct cad_softc *); 345 int cad_kstat_read(struct kstat *); 346 void cad_kstat_tick(void *); 347 #endif 348 349 #ifdef DDB 350 struct cad_softc *cad_sc[4]; 351 #endif 352 353 const struct cfattach cad_ca = { 354 sizeof(struct cad_softc), cad_match, cad_attach 355 }; 356 357 struct cfdriver cad_cd = { 358 NULL, "cad", DV_IFNET 359 }; 360 361 const struct { 362 const char *name; 363 enum cad_phy_mode mode; 364 } cad_phy_modes[] = { 365 { "gmii", CAD_PHY_MODE_GMII }, 366 { "rgmii", CAD_PHY_MODE_RGMII }, 367 { "rgmii-id", CAD_PHY_MODE_RGMII_ID }, 368 { "rgmii-rxid", CAD_PHY_MODE_RGMII_RXID }, 369 { "rgmii-txid", CAD_PHY_MODE_RGMII_TXID }, 370 { "sgmii", CAD_PHY_MODE_SGMII }, 371 }; 372 373 int 374 cad_match(struct device *parent, void *match, void *aux) 375 { 376 struct fdt_attach_args *faa = aux; 377 378 return (OF_is_compatible(faa->fa_node, "cdns,gem") || 379 OF_is_compatible(faa->fa_node, "cdns,macb") || 380 OF_is_compatible(faa->fa_node, "sifive,fu540-c000-gem") || 381 OF_is_compatible(faa->fa_node, "sifive,fu740-c000-gem")); 382 } 383 384 void 385 cad_attach(struct device *parent, struct device *self, void *aux) 386 { 387 char phy_mode[16]; 388 struct fdt_attach_args *faa = aux; 389 struct cad_softc *sc = (struct cad_softc *)self; 390 struct ifnet *ifp = &sc->sc_ac.ac_if; 391 uint32_t hi, lo; 392 uint32_t rev, ver; 393 uint32_t val; 394 unsigned int i; 395 int node, phy; 396 397 if (faa->fa_nreg < 1) { 398 printf(": no registers\n"); 399 return; 400 } 401 402 sc->sc_node = faa->fa_node; 403 sc->sc_dmat = faa->fa_dmat; 404 sc->sc_iot = faa->fa_iot; 405 if (bus_space_map(sc->sc_iot, faa->fa_reg[0].addr, 406 faa->fa_reg[0].size, 0, &sc->sc_ioh) != 0) { 407 printf(": can't map registers\n"); 408 return; 409 } 410 411 if (OF_getprop(faa->fa_node, "local-mac-address", sc->sc_ac.ac_enaddr, 412 sizeof(sc->sc_ac.ac_enaddr)) != sizeof(sc->sc_ac.ac_enaddr)) { 413 for (i = 0; i < GEM_LADDRNUM; i++) { 414 lo = HREAD4(sc, GEM_LADDRL(i)); 415 hi = HREAD4(sc, GEM_LADDRH(i)); 416 if (lo != 0 || hi != 0) { 417 sc->sc_ac.ac_enaddr[0] = lo; 418 sc->sc_ac.ac_enaddr[1] = lo >> 8; 419 sc->sc_ac.ac_enaddr[2] = lo >> 16; 420 sc->sc_ac.ac_enaddr[3] = lo >> 24; 421 sc->sc_ac.ac_enaddr[4] = hi; 422 sc->sc_ac.ac_enaddr[5] = hi >> 8; 423 break; 424 } 425 } 426 if (i == GEM_LADDRNUM) 427 ether_fakeaddr(ifp); 428 } 429 430 phy = OF_getpropint(faa->fa_node, "phy-handle", 0); 431 node = OF_getnodebyphandle(phy); 432 if (node != 0) 433 sc->sc_phy_loc = OF_getpropint(node, "reg", MII_PHY_ANY); 434 else 435 sc->sc_phy_loc = MII_PHY_ANY; 436 437 sc->sc_phy_mode = CAD_PHY_MODE_RGMII; 438 OF_getprop(faa->fa_node, "phy-mode", phy_mode, sizeof(phy_mode)); 439 for (i = 0; i < nitems(cad_phy_modes); i++) { 440 if (strcmp(phy_mode, cad_phy_modes[i].name) == 0) { 441 sc->sc_phy_mode = cad_phy_modes[i].mode; 442 break; 443 } 444 } 445 446 rev = HREAD4(sc, GEM_MID); 447 ver = (rev & GEM_MID_VERSION_MASK) >> GEM_MID_VERSION_SHIFT; 448 449 sc->sc_descsize = sizeof(struct cad_desc32); 450 /* Queue 0 is always present. */ 451 sc->sc_qmask = 0x1; 452 /* 453 * Registers CFG1 and CFG6-10 are not present 454 * on Zynq-7000 / GEM version 0x2. 455 */ 456 if (ver >= 0x7) { 457 val = HREAD4(sc, GEM_CFG6); 458 if (val & GEM_CFG6_DMA64) { 459 sc->sc_descsize = sizeof(struct cad_desc64); 460 sc->sc_dma64 = 1; 461 } 462 sc->sc_qmask |= GEM_CFG6_PRIQ_MASK(val); 463 464 val = HREAD4(sc, GEM_CFG8); 465 sc->sc_ntype1scr = GEM_CFG8_NUM_TYPE1_SCR(val); 466 sc->sc_ntype2scr = GEM_CFG8_NUM_TYPE2_SCR(val); 467 } 468 469 if (OF_is_compatible(faa->fa_node, "cdns,zynq-gem")) 470 sc->sc_rxhang_erratum = 1; 471 472 rw_init(&sc->sc_cfg_lock, "cadcfg"); 473 timeout_set(&sc->sc_tick, cad_tick, sc); 474 task_set(&sc->sc_statchg_task, cad_statchg_task, sc); 475 476 rw_enter_write(&sc->sc_cfg_lock); 477 cad_reset(sc); 478 rw_exit_write(&sc->sc_cfg_lock); 479 480 sc->sc_ih = fdt_intr_establish(faa->fa_node, IPL_NET | IPL_MPSAFE, 481 cad_intr, sc, sc->sc_dev.dv_xname); 482 if (sc->sc_ih == NULL) { 483 printf(": can't establish interrupt\n"); 484 goto fail; 485 } 486 487 ifp->if_softc = sc; 488 strlcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 489 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 490 ifp->if_xflags |= IFXF_MPSAFE; 491 ifp->if_ioctl = cad_ioctl; 492 ifp->if_qstart = cad_start; 493 ifp->if_watchdog = cad_watchdog; 494 ifp->if_hardmtu = ETHER_MAX_DIX_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN; 495 ifp->if_capabilities = IFCAP_VLAN_MTU; 496 497 /* 498 * Enable transmit checksum offload only on reliable hardware. 499 * At least Zynq-7000 appears to generate bad UDP header checksum if 500 * the checksum field has not been initialized to zero and 501 * UDP payload size is less than three octets. 502 */ 503 if (0) { 504 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | 505 IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4 | 506 IFCAP_CSUM_TCPv6 | IFCAP_CSUM_UDPv6; 507 } 508 509 printf(": rev 0x%x, address %s\n", rev, 510 ether_sprintf(sc->sc_ac.ac_enaddr)); 511 512 sc->sc_mii.mii_ifp = ifp; 513 sc->sc_mii.mii_readreg = cad_mii_readreg; 514 sc->sc_mii.mii_writereg = cad_mii_writereg; 515 sc->sc_mii.mii_statchg = cad_mii_statchg; 516 ifmedia_init(&sc->sc_media, 0, cad_media_change, cad_media_status); 517 518 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, sc->sc_phy_loc, 519 MII_OFFSET_ANY, MIIF_NOISOLATE); 520 521 if (LIST_EMPTY(&sc->sc_mii.mii_phys)) { 522 printf("%s: no PHY found\n", sc->sc_dev.dv_xname); 523 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_MANUAL, 0, NULL); 524 ifmedia_set(&sc->sc_media, IFM_ETHER | IFM_MANUAL); 525 } else { 526 ifmedia_set(&sc->sc_media, IFM_ETHER | IFM_AUTO); 527 } 528 529 if_attach(ifp); 530 ether_ifattach(ifp); 531 532 #if NKSTAT > 0 533 cad_kstat_attach(sc); 534 #endif 535 536 #ifdef DDB 537 if (sc->sc_dev.dv_unit < nitems(cad_sc)) 538 cad_sc[sc->sc_dev.dv_unit] = sc; 539 #endif 540 541 return; 542 543 fail: 544 if (sc->sc_ioh != 0) 545 bus_space_unmap(sc->sc_iot, sc->sc_ioh, faa->fa_reg[0].size); 546 } 547 548 int 549 cad_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 550 { 551 struct cad_softc *sc = ifp->if_softc; 552 struct ifreq *ifr = (struct ifreq *)data; 553 int error = 0; 554 int s; 555 556 NET_UNLOCK(); 557 rw_enter_write(&sc->sc_cfg_lock); 558 NET_LOCK(); 559 s = splnet(); 560 561 switch (cmd) { 562 case SIOCSIFADDR: 563 ifp->if_flags |= IFF_UP; 564 /* FALLTHROUGH */ 565 566 case SIOCSIFFLAGS: 567 if (ISSET(ifp->if_flags, IFF_UP)) { 568 if (ISSET(ifp->if_flags, IFF_RUNNING)) 569 error = ENETRESET; 570 else 571 error = cad_up(sc); 572 } else { 573 if (ISSET(ifp->if_flags, IFF_RUNNING)) 574 cad_down(sc); 575 } 576 break; 577 578 case SIOCGIFMEDIA: 579 case SIOCSIFMEDIA: 580 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 581 break; 582 583 case SIOCGIFRXR: 584 error = if_rxr_ioctl((struct if_rxrinfo *)ifr->ifr_data, 585 NULL, MCLBYTES, &sc->sc_rx_ring); 586 break; 587 588 default: 589 error = ether_ioctl(ifp, &sc->sc_ac, cmd, data); 590 break; 591 } 592 593 if (error == ENETRESET) { 594 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 595 (IFF_UP | IFF_RUNNING)) 596 cad_iff(sc); 597 error = 0; 598 } 599 600 splx(s); 601 rw_exit_write(&sc->sc_cfg_lock); 602 603 return error; 604 } 605 606 void 607 cad_reset(struct cad_softc *sc) 608 { 609 static const unsigned int mdcclk_divs[] = { 610 8, 16, 32, 48, 64, 96, 128, 224 611 }; 612 unsigned int freq, i; 613 uint32_t div, netcfg; 614 615 rw_assert_wrlock(&sc->sc_cfg_lock); 616 617 HWRITE4(sc, GEM_NETCTL, 0); 618 HWRITE4(sc, GEM_IDR, ~0U); 619 HWRITE4(sc, GEM_RXSR, 0); 620 HWRITE4(sc, GEM_TXSR, 0); 621 if (sc->sc_dma64) { 622 HWRITE4(sc, GEM_RXQBASEHI, 0); 623 HWRITE4(sc, GEM_TXQBASEHI, 0); 624 } 625 HWRITE4(sc, GEM_RXQBASE, 0); 626 HWRITE4(sc, GEM_TXQBASE, 0); 627 628 for (i = 1; i < GEM_MAX_PRIQ; i++) { 629 if (sc->sc_qmask & (1U << i)) { 630 if (i < 8) 631 HWRITE4(sc, GEM_RXQ1BASE(i - 1), 0); 632 else 633 HWRITE4(sc, GEM_RXQ8BASE(i - 8), 0); 634 HWRITE4(sc, GEM_TXQ1BASE(i - 1), 0); 635 } 636 } 637 638 /* Disable all screeners so that Rx goes through queue 0. */ 639 for (i = 0; i < sc->sc_ntype1scr; i++) 640 HWRITE4(sc, GEM_SCR_TYPE1(i), 0); 641 for (i = 0; i < sc->sc_ntype2scr; i++) 642 HWRITE4(sc, GEM_SCR_TYPE2(i), 0); 643 644 /* MDIO clock rate must not exceed 2.5 MHz. */ 645 freq = clock_get_frequency(sc->sc_node, "pclk"); 646 for (div = 0; div < nitems(mdcclk_divs) - 1; div++) { 647 if (freq / mdcclk_divs[div] <= 2500000) 648 break; 649 } 650 KASSERT(div < nitems(mdcclk_divs)); 651 652 netcfg = HREAD4(sc, GEM_NETCFG); 653 netcfg &= ~GEM_NETCFG_MDCCLKDIV_MASK; 654 netcfg |= div << GEM_NETCFG_MDCCLKDIV_SHIFT; 655 HWRITE4(sc, GEM_NETCFG, netcfg); 656 657 /* Enable MDIO bus. */ 658 sc->sc_netctl = GEM_NETCTL_MDEN; 659 HWRITE4(sc, GEM_NETCTL, sc->sc_netctl); 660 } 661 662 int 663 cad_up(struct cad_softc *sc) 664 { 665 struct ifnet *ifp = &sc->sc_ac.ac_if; 666 struct cad_buf *rxb, *txb; 667 struct cad_desc32 *desc32; 668 struct cad_desc64 *desc64; 669 uint64_t addr; 670 int flags = BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW; 671 unsigned int i, nrxd, ntxd; 672 uint32_t val; 673 674 rw_assert_wrlock(&sc->sc_cfg_lock); 675 676 /* Release lock for memory allocation. */ 677 NET_UNLOCK(); 678 679 if (sc->sc_dma64) 680 flags |= BUS_DMA_64BIT; 681 682 ntxd = CAD_NTXDESC; 683 nrxd = CAD_NRXDESC; 684 685 /* 686 * Allocate a dummy descriptor for unused priority queues. 687 * This is necessary with GEM revisions that have no option 688 * to disable queues. 689 */ 690 if (sc->sc_qmask & ~1U) { 691 ntxd++; 692 nrxd++; 693 } 694 695 /* 696 * Set up Tx descriptor ring. 697 */ 698 699 sc->sc_txring = cad_dmamem_alloc(sc, 700 ntxd * sc->sc_descsize, sc->sc_descsize); 701 sc->sc_txdesc = sc->sc_txring->cdm_kva; 702 703 desc32 = (struct cad_desc32 *)sc->sc_txdesc; 704 desc64 = (struct cad_desc64 *)sc->sc_txdesc; 705 706 sc->sc_txbuf = malloc(sizeof(*sc->sc_txbuf) * CAD_NTXDESC, 707 M_DEVBUF, M_WAITOK); 708 for (i = 0; i < CAD_NTXDESC; i++) { 709 txb = &sc->sc_txbuf[i]; 710 bus_dmamap_create(sc->sc_dmat, MCLBYTES, CAD_NTXSEGS, 711 MCLBYTES, 0, flags, &txb->bf_map); 712 txb->bf_m = NULL; 713 714 if (sc->sc_dma64) { 715 desc64[i].d_addrhi = 0; 716 desc64[i].d_addrlo = 0; 717 desc64[i].d_status = GEM_TXD_USED; 718 if (i == CAD_NTXDESC - 1) 719 desc64[i].d_status |= GEM_TXD_WRAP; 720 } else { 721 desc32[i].d_addr = 0; 722 desc32[i].d_status = GEM_TXD_USED; 723 if (i == CAD_NTXDESC - 1) 724 desc32[i].d_status |= GEM_TXD_WRAP; 725 } 726 } 727 728 /* The remaining descriptors are dummies. */ 729 for (; i < ntxd; i++) { 730 if (sc->sc_dma64) { 731 desc64[i].d_addrhi = 0; 732 desc64[i].d_addrlo = 0; 733 desc64[i].d_status = GEM_TXD_USED | GEM_TXD_WRAP; 734 } else { 735 desc32[i].d_addr = 0; 736 desc32[i].d_status = GEM_TXD_USED | GEM_TXD_WRAP; 737 } 738 } 739 740 sc->sc_tx_prod = 0; 741 sc->sc_tx_cons = 0; 742 743 bus_dmamap_sync(sc->sc_dmat, sc->sc_txring->cdm_map, 744 0, sc->sc_txring->cdm_size, 745 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 746 747 addr = sc->sc_txring->cdm_map->dm_segs[0].ds_addr; 748 if (sc->sc_dma64) 749 HWRITE4(sc, GEM_TXQBASEHI, addr >> 32); 750 HWRITE4(sc, GEM_TXQBASE, addr); 751 752 /* Initialize unused queues. Disable them if possible. */ 753 addr += CAD_NTXDESC * sc->sc_descsize; 754 for (i = 1; i < GEM_MAX_PRIQ; i++) { 755 if (sc->sc_qmask & (1U << i)) { 756 HWRITE4(sc, GEM_TXQ1BASE(i - 1), 757 addr | GEM_TXQ1BASE_DISABLE); 758 } 759 } 760 761 /* 762 * Set up Rx descriptor ring. 763 */ 764 765 sc->sc_rxring = cad_dmamem_alloc(sc, 766 nrxd * sc->sc_descsize, sc->sc_descsize); 767 sc->sc_rxdesc = sc->sc_rxring->cdm_kva; 768 769 desc32 = (struct cad_desc32 *)sc->sc_rxdesc; 770 desc64 = (struct cad_desc64 *)sc->sc_rxdesc; 771 772 sc->sc_rxbuf = malloc(sizeof(struct cad_buf) * CAD_NRXDESC, 773 M_DEVBUF, M_WAITOK); 774 for (i = 0; i < CAD_NRXDESC; i++) { 775 rxb = &sc->sc_rxbuf[i]; 776 bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 777 MCLBYTES, 0, flags, &rxb->bf_map); 778 rxb->bf_m = NULL; 779 780 /* Mark all descriptors as used so that driver owns them. */ 781 if (sc->sc_dma64) { 782 desc64[i].d_addrhi = 0; 783 desc64[i].d_addrlo = GEM_RXD_ADDR_USED; 784 if (i == CAD_NRXDESC - 1) 785 desc64[i].d_addrlo |= GEM_RXD_ADDR_WRAP; 786 } else { 787 desc32[i].d_addr = GEM_RXD_ADDR_USED; 788 if (i == CAD_NRXDESC - 1) 789 desc32[i].d_addr |= GEM_RXD_ADDR_WRAP; 790 } 791 } 792 793 /* The remaining descriptors are dummies. */ 794 for (; i < nrxd; i++) { 795 if (sc->sc_dma64) { 796 desc64[i].d_addrhi = 0; 797 desc64[i].d_addrlo = 798 GEM_RXD_ADDR_USED | GEM_RXD_ADDR_WRAP; 799 } else { 800 desc32[i].d_addr = 801 GEM_RXD_ADDR_USED | GEM_RXD_ADDR_WRAP; 802 } 803 } 804 805 if_rxr_init(&sc->sc_rx_ring, 2, CAD_NRXDESC); 806 807 sc->sc_rx_prod = 0; 808 sc->sc_rx_cons = 0; 809 cad_rxfill(sc); 810 811 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxring->cdm_map, 812 0, sc->sc_rxring->cdm_size, 813 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 814 815 addr = sc->sc_rxring->cdm_map->dm_segs[0].ds_addr; 816 if (sc->sc_dma64) 817 HWRITE4(sc, GEM_RXQBASEHI, addr >> 32); 818 HWRITE4(sc, GEM_RXQBASE, addr); 819 820 /* Initialize unused queues. Disable them if possible. */ 821 addr += sc->sc_descsize * CAD_NRXDESC; 822 for (i = 1; i < GEM_MAX_PRIQ; i++) { 823 if (sc->sc_qmask & (1U << i)) { 824 if (i < 8) { 825 HWRITE4(sc, GEM_RXQ1BASE(i - 1), 826 addr | GEM_RXQ1BASE_DISABLE); 827 } else { 828 HWRITE4(sc, GEM_RXQ8BASE(i - 8), 829 addr | GEM_RXQ8BASE_DISABLE); 830 } 831 } 832 } 833 834 NET_LOCK(); 835 836 /* 837 * Set MAC address filters. 838 */ 839 840 HWRITE4(sc, GEM_LADDRL(0), sc->sc_ac.ac_enaddr[0] | 841 ((uint32_t)sc->sc_ac.ac_enaddr[1] << 8) | 842 ((uint32_t)sc->sc_ac.ac_enaddr[2] << 16) | 843 ((uint32_t)sc->sc_ac.ac_enaddr[3] << 24)); 844 HWRITE4(sc, GEM_LADDRH(0), sc->sc_ac.ac_enaddr[4] | 845 ((uint32_t)sc->sc_ac.ac_enaddr[5] << 8)); 846 847 for (i = 1; i < GEM_LADDRNUM; i++) { 848 HWRITE4(sc, GEM_LADDRL(i), 0); 849 HWRITE4(sc, GEM_LADDRH(i), 0); 850 } 851 852 cad_iff(sc); 853 854 clock_set_frequency(sc->sc_node, GEM_CLK_TX, 2500000); 855 clock_enable(sc->sc_node, GEM_CLK_TX); 856 delay(1000); 857 858 val = HREAD4(sc, GEM_NETCFG); 859 860 val |= GEM_NETCFG_FCSREM | GEM_NETCFG_RXCSUMEN | GEM_NETCFG_1000 | 861 GEM_NETCFG_100 | GEM_NETCFG_FDEN | GEM_NETCFG_1536RXEN; 862 val &= ~GEM_NETCFG_RXOFFS_MASK; 863 val |= ETHER_ALIGN << GEM_NETCFG_RXOFFS_SHIFT; 864 val &= ~GEM_NETCFG_BCASTDI; 865 866 if (sc->sc_phy_mode == CAD_PHY_MODE_SGMII) 867 val |= GEM_NETCFG_SGMIIEN | GEM_NETCFG_PCSSEL; 868 else 869 val &= ~(GEM_NETCFG_SGMIIEN | GEM_NETCFG_PCSSEL); 870 871 HWRITE4(sc, GEM_NETCFG, val); 872 873 val = HREAD4(sc, GEM_DMACR); 874 875 if (sc->sc_dma64) 876 val |= GEM_DMACR_DMA64; 877 else 878 val &= ~GEM_DMACR_DMA64; 879 /* Use CPU's native byte order with descriptor words. */ 880 #if BYTE_ORDER == BIG_ENDIAN 881 val |= GEM_DMACR_ES_DESCR; 882 #else 883 val &= ~GEM_DMACR_ES_DESCR; 884 #endif 885 val &= ~GEM_DMACR_ES_PDATA; 886 val |= GEM_DMACR_AHBDISC | GEM_DMACR_TXSIZE; 887 val &= ~GEM_DMACR_RXSIZE_MASK; 888 val |= GEM_DMACR_RXSIZE_8K; 889 val &= ~GEM_DMACR_RXBUF_MASK; 890 val |= (MCLBYTES / 64) << GEM_DMACR_RXBUF_SHIFT; 891 val &= ~GEM_DMACR_BLEN_MASK; 892 val |= GEM_DMACR_BLEN_16; 893 894 if (ifp->if_capabilities & IFCAP_CSUM_IPv4) 895 val |= GEM_DMACR_TXCSUMEN; 896 897 HWRITE4(sc, GEM_DMACR, val); 898 899 /* Clear statistics. */ 900 HWRITE4(sc, GEM_NETCTL, sc->sc_netctl | GEM_NETCTL_STATCLR); 901 902 /* Enable Rx and Tx. */ 903 sc->sc_netctl |= GEM_NETCTL_RXEN | GEM_NETCTL_TXEN; 904 HWRITE4(sc, GEM_NETCTL, sc->sc_netctl); 905 906 /* Enable interrupts. */ 907 HWRITE4(sc, GEM_IER, GEM_IXR_HRESP | GEM_IXR_RXOVR | GEM_IXR_RXDONE | 908 GEM_IXR_TXDONE); 909 910 if (sc->sc_rxhang_erratum) 911 HWRITE4(sc, GEM_IER, GEM_IXR_RXUSED); 912 913 if (!LIST_EMPTY(&sc->sc_mii.mii_phys)) 914 mii_mediachg(&sc->sc_mii); 915 916 ifp->if_flags |= IFF_RUNNING; 917 ifq_clr_oactive(&ifp->if_snd); 918 919 timeout_add_sec(&sc->sc_tick, 1); 920 921 return 0; 922 } 923 924 void 925 cad_down(struct cad_softc *sc) 926 { 927 struct ifnet *ifp = &sc->sc_ac.ac_if; 928 struct cad_buf *rxb, *txb; 929 unsigned int i, timeout; 930 931 rw_assert_wrlock(&sc->sc_cfg_lock); 932 933 ifp->if_flags &= ~IFF_RUNNING; 934 935 ifq_clr_oactive(&ifp->if_snd); 936 ifp->if_timer = 0; 937 938 /* Avoid lock order issues with barriers. */ 939 NET_UNLOCK(); 940 941 timeout_del_barrier(&sc->sc_tick); 942 943 /* Disable data transfer. */ 944 sc->sc_netctl &= ~(GEM_NETCTL_TXEN | GEM_NETCTL_RXEN); 945 HWRITE4(sc, GEM_NETCTL, sc->sc_netctl); 946 947 /* Disable all interrupts. */ 948 HWRITE4(sc, GEM_IDR, ~0U); 949 950 /* Wait for transmitter to become idle. */ 951 for (timeout = 1000; timeout > 0; timeout--) { 952 if ((HREAD4(sc, GEM_TXSR) & GEM_TXSR_TXGO) == 0) 953 break; 954 delay(10); 955 } 956 if (timeout == 0) 957 printf("%s: transmitter not idle\n", sc->sc_dev.dv_xname); 958 959 mii_down(&sc->sc_mii); 960 961 /* Wait for activity to cease. */ 962 intr_barrier(sc->sc_ih); 963 ifq_barrier(&ifp->if_snd); 964 taskq_del_barrier(systq, &sc->sc_statchg_task); 965 966 /* Disable the packet clock as it is not needed any longer. */ 967 clock_disable(sc->sc_node, GEM_CLK_TX); 968 969 cad_reset(sc); 970 971 /* 972 * Tear down the Tx descriptor ring. 973 */ 974 975 for (i = 0; i < CAD_NTXDESC; i++) { 976 txb = &sc->sc_txbuf[i]; 977 if (txb->bf_m != NULL) { 978 bus_dmamap_sync(sc->sc_dmat, txb->bf_map, 0, 979 txb->bf_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 980 bus_dmamap_unload(sc->sc_dmat, txb->bf_map); 981 m_freem(txb->bf_m); 982 } 983 bus_dmamap_destroy(sc->sc_dmat, txb->bf_map); 984 } 985 free(sc->sc_txbuf, M_DEVBUF, sizeof(*sc->sc_txbuf) * CAD_NTXDESC); 986 sc->sc_txbuf = NULL; 987 988 cad_dmamem_free(sc, sc->sc_txring); 989 sc->sc_txring = NULL; 990 sc->sc_txdesc = NULL; 991 992 /* 993 * Tear down the Rx descriptor ring. 994 */ 995 996 for (i = 0; i < CAD_NRXDESC; i++) { 997 rxb = &sc->sc_rxbuf[i]; 998 if (rxb->bf_m != NULL) { 999 bus_dmamap_sync(sc->sc_dmat, rxb->bf_map, 0, 1000 rxb->bf_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1001 bus_dmamap_unload(sc->sc_dmat, rxb->bf_map); 1002 m_freem(rxb->bf_m); 1003 } 1004 bus_dmamap_destroy(sc->sc_dmat, rxb->bf_map); 1005 } 1006 free(sc->sc_rxbuf, M_DEVBUF, sizeof(*sc->sc_txbuf) * CAD_NRXDESC); 1007 sc->sc_rxbuf = NULL; 1008 1009 cad_dmamem_free(sc, sc->sc_rxring); 1010 sc->sc_rxring = NULL; 1011 sc->sc_rxdesc = NULL; 1012 1013 NET_LOCK(); 1014 } 1015 1016 uint8_t 1017 cad_hash_mac(const uint8_t *eaddr) 1018 { 1019 uint64_t val = 0; 1020 int i; 1021 uint8_t hash = 0; 1022 1023 for (i = ETHER_ADDR_LEN - 1; i >= 0; i--) 1024 val = (val << 8) | eaddr[i]; 1025 1026 for (i = 0; i < 8; i++) { 1027 hash ^= val; 1028 val >>= 6; 1029 } 1030 1031 return hash & 0x3f; 1032 } 1033 1034 void 1035 cad_iff(struct cad_softc *sc) 1036 { 1037 struct arpcom *ac = &sc->sc_ac; 1038 struct ifnet *ifp = &sc->sc_ac.ac_if; 1039 struct ether_multi *enm; 1040 struct ether_multistep step; 1041 uint64_t hash; 1042 uint32_t netcfg; 1043 1044 rw_assert_wrlock(&sc->sc_cfg_lock); 1045 1046 netcfg = HREAD4(sc, GEM_NETCFG); 1047 netcfg &= ~GEM_NETCFG_UCASTHASHEN; 1048 1049 ifp->if_flags &= ~IFF_ALLMULTI; 1050 1051 if (ifp->if_flags & IFF_PROMISC) { 1052 netcfg |= GEM_NETCFG_COPYALL; 1053 netcfg &= ~GEM_NETCFG_MCASTHASHEN; 1054 } else { 1055 netcfg &= ~GEM_NETCFG_COPYALL; 1056 netcfg |= GEM_NETCFG_MCASTHASHEN; 1057 1058 if (ac->ac_multirangecnt > 0) 1059 ifp->if_flags |= IFF_ALLMULTI; 1060 1061 if (ifp->if_flags & IFF_ALLMULTI) { 1062 hash = ~0ULL; 1063 } else { 1064 hash = 0; 1065 ETHER_FIRST_MULTI(step, ac, enm); 1066 while (enm != NULL) { 1067 hash |= 1ULL << cad_hash_mac(enm->enm_addrlo); 1068 ETHER_NEXT_MULTI(step, enm); 1069 } 1070 } 1071 1072 HWRITE4(sc, GEM_HASHL, hash); 1073 HWRITE4(sc, GEM_HASHH, hash >> 32); 1074 } 1075 1076 HWRITE4(sc, GEM_NETCFG, netcfg); 1077 } 1078 1079 void 1080 cad_start(struct ifqueue *ifq) 1081 { 1082 struct ifnet *ifp = ifq->ifq_if; 1083 struct cad_softc *sc = ifp->if_softc; 1084 struct mbuf *m; 1085 unsigned int free, head, used; 1086 1087 free = sc->sc_tx_cons; 1088 head = sc->sc_tx_prod; 1089 if (free <= head) 1090 free += CAD_NTXDESC; 1091 free -= head; 1092 1093 for (;;) { 1094 if (free <= CAD_NTXSEGS) { 1095 ifq_set_oactive(ifq); 1096 break; 1097 } 1098 1099 m = ifq_dequeue(ifq); 1100 if (m == NULL) 1101 break; 1102 1103 used = cad_encap(sc, m); 1104 if (used == 0) { 1105 m_freem(m); 1106 continue; 1107 } 1108 1109 #if NBPFILTER > 0 1110 if (ifp->if_bpf != NULL) 1111 bpf_mtap_ether(ifp->if_bpf, m, BPF_DIRECTION_OUT); 1112 #endif 1113 1114 ifp->if_timer = 5; 1115 1116 KASSERT(free >= used); 1117 free -= used; 1118 } 1119 1120 HWRITE4(sc, GEM_NETCTL, sc->sc_netctl | GEM_NETCTL_STARTTX); 1121 } 1122 1123 void 1124 cad_watchdog(struct ifnet *ifp) 1125 { 1126 struct cad_softc *sc = ifp->if_softc; 1127 1128 ifp->if_timer = 0; 1129 1130 if ((ifp->if_flags & IFF_RUNNING) == 0) 1131 return; 1132 1133 if (sc->sc_tx_cons == sc->sc_tx_prod) 1134 return; 1135 1136 /* XXX */ 1137 HWRITE4(sc, GEM_NETCTL, sc->sc_netctl | GEM_NETCTL_STARTTX); 1138 } 1139 1140 unsigned int 1141 cad_encap(struct cad_softc *sc, struct mbuf *m) 1142 { 1143 bus_dmamap_t map; 1144 struct cad_buf *txb; 1145 struct cad_desc32 *desc32 = (struct cad_desc32 *)sc->sc_txdesc; 1146 struct cad_desc64 *desc64 = (struct cad_desc64 *)sc->sc_txdesc; 1147 unsigned int head, idx, nsegs; 1148 uint32_t status; 1149 int i; 1150 1151 head = sc->sc_tx_prod; 1152 1153 txb = &sc->sc_txbuf[head]; 1154 map = txb->bf_map; 1155 1156 switch (bus_dmamap_load_mbuf(sc->sc_dmat, map, m, BUS_DMA_NOWAIT)) { 1157 case 0: 1158 break; 1159 case EFBIG: 1160 if (m_defrag(m, M_DONTWAIT) != 0) 1161 return 0; 1162 if (bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1163 BUS_DMA_NOWAIT) != 0) 1164 return 0; 1165 break; 1166 default: 1167 return 0; 1168 } 1169 1170 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1171 BUS_DMASYNC_PREWRITE); 1172 1173 nsegs = map->dm_nsegs; 1174 KASSERT(nsegs > 0); 1175 1176 txb->bf_m = m; 1177 1178 /* 1179 * Fill descriptors in reverse order so that all the descriptors 1180 * are ready when the first descriptor's GEM_TXD_USED bit is cleared. 1181 */ 1182 for (i = nsegs - 1; i >= 0; i--) { 1183 idx = (head + i) % CAD_NTXDESC; 1184 1185 status = map->dm_segs[i].ds_len & GEM_TXD_LEN_MASK; 1186 if (i == nsegs - 1) 1187 status |= GEM_TXD_LAST; 1188 if (idx == CAD_NTXDESC - 1) 1189 status |= GEM_TXD_WRAP; 1190 1191 if (sc->sc_dma64) { 1192 uint64_t addr = map->dm_segs[i].ds_addr; 1193 1194 desc64[idx].d_addrlo = addr; 1195 desc64[idx].d_addrhi = addr >> 32; 1196 } else { 1197 desc32[idx].d_addr = map->dm_segs[i].ds_addr; 1198 } 1199 1200 /* Make d_addr visible before GEM_TXD_USED is cleared 1201 * in d_status. */ 1202 bus_dmamap_sync(sc->sc_dmat, sc->sc_txring->cdm_map, 1203 idx * sc->sc_descsize, sc->sc_descsize, 1204 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1205 1206 if (sc->sc_dma64) 1207 desc64[idx].d_status = status; 1208 else 1209 desc32[idx].d_status = status; 1210 1211 bus_dmamap_sync(sc->sc_dmat, sc->sc_txring->cdm_map, 1212 idx * sc->sc_descsize, sc->sc_descsize, 1213 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1214 } 1215 1216 sc->sc_tx_prod = (head + nsegs) % CAD_NTXDESC; 1217 1218 return nsegs; 1219 } 1220 1221 int 1222 cad_intr(void *arg) 1223 { 1224 struct cad_softc *sc = arg; 1225 struct ifnet *ifp = &sc->sc_ac.ac_if; 1226 uint32_t isr; 1227 1228 isr = HREAD4(sc, GEM_ISR); 1229 HWRITE4(sc, GEM_ISR, isr); 1230 1231 if (isr & GEM_IXR_RXDONE) 1232 cad_rxeof(sc); 1233 if (isr & GEM_IXR_TXDONE) 1234 cad_txeof(sc); 1235 1236 if (isr & GEM_IXR_RXOVR) 1237 ifp->if_ierrors++; 1238 1239 if (sc->sc_rxhang_erratum && (isr & GEM_IXR_RXUSED)) { 1240 /* 1241 * Try to flush a packet from the Rx SRAM to avoid triggering 1242 * the Rx hang. 1243 */ 1244 HWRITE4(sc, GEM_NETCTL, sc->sc_netctl | GEM_NETCTL_DPRAM); 1245 cad_rxfill(sc); 1246 } 1247 1248 /* If there has been a DMA error, stop the interface to limit damage. */ 1249 if (isr & GEM_IXR_HRESP) { 1250 sc->sc_netctl &= ~(GEM_NETCTL_TXEN | GEM_NETCTL_RXEN); 1251 HWRITE4(sc, GEM_NETCTL, sc->sc_netctl); 1252 HWRITE4(sc, GEM_IDR, ~0U); 1253 1254 printf("%s: hresp error, interface stopped\n", 1255 sc->sc_dev.dv_xname); 1256 } 1257 1258 return 1; 1259 } 1260 1261 void 1262 cad_rxeof(struct cad_softc *sc) 1263 { 1264 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 1265 struct ifnet *ifp = &sc->sc_ac.ac_if; 1266 struct mbuf *m; 1267 struct cad_buf *rxb; 1268 struct cad_desc32 *desc32 = (struct cad_desc32 *)sc->sc_rxdesc; 1269 struct cad_desc64 *desc64 = (struct cad_desc64 *)sc->sc_rxdesc; 1270 size_t len; 1271 unsigned int idx; 1272 uint32_t addr, status; 1273 1274 idx = sc->sc_rx_cons; 1275 1276 while (if_rxr_inuse(&sc->sc_rx_ring) > 0) { 1277 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxring->cdm_map, 1278 idx * sc->sc_descsize, sc->sc_descsize, 1279 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1280 1281 if (sc->sc_dma64) 1282 addr = desc64[idx].d_addrlo; 1283 else 1284 addr = desc32[idx].d_addr; 1285 if ((addr & GEM_RXD_ADDR_USED) == 0) 1286 break; 1287 1288 /* Prevent premature read of d_status. */ 1289 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxring->cdm_map, 1290 idx * sc->sc_descsize, sc->sc_descsize, 1291 BUS_DMASYNC_POSTREAD); 1292 1293 if (sc->sc_dma64) 1294 status = desc64[idx].d_status; 1295 else 1296 status = desc32[idx].d_status; 1297 len = status & GEM_RXD_LEN_MASK; 1298 1299 rxb = &sc->sc_rxbuf[idx]; 1300 1301 bus_dmamap_sync(sc->sc_dmat, rxb->bf_map, ETHER_ALIGN, len, 1302 BUS_DMASYNC_POSTREAD); 1303 bus_dmamap_unload(sc->sc_dmat, rxb->bf_map); 1304 1305 m = rxb->bf_m; 1306 rxb->bf_m = NULL; 1307 KASSERT(m != NULL); 1308 1309 if_rxr_put(&sc->sc_rx_ring, 1); 1310 idx = (idx + 1) % CAD_NRXDESC; 1311 1312 if ((status & (GEM_RXD_SOF | GEM_RXD_EOF)) != 1313 (GEM_RXD_SOF | GEM_RXD_EOF)) { 1314 m_freem(m); 1315 ifp->if_ierrors++; 1316 continue; 1317 } 1318 1319 m_adj(m, ETHER_ALIGN); 1320 m->m_len = m->m_pkthdr.len = len; 1321 1322 m->m_pkthdr.csum_flags = 0; 1323 switch (status & GEM_RXD_CSUM_MASK) { 1324 case GEM_RXD_CSUM_IP_OK: 1325 m->m_pkthdr.csum_flags = M_IPV4_CSUM_IN_OK; 1326 break; 1327 case GEM_RXD_CSUM_TCP_OK: 1328 case GEM_RXD_CSUM_UDP_OK: 1329 m->m_pkthdr.csum_flags = M_IPV4_CSUM_IN_OK | 1330 M_TCP_CSUM_IN_OK | M_UDP_CSUM_IN_OK; 1331 break; 1332 } 1333 1334 ml_enqueue(&ml, m); 1335 1336 sc->sc_rxdone = 1; 1337 } 1338 1339 sc->sc_rx_cons = idx; 1340 1341 cad_rxfill(sc); 1342 1343 if (ifiq_input(&ifp->if_rcv, &ml)) 1344 if_rxr_livelocked(&sc->sc_rx_ring); 1345 } 1346 1347 void 1348 cad_rxfill(struct cad_softc *sc) 1349 { 1350 struct cad_buf *rxb; 1351 struct cad_desc32 *desc32 = (struct cad_desc32 *)sc->sc_rxdesc; 1352 struct cad_desc64 *desc64 = (struct cad_desc64 *)sc->sc_rxdesc; 1353 uint64_t addr; 1354 unsigned int idx; 1355 u_int slots; 1356 1357 idx = sc->sc_rx_prod; 1358 1359 for (slots = if_rxr_get(&sc->sc_rx_ring, CAD_NRXDESC); 1360 slots > 0; slots--) { 1361 rxb = &sc->sc_rxbuf[idx]; 1362 rxb->bf_m = cad_alloc_mbuf(sc, rxb->bf_map); 1363 if (rxb->bf_m == NULL) 1364 break; 1365 1366 addr = rxb->bf_map->dm_segs[0].ds_addr; 1367 KASSERT((addr & (GEM_RXD_ADDR_WRAP | GEM_RXD_ADDR_USED)) == 0); 1368 if (idx == CAD_NRXDESC - 1) 1369 addr |= GEM_RXD_ADDR_WRAP; 1370 1371 if (sc->sc_dma64) { 1372 desc64[idx].d_addrhi = addr >> 32; 1373 desc64[idx].d_status = 0; 1374 } else { 1375 desc32[idx].d_status = 0; 1376 } 1377 1378 /* Make d_addrhi and d_status visible before clearing 1379 * GEM_RXD_ADDR_USED in d_addr or d_addrlo. */ 1380 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxring->cdm_map, 1381 idx * sc->sc_descsize, sc->sc_descsize, 1382 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1383 1384 if (sc->sc_dma64) 1385 desc64[idx].d_addrlo = addr; 1386 else 1387 desc32[idx].d_addr = addr; 1388 1389 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxring->cdm_map, 1390 idx * sc->sc_descsize, sc->sc_descsize, 1391 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1392 1393 idx = (idx + 1) % CAD_NRXDESC; 1394 } 1395 if_rxr_put(&sc->sc_rx_ring, slots); 1396 1397 sc->sc_rx_prod = idx; 1398 } 1399 1400 void 1401 cad_txeof(struct cad_softc *sc) 1402 { 1403 struct ifnet *ifp = &sc->sc_ac.ac_if; 1404 struct cad_buf *txb; 1405 struct cad_desc32 *desc32 = (struct cad_desc32 *)sc->sc_txdesc; 1406 struct cad_desc64 *desc64 = (struct cad_desc64 *)sc->sc_txdesc; 1407 unsigned int free = 0; 1408 unsigned int idx, nsegs; 1409 uint32_t status; 1410 1411 idx = sc->sc_tx_cons; 1412 1413 while (idx != sc->sc_tx_prod) { 1414 bus_dmamap_sync(sc->sc_dmat, sc->sc_txring->cdm_map, 1415 idx * sc->sc_descsize, sc->sc_descsize, 1416 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1417 1418 if (sc->sc_dma64) 1419 status = desc64[idx].d_status; 1420 else 1421 status = desc32[idx].d_status; 1422 if ((status & GEM_TXD_USED) == 0) 1423 break; 1424 1425 if (status & (GEM_TXD_RLIMIT | GEM_TXD_CORRUPT | 1426 GEM_TXD_LCOLL | GEM_TXD_CSUMERR_MASK)) 1427 ifp->if_oerrors++; 1428 1429 txb = &sc->sc_txbuf[idx]; 1430 nsegs = txb->bf_map->dm_nsegs; 1431 KASSERT(nsegs > 0); 1432 1433 bus_dmamap_sync(sc->sc_dmat, txb->bf_map, 0, 1434 txb->bf_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1435 bus_dmamap_unload(sc->sc_dmat, txb->bf_map); 1436 1437 m_freem(txb->bf_m); 1438 txb->bf_m = NULL; 1439 1440 for (;;) { 1441 idx = (idx + 1) % CAD_NTXDESC; 1442 1443 nsegs--; 1444 if (nsegs == 0) 1445 break; 1446 1447 /* 1448 * The controller marks only the initial segment used. 1449 * Mark the remaining segments used manually, so that 1450 * the controller will not accidentally use them later. 1451 * 1452 * This could be done lazily on the Tx ring producer 1453 * side by ensuring that the subsequent descriptor 1454 * after the actual segments is marked used. 1455 * However, this would make the ring trickier to debug. 1456 */ 1457 1458 bus_dmamap_sync(sc->sc_dmat, sc->sc_txring->cdm_map, 1459 idx * sc->sc_descsize, sc->sc_descsize, 1460 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1461 1462 if (sc->sc_dma64) 1463 desc64[idx].d_status |= GEM_TXD_USED; 1464 else 1465 desc32[idx].d_status |= GEM_TXD_USED; 1466 1467 bus_dmamap_sync(sc->sc_dmat, sc->sc_txring->cdm_map, 1468 idx * sc->sc_descsize, sc->sc_descsize, 1469 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1470 } 1471 1472 free++; 1473 } 1474 1475 if (free == 0) 1476 return; 1477 1478 sc->sc_tx_cons = idx; 1479 1480 if (ifq_is_oactive(&ifp->if_snd)) 1481 ifq_restart(&ifp->if_snd); 1482 } 1483 1484 void 1485 cad_tick(void *arg) 1486 { 1487 struct cad_softc *sc = arg; 1488 struct ifnet *ifp = &sc->sc_ac.ac_if; 1489 int s; 1490 1491 if ((ifp->if_flags & IFF_RUNNING) == 0) 1492 return; 1493 1494 s = splnet(); 1495 1496 mii_tick(&sc->sc_mii); 1497 1498 /* 1499 * If there has been no Rx for a moment, Rx DMA might be stuck. 1500 * Try to recover by restarting the receiver. 1501 */ 1502 if (sc->sc_rxhang_erratum && !sc->sc_rxdone) { 1503 HWRITE4(sc, GEM_NETCTL, sc->sc_netctl & ~GEM_NETCTL_RXEN); 1504 (void)HREAD4(sc, GEM_NETCTL); 1505 HWRITE4(sc, GEM_NETCTL, sc->sc_netctl); 1506 } 1507 sc->sc_rxdone = 0; 1508 1509 splx(s); 1510 1511 timeout_add_sec(&sc->sc_tick, 1); 1512 } 1513 1514 int 1515 cad_media_change(struct ifnet *ifp) 1516 { 1517 struct cad_softc *sc = ifp->if_softc; 1518 1519 if (!LIST_EMPTY(&sc->sc_mii.mii_phys)) 1520 mii_mediachg(&sc->sc_mii); 1521 1522 return 0; 1523 } 1524 1525 void 1526 cad_media_status(struct ifnet *ifp, struct ifmediareq *imr) 1527 { 1528 struct cad_softc *sc = ifp->if_softc; 1529 1530 if (!LIST_EMPTY(&sc->sc_mii.mii_phys)) { 1531 mii_pollstat(&sc->sc_mii); 1532 imr->ifm_active = sc->sc_mii.mii_media_active; 1533 imr->ifm_status = sc->sc_mii.mii_media_status; 1534 } 1535 } 1536 1537 int 1538 cad_mii_wait(struct cad_softc *sc) 1539 { 1540 int timeout; 1541 1542 for (timeout = 10000; timeout > 0; timeout--) { 1543 if (HREAD4(sc, GEM_NETSR) & GEM_NETSR_PHY_MGMT_IDLE) 1544 break; 1545 delay(10); 1546 } 1547 if (timeout == 0) 1548 return ETIMEDOUT; 1549 return 0; 1550 } 1551 1552 void 1553 cad_mii_oper(struct cad_softc *sc, int phy_no, int reg, uint32_t oper) 1554 { 1555 oper |= (phy_no << GEM_PHYMNTNC_ADDR_SHIFT) & GEM_PHYMNTNC_ADDR_MASK; 1556 oper |= (reg << GEM_PHYMNTNC_REG_SHIFT) & GEM_PHYMNTNC_REG_MASK; 1557 oper |= GEM_PHYMNTNC_CLAUSE_22 | GEM_PHYMNTNC_MUST_10; 1558 1559 if (cad_mii_wait(sc) != 0) { 1560 printf("%s: MII bus idle timeout\n", sc->sc_dev.dv_xname); 1561 return; 1562 } 1563 1564 HWRITE4(sc, GEM_PHYMNTNC, oper); 1565 1566 if (cad_mii_wait(sc) != 0) { 1567 printf("%s: MII bus operation timeout\n", sc->sc_dev.dv_xname); 1568 return; 1569 } 1570 } 1571 1572 int 1573 cad_mii_readreg(struct device *self, int phy_no, int reg) 1574 { 1575 struct cad_softc *sc = (struct cad_softc *)self; 1576 int val; 1577 1578 cad_mii_oper(sc, phy_no, reg, GEM_PHYMNTNC_OP_READ); 1579 1580 val = HREAD4(sc, GEM_PHYMNTNC) & GEM_PHYMNTNC_DATA_MASK; 1581 1582 /* The MAC does not handle 1000baseT in half duplex mode. */ 1583 if (reg == MII_EXTSR) 1584 val &= ~EXTSR_1000THDX; 1585 1586 return val; 1587 } 1588 1589 void 1590 cad_mii_writereg(struct device *self, int phy_no, int reg, int val) 1591 { 1592 struct cad_softc *sc = (struct cad_softc *)self; 1593 1594 cad_mii_oper(sc, phy_no, reg, GEM_PHYMNTNC_OP_WRITE | 1595 (val & GEM_PHYMNTNC_DATA_MASK)); 1596 } 1597 1598 void 1599 cad_mii_statchg(struct device *self) 1600 { 1601 struct cad_softc *sc = (struct cad_softc *)self; 1602 uint32_t netcfg; 1603 1604 netcfg = HREAD4(sc, GEM_NETCFG); 1605 if (sc->sc_mii.mii_media_active & IFM_FDX) 1606 netcfg |= GEM_NETCFG_FDEN; 1607 else 1608 netcfg &= ~GEM_NETCFG_FDEN; 1609 1610 netcfg &= ~(GEM_NETCFG_100 | GEM_NETCFG_1000); 1611 switch (IFM_SUBTYPE(sc->sc_mii.mii_media_active)) { 1612 default: 1613 sc->sc_tx_freq = 2500000; 1614 break; 1615 case IFM_100_TX: 1616 netcfg |= GEM_NETCFG_100; 1617 sc->sc_tx_freq = 25000000; 1618 break; 1619 case IFM_1000_T: 1620 netcfg |= GEM_NETCFG_100 | GEM_NETCFG_1000; 1621 sc->sc_tx_freq = 125000000; 1622 break; 1623 } 1624 1625 HWRITE4(sc, GEM_NETCFG, netcfg); 1626 1627 /* Defer clock setting because it allocates memory with M_WAITOK. */ 1628 task_add(systq, &sc->sc_statchg_task); 1629 } 1630 1631 void 1632 cad_statchg_task(void *arg) 1633 { 1634 struct cad_softc *sc = arg; 1635 1636 clock_set_frequency(sc->sc_node, GEM_CLK_TX, sc->sc_tx_freq); 1637 } 1638 1639 struct cad_dmamem * 1640 cad_dmamem_alloc(struct cad_softc *sc, bus_size_t size, bus_size_t align) 1641 { 1642 struct cad_dmamem *cdm; 1643 bus_size_t boundary = 0; 1644 int flags = BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW; 1645 int nsegs; 1646 1647 cdm = malloc(sizeof(*cdm), M_DEVBUF, M_WAITOK | M_ZERO); 1648 cdm->cdm_size = size; 1649 1650 if (sc->sc_dma64) { 1651 /* 1652 * The segment contains an actual ring and possibly 1653 * a dummy ring for unused priority queues. 1654 * The segment must not cross a 32-bit boundary so that 1655 * the rings have the same base address bits 63:32. 1656 */ 1657 boundary = 1ULL << 32; 1658 flags |= BUS_DMA_64BIT; 1659 } 1660 1661 if (bus_dmamap_create(sc->sc_dmat, size, 1, size, boundary, 1662 flags, &cdm->cdm_map) != 0) 1663 goto cdmfree; 1664 if (bus_dmamem_alloc(sc->sc_dmat, size, align, boundary, 1665 &cdm->cdm_seg, 1, &nsegs, BUS_DMA_WAITOK) != 0) 1666 goto destroy; 1667 if (bus_dmamem_map(sc->sc_dmat, &cdm->cdm_seg, nsegs, size, 1668 &cdm->cdm_kva, BUS_DMA_WAITOK | BUS_DMA_COHERENT) != 0) 1669 goto free; 1670 if (bus_dmamap_load(sc->sc_dmat, cdm->cdm_map, cdm->cdm_kva, size, 1671 NULL, BUS_DMA_WAITOK) != 0) 1672 goto unmap; 1673 memset(cdm->cdm_kva, 0, size); 1674 return cdm; 1675 1676 unmap: 1677 bus_dmamem_unmap(sc->sc_dmat, cdm->cdm_kva, size); 1678 free: 1679 bus_dmamem_free(sc->sc_dmat, &cdm->cdm_seg, 1); 1680 destroy: 1681 bus_dmamap_destroy(sc->sc_dmat, cdm->cdm_map); 1682 cdmfree: 1683 free(cdm, M_DEVBUF, sizeof(*cdm)); 1684 return NULL; 1685 } 1686 1687 void 1688 cad_dmamem_free(struct cad_softc *sc, struct cad_dmamem *cdm) 1689 { 1690 bus_dmamem_unmap(sc->sc_dmat, cdm->cdm_kva, cdm->cdm_size); 1691 bus_dmamem_free(sc->sc_dmat, &cdm->cdm_seg, 1); 1692 bus_dmamap_destroy(sc->sc_dmat, cdm->cdm_map); 1693 free(cdm, M_DEVBUF, sizeof(*cdm)); 1694 } 1695 1696 struct mbuf * 1697 cad_alloc_mbuf(struct cad_softc *sc, bus_dmamap_t map) 1698 { 1699 struct mbuf *m; 1700 1701 m = MCLGETL(NULL, M_DONTWAIT, MCLBYTES); 1702 if (m == NULL) 1703 return NULL; 1704 m->m_len = m->m_pkthdr.len = MCLBYTES; 1705 1706 if (bus_dmamap_load_mbuf(sc->sc_dmat, map, m, BUS_DMA_NOWAIT) != 0) { 1707 m_freem(m); 1708 return NULL; 1709 } 1710 1711 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1712 BUS_DMASYNC_PREREAD); 1713 1714 return m; 1715 } 1716 1717 #if NKSTAT > 0 1718 enum cad_stat { 1719 cad_stat_tx_toto, 1720 cad_stat_tx_totp, 1721 cad_stat_tx_bcast, 1722 cad_stat_tx_mcast, 1723 cad_stat_tx_pause, 1724 cad_stat_tx_h64, 1725 cad_stat_tx_h65, 1726 cad_stat_tx_h128, 1727 cad_stat_tx_h256, 1728 cad_stat_tx_h512, 1729 cad_stat_tx_h1024, 1730 cad_stat_tx_underrun, 1731 cad_stat_tx_scoll, 1732 cad_stat_tx_mcoll, 1733 cad_stat_tx_ecoll, 1734 cad_stat_tx_lcoll, 1735 cad_stat_tx_defer, 1736 cad_stat_tx_sense, 1737 cad_stat_rx_toto, 1738 cad_stat_rx_totp, 1739 cad_stat_rx_bcast, 1740 cad_stat_rx_mcast, 1741 cad_stat_rx_pause, 1742 cad_stat_rx_h64, 1743 cad_stat_rx_h65, 1744 cad_stat_rx_h128, 1745 cad_stat_rx_h256, 1746 cad_stat_rx_h512, 1747 cad_stat_rx_h1024, 1748 cad_stat_rx_undersz, 1749 cad_stat_rx_oversz, 1750 cad_stat_rx_jabber, 1751 cad_stat_rx_fcs, 1752 cad_stat_rx_symberr, 1753 cad_stat_rx_align, 1754 cad_stat_rx_reserr, 1755 cad_stat_rx_overrun, 1756 cad_stat_rx_ipcsum, 1757 cad_stat_rx_tcpcsum, 1758 cad_stat_rx_udpcsum, 1759 cad_stat_count 1760 }; 1761 1762 struct cad_counter { 1763 const char *c_name; 1764 enum kstat_kv_unit c_unit; 1765 uint32_t c_reg; 1766 }; 1767 1768 const struct cad_counter cad_counters[cad_stat_count] = { 1769 [cad_stat_tx_toto] = 1770 { "tx total", KSTAT_KV_U_BYTES, 0 }, 1771 [cad_stat_tx_totp] = 1772 { "tx total", KSTAT_KV_U_PACKETS, GEM_TXCNT }, 1773 [cad_stat_tx_bcast] = 1774 { "tx bcast", KSTAT_KV_U_PACKETS, GEM_TXBCCNT }, 1775 [cad_stat_tx_mcast] = 1776 { "tx mcast", KSTAT_KV_U_PACKETS, GEM_TXMCCNT }, 1777 [cad_stat_tx_pause] = 1778 { "tx pause", KSTAT_KV_U_PACKETS, GEM_TXPAUSECNT }, 1779 [cad_stat_tx_h64] = 1780 { "tx 64B", KSTAT_KV_U_PACKETS, GEM_TX64CNT }, 1781 [cad_stat_tx_h65] = 1782 { "tx 65-127B", KSTAT_KV_U_PACKETS, GEM_TX65CNT }, 1783 [cad_stat_tx_h128] = 1784 { "tx 128-255B", KSTAT_KV_U_PACKETS, GEM_TX128CNT }, 1785 [cad_stat_tx_h256] = 1786 { "tx 256-511B", KSTAT_KV_U_PACKETS, GEM_TX256CNT }, 1787 [cad_stat_tx_h512] = 1788 { "tx 512-1023B", KSTAT_KV_U_PACKETS, GEM_TX512CNT }, 1789 [cad_stat_tx_h1024] = 1790 { "tx 1024-1518B", KSTAT_KV_U_PACKETS, GEM_TX1024CNT }, 1791 [cad_stat_tx_underrun] = 1792 { "tx underrun", KSTAT_KV_U_PACKETS, GEM_TXURUNCNT }, 1793 [cad_stat_tx_scoll] = 1794 { "tx scoll", KSTAT_KV_U_PACKETS, GEM_SNGLCOLLCNT }, 1795 [cad_stat_tx_mcoll] = 1796 { "tx mcoll", KSTAT_KV_U_PACKETS, GEM_MULTICOLLCNT }, 1797 [cad_stat_tx_ecoll] = 1798 { "tx excess coll", KSTAT_KV_U_PACKETS, GEM_EXCESSCOLLCNT }, 1799 [cad_stat_tx_lcoll] = 1800 { "tx late coll", KSTAT_KV_U_PACKETS, GEM_LATECOLLCNT }, 1801 [cad_stat_tx_defer] = 1802 { "tx defer", KSTAT_KV_U_PACKETS, GEM_TXDEFERCNT }, 1803 [cad_stat_tx_sense] = 1804 { "tx csense", KSTAT_KV_U_PACKETS, GEM_TXCSENSECNT }, 1805 [cad_stat_rx_toto] = 1806 { "rx total", KSTAT_KV_U_BYTES, 0 }, 1807 [cad_stat_rx_totp] = 1808 { "rx total", KSTAT_KV_U_PACKETS, GEM_RXCNT }, 1809 [cad_stat_rx_bcast] = 1810 { "rx bcast", KSTAT_KV_U_PACKETS, GEM_RXBROADCNT }, 1811 [cad_stat_rx_mcast] = 1812 { "rx mcast", KSTAT_KV_U_PACKETS, GEM_RXMULTICNT }, 1813 [cad_stat_rx_pause] = 1814 { "rx pause", KSTAT_KV_U_PACKETS, GEM_RXPAUSECNT }, 1815 [cad_stat_rx_h64] = 1816 { "rx 64B", KSTAT_KV_U_PACKETS, GEM_RX64CNT }, 1817 [cad_stat_rx_h65] = 1818 { "rx 65-127B", KSTAT_KV_U_PACKETS, GEM_RX65CNT }, 1819 [cad_stat_rx_h128] = 1820 { "rx 128-255B", KSTAT_KV_U_PACKETS, GEM_RX128CNT }, 1821 [cad_stat_rx_h256] = 1822 { "rx 256-511B", KSTAT_KV_U_PACKETS, GEM_RX256CNT }, 1823 [cad_stat_rx_h512] = 1824 { "rx 512-1023B", KSTAT_KV_U_PACKETS, GEM_RX512CNT }, 1825 [cad_stat_rx_h1024] = 1826 { "rx 1024-1518B", KSTAT_KV_U_PACKETS, GEM_RX1024CNT }, 1827 [cad_stat_rx_undersz] = 1828 { "rx undersz", KSTAT_KV_U_PACKETS, GEM_RXUNDRCNT }, 1829 [cad_stat_rx_oversz] = 1830 { "rx oversz", KSTAT_KV_U_PACKETS, GEM_RXOVRCNT }, 1831 [cad_stat_rx_jabber] = 1832 { "rx jabber", KSTAT_KV_U_PACKETS, GEM_RXJABCNT }, 1833 [cad_stat_rx_fcs] = 1834 { "rx fcs", KSTAT_KV_U_PACKETS, GEM_RXFCSCNT }, 1835 [cad_stat_rx_symberr] = 1836 { "rx symberr", KSTAT_KV_U_PACKETS, GEM_RXSYMBCNT }, 1837 [cad_stat_rx_align] = 1838 { "rx align", KSTAT_KV_U_PACKETS, GEM_RXALIGNCNT }, 1839 [cad_stat_rx_reserr] = 1840 { "rx reserr", KSTAT_KV_U_PACKETS, GEM_RXRESERRCNT }, 1841 [cad_stat_rx_overrun] = 1842 { "rx overrun", KSTAT_KV_U_PACKETS, GEM_RXORCNT }, 1843 [cad_stat_rx_ipcsum] = 1844 { "rx ip csum", KSTAT_KV_U_PACKETS, GEM_RXIPCCNT }, 1845 [cad_stat_rx_tcpcsum] = 1846 { "rx tcp csum", KSTAT_KV_U_PACKETS, GEM_RXTCPCCNT }, 1847 [cad_stat_rx_udpcsum] = 1848 { "rx udp csum", KSTAT_KV_U_PACKETS, GEM_RXUDPCCNT }, 1849 }; 1850 1851 void 1852 cad_kstat_attach(struct cad_softc *sc) 1853 { 1854 const struct cad_counter *c; 1855 struct kstat *ks; 1856 struct kstat_kv *kvs; 1857 int i; 1858 1859 mtx_init(&sc->sc_kstat_mtx, IPL_SOFTCLOCK); 1860 1861 ks = kstat_create(sc->sc_dev.dv_xname, 0, "cad-stats", 0, 1862 KSTAT_T_KV, 0); 1863 if (ks == NULL) 1864 return; 1865 1866 kvs = mallocarray(nitems(cad_counters), sizeof(*kvs), 1867 M_DEVBUF, M_WAITOK | M_ZERO); 1868 for (i = 0; i < nitems(cad_counters); i++) { 1869 c = &cad_counters[i]; 1870 kstat_kv_unit_init(&kvs[i], c->c_name, KSTAT_KV_T_COUNTER64, 1871 c->c_unit); 1872 } 1873 1874 kstat_set_mutex(ks, &sc->sc_kstat_mtx); 1875 ks->ks_softc = sc; 1876 ks->ks_data = kvs; 1877 ks->ks_datalen = nitems(cad_counters) * sizeof(*kvs); 1878 ks->ks_read = cad_kstat_read; 1879 1880 sc->sc_kstat = ks; 1881 kstat_install(ks); 1882 } 1883 1884 int 1885 cad_kstat_read(struct kstat *ks) 1886 { 1887 const struct cad_counter *c; 1888 struct kstat_kv *kvs = ks->ks_data; 1889 struct cad_softc *sc = ks->ks_softc; 1890 uint64_t v64; 1891 int i; 1892 1893 v64 = HREAD4(sc, GEM_OCTTXL); 1894 v64 |= (uint64_t)HREAD4(sc, GEM_OCTTXH) << 32; 1895 kstat_kv_u64(&kvs[cad_stat_tx_toto]) += v64; 1896 1897 v64 = HREAD4(sc, GEM_OCTRXL); 1898 v64 |= (uint64_t)HREAD4(sc, GEM_OCTRXH) << 32; 1899 kstat_kv_u64(&kvs[cad_stat_rx_toto]) += v64; 1900 1901 for (i = 0; i < nitems(cad_counters); i++) { 1902 c = &cad_counters[i]; 1903 if (c->c_reg == 0) 1904 continue; 1905 kstat_kv_u64(&kvs[i]) += HREAD4(sc, c->c_reg); 1906 } 1907 1908 getnanouptime(&ks->ks_updated); 1909 1910 return 0; 1911 } 1912 1913 void 1914 cad_kstat_tick(void *arg) 1915 { 1916 struct cad_softc *sc = arg; 1917 1918 if (mtx_enter_try(&sc->sc_kstat_mtx)) { 1919 cad_kstat_read(sc->sc_kstat); 1920 mtx_leave(&sc->sc_kstat_mtx); 1921 } 1922 } 1923 #endif /* NKSTAT > 0 */ 1924 1925 #ifdef DDB 1926 void 1927 cad_dump(struct cad_softc *sc) 1928 { 1929 struct cad_buf *rxb, *txb; 1930 struct cad_desc32 *desc32; 1931 struct cad_desc64 *desc64; 1932 int i; 1933 1934 printf("isr 0x%x txsr 0x%x rxsr 0x%x\n", HREAD4(sc, GEM_ISR), 1935 HREAD4(sc, GEM_TXSR), HREAD4(sc, GEM_RXSR)); 1936 1937 if (sc->sc_dma64) { 1938 printf("tx q 0x%08x%08x\n", 1939 HREAD4(sc, GEM_TXQBASEHI), 1940 HREAD4(sc, GEM_TXQBASE)); 1941 } else { 1942 printf("tx q 0x%08x\n", 1943 HREAD4(sc, GEM_TXQBASE)); 1944 } 1945 desc32 = (struct cad_desc32 *)sc->sc_txdesc; 1946 desc64 = (struct cad_desc64 *)sc->sc_txdesc; 1947 if (sc->sc_txbuf != NULL) { 1948 for (i = 0; i < CAD_NTXDESC; i++) { 1949 txb = &sc->sc_txbuf[i]; 1950 if (sc->sc_dma64) { 1951 printf(" %3i %p 0x%08x%08x 0x%08x %s%s " 1952 "m %p\n", i, 1953 &desc64[i], 1954 desc64[i].d_addrhi, desc64[i].d_addrlo, 1955 desc64[i].d_status, 1956 sc->sc_tx_cons == i ? ">" : " ", 1957 sc->sc_tx_prod == i ? "<" : " ", 1958 txb->bf_m); 1959 } else { 1960 printf(" %3i %p 0x%08x 0x%08x %s%s m %p\n", i, 1961 &desc32[i], 1962 desc32[i].d_addr, 1963 desc32[i].d_status, 1964 sc->sc_tx_cons == i ? ">" : " ", 1965 sc->sc_tx_prod == i ? "<" : " ", 1966 txb->bf_m); 1967 } 1968 } 1969 } 1970 for (i = 1; i < GEM_MAX_PRIQ; i++) { 1971 if (sc->sc_qmask & (1U << i)) { 1972 printf("tx q%d 0x%08x\n", i, 1973 HREAD4(sc, GEM_TXQ1BASE(i - 1))); 1974 } 1975 } 1976 1977 if (sc->sc_dma64) { 1978 printf("rx q 0x%08x%08x\n", 1979 HREAD4(sc, GEM_RXQBASEHI), 1980 HREAD4(sc, GEM_RXQBASE)); 1981 } else { 1982 printf("rx q 0x%08x\n", 1983 HREAD4(sc, GEM_RXQBASE)); 1984 } 1985 desc32 = (struct cad_desc32 *)sc->sc_rxdesc; 1986 desc64 = (struct cad_desc64 *)sc->sc_rxdesc; 1987 if (sc->sc_rxbuf != NULL) { 1988 for (i = 0; i < CAD_NRXDESC; i++) { 1989 rxb = &sc->sc_rxbuf[i]; 1990 if (sc->sc_dma64) { 1991 printf(" %3i %p 0x%08x%08x 0x%08x %s%s " 1992 "m %p\n", i, 1993 &desc64[i], 1994 desc64[i].d_addrhi, desc64[i].d_addrlo, 1995 desc64[i].d_status, 1996 sc->sc_rx_cons == i ? ">" : " ", 1997 sc->sc_rx_prod == i ? "<" : " ", 1998 rxb->bf_m); 1999 } else { 2000 printf(" %3i %p 0x%08x 0x%08x %s%s m %p\n", i, 2001 &desc32[i], 2002 desc32[i].d_addr, 2003 desc32[i].d_status, 2004 sc->sc_rx_cons == i ? ">" : " ", 2005 sc->sc_rx_prod == i ? "<" : " ", 2006 rxb->bf_m); 2007 } 2008 } 2009 } 2010 for (i = 1; i < GEM_MAX_PRIQ; i++) { 2011 if (sc->sc_qmask & (1U << i)) { 2012 printf("rx q%d 0x%08x\n", i, 2013 HREAD4(sc, (i < 8) ? GEM_RXQ1BASE(i - 1) 2014 : GEM_RXQ8BASE(i - 8))); 2015 } 2016 } 2017 } 2018 #endif 2019