1 /* $OpenBSD: dwpcie.c,v 1.27 2021/03/01 21:03:24 patrick Exp $ */ 2 /* 3 * Copyright (c) 2018 Mark Kettenis <kettenis@openbsd.org> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #include <sys/param.h> 19 #include <sys/systm.h> 20 #include <sys/device.h> 21 #include <sys/extent.h> 22 #include <sys/malloc.h> 23 24 #include <machine/intr.h> 25 #include <machine/bus.h> 26 #include <machine/fdt.h> 27 28 #include <dev/pci/pcidevs.h> 29 #include <dev/pci/pcireg.h> 30 #include <dev/pci/pcivar.h> 31 #include <dev/pci/ppbreg.h> 32 33 #include <dev/ofw/openfirm.h> 34 #include <dev/ofw/ofw_clock.h> 35 #include <dev/ofw/ofw_gpio.h> 36 #include <dev/ofw/ofw_misc.h> 37 #include <dev/ofw/ofw_pinctrl.h> 38 #include <dev/ofw/ofw_power.h> 39 #include <dev/ofw/fdt.h> 40 41 /* Registers */ 42 #define PCIE_PORT_LINK_CTRL 0x710 43 #define PCIE_PORT_LINK_CTRL_LANES_MASK (0x3f << 16) 44 #define PCIE_PORT_LINK_CTRL_LANES_1 (0x1 << 16) 45 #define PCIE_PORT_LINK_CTRL_LANES_2 (0x3 << 16) 46 #define PCIE_PORT_LINK_CTRL_LANES_4 (0x7 << 16) 47 #define PCIE_PORT_LINK_CTRL_LANES_8 (0xf << 16) 48 #define PCIE_PHY_DEBUG_R1 0x72c 49 #define PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING (1 << 29) 50 #define PCIE_PHY_DEBUG_R1_XMLH_LINK_UP (1 << 4) 51 #define PCIE_LINK_WIDTH_SPEED_CTRL 0x80c 52 #define PCIE_LINK_WIDTH_SPEED_CTRL_LANES_MASK (0x1f << 8) 53 #define PCIE_LINK_WIDTH_SPEED_CTRL_LANES_1 (0x1 << 8) 54 #define PCIE_LINK_WIDTH_SPEED_CTRL_LANES_2 (0x2 << 8) 55 #define PCIE_LINK_WIDTH_SPEED_CTRL_LANES_4 (0x4 << 8) 56 #define PCIE_LINK_WIDTH_SPEED_CTRL_LANES_8 (0x8 << 8) 57 #define PCIE_LINK_WIDTH_SPEED_CTRL_CHANGE (1 << 17) 58 59 #define MISC_CONTROL_1 0x8bc 60 #define MISC_CONTROL_1_DBI_RO_WR_EN (1 << 0) 61 #define IATU_VIEWPORT 0x900 62 #define IATU_VIEWPORT_INDEX0 0 63 #define IATU_VIEWPORT_INDEX1 1 64 #define IATU_VIEWPORT_INDEX2 2 65 #define IATU_OFFSET_VIEWPORT 0x904 66 #define IATU_OFFSET_UNROLL(x) (0x200 * (x)) 67 #define IATU_REGION_CTRL_1 0x000 68 #define IATU_REGION_CTRL_1_TYPE_MEM 0 69 #define IATU_REGION_CTRL_1_TYPE_IO 2 70 #define IATU_REGION_CTRL_1_TYPE_CFG0 4 71 #define IATU_REGION_CTRL_1_TYPE_CFG1 5 72 #define IATU_REGION_CTRL_2 0x004 73 #define IATU_REGION_CTRL_2_REGION_EN (1U << 31) 74 #define IATU_LWR_BASE_ADDR 0x08 75 #define IATU_UPPER_BASE_ADDR 0x0c 76 #define IATU_LIMIT_ADDR 0x10 77 #define IATU_LWR_TARGET_ADDR 0x14 78 #define IATU_UPPER_TARGET_ADDR 0x18 79 80 #define PCIE_GLOBAL_CTRL 0x8000 81 #define PCIE_GLOBAL_CTRL_APP_LTSSM_EN (1 << 2) 82 #define PCIE_GLOBAL_CTRL_DEVICE_TYPE_MASK (0xf << 4) 83 #define PCIE_GLOBAL_CTRL_DEVICE_TYPE_RC (0x4 << 4) 84 #define PCIE_GLOBAL_STATUS 0x8008 85 #define PCIE_GLOBAL_STATUS_RDLH_LINK_UP (1 << 1) 86 #define PCIE_GLOBAL_STATUS_PHY_LINK_UP (1 << 9) 87 #define PCIE_PM_STATUS 0x8014 88 #define PCIE_GLOBAL_INT_CAUSE 0x801c 89 #define PCIE_GLOBAL_INT_MASK 0x8020 90 #define PCIE_GLOBAL_INT_MASK_INT_A (1 << 9) 91 #define PCIE_GLOBAL_INT_MASK_INT_B (1 << 10) 92 #define PCIE_GLOBAL_INT_MASK_INT_C (1 << 11) 93 #define PCIE_GLOBAL_INT_MASK_INT_D (1 << 12) 94 #define PCIE_ARCACHE_TRC 0x8050 95 #define PCIE_ARCACHE_TRC_DEFAULT 0x3511 96 #define PCIE_AWCACHE_TRC 0x8054 97 #define PCIE_AWCACHE_TRC_DEFAULT 0x5311 98 #define PCIE_ARUSER 0x805c 99 #define PCIE_AWUSER 0x8060 100 #define PCIE_AXUSER_DOMAIN_MASK (0x3 << 4) 101 #define PCIE_AXUSER_DOMAIN_INNER_SHARABLE (0x1 << 4) 102 #define PCIE_AXUSER_DOMAIN_OUTER_SHARABLE (0x2 << 4) 103 #define PCIE_STREAMID 0x8064 104 #define PCIE_STREAMID_FUNC_BITS(x) ((x) << 0) 105 #define PCIE_STREAMID_DEV_BITS(x) ((x) << 4) 106 #define PCIE_STREAMID_BUS_BITS(x) ((x) << 8) 107 #define PCIE_STREAMID_ROOTPORT(x) ((x) << 12) 108 #define PCIE_STREAMID_8040 \ 109 (PCIE_STREAMID_ROOTPORT(0x80) | PCIE_STREAMID_BUS_BITS(2) | \ 110 PCIE_STREAMID_DEV_BITS(2) | PCIE_STREAMID_FUNC_BITS(3)) 111 112 /* Amlogic G12A registers */ 113 #define PCIE_CFG0 0x0000 114 #define PCIE_CFG0_APP_LTSSM_EN (1 << 7) 115 #define PCIE_STATUS12 0x0030 116 #define PCIE_STATUS12_RDLH_LINK_UP (1 << 16) 117 #define PCIE_STATUS12_LTSSM_MASK (0x1f << 10) 118 #define PCIE_STATUS12_LTSSM_UP (0x11 << 10) 119 #define PCIE_STATUS12_SMLH_LINK_UP (1 << 6) 120 121 /* NXP i.MX8MQ registers */ 122 #define PCIE_RC_LCR 0x7c 123 #define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1 0x1 124 #define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2 0x2 125 #define PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK 0xf 126 #define PCIE_RC_LCR_L1EL_MASK (0x7 << 15) 127 #define PCIE_RC_LCR_L1EL_64US (0x6 << 15) 128 129 #define IOMUXC_GPR12 0x30 130 #define IMX8MQ_GPR_PCIE2_DEVICE_TYPE_MASK (0xf << 8) 131 #define IMX8MQ_GPR_PCIE2_DEVICE_TYPE_RC (0x4 << 8) 132 #define IMX8MQ_GPR_PCIE1_DEVICE_TYPE_MASK (0xf << 12) 133 #define IMX8MQ_GPR_PCIE1_DEVICE_TYPE_RC (0x4 << 12) 134 #define IOMUXC_GPR14 0x38 135 #define IOMUXC_GPR16 0x40 136 #define IMX8MQ_GPR_PCIE_REF_USE_PAD (1 << 9) 137 #define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN (1 << 10) 138 #define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE (1 << 11) 139 #define IMX8MM_GPR_PCIE_SSC_EN (1 << 16) 140 #define IMX8MM_GPR_PCIE_POWER_OFF (1 << 17) 141 #define IMX8MM_GPR_PCIE_CMN_RST (1 << 18) 142 #define IMX8MM_GPR_PCIE_AUX_EN (1 << 19) 143 #define IMX8MM_GPR_PCIE_REF_CLK_MASK (0x3 << 24) 144 #define IMX8MM_GPR_PCIE_REF_CLK_PLL (0x3 << 24) 145 #define IMX8MM_GPR_PCIE_REF_CLK_EXT (0x2 << 24) 146 147 #define IMX8MM_PCIE_PHY_CMN_REG62 0x188 148 #define IMX8MM_PCIE_PHY_CMN_REG62_PLL_CLK_OUT 0x08 149 #define IMX8MM_PCIE_PHY_CMN_REG64 0x190 150 #define IMX8MM_PCIE_PHY_CMN_REG64_AUX_RX_TX_TERM 0x8c 151 #define IMX8MM_PCIE_PHY_CMN_REG75 0x1d4 152 #define IMX8MM_PCIE_PHY_CMN_REG75_PLL_DONE 0x3 153 #define IMX8MM_PCIE_PHY_TRSV_REG5 0x414 154 #define IMX8MM_PCIE_PHY_TRSV_REG5_GEN1_DEEMP 0x2d 155 #define IMX8MM_PCIE_PHY_TRSV_REG6 0x418 156 #define IMX8MM_PCIE_PHY_TRSV_REG6_GEN2_DEEMP 0xf 157 158 #define ANATOP_PLLOUT_CTL 0x74 159 #define ANATOP_PLLOUT_CTL_CKE (1 << 4) 160 #define ANATOP_PLLOUT_CTL_SEL_SYSPLL1 0xb 161 #define ANATOP_PLLOUT_CTL_SEL_MASK 0xf 162 #define ANATOP_PLLOUT_DIV 0x7c 163 #define ANATOP_PLLOUT_DIV_SYSPLL1 0x7 164 165 #define HREAD4(sc, reg) \ 166 (bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg))) 167 #define HWRITE4(sc, reg, val) \ 168 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 169 #define HSET4(sc, reg, bits) \ 170 HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits)) 171 #define HCLR4(sc, reg, bits) \ 172 HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits)) 173 174 struct dwpcie_range { 175 uint32_t flags; 176 uint64_t pci_base; 177 uint64_t phys_base; 178 uint64_t size; 179 }; 180 181 struct dwpcie_softc { 182 struct device sc_dev; 183 bus_space_tag_t sc_iot; 184 bus_space_handle_t sc_ioh; 185 bus_space_handle_t sc_cfg0_ioh; 186 bus_space_handle_t sc_cfg1_ioh; 187 bus_dma_tag_t sc_dmat; 188 189 bus_addr_t sc_ctrl_base; 190 bus_size_t sc_ctrl_size; 191 bus_addr_t sc_cfg0_base; 192 bus_size_t sc_cfg0_size; 193 bus_addr_t sc_cfg1_base; 194 bus_size_t sc_cfg1_size; 195 196 bus_addr_t sc_glue_base; 197 bus_size_t sc_glue_size; 198 bus_space_handle_t sc_glue_ioh; 199 200 bus_addr_t sc_io_base; 201 bus_addr_t sc_io_bus_addr; 202 bus_size_t sc_io_size; 203 bus_addr_t sc_mem_base; 204 bus_addr_t sc_mem_bus_addr; 205 bus_size_t sc_mem_size; 206 207 int sc_node; 208 int sc_acells; 209 int sc_scells; 210 int sc_pacells; 211 int sc_pscells; 212 struct dwpcie_range *sc_ranges; 213 int sc_nranges; 214 215 struct bus_space sc_bus_iot; 216 struct bus_space sc_bus_memt; 217 218 struct arm64_pci_chipset sc_pc; 219 int sc_bus; 220 221 int sc_num_viewport; 222 bus_addr_t sc_atu_base; 223 int sc_atu_unroll; 224 225 void *sc_ih; 226 }; 227 228 int dwpcie_match(struct device *, void *, void *); 229 void dwpcie_attach(struct device *, struct device *, void *); 230 231 struct cfattach dwpcie_ca = { 232 sizeof (struct dwpcie_softc), dwpcie_match, dwpcie_attach 233 }; 234 235 struct cfdriver dwpcie_cd = { 236 NULL, "dwpcie", DV_DULL 237 }; 238 239 int 240 dwpcie_match(struct device *parent, void *match, void *aux) 241 { 242 struct fdt_attach_args *faa = aux; 243 244 return (OF_is_compatible(faa->fa_node, "amlogic,g12a-pcie") || 245 OF_is_compatible(faa->fa_node, "marvell,armada8k-pcie") || 246 OF_is_compatible(faa->fa_node, "fsl,imx8mm-pcie") || 247 OF_is_compatible(faa->fa_node, "fsl,imx8mq-pcie")); 248 } 249 250 void dwpcie_attach_deferred(struct device *); 251 252 void dwpcie_atu_config(struct dwpcie_softc *, int, int, 253 uint64_t, uint64_t, uint64_t); 254 void dwpcie_link_config(struct dwpcie_softc *); 255 int dwpcie_link_up(struct dwpcie_softc *); 256 257 int dwpcie_armada8k_init(struct dwpcie_softc *); 258 int dwpcie_armada8k_link_up(struct dwpcie_softc *); 259 int dwpcie_armada8k_intr(void *); 260 261 int dwpcie_g12a_init(struct dwpcie_softc *); 262 int dwpcie_g12a_link_up(struct dwpcie_softc *); 263 264 int dwpcie_imx8mq_init(struct dwpcie_softc *); 265 int dwpcie_imx8mq_intr(void *); 266 267 void dwpcie_attach_hook(struct device *, struct device *, 268 struct pcibus_attach_args *); 269 int dwpcie_bus_maxdevs(void *, int); 270 pcitag_t dwpcie_make_tag(void *, int, int, int); 271 void dwpcie_decompose_tag(void *, pcitag_t, int *, int *, int *); 272 int dwpcie_conf_size(void *, pcitag_t); 273 pcireg_t dwpcie_conf_read(void *, pcitag_t, int); 274 void dwpcie_conf_write(void *, pcitag_t, int, pcireg_t); 275 int dwpcie_probe_device_hook(void *, struct pci_attach_args *); 276 277 int dwpcie_intr_map(struct pci_attach_args *, pci_intr_handle_t *); 278 const char *dwpcie_intr_string(void *, pci_intr_handle_t); 279 void *dwpcie_intr_establish(void *, pci_intr_handle_t, int, 280 struct cpu_info *, int (*)(void *), void *, char *); 281 void dwpcie_intr_disestablish(void *, void *); 282 283 int dwpcie_bs_iomap(bus_space_tag_t, bus_addr_t, bus_size_t, int, 284 bus_space_handle_t *); 285 int dwpcie_bs_memmap(bus_space_tag_t, bus_addr_t, bus_size_t, int, 286 bus_space_handle_t *); 287 288 void 289 dwpcie_attach(struct device *parent, struct device *self, void *aux) 290 { 291 struct dwpcie_softc *sc = (struct dwpcie_softc *)self; 292 struct fdt_attach_args *faa = aux; 293 uint32_t *ranges; 294 int i, j, nranges, rangeslen; 295 int config, glue; 296 297 if (faa->fa_nreg < 2) { 298 printf(": no registers\n"); 299 return; 300 } 301 302 sc->sc_ctrl_base = faa->fa_reg[0].addr; 303 sc->sc_ctrl_size = faa->fa_reg[0].size; 304 305 config = OF_getindex(faa->fa_node, "config", "reg-names"); 306 if (config < 0 || config >= faa->fa_nreg) { 307 printf(": no config registers\n"); 308 return; 309 } 310 311 sc->sc_cfg0_base = faa->fa_reg[config].addr; 312 sc->sc_cfg0_size = faa->fa_reg[config].size / 2; 313 sc->sc_cfg0_base = faa->fa_reg[config].addr + sc->sc_cfg0_size; 314 sc->sc_cfg1_size = sc->sc_cfg0_size; 315 316 if (OF_is_compatible(faa->fa_node, "amlogic,g12a-pcie")) { 317 glue = OF_getindex(faa->fa_node, "cfg", "reg-names"); 318 if (glue < 0 || glue >= faa->fa_nreg) { 319 printf(": no glue registers\n"); 320 return; 321 } 322 323 sc->sc_glue_base = faa->fa_reg[glue].addr; 324 sc->sc_glue_size = faa->fa_reg[glue].size; 325 } 326 327 sc->sc_iot = faa->fa_iot; 328 sc->sc_dmat = faa->fa_dmat; 329 sc->sc_node = faa->fa_node; 330 331 sc->sc_acells = OF_getpropint(sc->sc_node, "#address-cells", 332 faa->fa_acells); 333 sc->sc_scells = OF_getpropint(sc->sc_node, "#size-cells", 334 faa->fa_scells); 335 sc->sc_pacells = faa->fa_acells; 336 sc->sc_pscells = faa->fa_scells; 337 338 rangeslen = OF_getproplen(sc->sc_node, "ranges"); 339 if (rangeslen <= 0 || (rangeslen % sizeof(uint32_t)) || 340 (rangeslen / sizeof(uint32_t)) % (sc->sc_acells + 341 sc->sc_pacells + sc->sc_scells)) { 342 printf(": invalid ranges property\n"); 343 return; 344 } 345 346 ranges = malloc(rangeslen, M_TEMP, M_WAITOK); 347 OF_getpropintarray(sc->sc_node, "ranges", ranges, 348 rangeslen); 349 350 nranges = (rangeslen / sizeof(uint32_t)) / 351 (sc->sc_acells + sc->sc_pacells + sc->sc_scells); 352 sc->sc_ranges = mallocarray(nranges, 353 sizeof(struct dwpcie_range), M_TEMP, M_WAITOK); 354 sc->sc_nranges = nranges; 355 356 for (i = 0, j = 0; i < sc->sc_nranges; i++) { 357 sc->sc_ranges[i].flags = ranges[j++]; 358 sc->sc_ranges[i].pci_base = ranges[j++]; 359 if (sc->sc_acells - 1 == 2) { 360 sc->sc_ranges[i].pci_base <<= 32; 361 sc->sc_ranges[i].pci_base |= ranges[j++]; 362 } 363 sc->sc_ranges[i].phys_base = ranges[j++]; 364 if (sc->sc_pacells == 2) { 365 sc->sc_ranges[i].phys_base <<= 32; 366 sc->sc_ranges[i].phys_base |= ranges[j++]; 367 } 368 sc->sc_ranges[i].size = ranges[j++]; 369 if (sc->sc_scells == 2) { 370 sc->sc_ranges[i].size <<= 32; 371 sc->sc_ranges[i].size |= ranges[j++]; 372 } 373 } 374 375 free(ranges, M_TEMP, rangeslen); 376 377 if (bus_space_map(sc->sc_iot, sc->sc_ctrl_base, 378 sc->sc_ctrl_size, 0, &sc->sc_ioh)) { 379 free(sc->sc_ranges, M_TEMP, sc->sc_nranges * 380 sizeof(struct dwpcie_range)); 381 printf(": can't map ctrl registers\n"); 382 return; 383 } 384 385 if (bus_space_map(sc->sc_iot, sc->sc_cfg0_base, 386 sc->sc_cfg1_size, 0, &sc->sc_cfg0_ioh)) { 387 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ctrl_size); 388 free(sc->sc_ranges, M_TEMP, sc->sc_nranges * 389 sizeof(struct dwpcie_range)); 390 printf(": can't map config registers\n"); 391 return; 392 } 393 394 if (bus_space_map(sc->sc_iot, sc->sc_cfg1_base, 395 sc->sc_cfg1_size, 0, &sc->sc_cfg1_ioh)) { 396 bus_space_unmap(sc->sc_iot, sc->sc_cfg0_ioh, sc->sc_cfg0_size); 397 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ctrl_size); 398 free(sc->sc_ranges, M_TEMP, sc->sc_nranges * 399 sizeof(struct dwpcie_range)); 400 printf(": can't map config registers\n"); 401 return; 402 } 403 404 sc->sc_num_viewport = OF_getpropint(sc->sc_node, "num-viewport", 2); 405 406 printf("\n"); 407 408 pinctrl_byname(sc->sc_node, "default"); 409 clock_set_assigned(sc->sc_node); 410 411 config_defer(self, dwpcie_attach_deferred); 412 } 413 414 void 415 dwpcie_attach_deferred(struct device *self) 416 { 417 struct dwpcie_softc *sc = (struct dwpcie_softc *)self; 418 struct pcibus_attach_args pba; 419 bus_addr_t iobase, iolimit; 420 bus_addr_t membase, memlimit; 421 uint32_t bus_range[2]; 422 pcireg_t bir, blr, csr; 423 int i, error = 0; 424 425 if (OF_is_compatible(sc->sc_node, "marvell,armada8k-pcie")) 426 error = dwpcie_armada8k_init(sc); 427 if (OF_is_compatible(sc->sc_node, "amlogic,g12a-pcie")) 428 error = dwpcie_g12a_init(sc); 429 if (OF_is_compatible(sc->sc_node, "fsl,imx8mm-pcie") || 430 OF_is_compatible(sc->sc_node, "fsl,imx8mq-pcie")) 431 error = dwpcie_imx8mq_init(sc); 432 if (error != 0) { 433 bus_space_unmap(sc->sc_iot, sc->sc_cfg1_ioh, sc->sc_cfg1_size); 434 bus_space_unmap(sc->sc_iot, sc->sc_cfg0_ioh, sc->sc_cfg0_size); 435 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ctrl_size); 436 free(sc->sc_ranges, M_TEMP, sc->sc_nranges * 437 sizeof(struct dwpcie_range)); 438 printf("%s: can't initialize hardware\n", 439 sc->sc_dev.dv_xname); 440 return; 441 } 442 443 if (HREAD4(sc, IATU_VIEWPORT) == 0xffffffff) { 444 sc->sc_atu_base = 0x300000; 445 sc->sc_atu_unroll = 1; 446 } 447 448 /* Set up address translation for I/O space. */ 449 sc->sc_io_bus_addr = sc->sc_mem_bus_addr = -1; 450 for (i = 0; i < sc->sc_nranges; i++) { 451 if ((sc->sc_ranges[i].flags & 0x03000000) == 0x01000000 && 452 sc->sc_ranges[i].size > 0) { 453 sc->sc_io_base = sc->sc_ranges[i].phys_base; 454 sc->sc_io_bus_addr = sc->sc_ranges[i].pci_base; 455 sc->sc_io_size = sc->sc_ranges[i].size; 456 } 457 if ((sc->sc_ranges[i].flags & 0x03000000) == 0x02000000 && 458 sc->sc_ranges[i].size > 0) { 459 sc->sc_mem_base = sc->sc_ranges[i].phys_base; 460 sc->sc_mem_bus_addr = sc->sc_ranges[i].pci_base; 461 sc->sc_mem_size = sc->sc_ranges[i].size; 462 } 463 } 464 465 dwpcie_atu_config(sc, IATU_VIEWPORT_INDEX0, 466 IATU_REGION_CTRL_1_TYPE_MEM, sc->sc_mem_base, 467 sc->sc_mem_bus_addr, sc->sc_mem_size); 468 if (sc->sc_num_viewport > 2) 469 dwpcie_atu_config(sc, IATU_VIEWPORT_INDEX2, 470 IATU_REGION_CTRL_1_TYPE_IO, sc->sc_io_base, 471 sc->sc_io_bus_addr, sc->sc_io_size); 472 473 /* Enable modification of read-only bits. */ 474 HSET4(sc, MISC_CONTROL_1, MISC_CONTROL_1_DBI_RO_WR_EN); 475 476 /* A Root Port is a PCI-PCI Bridge. */ 477 HWRITE4(sc, PCI_CLASS_REG, 478 PCI_CLASS_BRIDGE << PCI_CLASS_SHIFT | 479 PCI_SUBCLASS_BRIDGE_PCI << PCI_SUBCLASS_SHIFT); 480 481 /* Clear BAR as U-Boot seems to leave garbage in it. */ 482 HWRITE4(sc, PCI_MAPREG_START, PCI_MAPREG_MEM_TYPE_64BIT); 483 HWRITE4(sc, PCI_MAPREG_START + 4, 0); 484 485 /* Make sure read-only bits are write-protected. */ 486 HCLR4(sc, MISC_CONTROL_1, MISC_CONTROL_1_DBI_RO_WR_EN); 487 488 /* Set up bus range. */ 489 if (OF_getpropintarray(sc->sc_node, "bus-range", bus_range, 490 sizeof(bus_range)) != sizeof(bus_range) || 491 bus_range[0] >= 32 || bus_range[1] >= 32) { 492 bus_range[0] = 0; 493 bus_range[1] = 31; 494 } 495 sc->sc_bus = bus_range[0]; 496 497 /* Initialize bus range. */ 498 bir = bus_range[0]; 499 bir |= ((bus_range[0] + 1) << 8); 500 bir |= (bus_range[1] << 16); 501 HWRITE4(sc, PPB_REG_BUSINFO, bir); 502 503 /* Initialize I/O window. */ 504 iobase = sc->sc_io_bus_addr; 505 iolimit = iobase + sc->sc_io_size - 1; 506 blr = iolimit & PPB_IO_MASK; 507 blr |= (iobase >> PPB_IO_SHIFT); 508 HWRITE4(sc, PPB_REG_IOSTATUS, blr); 509 blr = (iobase & 0xffff0000) >> 16; 510 blr |= iolimit & 0xffff0000; 511 HWRITE4(sc, PPB_REG_IO_HI, blr); 512 513 /* Initialize memory mapped I/O window. */ 514 membase = sc->sc_mem_bus_addr; 515 memlimit = membase + sc->sc_mem_size - 1; 516 blr = memlimit & PPB_MEM_MASK; 517 blr |= (membase >> PPB_MEM_SHIFT); 518 HWRITE4(sc, PPB_REG_MEM, blr); 519 520 /* Reset prefetchable memory mapped I/O window. */ 521 HWRITE4(sc, PPB_REG_PREFMEM, 0x0000ffff); 522 HWRITE4(sc, PPB_REG_PREFBASE_HI32, 0); 523 HWRITE4(sc, PPB_REG_PREFLIM_HI32, 0); 524 525 csr = PCI_COMMAND_MASTER_ENABLE; 526 if (iolimit > iobase) 527 csr |= PCI_COMMAND_IO_ENABLE; 528 if (memlimit > membase) 529 csr |= PCI_COMMAND_MEM_ENABLE; 530 HWRITE4(sc, PCI_COMMAND_STATUS_REG, csr); 531 532 memcpy(&sc->sc_bus_iot, sc->sc_iot, sizeof(sc->sc_bus_iot)); 533 sc->sc_bus_iot.bus_private = sc; 534 sc->sc_bus_iot._space_map = dwpcie_bs_iomap; 535 memcpy(&sc->sc_bus_memt, sc->sc_iot, sizeof(sc->sc_bus_memt)); 536 sc->sc_bus_memt.bus_private = sc; 537 sc->sc_bus_memt._space_map = dwpcie_bs_memmap; 538 539 sc->sc_pc.pc_conf_v = sc; 540 sc->sc_pc.pc_attach_hook = dwpcie_attach_hook; 541 sc->sc_pc.pc_bus_maxdevs = dwpcie_bus_maxdevs; 542 sc->sc_pc.pc_make_tag = dwpcie_make_tag; 543 sc->sc_pc.pc_decompose_tag = dwpcie_decompose_tag; 544 sc->sc_pc.pc_conf_size = dwpcie_conf_size; 545 sc->sc_pc.pc_conf_read = dwpcie_conf_read; 546 sc->sc_pc.pc_conf_write = dwpcie_conf_write; 547 sc->sc_pc.pc_probe_device_hook = dwpcie_probe_device_hook; 548 549 sc->sc_pc.pc_intr_v = sc; 550 sc->sc_pc.pc_intr_map = dwpcie_intr_map; 551 sc->sc_pc.pc_intr_map_msi = _pci_intr_map_msi; 552 sc->sc_pc.pc_intr_map_msix = _pci_intr_map_msix; 553 sc->sc_pc.pc_intr_string = dwpcie_intr_string; 554 sc->sc_pc.pc_intr_establish = dwpcie_intr_establish; 555 sc->sc_pc.pc_intr_disestablish = dwpcie_intr_disestablish; 556 557 memset(&pba, 0, sizeof(pba)); 558 pba.pba_busname = "pci"; 559 pba.pba_iot = &sc->sc_bus_iot; 560 pba.pba_memt = &sc->sc_bus_memt; 561 pba.pba_dmat = sc->sc_dmat; 562 pba.pba_pc = &sc->sc_pc; 563 pba.pba_domain = pci_ndomains++; 564 pba.pba_bus = sc->sc_bus; 565 if (OF_is_compatible(sc->sc_node, "marvell,armada8k-pcie")) 566 pba.pba_flags |= PCI_FLAGS_MSI_ENABLED; 567 568 config_found(self, &pba, NULL); 569 } 570 571 void 572 dwpcie_link_config(struct dwpcie_softc *sc) 573 { 574 uint32_t mode, width, reg; 575 int lanes; 576 577 lanes = OF_getpropint(sc->sc_node, "num-lanes", 0); 578 579 switch (lanes) { 580 case 1: 581 mode = PCIE_PORT_LINK_CTRL_LANES_1; 582 width = PCIE_LINK_WIDTH_SPEED_CTRL_LANES_1; 583 break; 584 case 2: 585 mode = PCIE_PORT_LINK_CTRL_LANES_2; 586 width = PCIE_LINK_WIDTH_SPEED_CTRL_LANES_2; 587 break; 588 case 4: 589 mode = PCIE_PORT_LINK_CTRL_LANES_4; 590 width = PCIE_LINK_WIDTH_SPEED_CTRL_LANES_4; 591 break; 592 case 8: 593 mode = PCIE_PORT_LINK_CTRL_LANES_8; 594 width = PCIE_LINK_WIDTH_SPEED_CTRL_LANES_8; 595 break; 596 default: 597 printf("%s: %d lanes not supported\n", __func__, lanes); 598 return; 599 } 600 601 reg = HREAD4(sc, PCIE_PORT_LINK_CTRL); 602 reg &= ~PCIE_PORT_LINK_CTRL_LANES_MASK; 603 reg |= mode; 604 HWRITE4(sc, PCIE_PORT_LINK_CTRL, reg); 605 606 reg = HREAD4(sc, PCIE_LINK_WIDTH_SPEED_CTRL); 607 reg &= ~PCIE_LINK_WIDTH_SPEED_CTRL_LANES_MASK; 608 reg |= width; 609 HWRITE4(sc, PCIE_LINK_WIDTH_SPEED_CTRL, reg); 610 611 reg = HREAD4(sc, PCIE_LINK_WIDTH_SPEED_CTRL); 612 reg |= PCIE_LINK_WIDTH_SPEED_CTRL_CHANGE; 613 HWRITE4(sc, PCIE_LINK_WIDTH_SPEED_CTRL, reg); 614 } 615 616 int 617 dwpcie_armada8k_init(struct dwpcie_softc *sc) 618 { 619 uint32_t reg; 620 int timo; 621 622 clock_enable_all(sc->sc_node); 623 624 dwpcie_link_config(sc); 625 626 if (!dwpcie_armada8k_link_up(sc)) { 627 reg = HREAD4(sc, PCIE_GLOBAL_CTRL); 628 reg &= ~PCIE_GLOBAL_CTRL_APP_LTSSM_EN; 629 HWRITE4(sc, PCIE_GLOBAL_CTRL, reg); 630 } 631 632 /* 633 * Setup Requester-ID to Stream-ID mapping 634 * XXX: TF-A is supposed to set this up, but doesn't! 635 */ 636 HWRITE4(sc, PCIE_STREAMID, PCIE_STREAMID_8040); 637 638 /* Enable Root Complex mode. */ 639 reg = HREAD4(sc, PCIE_GLOBAL_CTRL); 640 reg &= ~PCIE_GLOBAL_CTRL_DEVICE_TYPE_MASK; 641 reg |= PCIE_GLOBAL_CTRL_DEVICE_TYPE_RC; 642 HWRITE4(sc, PCIE_GLOBAL_CTRL, reg); 643 644 HWRITE4(sc, PCIE_ARCACHE_TRC, PCIE_ARCACHE_TRC_DEFAULT); 645 HWRITE4(sc, PCIE_AWCACHE_TRC, PCIE_AWCACHE_TRC_DEFAULT); 646 reg = HREAD4(sc, PCIE_ARUSER); 647 reg &= ~PCIE_AXUSER_DOMAIN_MASK; 648 reg |= PCIE_AXUSER_DOMAIN_OUTER_SHARABLE; 649 HWRITE4(sc, PCIE_ARUSER, reg); 650 reg = HREAD4(sc, PCIE_AWUSER); 651 reg &= ~PCIE_AXUSER_DOMAIN_MASK; 652 reg |= PCIE_AXUSER_DOMAIN_OUTER_SHARABLE; 653 HWRITE4(sc, PCIE_AWUSER, reg); 654 655 if (!dwpcie_armada8k_link_up(sc)) { 656 reg = HREAD4(sc, PCIE_GLOBAL_CTRL); 657 reg |= PCIE_GLOBAL_CTRL_APP_LTSSM_EN; 658 HWRITE4(sc, PCIE_GLOBAL_CTRL, reg); 659 } 660 661 for (timo = 40; timo > 0; timo--) { 662 if (dwpcie_armada8k_link_up(sc)) 663 break; 664 delay(1000); 665 } 666 if (timo == 0) 667 return ETIMEDOUT; 668 669 sc->sc_ih = fdt_intr_establish(sc->sc_node, IPL_AUDIO | IPL_MPSAFE, 670 dwpcie_armada8k_intr, sc, sc->sc_dev.dv_xname); 671 672 /* Unmask INTx interrupts. */ 673 HWRITE4(sc, PCIE_GLOBAL_INT_MASK, 674 PCIE_GLOBAL_INT_MASK_INT_A | PCIE_GLOBAL_INT_MASK_INT_B | 675 PCIE_GLOBAL_INT_MASK_INT_C | PCIE_GLOBAL_INT_MASK_INT_D); 676 677 return 0; 678 } 679 680 int 681 dwpcie_armada8k_link_up(struct dwpcie_softc *sc) 682 { 683 uint32_t reg, mask; 684 685 mask = PCIE_GLOBAL_STATUS_RDLH_LINK_UP; 686 mask |= PCIE_GLOBAL_STATUS_PHY_LINK_UP; 687 reg = HREAD4(sc, PCIE_GLOBAL_STATUS); 688 return ((reg & mask) == mask); 689 } 690 691 int 692 dwpcie_armada8k_intr(void *arg) 693 { 694 struct dwpcie_softc *sc = arg; 695 uint32_t cause; 696 697 /* Acknowledge interrupts. */ 698 cause = HREAD4(sc, PCIE_GLOBAL_INT_CAUSE); 699 HWRITE4(sc, PCIE_GLOBAL_INT_CAUSE, cause); 700 701 /* INTx interrupt, so not really ours. */ 702 return 0; 703 } 704 705 int 706 dwpcie_g12a_init(struct dwpcie_softc *sc) 707 { 708 uint32_t *reset_gpio; 709 ssize_t reset_gpiolen; 710 uint32_t reg; 711 int timo; 712 713 reset_gpiolen = OF_getproplen(sc->sc_node, "reset-gpios"); 714 if (reset_gpiolen <= 0) 715 return ENXIO; 716 717 if (bus_space_map(sc->sc_iot, sc->sc_glue_base, 718 sc->sc_glue_size, 0, &sc->sc_glue_ioh)) 719 return ENOMEM; 720 721 power_domain_enable(sc->sc_node); 722 723 phy_enable(sc->sc_node, "pcie"); 724 725 reset_assert_all(sc->sc_node); 726 delay(500); 727 reset_deassert_all(sc->sc_node); 728 delay(500); 729 730 clock_set_frequency(sc->sc_node, "port", 100000000UL); 731 clock_enable_all(sc->sc_node); 732 733 reset_gpio = malloc(reset_gpiolen, M_TEMP, M_WAITOK); 734 OF_getpropintarray(sc->sc_node, "reset-gpios", reset_gpio, 735 reset_gpiolen); 736 gpio_controller_config_pin(reset_gpio, GPIO_CONFIG_OUTPUT); 737 gpio_controller_set_pin(reset_gpio, 1); 738 739 dwpcie_link_config(sc); 740 741 reg = bus_space_read_4(sc->sc_iot, sc->sc_glue_ioh, PCIE_CFG0); 742 reg |= PCIE_CFG0_APP_LTSSM_EN; 743 bus_space_write_4(sc->sc_iot, sc->sc_glue_ioh, PCIE_CFG0, reg); 744 745 gpio_controller_set_pin(reset_gpio, 1); 746 delay(500); 747 gpio_controller_set_pin(reset_gpio, 0); 748 749 free(reset_gpio, M_TEMP, reset_gpiolen); 750 751 for (timo = 40; timo > 0; timo--) { 752 if (dwpcie_g12a_link_up(sc)) 753 break; 754 delay(1000); 755 } 756 if (timo == 0) 757 return ETIMEDOUT; 758 759 return 0; 760 } 761 762 int 763 dwpcie_g12a_link_up(struct dwpcie_softc *sc) 764 { 765 uint32_t reg; 766 767 reg = bus_space_read_4(sc->sc_iot, sc->sc_glue_ioh, PCIE_STATUS12); 768 if ((reg & PCIE_STATUS12_SMLH_LINK_UP) && 769 (reg & PCIE_STATUS12_RDLH_LINK_UP) && 770 (reg & PCIE_STATUS12_LTSSM_MASK) == PCIE_STATUS12_LTSSM_UP) 771 return 1; 772 return 0; 773 } 774 775 int 776 dwpcie_imx8mq_init(struct dwpcie_softc *sc) 777 { 778 uint32_t *clkreq_gpio, *disable_gpio, *reset_gpio; 779 ssize_t clkreq_gpiolen, disable_gpiolen, reset_gpiolen; 780 struct regmap *anatop, *gpr, *phy; 781 uint32_t off, reg; 782 int error, timo; 783 784 if (OF_is_compatible(sc->sc_node, "fsl,imx8mm-pcie")) { 785 anatop = regmap_bycompatible("fsl,imx8mm-anatop"); 786 gpr = regmap_bycompatible("fsl,imx8mm-iomuxc-gpr"); 787 phy = regmap_bycompatible("fsl,imx7d-pcie-phy"); 788 KASSERT(phy != NULL); 789 } else { 790 anatop = regmap_bycompatible("fsl,imx8mq-anatop"); 791 gpr = regmap_bycompatible("fsl,imx8mq-iomuxc-gpr"); 792 } 793 KASSERT(anatop != NULL); 794 KASSERT(gpr != NULL); 795 796 clkreq_gpiolen = OF_getproplen(sc->sc_node, "clkreq-gpio"); 797 disable_gpiolen = OF_getproplen(sc->sc_node, "disable-gpio"); 798 reset_gpiolen = OF_getproplen(sc->sc_node, "reset-gpio"); 799 800 if (clkreq_gpiolen > 0) { 801 clkreq_gpio = malloc(clkreq_gpiolen, M_TEMP, M_WAITOK); 802 OF_getpropintarray(sc->sc_node, "clkreq-gpio", clkreq_gpio, 803 clkreq_gpiolen); 804 gpio_controller_config_pin(clkreq_gpio, GPIO_CONFIG_OUTPUT); 805 gpio_controller_set_pin(clkreq_gpio, 1); 806 } 807 808 if (disable_gpiolen > 0) { 809 disable_gpio = malloc(disable_gpiolen, M_TEMP, M_WAITOK); 810 OF_getpropintarray(sc->sc_node, "disable-gpio", disable_gpio, 811 disable_gpiolen); 812 gpio_controller_config_pin(disable_gpio, GPIO_CONFIG_OUTPUT); 813 gpio_controller_set_pin(disable_gpio, 0); 814 } 815 816 if (reset_gpiolen > 0) { 817 reset_gpio = malloc(reset_gpiolen, M_TEMP, M_WAITOK); 818 OF_getpropintarray(sc->sc_node, "reset-gpio", reset_gpio, 819 reset_gpiolen); 820 gpio_controller_config_pin(reset_gpio, GPIO_CONFIG_OUTPUT); 821 gpio_controller_set_pin(reset_gpio, 1); 822 } 823 824 power_domain_enable(sc->sc_node); 825 reset_assert(sc->sc_node, "pciephy"); 826 reset_assert(sc->sc_node, "apps"); 827 828 reg = regmap_read_4(gpr, IOMUXC_GPR12); 829 if (OF_getpropint(sc->sc_node, "ctrl-id", 0) == 0) { 830 off = IOMUXC_GPR14; 831 reg &= ~IMX8MQ_GPR_PCIE1_DEVICE_TYPE_MASK; 832 reg |= IMX8MQ_GPR_PCIE1_DEVICE_TYPE_RC; 833 } else { 834 off = IOMUXC_GPR16; 835 reg &= ~IMX8MQ_GPR_PCIE2_DEVICE_TYPE_MASK; 836 reg |= IMX8MQ_GPR_PCIE2_DEVICE_TYPE_RC; 837 } 838 regmap_write_4(gpr, IOMUXC_GPR12, reg); 839 840 if (OF_is_compatible(sc->sc_node, "fsl,imx8mm-pcie")) { 841 if (OF_getproplen(sc->sc_node, "ext_osc") == 0 || 842 OF_getpropint(sc->sc_node, "ext_osc", 0)) { 843 reg = regmap_read_4(gpr, off); 844 reg &= ~(IMX8MQ_GPR_PCIE_REF_USE_PAD | 845 IMX8MM_GPR_PCIE_SSC_EN | 846 IMX8MM_GPR_PCIE_POWER_OFF | 847 IMX8MM_GPR_PCIE_REF_CLK_MASK); 848 reg |= (IMX8MM_GPR_PCIE_AUX_EN | 849 IMX8MM_GPR_PCIE_REF_CLK_EXT); 850 regmap_write_4(gpr, off, reg); 851 delay(100); 852 reg = regmap_read_4(gpr, off); 853 reg |= IMX8MM_GPR_PCIE_CMN_RST; 854 regmap_write_4(gpr, off, reg); 855 delay(200); 856 } else { 857 reg = regmap_read_4(gpr, off); 858 reg &= ~(IMX8MQ_GPR_PCIE_REF_USE_PAD | 859 IMX8MM_GPR_PCIE_SSC_EN | 860 IMX8MM_GPR_PCIE_POWER_OFF | 861 IMX8MM_GPR_PCIE_REF_CLK_MASK); 862 reg |= (IMX8MM_GPR_PCIE_AUX_EN | 863 IMX8MM_GPR_PCIE_REF_CLK_PLL); 864 regmap_write_4(gpr, off, reg); 865 delay(100); 866 regmap_write_4(phy, IMX8MM_PCIE_PHY_CMN_REG62, 867 IMX8MM_PCIE_PHY_CMN_REG62_PLL_CLK_OUT); 868 regmap_write_4(phy, IMX8MM_PCIE_PHY_CMN_REG64, 869 IMX8MM_PCIE_PHY_CMN_REG64_AUX_RX_TX_TERM); 870 reg = regmap_read_4(gpr, off); 871 reg |= IMX8MM_GPR_PCIE_CMN_RST; 872 regmap_write_4(gpr, off, reg); 873 delay(200); 874 regmap_write_4(phy, IMX8MM_PCIE_PHY_TRSV_REG5, 875 IMX8MM_PCIE_PHY_TRSV_REG5_GEN1_DEEMP); 876 regmap_write_4(phy, IMX8MM_PCIE_PHY_TRSV_REG6, 877 IMX8MM_PCIE_PHY_TRSV_REG6_GEN2_DEEMP); 878 } 879 } else { 880 if (OF_getproplen(sc->sc_node, "ext_osc") == 0 || 881 OF_getpropint(sc->sc_node, "ext_osc", 0)) { 882 reg = regmap_read_4(gpr, off); 883 reg |= IMX8MQ_GPR_PCIE_REF_USE_PAD; 884 regmap_write_4(gpr, off, reg); 885 } else { 886 reg = regmap_read_4(gpr, off); 887 reg &= ~IMX8MQ_GPR_PCIE_REF_USE_PAD; 888 regmap_write_4(gpr, off, reg); 889 890 regmap_write_4(anatop, ANATOP_PLLOUT_CTL, 891 ANATOP_PLLOUT_CTL_CKE | 892 ANATOP_PLLOUT_CTL_SEL_SYSPLL1); 893 regmap_write_4(anatop, ANATOP_PLLOUT_DIV, 894 ANATOP_PLLOUT_DIV_SYSPLL1); 895 } 896 } 897 898 clock_enable(sc->sc_node, "pcie_phy"); 899 clock_enable(sc->sc_node, "pcie_bus"); 900 clock_enable(sc->sc_node, "pcie"); 901 clock_enable(sc->sc_node, "pcie_aux"); 902 903 /* Allow clocks to stabilize. */ 904 delay(200); 905 906 if (reset_gpiolen > 0) { 907 gpio_controller_set_pin(reset_gpio, 1); 908 delay(100000); 909 gpio_controller_set_pin(reset_gpio, 0); 910 } 911 912 reset_deassert(sc->sc_node, "pciephy"); 913 914 if (OF_is_compatible(sc->sc_node, "fsl,imx8mm-pcie")) { 915 for (timo = 2000; timo > 0; timo--) { 916 if (regmap_read_4(phy, IMX8MM_PCIE_PHY_CMN_REG75) == 917 IMX8MM_PCIE_PHY_CMN_REG75_PLL_DONE) 918 break; 919 delay(10); 920 } 921 if (timo == 0) { 922 error = ETIMEDOUT; 923 goto err; 924 } 925 } 926 927 reg = HREAD4(sc, 0x100000 + PCIE_RC_LCR); 928 reg &= ~PCIE_RC_LCR_L1EL_MASK; 929 reg |= PCIE_RC_LCR_L1EL_64US; 930 HWRITE4(sc, 0x100000 + PCIE_RC_LCR, reg); 931 932 dwpcie_link_config(sc); 933 934 reg = HREAD4(sc, PCIE_RC_LCR); 935 reg &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK; 936 reg |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1; 937 HWRITE4(sc, PCIE_RC_LCR, reg); 938 939 reset_deassert(sc->sc_node, "apps"); 940 941 for (timo = 20000; timo > 0; timo--) { 942 if (dwpcie_link_up(sc)) 943 break; 944 delay(10); 945 } 946 if (timo == 0) { 947 error = ETIMEDOUT; 948 goto err; 949 } 950 951 if (OF_getpropint(sc->sc_node, "fsl,max-link-speed", 1) >= 2) { 952 reg = HREAD4(sc, PCIE_RC_LCR); 953 reg &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK; 954 reg |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2; 955 HWRITE4(sc, PCIE_RC_LCR, reg); 956 957 reg = HREAD4(sc, PCIE_LINK_WIDTH_SPEED_CTRL); 958 reg |= PCIE_LINK_WIDTH_SPEED_CTRL_CHANGE; 959 HWRITE4(sc, PCIE_LINK_WIDTH_SPEED_CTRL, reg); 960 961 for (timo = 20000; timo > 0; timo--) { 962 if (dwpcie_link_up(sc)) 963 break; 964 delay(10); 965 } 966 if (timo == 0) { 967 error = ETIMEDOUT; 968 goto err; 969 } 970 } 971 972 sc->sc_ih = fdt_intr_establish(sc->sc_node, IPL_AUDIO | IPL_MPSAFE, 973 dwpcie_imx8mq_intr, sc, sc->sc_dev.dv_xname); 974 975 /* Unmask INTx interrupts. */ 976 HWRITE4(sc, PCIE_GLOBAL_INT_MASK, 977 PCIE_GLOBAL_INT_MASK_INT_A | PCIE_GLOBAL_INT_MASK_INT_B | 978 PCIE_GLOBAL_INT_MASK_INT_C | PCIE_GLOBAL_INT_MASK_INT_D); 979 980 error = 0; 981 err: 982 if (clkreq_gpiolen > 0) 983 free(clkreq_gpio, M_TEMP, clkreq_gpiolen); 984 if (disable_gpiolen > 0) 985 free(disable_gpio, M_TEMP, disable_gpiolen); 986 if (reset_gpiolen > 0) 987 free(reset_gpio, M_TEMP, reset_gpiolen); 988 return error; 989 } 990 991 int 992 dwpcie_imx8mq_intr(void *arg) 993 { 994 struct dwpcie_softc *sc = arg; 995 uint32_t cause; 996 997 /* Acknowledge interrupts. */ 998 cause = HREAD4(sc, PCIE_GLOBAL_INT_CAUSE); 999 HWRITE4(sc, PCIE_GLOBAL_INT_CAUSE, cause); 1000 1001 /* INTx interrupt, so not really ours. */ 1002 return 0; 1003 } 1004 1005 void 1006 dwpcie_atu_config(struct dwpcie_softc *sc, int index, int type, 1007 uint64_t cpu_addr, uint64_t pci_addr, uint64_t size) 1008 { 1009 uint32_t reg, off; 1010 int timo; 1011 1012 off = sc->sc_atu_base + IATU_OFFSET_UNROLL(index); 1013 if (!sc->sc_atu_unroll) { 1014 off = IATU_OFFSET_VIEWPORT; 1015 HWRITE4(sc, IATU_VIEWPORT, index); 1016 } 1017 1018 HWRITE4(sc, off + IATU_LWR_BASE_ADDR, cpu_addr); 1019 HWRITE4(sc, off + IATU_UPPER_BASE_ADDR, cpu_addr >> 32); 1020 HWRITE4(sc, off + IATU_LIMIT_ADDR, cpu_addr + size - 1); 1021 HWRITE4(sc, off + IATU_LWR_TARGET_ADDR, pci_addr); 1022 HWRITE4(sc, off + IATU_UPPER_TARGET_ADDR, pci_addr >> 32); 1023 HWRITE4(sc, off + IATU_REGION_CTRL_1, type); 1024 HWRITE4(sc, off + IATU_REGION_CTRL_2, IATU_REGION_CTRL_2_REGION_EN); 1025 1026 for (timo = 5; timo > 0; timo--) { 1027 reg = HREAD4(sc, off + IATU_REGION_CTRL_2); 1028 if (reg & IATU_REGION_CTRL_2_REGION_EN) 1029 break; 1030 delay(9000); 1031 } 1032 if (timo == 0) 1033 printf("%s:%d: timeout\n", __func__, __LINE__); 1034 } 1035 1036 int 1037 dwpcie_link_up(struct dwpcie_softc *sc) 1038 { 1039 uint32_t reg; 1040 1041 reg = HREAD4(sc, PCIE_PHY_DEBUG_R1); 1042 if ((reg & PCIE_PHY_DEBUG_R1_XMLH_LINK_UP) != 0 && 1043 (reg & PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING) == 0) 1044 return 1; 1045 return 0; 1046 } 1047 1048 void 1049 dwpcie_attach_hook(struct device *parent, struct device *self, 1050 struct pcibus_attach_args *pba) 1051 { 1052 } 1053 1054 int 1055 dwpcie_bus_maxdevs(void *v, int bus) 1056 { 1057 struct dwpcie_softc *sc = v; 1058 1059 if (bus == sc->sc_bus || bus == sc->sc_bus + 1) 1060 return 1; 1061 return 32; 1062 } 1063 1064 pcitag_t 1065 dwpcie_make_tag(void *v, int bus, int device, int function) 1066 { 1067 return ((bus << 24) | (device << 19) | (function << 16)); 1068 } 1069 1070 void 1071 dwpcie_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 1072 { 1073 if (bp != NULL) 1074 *bp = (tag >> 24) & 0xff; 1075 if (dp != NULL) 1076 *dp = (tag >> 19) & 0x1f; 1077 if (fp != NULL) 1078 *fp = (tag >> 16) & 0x7; 1079 } 1080 1081 int 1082 dwpcie_conf_size(void *v, pcitag_t tag) 1083 { 1084 return PCIE_CONFIG_SPACE_SIZE; 1085 } 1086 1087 pcireg_t 1088 dwpcie_conf_read(void *v, pcitag_t tag, int reg) 1089 { 1090 struct dwpcie_softc *sc = v; 1091 int bus, dev, fn; 1092 uint32_t ret; 1093 1094 dwpcie_decompose_tag(sc, tag, &bus, &dev, &fn); 1095 if (bus == sc->sc_bus) { 1096 KASSERT(dev == 0); 1097 return HREAD4(sc, tag | reg); 1098 } 1099 1100 if (bus == sc->sc_bus + 1) { 1101 dwpcie_atu_config(sc, IATU_VIEWPORT_INDEX1, 1102 IATU_REGION_CTRL_1_TYPE_CFG0, 1103 sc->sc_cfg0_base, tag, sc->sc_cfg0_size); 1104 ret = bus_space_read_4(sc->sc_iot, sc->sc_cfg0_ioh, reg); 1105 } else { 1106 dwpcie_atu_config(sc, IATU_VIEWPORT_INDEX1, 1107 IATU_REGION_CTRL_1_TYPE_CFG1, 1108 sc->sc_cfg1_base, tag, sc->sc_cfg1_size); 1109 ret = bus_space_read_4(sc->sc_iot, sc->sc_cfg1_ioh, reg); 1110 } 1111 if (sc->sc_num_viewport <= 2) 1112 dwpcie_atu_config(sc, IATU_VIEWPORT_INDEX1, 1113 IATU_REGION_CTRL_1_TYPE_IO, sc->sc_io_base, 1114 sc->sc_io_bus_addr, sc->sc_io_size); 1115 1116 return ret; 1117 } 1118 1119 void 1120 dwpcie_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data) 1121 { 1122 struct dwpcie_softc *sc = v; 1123 int bus, dev, fn; 1124 1125 dwpcie_decompose_tag(sc, tag, &bus, &dev, &fn); 1126 if (bus == sc->sc_bus) { 1127 KASSERT(dev == 0); 1128 HWRITE4(sc, tag | reg, data); 1129 return; 1130 } 1131 1132 if (bus == sc->sc_bus + 1) { 1133 dwpcie_atu_config(sc, IATU_VIEWPORT_INDEX1, 1134 IATU_REGION_CTRL_1_TYPE_CFG0, 1135 sc->sc_cfg0_base, tag, sc->sc_cfg0_size); 1136 bus_space_write_4(sc->sc_iot, sc->sc_cfg0_ioh, reg, data); 1137 } else { 1138 dwpcie_atu_config(sc, IATU_VIEWPORT_INDEX1, 1139 IATU_REGION_CTRL_1_TYPE_CFG1, 1140 sc->sc_cfg1_base, tag, sc->sc_cfg1_size); 1141 bus_space_write_4(sc->sc_iot, sc->sc_cfg1_ioh, reg, data); 1142 } 1143 if (sc->sc_num_viewport <= 2) 1144 dwpcie_atu_config(sc, IATU_VIEWPORT_INDEX1, 1145 IATU_REGION_CTRL_1_TYPE_IO, sc->sc_io_base, 1146 sc->sc_io_bus_addr, sc->sc_io_size); 1147 } 1148 1149 int 1150 dwpcie_probe_device_hook(void *v, struct pci_attach_args *pa) 1151 { 1152 struct dwpcie_softc *sc = v; 1153 uint16_t rid; 1154 1155 rid = pci_requester_id(pa->pa_pc, pa->pa_tag); 1156 pa->pa_dmat = iommu_device_map_pci(sc->sc_node, rid, pa->pa_dmat); 1157 1158 return 0; 1159 } 1160 1161 int 1162 dwpcie_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 1163 { 1164 int pin = pa->pa_rawintrpin; 1165 1166 if (pin == 0 || pin > PCI_INTERRUPT_PIN_MAX) 1167 return -1; 1168 1169 if (pa->pa_tag == 0) 1170 return -1; 1171 1172 ihp->ih_pc = pa->pa_pc; 1173 ihp->ih_tag = pa->pa_intrtag; 1174 ihp->ih_intrpin = pa->pa_intrpin; 1175 ihp->ih_type = PCI_INTX; 1176 1177 return 0; 1178 } 1179 1180 const char * 1181 dwpcie_intr_string(void *v, pci_intr_handle_t ih) 1182 { 1183 switch (ih.ih_type) { 1184 case PCI_MSI: 1185 return "msi"; 1186 case PCI_MSIX: 1187 return "msix"; 1188 } 1189 1190 return "intx"; 1191 } 1192 1193 void * 1194 dwpcie_intr_establish(void *v, pci_intr_handle_t ih, int level, 1195 struct cpu_info *ci, int (*func)(void *), void *arg, char *name) 1196 { 1197 struct dwpcie_softc *sc = v; 1198 void *cookie; 1199 1200 KASSERT(ih.ih_type != PCI_NONE); 1201 1202 if (ih.ih_type != PCI_INTX) { 1203 uint64_t addr, data; 1204 1205 /* Assume hardware passes Requester ID as sideband data. */ 1206 data = pci_requester_id(ih.ih_pc, ih.ih_tag); 1207 cookie = fdt_intr_establish_msi_cpu(sc->sc_node, &addr, 1208 &data, level, ci, func, arg, (void *)name); 1209 if (cookie == NULL) 1210 return NULL; 1211 1212 /* TODO: translate address to the PCI device's view */ 1213 1214 if (ih.ih_type == PCI_MSIX) { 1215 pci_msix_enable(ih.ih_pc, ih.ih_tag, 1216 &sc->sc_bus_memt, ih.ih_intrpin, addr, data); 1217 } else 1218 pci_msi_enable(ih.ih_pc, ih.ih_tag, addr, data); 1219 } else { 1220 int bus, dev, fn; 1221 uint32_t reg[4]; 1222 1223 dwpcie_decompose_tag(sc, ih.ih_tag, &bus, &dev, &fn); 1224 1225 reg[0] = bus << 16 | dev << 11 | fn << 8; 1226 reg[1] = reg[2] = 0; 1227 reg[3] = ih.ih_intrpin; 1228 1229 cookie = fdt_intr_establish_imap_cpu(sc->sc_node, reg, 1230 sizeof(reg), level, ci, func, arg, name); 1231 } 1232 1233 return cookie; 1234 } 1235 1236 void 1237 dwpcie_intr_disestablish(void *v, void *cookie) 1238 { 1239 panic("%s", __func__); 1240 } 1241 1242 int 1243 dwpcie_bs_iomap(bus_space_tag_t t, bus_addr_t addr, bus_size_t size, 1244 int flags, bus_space_handle_t *bshp) 1245 { 1246 struct dwpcie_softc *sc = t->bus_private; 1247 int i; 1248 1249 for (i = 0; i < sc->sc_nranges; i++) { 1250 uint64_t pci_start = sc->sc_ranges[i].pci_base; 1251 uint64_t pci_end = pci_start + sc->sc_ranges[i].size; 1252 uint64_t phys_start = sc->sc_ranges[i].phys_base; 1253 1254 if ((sc->sc_ranges[i].flags & 0x03000000) == 0x01000000 && 1255 addr >= pci_start && addr + size <= pci_end) { 1256 return bus_space_map(sc->sc_iot, 1257 addr - pci_start + phys_start, size, flags, bshp); 1258 } 1259 } 1260 1261 return ENXIO; 1262 } 1263 1264 int 1265 dwpcie_bs_memmap(bus_space_tag_t t, bus_addr_t addr, bus_size_t size, 1266 int flags, bus_space_handle_t *bshp) 1267 { 1268 struct dwpcie_softc *sc = t->bus_private; 1269 int i; 1270 1271 for (i = 0; i < sc->sc_nranges; i++) { 1272 uint64_t pci_start = sc->sc_ranges[i].pci_base; 1273 uint64_t pci_end = pci_start + sc->sc_ranges[i].size; 1274 uint64_t phys_start = sc->sc_ranges[i].phys_base; 1275 1276 if ((sc->sc_ranges[i].flags & 0x03000000) == 0x02000000 && 1277 addr >= pci_start && addr + size <= pci_end) { 1278 return bus_space_map(sc->sc_iot, 1279 addr - pci_start + phys_start, size, flags, bshp); 1280 } 1281 } 1282 1283 return ENXIO; 1284 } 1285