1 /* $OpenBSD: amlmmc.c,v 1.6 2020/05/19 15:47:32 kettenis Exp $ */ 2 /* 3 * Copyright (c) 2019 Mark Kettenis <kettenis@openbsd.org> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #include <sys/param.h> 19 #include <sys/systm.h> 20 #include <sys/device.h> 21 #include <sys/malloc.h> 22 23 #include <machine/intr.h> 24 #include <machine/bus.h> 25 #include <machine/fdt.h> 26 27 #include <dev/ofw/openfirm.h> 28 #include <dev/ofw/ofw_clock.h> 29 #include <dev/ofw/ofw_gpio.h> 30 #include <dev/ofw/ofw_pinctrl.h> 31 #include <dev/ofw/ofw_regulator.h> 32 #include <dev/ofw/fdt.h> 33 34 #include <dev/sdmmc/sdmmcvar.h> 35 36 #define SD_EMMC_CLOCK 0x0000 37 #define SD_EMMC_CLOCK_RX_PHASE_0 (0 << 12) 38 #define SD_EMMC_CLOCK_RX_PHASE_90 (1 << 12) 39 #define SD_EMMC_CLOCK_RX_PHASE_180 (2 << 12) 40 #define SD_EMMC_CLOCK_RX_PHASE_270 (3 << 12) 41 #define SD_EMMC_CLOCK_TX_PHASE_0 (0 << 10) 42 #define SD_EMMC_CLOCK_TX_PHASE_90 (1 << 10) 43 #define SD_EMMC_CLOCK_TX_PHASE_180 (2 << 10) 44 #define SD_EMMC_CLOCK_TX_PHASE_270 (3 << 10) 45 #define SD_EMMC_CLOCK_CO_PHASE_0 (0 << 8) 46 #define SD_EMMC_CLOCK_CO_PHASE_90 (1 << 8) 47 #define SD_EMMC_CLOCK_CO_PHASE_180 (2 << 8) 48 #define SD_EMMC_CLOCK_CO_PHASE_270 (3 << 8) 49 #define SD_EMMC_CLOCK_CLK_SRC_24M (0 << 6) 50 #define SD_EMMC_CLOCK_CLK_SRC_FCLK (1 << 6) 51 #define SD_EMMC_CLOCK_DIV_MAX 63 52 #define SD_EMMC_DELAY1 0x0004 53 #define SD_EMMC_DELAY2 0x0008 54 #define SD_EMMC_ADJUST 0x000c 55 #define SD_EMMC_START 0x0040 56 #define SD_EMMC_START_START (1 << 1) 57 #define SD_EMMC_START_STOP (0 << 1) 58 #define SD_EMMC_CFG 0x0044 59 #define SD_EMMC_CFG_AUTO_CLK (1 << 23) 60 #define SD_EMMC_CFG_STOP_CLOCK (1 << 22) 61 #define SD_EMMC_CFG_SDCLK_ALWAYS_ON (1 << 18) 62 #define SD_EMMC_CFG_RC_CC_MASK (0xf << 12) 63 #define SD_EMMC_CFG_RC_CC_16 (0x4 << 12) 64 #define SD_EMMC_CFG_RESP_TIMEOUT_MASK (0xf << 8) 65 #define SD_EMMC_CFG_RESP_TIMEOUT_256 (0x8 << 8) 66 #define SD_EMMC_CFG_BL_LEN_MASK (0xf << 4) 67 #define SD_EMMC_CFG_BL_LEN_SHIFT 4 68 #define SD_EMMC_CFG_BL_LEN_512 (0x9 << 4) 69 #define SD_EMMC_CFG_DDR (1 << 2) 70 #define SD_EMMC_CFG_BUS_WIDTH_MASK (0x3 << 0) 71 #define SD_EMMC_CFG_BUS_WIDTH_1 (0x0 << 0) 72 #define SD_EMMC_CFG_BUS_WIDTH_4 (0x1 << 0) 73 #define SD_EMMC_CFG_BUS_WIDTH_8 (0x2 << 0) 74 #define SD_EMMC_STATUS 0x0048 75 #define SD_EMMC_STATUS_END_OF_CHAIN (1 << 13) 76 #define SD_EMMC_STATUS_DESC_TIMEOUT (1 << 12) 77 #define SD_EMMC_STATUS_RESP_TIMEOUT (1 << 11) 78 #define SD_EMMC_STATUS_MASK 0x00003fff 79 #define SD_EMMC_STATUS_ERR_MASK 0x000007ff 80 #define SD_EMMC_IRQ_EN 0x004c 81 #define SD_EMMC_IRQ_EN_MASK SD_EMMC_STATUS_MASK 82 #define SD_EMMC_CMD_CFG 0x0050 83 #define SD_EMMC_CMD_CFG_BLOCK_MODE (1 << 9) 84 #define SD_EMMC_CMD_CFG_R1B (1 << 10) 85 #define SD_EMMC_CMD_CFG_END_OF_CHAIN (1 << 11) 86 #define SD_EMMC_CMD_CFG_TIMEOUT_1024 (10 << 12) 87 #define SD_EMMC_CMD_CFG_TIMEOUT_4096 (12 << 12) 88 #define SD_EMMC_CMD_CFG_NO_RESP (1 << 16) 89 #define SD_EMMC_CMD_CFG_NO_CMD (1 << 17) 90 #define SD_EMMC_CMD_CFG_DATA_IO (1 << 18) 91 #define SD_EMMC_CMD_CFG_DATA_WR (1 << 19) 92 #define SD_EMMC_CMD_CFG_RESP_NOCRC (1 << 20) 93 #define SD_EMMC_CMD_CFG_RESP_128 (1 << 21) 94 #define SD_EMMC_CMD_CFG_CMD_INDEX_SHIFT 24 95 #define SD_EMMC_CMD_CFG_OWNER (1U << 31) 96 #define SD_EMMC_CMD_ARG 0x0054 97 #define SD_EMMC_CMD_DAT 0x0058 98 #define SD_EMMC_CMD_RSP 0x005c 99 #define SD_EMMC_CMD_RSP1 0x0060 100 #define SD_EMMC_CMD_RSP2 0x0064 101 #define SD_EMMC_CMD_RSP3 0x0068 102 103 #define HREAD4(sc, reg) \ 104 (bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg))) 105 #define HWRITE4(sc, reg, val) \ 106 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 107 #define HSET4(sc, reg, bits) \ 108 HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits)) 109 #define HCLR4(sc, reg, bits) \ 110 HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits)) 111 112 struct amlmmc_desc { 113 uint32_t cmd_cfg; 114 uint32_t cmd_arg; 115 uint32_t data_addr; 116 uint32_t resp_addr; 117 }; 118 119 #define AMLMMC_NDESC (PAGE_SIZE / sizeof(struct amlmmc_desc)) 120 #define AMLMMC_MAXSEGSZ 0x20000 121 122 struct amlmmc_softc { 123 struct device sc_dev; 124 bus_space_tag_t sc_iot; 125 bus_space_handle_t sc_ioh; 126 bus_dma_tag_t sc_dmat; 127 bus_dmamap_t sc_dmap; 128 129 void *sc_ih; 130 uint32_t sc_status; 131 132 bus_dmamap_t sc_desc_map; 133 bus_dma_segment_t sc_desc_segs[1]; 134 int sc_desc_nsegs; 135 caddr_t sc_desc; 136 137 int sc_node; 138 uint32_t sc_clkin0; 139 uint32_t sc_clkin1; 140 uint32_t sc_gpio[4]; 141 uint32_t sc_vmmc; 142 uint32_t sc_vqmmc; 143 uint32_t sc_pwrseq; 144 uint32_t sc_vdd; 145 146 int sc_blklen; 147 struct device *sc_sdmmc; 148 }; 149 150 int amlmmc_match(struct device *, void *, void *); 151 void amlmmc_attach(struct device *, struct device *, void *); 152 153 struct cfattach amlmmc_ca = { 154 sizeof (struct amlmmc_softc), amlmmc_match, amlmmc_attach 155 }; 156 157 struct cfdriver amlmmc_cd = { 158 NULL, "amlmmc", DV_DULL 159 }; 160 161 int amlmmc_alloc_descriptors(struct amlmmc_softc *); 162 void amlmmc_free_descriptors(struct amlmmc_softc *); 163 int amlmmc_intr(void *); 164 165 void amlmmc_pwrseq_reset(uint32_t); 166 167 int amlmmc_host_reset(sdmmc_chipset_handle_t); 168 uint32_t amlmmc_host_ocr(sdmmc_chipset_handle_t); 169 int amlmmc_host_maxblklen(sdmmc_chipset_handle_t); 170 int amlmmc_card_detect(sdmmc_chipset_handle_t); 171 int amlmmc_bus_power(sdmmc_chipset_handle_t, uint32_t); 172 int amlmmc_bus_clock(sdmmc_chipset_handle_t, int, int); 173 int amlmmc_bus_width(sdmmc_chipset_handle_t, int); 174 void amlmmc_exec_command(sdmmc_chipset_handle_t, struct sdmmc_command *); 175 int amlmmc_signal_voltage(sdmmc_chipset_handle_t, int); 176 177 struct sdmmc_chip_functions amlmmc_chip_functions = { 178 .host_reset = amlmmc_host_reset, 179 .host_ocr = amlmmc_host_ocr, 180 .host_maxblklen = amlmmc_host_maxblklen, 181 .card_detect = amlmmc_card_detect, 182 .bus_power = amlmmc_bus_power, 183 .bus_clock = amlmmc_bus_clock, 184 .bus_width = amlmmc_bus_width, 185 .exec_command = amlmmc_exec_command, 186 .signal_voltage = amlmmc_signal_voltage, 187 }; 188 189 int 190 amlmmc_match(struct device *parent, void *match, void *aux) 191 { 192 struct fdt_attach_args *faa = aux; 193 194 return OF_is_compatible(faa->fa_node, "amlogic,meson-axg-mmc"); 195 } 196 197 void 198 amlmmc_attach(struct device *parent, struct device *self, void *aux) 199 { 200 struct amlmmc_softc *sc = (struct amlmmc_softc *)self; 201 struct fdt_attach_args *faa = aux; 202 struct sdmmcbus_attach_args saa; 203 uint32_t cfg, width; 204 int error; 205 206 if (faa->fa_nreg < 1) { 207 printf(": no registers\n"); 208 return; 209 } 210 211 sc->sc_iot = faa->fa_iot; 212 if (bus_space_map(sc->sc_iot, faa->fa_reg[0].addr, 213 faa->fa_reg[0].size, 0, &sc->sc_ioh)) { 214 printf(": can't map registers\n"); 215 return; 216 } 217 218 sc->sc_dmat = faa->fa_dmat; 219 error = amlmmc_alloc_descriptors(sc); 220 if (error) { 221 printf(": can't allocate desctiptors\n"); 222 goto unmap; 223 } 224 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, AMLMMC_NDESC, 225 AMLMMC_MAXSEGSZ, 0, BUS_DMA_WAITOK|BUS_DMA_ALLOCNOW, &sc->sc_dmap); 226 if (error) { 227 printf(": can't create DMA map\n"); 228 goto free; 229 } 230 231 sc->sc_ih = fdt_intr_establish(faa->fa_node, IPL_BIO, 232 amlmmc_intr, sc, sc->sc_dev.dv_xname); 233 if (sc->sc_ih == NULL) { 234 printf(": can't establish interrupt\n"); 235 goto destroy; 236 } 237 238 sc->sc_node = faa->fa_node; 239 printf("\n"); 240 241 pinctrl_byname(faa->fa_node, "default"); 242 243 clock_enable_all(faa->fa_node); 244 reset_deassert_all(faa->fa_node); 245 246 sc->sc_clkin0 = clock_get_frequency(faa->fa_node, "clkin0"); 247 sc->sc_clkin1 = clock_get_frequency(faa->fa_node, "clkin1"); 248 249 OF_getpropintarray(faa->fa_node, "cd-gpios", sc->sc_gpio, 250 sizeof(sc->sc_gpio)); 251 if (sc->sc_gpio[0]) 252 gpio_controller_config_pin(sc->sc_gpio, GPIO_CONFIG_INPUT); 253 254 sc->sc_vmmc = OF_getpropint(sc->sc_node, "vmmc-supply", 0); 255 sc->sc_vqmmc = OF_getpropint(sc->sc_node, "vqmmc-supply", 0); 256 sc->sc_pwrseq = OF_getpropint(sc->sc_node, "mmc-pwrseq", 0); 257 258 /* Configure clock mode. */ 259 cfg = HREAD4(sc, SD_EMMC_CFG); 260 cfg &= ~SD_EMMC_CFG_SDCLK_ALWAYS_ON; 261 cfg |= SD_EMMC_CFG_AUTO_CLK; 262 HWRITE4(sc, SD_EMMC_CFG, cfg); 263 264 amlmmc_bus_width(sc, 1); 265 266 /* Initialize timings and block size. */ 267 cfg = HREAD4(sc, SD_EMMC_CFG); 268 cfg &= ~SD_EMMC_CFG_RC_CC_MASK; 269 cfg |= SD_EMMC_CFG_RC_CC_16; 270 cfg &= ~SD_EMMC_CFG_RESP_TIMEOUT_MASK; 271 cfg |= SD_EMMC_CFG_RESP_TIMEOUT_256; 272 cfg &= ~SD_EMMC_CFG_BL_LEN_MASK; 273 cfg |= SD_EMMC_CFG_BL_LEN_512; 274 HWRITE4(sc, SD_EMMC_CFG, cfg); 275 276 /* Clear status bits & enable interrupts. */ 277 HWRITE4(sc, SD_EMMC_STATUS, SD_EMMC_STATUS_MASK); 278 HWRITE4(sc, SD_EMMC_IRQ_EN, SD_EMMC_IRQ_EN_MASK); 279 280 /* Reset eMMC. */ 281 if (sc->sc_pwrseq) 282 amlmmc_pwrseq_reset(sc->sc_pwrseq); 283 284 memset(&saa, 0, sizeof(saa)); 285 saa.saa_busname = "sdmmc"; 286 saa.sct = &amlmmc_chip_functions; 287 saa.sch = sc; 288 saa.dmat = sc->sc_dmat; 289 saa.dmap = sc->sc_dmap; 290 saa.caps = SMC_CAPS_DMA; 291 saa.flags = SMF_STOP_AFTER_MULTIPLE; 292 293 if (OF_getproplen(sc->sc_node, "cap-mmc-highspeed") == 0) 294 saa.caps |= SMC_CAPS_MMC_HIGHSPEED; 295 if (OF_getproplen(sc->sc_node, "cap-sd-highspeed") == 0) 296 saa.caps |= SMC_CAPS_SD_HIGHSPEED; 297 if (OF_getproplen(sc->sc_node, "mmc-ddr-1_8v") == 0) 298 saa.caps |= SMC_CAPS_MMC_DDR52; 299 300 width = OF_getpropint(faa->fa_node, "bus-width", 1); 301 if (width >= 8) 302 saa.caps |= SMC_CAPS_8BIT_MODE; 303 if (width >= 4) 304 saa.caps |= SMC_CAPS_4BIT_MODE; 305 306 sc->sc_sdmmc = config_found(self, &saa, NULL); 307 return; 308 309 destroy: 310 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmap); 311 free: 312 amlmmc_free_descriptors(sc); 313 unmap: 314 bus_space_unmap(sc->sc_iot, sc->sc_ioh, faa->fa_reg[0].size); 315 } 316 317 int 318 amlmmc_alloc_descriptors(struct amlmmc_softc *sc) 319 { 320 int error, rseg; 321 322 /* Allocate descriptor memory */ 323 error = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, PAGE_SIZE, 324 PAGE_SIZE, sc->sc_desc_segs, 1, &rseg, 325 BUS_DMA_WAITOK | BUS_DMA_ZERO); 326 if (error) 327 return error; 328 error = bus_dmamem_map(sc->sc_dmat, sc->sc_desc_segs, rseg, 329 PAGE_SIZE, &sc->sc_desc, BUS_DMA_WAITOK | BUS_DMA_COHERENT); 330 if (error) { 331 bus_dmamem_free(sc->sc_dmat, sc->sc_desc_segs, rseg); 332 return error; 333 } 334 error = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, 1, PAGE_SIZE, 335 0, BUS_DMA_WAITOK, &sc->sc_desc_map); 336 if (error) { 337 bus_dmamem_unmap(sc->sc_dmat, sc->sc_desc, PAGE_SIZE); 338 bus_dmamem_free(sc->sc_dmat, sc->sc_desc_segs, rseg); 339 return error; 340 } 341 error = bus_dmamap_load(sc->sc_dmat, sc->sc_desc_map, 342 sc->sc_desc, PAGE_SIZE, NULL, BUS_DMA_WAITOK | BUS_DMA_WRITE); 343 if (error) { 344 bus_dmamap_destroy(sc->sc_dmat, sc->sc_desc_map); 345 bus_dmamem_unmap(sc->sc_dmat, sc->sc_desc, PAGE_SIZE); 346 bus_dmamem_free(sc->sc_dmat, sc->sc_desc_segs, rseg); 347 return error; 348 } 349 350 sc->sc_desc_nsegs = rseg; 351 return 0; 352 } 353 354 void 355 amlmmc_free_descriptors(struct amlmmc_softc *sc) 356 { 357 bus_dmamap_unload(sc->sc_dmat, sc->sc_desc_map); 358 bus_dmamap_destroy(sc->sc_dmat, sc->sc_desc_map); 359 bus_dmamem_unmap(sc->sc_dmat, sc->sc_desc, PAGE_SIZE); 360 bus_dmamem_free(sc->sc_dmat, sc->sc_desc_segs, sc->sc_desc_nsegs); 361 } 362 363 int 364 amlmmc_intr(void *arg) 365 { 366 struct amlmmc_softc *sc = arg; 367 uint32_t status; 368 369 status = HREAD4(sc, SD_EMMC_STATUS); 370 if ((status & SD_EMMC_STATUS_MASK) == 0) 371 return 0; 372 373 HWRITE4(sc, SD_EMMC_STATUS, status); 374 sc->sc_status = status & SD_EMMC_STATUS_MASK; 375 wakeup(sc); 376 return 1; 377 } 378 379 void 380 amlmmc_set_blklen(struct amlmmc_softc *sc, int blklen) 381 { 382 uint32_t cfg; 383 384 if (blklen == sc->sc_blklen) 385 return; 386 387 cfg = HREAD4(sc, SD_EMMC_CFG); 388 cfg &= ~SD_EMMC_CFG_BL_LEN_MASK; 389 cfg |= (fls(blklen) - 1) << SD_EMMC_CFG_BL_LEN_SHIFT; 390 HWRITE4(sc, SD_EMMC_CFG, cfg); 391 sc->sc_blklen = blklen; 392 } 393 394 void 395 amlmmc_pwrseq_reset(uint32_t phandle) 396 { 397 uint32_t *gpios, *gpio; 398 int node; 399 int len; 400 401 node = OF_getnodebyphandle(phandle); 402 if (node == 0) 403 return; 404 405 if (!OF_is_compatible(node, "mmc-pwrseq-emmc")) 406 return; 407 408 len = OF_getproplen(node, "reset-gpios"); 409 if (len <= 0) 410 return; 411 412 gpios = malloc(len, M_TEMP, M_WAITOK); 413 OF_getpropintarray(node, "reset-gpios", gpios, len); 414 415 gpio = gpios; 416 while (gpio && gpio < gpios + (len / sizeof(uint32_t))) { 417 gpio_controller_config_pin(gpio, GPIO_CONFIG_OUTPUT); 418 gpio_controller_set_pin(gpio, 1); 419 delay(1); 420 gpio_controller_set_pin(gpio, 0); 421 delay(200); 422 gpio = gpio_controller_next_pin(gpio); 423 } 424 425 free(gpios, M_TEMP, len); 426 } 427 428 int 429 amlmmc_host_reset(sdmmc_chipset_handle_t sch) 430 { 431 printf("%s\n", __func__); 432 return 0; 433 } 434 435 uint32_t 436 amlmmc_host_ocr(sdmmc_chipset_handle_t sch) 437 { 438 return MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V; 439 } 440 441 int 442 amlmmc_host_maxblklen(sdmmc_chipset_handle_t sch) 443 { 444 return 512; 445 } 446 447 int 448 amlmmc_card_detect(sdmmc_chipset_handle_t sch) 449 { 450 struct amlmmc_softc *sc = sch; 451 452 if (OF_getproplen(sc->sc_node, "non-removable") == 0) 453 return 1; 454 455 if (sc->sc_gpio[0]) { 456 int inverted, val; 457 458 val = gpio_controller_get_pin(sc->sc_gpio); 459 460 inverted = (OF_getproplen(sc->sc_node, "cd-inverted") == 0); 461 return inverted ? !val : val; 462 } 463 464 return 1; 465 } 466 467 int 468 amlmmc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 469 { 470 struct amlmmc_softc *sc = sch; 471 uint32_t vdd = 0; 472 473 if (ISSET(ocr, MMC_OCR_3_2V_3_3V|MMC_OCR_3_3V_3_4V)) 474 vdd = 3300000; 475 476 /* enable mmc power */ 477 if (sc->sc_vmmc && vdd > 0) 478 regulator_enable(sc->sc_vmmc); 479 480 if (sc->sc_vqmmc && vdd > 0) 481 regulator_enable(sc->sc_vqmmc); 482 483 delay(10000); 484 485 sc->sc_vdd = vdd; 486 return 0; 487 } 488 489 int 490 amlmmc_bus_clock(sdmmc_chipset_handle_t sch, int freq, int timing) 491 { 492 struct amlmmc_softc *sc = sch; 493 uint32_t div, clock; 494 495 pinctrl_byname(sc->sc_node, "clk-gate"); 496 497 if (freq == 0) 498 return 0; 499 500 /* Convert clock frequency from kHz to Hz. */ 501 freq = freq * 1000; 502 503 /* Double the clock rate for DDR modes. */ 504 if (timing == SDMMC_TIMING_MMC_DDR52) 505 freq = freq * 2; 506 507 if (freq < (sc->sc_clkin1 / SD_EMMC_CLOCK_DIV_MAX)) { 508 div = (sc->sc_clkin0 + freq - 1) / freq; 509 clock = SD_EMMC_CLOCK_CLK_SRC_24M | div; 510 } else { 511 div = (sc->sc_clkin1 + freq - 1) / freq; 512 clock = SD_EMMC_CLOCK_CLK_SRC_FCLK | div; 513 } 514 if (div > SD_EMMC_CLOCK_DIV_MAX) 515 return EINVAL; 516 517 HSET4(sc, SD_EMMC_CFG, SD_EMMC_CFG_STOP_CLOCK); 518 519 if (timing == SDMMC_TIMING_MMC_DDR52) 520 HSET4(sc, SD_EMMC_CFG, SD_EMMC_CFG_DDR); 521 else 522 HCLR4(sc, SD_EMMC_CFG, SD_EMMC_CFG_DDR); 523 524 clock |= SD_EMMC_CLOCK_CO_PHASE_180; 525 clock |= SD_EMMC_CLOCK_TX_PHASE_0; 526 clock |= SD_EMMC_CLOCK_RX_PHASE_0; 527 HWRITE4(sc, SD_EMMC_CLOCK, clock); 528 529 HCLR4(sc, SD_EMMC_CFG, SD_EMMC_CFG_STOP_CLOCK); 530 531 pinctrl_byname(sc->sc_node, "default"); 532 533 return 0; 534 } 535 536 int 537 amlmmc_bus_width(sdmmc_chipset_handle_t sch, int width) 538 { 539 struct amlmmc_softc *sc = sch; 540 uint32_t cfg; 541 542 cfg = HREAD4(sc, SD_EMMC_CFG); 543 cfg &= ~SD_EMMC_CFG_BUS_WIDTH_MASK; 544 switch (width) { 545 case 1: 546 cfg |= SD_EMMC_CFG_BUS_WIDTH_1; 547 break; 548 case 4: 549 cfg |= SD_EMMC_CFG_BUS_WIDTH_4; 550 break; 551 case 8: 552 cfg |= SD_EMMC_CFG_BUS_WIDTH_8; 553 break; 554 default: 555 return EINVAL; 556 } 557 HWRITE4(sc, SD_EMMC_CFG, cfg); 558 559 return 0; 560 } 561 562 void 563 amlmmc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 564 { 565 struct amlmmc_softc *sc = sch; 566 uint32_t cmd_cfg, status; 567 uint32_t data_addr = 0; 568 int s; 569 570 KASSERT(sc->sc_status == 0); 571 572 /* Setup descriptor flags. */ 573 cmd_cfg = cmd->c_opcode << SD_EMMC_CMD_CFG_CMD_INDEX_SHIFT; 574 if (!ISSET(cmd->c_flags, SCF_RSP_PRESENT)) 575 cmd_cfg |= SD_EMMC_CMD_CFG_NO_RESP; 576 if (ISSET(cmd->c_flags, SCF_RSP_136)) 577 cmd_cfg |= SD_EMMC_CMD_CFG_RESP_128; 578 if (ISSET(cmd->c_flags, SCF_RSP_BSY)) 579 cmd_cfg |= SD_EMMC_CMD_CFG_R1B; 580 if (!ISSET(cmd->c_flags, SCF_RSP_CRC)) 581 cmd_cfg |= SD_EMMC_CMD_CFG_RESP_NOCRC; 582 if (cmd->c_datalen > 0) { 583 cmd_cfg |= SD_EMMC_CMD_CFG_DATA_IO; 584 if (cmd->c_datalen >= cmd->c_blklen) 585 cmd_cfg |= SD_EMMC_CMD_CFG_BLOCK_MODE; 586 if (!ISSET(cmd->c_flags, SCF_CMD_READ)) 587 cmd_cfg |= SD_EMMC_CMD_CFG_DATA_WR; 588 cmd_cfg |= SD_EMMC_CMD_CFG_TIMEOUT_4096; 589 } else { 590 cmd_cfg |= SD_EMMC_CMD_CFG_TIMEOUT_1024; 591 } 592 cmd_cfg |= SD_EMMC_CMD_CFG_OWNER; 593 594 /* If we have multiple DMA segments we need to use descriptors. */ 595 if (cmd->c_datalen > 0 && 596 cmd->c_dmamap && cmd->c_dmamap->dm_nsegs > 1) { 597 struct amlmmc_desc *desc = (struct amlmmc_desc *)sc->sc_desc; 598 int seg; 599 600 for (seg = 0; seg < cmd->c_dmamap->dm_nsegs; seg++) { 601 bus_addr_t addr = cmd->c_dmamap->dm_segs[seg].ds_addr; 602 bus_size_t len = cmd->c_dmamap->dm_segs[seg].ds_len; 603 604 if (seg == cmd->c_dmamap->dm_nsegs - 1) 605 cmd_cfg |= SD_EMMC_CMD_CFG_END_OF_CHAIN; 606 607 KASSERT((addr & 0x7) == 0); 608 desc[seg].cmd_cfg = cmd_cfg | (len / cmd->c_blklen); 609 desc[seg].cmd_arg = cmd->c_arg; 610 desc[seg].data_addr = addr; 611 desc[seg].resp_addr = 0; 612 cmd_cfg |= SD_EMMC_CMD_CFG_NO_CMD; 613 } 614 615 bus_dmamap_sync(sc->sc_dmat, sc->sc_desc_map, 0, 616 cmd->c_dmamap->dm_nsegs * sizeof(struct amlmmc_desc), 617 BUS_DMASYNC_PREWRITE); 618 HWRITE4(sc, SD_EMMC_START, SD_EMMC_START_START | 619 sc->sc_desc_map->dm_segs[0].ds_addr); 620 goto wait; 621 } 622 623 /* Bounce if we don't have a DMA map. */ 624 if (cmd->c_datalen > 0 && !cmd->c_dmamap) { 625 /* Abuse DMA descriptor memory as bounce buffer. */ 626 KASSERT(cmd->c_datalen <= PAGE_SIZE); 627 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 628 bus_dmamap_sync(sc->sc_dmat, sc->sc_desc_map, 0, 629 cmd->c_datalen, BUS_DMASYNC_PREREAD); 630 } else { 631 memcpy(sc->sc_desc, cmd->c_data, cmd->c_datalen); 632 bus_dmamap_sync(sc->sc_dmat, sc->sc_desc_map, 0, 633 cmd->c_datalen, BUS_DMASYNC_PREWRITE); 634 } 635 } 636 637 if (cmd->c_datalen > 0) { 638 if (cmd->c_datalen >= cmd->c_blklen) { 639 amlmmc_set_blklen(sc, cmd->c_blklen); 640 cmd_cfg |= cmd->c_datalen / cmd->c_blklen; 641 } else { 642 cmd_cfg |= cmd->c_datalen; 643 } 644 645 if (cmd->c_dmamap) 646 data_addr = cmd->c_dmamap->dm_segs[0].ds_addr; 647 else 648 data_addr = sc->sc_desc_map->dm_segs[0].ds_addr; 649 } 650 651 cmd_cfg |= SD_EMMC_CMD_CFG_END_OF_CHAIN; 652 653 KASSERT((data_addr & 0x7) == 0); 654 HWRITE4(sc, SD_EMMC_CMD_CFG, cmd_cfg); 655 HWRITE4(sc, SD_EMMC_CMD_DAT, data_addr); 656 HWRITE4(sc, SD_EMMC_CMD_RSP, 0); 657 bus_space_barrier(sc->sc_iot, sc->sc_ioh, SD_EMMC_CMD_CFG, 658 SD_EMMC_CMD_RSP1 - SD_EMMC_CMD_CFG, BUS_SPACE_BARRIER_WRITE); 659 HWRITE4(sc, SD_EMMC_CMD_ARG, cmd->c_arg); 660 661 wait: 662 s = splbio(); 663 while (sc->sc_status == 0) { 664 if (tsleep_nsec(sc, PWAIT, "amlmmc", 10000000000)) 665 break; 666 } 667 status = sc->sc_status; 668 sc->sc_status = 0; 669 splx(s); 670 671 if (!ISSET(status, SD_EMMC_STATUS_END_OF_CHAIN)) 672 cmd->c_error = ETIMEDOUT; 673 else if (ISSET(status, SD_EMMC_STATUS_DESC_TIMEOUT)) 674 cmd->c_error = ETIMEDOUT; 675 else if (ISSET(status, SD_EMMC_STATUS_RESP_TIMEOUT)) 676 cmd->c_error = ETIMEDOUT; 677 else if (ISSET(status, SD_EMMC_STATUS_ERR_MASK)) 678 cmd->c_error = EIO; 679 680 if (ISSET(cmd->c_flags, SCF_RSP_PRESENT)) { 681 if (ISSET(cmd->c_flags, SCF_RSP_136)) { 682 cmd->c_resp[0] = HREAD4(sc, SD_EMMC_CMD_RSP); 683 cmd->c_resp[1] = HREAD4(sc, SD_EMMC_CMD_RSP1); 684 cmd->c_resp[2] = HREAD4(sc, SD_EMMC_CMD_RSP2); 685 cmd->c_resp[3] = HREAD4(sc, SD_EMMC_CMD_RSP3); 686 if (ISSET(cmd->c_flags, SCF_RSP_CRC)) { 687 cmd->c_resp[0] = (cmd->c_resp[0] >> 8) | 688 (cmd->c_resp[1] << 24); 689 cmd->c_resp[1] = (cmd->c_resp[1] >> 8) | 690 (cmd->c_resp[2] << 24); 691 cmd->c_resp[2] = (cmd->c_resp[2] >> 8) | 692 (cmd->c_resp[3] << 24); 693 cmd->c_resp[3] = (cmd->c_resp[3] >> 8); 694 } 695 } else { 696 cmd->c_resp[0] = HREAD4(sc, SD_EMMC_CMD_RSP); 697 } 698 } 699 700 /* Unbounce if we don't have a DMA map. */ 701 if (cmd->c_datalen > 0 && !cmd->c_dmamap) { 702 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 703 bus_dmamap_sync(sc->sc_dmat, sc->sc_desc_map, 0, 704 cmd->c_datalen, BUS_DMASYNC_POSTREAD); 705 memcpy(cmd->c_data, sc->sc_desc, cmd->c_datalen); 706 } else { 707 bus_dmamap_sync(sc->sc_dmat, sc->sc_desc_map, 0, 708 cmd->c_datalen, BUS_DMASYNC_POSTWRITE); 709 } 710 } 711 712 /* Cleanup descriptors. */ 713 if (cmd->c_datalen > 0 && 714 cmd->c_dmamap && cmd->c_dmamap->dm_nsegs > 1) { 715 HWRITE4(sc, SD_EMMC_START, SD_EMMC_START_STOP); 716 bus_dmamap_sync(sc->sc_dmat, sc->sc_desc_map, 0, 717 cmd->c_dmamap->dm_nsegs * sizeof(struct amlmmc_desc), 718 BUS_DMASYNC_POSTWRITE); 719 } 720 721 SET(cmd->c_flags, SCF_ITSDONE); 722 } 723 724 int 725 amlmmc_signal_voltage(sdmmc_chipset_handle_t sch, int signal_voltage) 726 { 727 /* XXX Check/set signaling voltage. */ 728 return 0; 729 } 730