1 /* $OpenBSD: amlmmc.c,v 1.9 2020/08/24 15:15:08 kettenis Exp $ */ 2 /* 3 * Copyright (c) 2019 Mark Kettenis <kettenis@openbsd.org> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #include <sys/param.h> 19 #include <sys/systm.h> 20 #include <sys/device.h> 21 #include <sys/malloc.h> 22 23 #include <machine/intr.h> 24 #include <machine/bus.h> 25 #include <machine/fdt.h> 26 27 #include <dev/ofw/openfirm.h> 28 #include <dev/ofw/ofw_clock.h> 29 #include <dev/ofw/ofw_gpio.h> 30 #include <dev/ofw/ofw_pinctrl.h> 31 #include <dev/ofw/ofw_regulator.h> 32 #include <dev/ofw/fdt.h> 33 34 #include <dev/sdmmc/sdmmcvar.h> 35 36 #define SD_EMMC_CLOCK 0x0000 37 #define SD_EMMC_CLOCK_ALWAYS_ON (1 << 28) 38 #define SD_EMMC_CLOCK_RX_PHASE_0 (0 << 12) 39 #define SD_EMMC_CLOCK_RX_PHASE_90 (1 << 12) 40 #define SD_EMMC_CLOCK_RX_PHASE_180 (2 << 12) 41 #define SD_EMMC_CLOCK_RX_PHASE_270 (3 << 12) 42 #define SD_EMMC_CLOCK_TX_PHASE_0 (0 << 10) 43 #define SD_EMMC_CLOCK_TX_PHASE_90 (1 << 10) 44 #define SD_EMMC_CLOCK_TX_PHASE_180 (2 << 10) 45 #define SD_EMMC_CLOCK_TX_PHASE_270 (3 << 10) 46 #define SD_EMMC_CLOCK_CO_PHASE_0 (0 << 8) 47 #define SD_EMMC_CLOCK_CO_PHASE_90 (1 << 8) 48 #define SD_EMMC_CLOCK_CO_PHASE_180 (2 << 8) 49 #define SD_EMMC_CLOCK_CO_PHASE_270 (3 << 8) 50 #define SD_EMMC_CLOCK_CLK_SRC_24M (0 << 6) 51 #define SD_EMMC_CLOCK_CLK_SRC_FCLK (1 << 6) 52 #define SD_EMMC_CLOCK_DIV_MAX 63 53 #define SD_EMMC_DELAY1 0x0004 54 #define SD_EMMC_DELAY2 0x0008 55 #define SD_EMMC_ADJUST 0x000c 56 #define SD_EMMC_ADJUST_ADJ_FIXED (1 << 13) 57 #define SD_EMMC_ADJUST_ADJ_DELAY_MASK (0x3f << 16) 58 #define SD_EMMC_ADJUST_ADJ_DELAY_SHIFT 16 59 #define SD_EMMC_START 0x0040 60 #define SD_EMMC_START_START (1 << 1) 61 #define SD_EMMC_START_STOP (0 << 1) 62 #define SD_EMMC_CFG 0x0044 63 #define SD_EMMC_CFG_ERR_ABORT (1 << 27) 64 #define SD_EMMC_CFG_AUTO_CLK (1 << 23) 65 #define SD_EMMC_CFG_STOP_CLOCK (1 << 22) 66 #define SD_EMMC_CFG_SDCLK_ALWAYS_ON (1 << 18) 67 #define SD_EMMC_CFG_RC_CC_MASK (0xf << 12) 68 #define SD_EMMC_CFG_RC_CC_16 (0x4 << 12) 69 #define SD_EMMC_CFG_RESP_TIMEOUT_MASK (0xf << 8) 70 #define SD_EMMC_CFG_RESP_TIMEOUT_256 (0x8 << 8) 71 #define SD_EMMC_CFG_BL_LEN_MASK (0xf << 4) 72 #define SD_EMMC_CFG_BL_LEN_SHIFT 4 73 #define SD_EMMC_CFG_BL_LEN_512 (0x9 << 4) 74 #define SD_EMMC_CFG_DDR (1 << 2) 75 #define SD_EMMC_CFG_BUS_WIDTH_MASK (0x3 << 0) 76 #define SD_EMMC_CFG_BUS_WIDTH_1 (0x0 << 0) 77 #define SD_EMMC_CFG_BUS_WIDTH_4 (0x1 << 0) 78 #define SD_EMMC_CFG_BUS_WIDTH_8 (0x2 << 0) 79 #define SD_EMMC_STATUS 0x0048 80 #define SD_EMMC_STATUS_END_OF_CHAIN (1 << 13) 81 #define SD_EMMC_STATUS_DESC_TIMEOUT (1 << 12) 82 #define SD_EMMC_STATUS_RESP_TIMEOUT (1 << 11) 83 #define SD_EMMC_STATUS_MASK 0x00003fff 84 #define SD_EMMC_STATUS_ERR_MASK 0x000007ff 85 #define SD_EMMC_IRQ_EN 0x004c 86 #define SD_EMMC_IRQ_EN_MASK SD_EMMC_STATUS_MASK 87 #define SD_EMMC_CMD_CFG 0x0050 88 #define SD_EMMC_CMD_CFG_BLOCK_MODE (1 << 9) 89 #define SD_EMMC_CMD_CFG_R1B (1 << 10) 90 #define SD_EMMC_CMD_CFG_END_OF_CHAIN (1 << 11) 91 #define SD_EMMC_CMD_CFG_TIMEOUT_1024 (10 << 12) 92 #define SD_EMMC_CMD_CFG_TIMEOUT_4096 (12 << 12) 93 #define SD_EMMC_CMD_CFG_NO_RESP (1 << 16) 94 #define SD_EMMC_CMD_CFG_NO_CMD (1 << 17) 95 #define SD_EMMC_CMD_CFG_DATA_IO (1 << 18) 96 #define SD_EMMC_CMD_CFG_DATA_WR (1 << 19) 97 #define SD_EMMC_CMD_CFG_RESP_NOCRC (1 << 20) 98 #define SD_EMMC_CMD_CFG_RESP_128 (1 << 21) 99 #define SD_EMMC_CMD_CFG_CMD_INDEX_SHIFT 24 100 #define SD_EMMC_CMD_CFG_OWNER (1U << 31) 101 #define SD_EMMC_CMD_ARG 0x0054 102 #define SD_EMMC_CMD_DAT 0x0058 103 #define SD_EMMC_CMD_RSP 0x005c 104 #define SD_EMMC_CMD_RSP1 0x0060 105 #define SD_EMMC_CMD_RSP2 0x0064 106 #define SD_EMMC_CMD_RSP3 0x0068 107 108 #define HREAD4(sc, reg) \ 109 (bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg))) 110 #define HWRITE4(sc, reg, val) \ 111 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 112 #define HSET4(sc, reg, bits) \ 113 HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits)) 114 #define HCLR4(sc, reg, bits) \ 115 HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits)) 116 117 struct amlmmc_desc { 118 uint32_t cmd_cfg; 119 uint32_t cmd_arg; 120 uint32_t data_addr; 121 uint32_t resp_addr; 122 }; 123 124 #define AMLMMC_NDESC (PAGE_SIZE / sizeof(struct amlmmc_desc)) 125 #define AMLMMC_MAXSEGSZ 0x20000 126 127 struct amlmmc_softc { 128 struct device sc_dev; 129 bus_space_tag_t sc_iot; 130 bus_space_handle_t sc_ioh; 131 bus_dma_tag_t sc_dmat; 132 bus_dmamap_t sc_dmap; 133 134 void *sc_ih; 135 uint32_t sc_status; 136 137 bus_dmamap_t sc_desc_map; 138 bus_dma_segment_t sc_desc_segs[1]; 139 int sc_desc_nsegs; 140 caddr_t sc_desc; 141 142 int sc_node; 143 uint32_t sc_clkin0; 144 uint32_t sc_clkin1; 145 uint32_t sc_gpio[4]; 146 uint32_t sc_vmmc; 147 uint32_t sc_vqmmc; 148 uint32_t sc_pwrseq; 149 uint32_t sc_vdd; 150 uint32_t sc_ocr; 151 152 int sc_blklen; 153 struct device *sc_sdmmc; 154 }; 155 156 int amlmmc_match(struct device *, void *, void *); 157 void amlmmc_attach(struct device *, struct device *, void *); 158 159 struct cfattach amlmmc_ca = { 160 sizeof (struct amlmmc_softc), amlmmc_match, amlmmc_attach 161 }; 162 163 struct cfdriver amlmmc_cd = { 164 NULL, "amlmmc", DV_DULL 165 }; 166 167 int amlmmc_alloc_descriptors(struct amlmmc_softc *); 168 void amlmmc_free_descriptors(struct amlmmc_softc *); 169 int amlmmc_intr(void *); 170 171 void amlmmc_pwrseq_reset(uint32_t); 172 173 int amlmmc_host_reset(sdmmc_chipset_handle_t); 174 uint32_t amlmmc_host_ocr(sdmmc_chipset_handle_t); 175 int amlmmc_host_maxblklen(sdmmc_chipset_handle_t); 176 int amlmmc_card_detect(sdmmc_chipset_handle_t); 177 int amlmmc_bus_power(sdmmc_chipset_handle_t, uint32_t); 178 int amlmmc_bus_clock(sdmmc_chipset_handle_t, int, int); 179 int amlmmc_bus_width(sdmmc_chipset_handle_t, int); 180 void amlmmc_exec_command(sdmmc_chipset_handle_t, struct sdmmc_command *); 181 int amlmmc_signal_voltage(sdmmc_chipset_handle_t, int); 182 int amlmmc_execute_tuning(sdmmc_chipset_handle_t, int); 183 184 struct sdmmc_chip_functions amlmmc_chip_functions = { 185 .host_reset = amlmmc_host_reset, 186 .host_ocr = amlmmc_host_ocr, 187 .host_maxblklen = amlmmc_host_maxblklen, 188 .card_detect = amlmmc_card_detect, 189 .bus_power = amlmmc_bus_power, 190 .bus_clock = amlmmc_bus_clock, 191 .bus_width = amlmmc_bus_width, 192 .exec_command = amlmmc_exec_command, 193 .signal_voltage = amlmmc_signal_voltage, 194 .execute_tuning = amlmmc_execute_tuning, 195 }; 196 197 int 198 amlmmc_match(struct device *parent, void *match, void *aux) 199 { 200 struct fdt_attach_args *faa = aux; 201 202 return OF_is_compatible(faa->fa_node, "amlogic,meson-axg-mmc"); 203 } 204 205 void 206 amlmmc_attach(struct device *parent, struct device *self, void *aux) 207 { 208 struct amlmmc_softc *sc = (struct amlmmc_softc *)self; 209 struct fdt_attach_args *faa = aux; 210 struct sdmmcbus_attach_args saa; 211 uint32_t cfg, width; 212 int error; 213 214 if (faa->fa_nreg < 1) { 215 printf(": no registers\n"); 216 return; 217 } 218 219 sc->sc_iot = faa->fa_iot; 220 if (bus_space_map(sc->sc_iot, faa->fa_reg[0].addr, 221 faa->fa_reg[0].size, 0, &sc->sc_ioh)) { 222 printf(": can't map registers\n"); 223 return; 224 } 225 226 sc->sc_dmat = faa->fa_dmat; 227 error = amlmmc_alloc_descriptors(sc); 228 if (error) { 229 printf(": can't allocate desctiptors\n"); 230 goto unmap; 231 } 232 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, AMLMMC_NDESC, 233 AMLMMC_MAXSEGSZ, 0, BUS_DMA_WAITOK|BUS_DMA_ALLOCNOW, &sc->sc_dmap); 234 if (error) { 235 printf(": can't create DMA map\n"); 236 goto free; 237 } 238 239 sc->sc_ih = fdt_intr_establish(faa->fa_node, IPL_BIO, 240 amlmmc_intr, sc, sc->sc_dev.dv_xname); 241 if (sc->sc_ih == NULL) { 242 printf(": can't establish interrupt\n"); 243 goto destroy; 244 } 245 246 sc->sc_node = faa->fa_node; 247 printf("\n"); 248 249 pinctrl_byname(faa->fa_node, "default"); 250 251 clock_enable_all(faa->fa_node); 252 reset_deassert_all(faa->fa_node); 253 254 sc->sc_clkin0 = clock_get_frequency(faa->fa_node, "clkin0"); 255 sc->sc_clkin1 = clock_get_frequency(faa->fa_node, "clkin1"); 256 257 OF_getpropintarray(faa->fa_node, "cd-gpios", sc->sc_gpio, 258 sizeof(sc->sc_gpio)); 259 if (sc->sc_gpio[0]) 260 gpio_controller_config_pin(sc->sc_gpio, GPIO_CONFIG_INPUT); 261 262 sc->sc_vmmc = OF_getpropint(sc->sc_node, "vmmc-supply", 0); 263 sc->sc_vqmmc = OF_getpropint(sc->sc_node, "vqmmc-supply", 0); 264 sc->sc_pwrseq = OF_getpropint(sc->sc_node, "mmc-pwrseq", 0); 265 266 /* XXX Pretend we only support 3.3V for now. */ 267 sc->sc_ocr = MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V; 268 269 /* Initialize timings and block size. */ 270 cfg = SD_EMMC_CFG_ERR_ABORT; 271 cfg |= SD_EMMC_CFG_RC_CC_16; 272 cfg |= SD_EMMC_CFG_RESP_TIMEOUT_256; 273 cfg |= SD_EMMC_CFG_BL_LEN_512; 274 HWRITE4(sc, SD_EMMC_CFG, cfg); 275 276 /* Clear status bits & enable interrupts. */ 277 HWRITE4(sc, SD_EMMC_STATUS, SD_EMMC_STATUS_MASK); 278 HWRITE4(sc, SD_EMMC_IRQ_EN, SD_EMMC_IRQ_EN_MASK); 279 280 /* Reset eMMC. */ 281 if (sc->sc_pwrseq) 282 amlmmc_pwrseq_reset(sc->sc_pwrseq); 283 284 memset(&saa, 0, sizeof(saa)); 285 saa.saa_busname = "sdmmc"; 286 saa.sct = &amlmmc_chip_functions; 287 saa.sch = sc; 288 saa.dmat = sc->sc_dmat; 289 saa.dmap = sc->sc_dmap; 290 saa.caps = SMC_CAPS_DMA; 291 saa.flags = SMF_STOP_AFTER_MULTIPLE; 292 293 if (OF_getproplen(sc->sc_node, "cap-mmc-highspeed") == 0) 294 saa.caps |= SMC_CAPS_MMC_HIGHSPEED; 295 if (OF_getproplen(sc->sc_node, "cap-sd-highspeed") == 0) 296 saa.caps |= SMC_CAPS_SD_HIGHSPEED; 297 if (OF_getproplen(sc->sc_node, "mmc-ddr-1_8v") == 0) 298 saa.caps |= SMC_CAPS_MMC_DDR52; 299 if (OF_getproplen(sc->sc_node, "mmc-hs200-1_8v") == 0) 300 saa.caps |= SMC_CAPS_MMC_HS200; 301 if (OF_getproplen(sc->sc_node, "sd-uhs-sdr50") == 0) 302 saa.caps |= SMC_CAPS_UHS_SDR50; 303 #ifdef notyet 304 if (OF_getproplen(sc->sc_node, "sd-uhs-sdr104") == 0) 305 saa.caps |= SMC_CAPS_UHS_SDR104; 306 #endif 307 308 if (saa.caps & SMC_CAPS_UHS_MASK) 309 sc->sc_ocr |= MMC_OCR_S18A; 310 311 width = OF_getpropint(faa->fa_node, "bus-width", 1); 312 if (width >= 8) 313 saa.caps |= SMC_CAPS_8BIT_MODE; 314 if (width >= 4) 315 saa.caps |= SMC_CAPS_4BIT_MODE; 316 317 sc->sc_sdmmc = config_found(self, &saa, NULL); 318 return; 319 320 destroy: 321 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmap); 322 free: 323 amlmmc_free_descriptors(sc); 324 unmap: 325 bus_space_unmap(sc->sc_iot, sc->sc_ioh, faa->fa_reg[0].size); 326 } 327 328 int 329 amlmmc_alloc_descriptors(struct amlmmc_softc *sc) 330 { 331 int error, rseg; 332 333 /* Allocate descriptor memory */ 334 error = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, PAGE_SIZE, 335 PAGE_SIZE, sc->sc_desc_segs, 1, &rseg, 336 BUS_DMA_WAITOK | BUS_DMA_ZERO); 337 if (error) 338 return error; 339 error = bus_dmamem_map(sc->sc_dmat, sc->sc_desc_segs, rseg, 340 PAGE_SIZE, &sc->sc_desc, BUS_DMA_WAITOK | BUS_DMA_COHERENT); 341 if (error) { 342 bus_dmamem_free(sc->sc_dmat, sc->sc_desc_segs, rseg); 343 return error; 344 } 345 error = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, 1, PAGE_SIZE, 346 0, BUS_DMA_WAITOK, &sc->sc_desc_map); 347 if (error) { 348 bus_dmamem_unmap(sc->sc_dmat, sc->sc_desc, PAGE_SIZE); 349 bus_dmamem_free(sc->sc_dmat, sc->sc_desc_segs, rseg); 350 return error; 351 } 352 error = bus_dmamap_load(sc->sc_dmat, sc->sc_desc_map, 353 sc->sc_desc, PAGE_SIZE, NULL, BUS_DMA_WAITOK | BUS_DMA_WRITE); 354 if (error) { 355 bus_dmamap_destroy(sc->sc_dmat, sc->sc_desc_map); 356 bus_dmamem_unmap(sc->sc_dmat, sc->sc_desc, PAGE_SIZE); 357 bus_dmamem_free(sc->sc_dmat, sc->sc_desc_segs, rseg); 358 return error; 359 } 360 361 sc->sc_desc_nsegs = rseg; 362 return 0; 363 } 364 365 void 366 amlmmc_free_descriptors(struct amlmmc_softc *sc) 367 { 368 bus_dmamap_unload(sc->sc_dmat, sc->sc_desc_map); 369 bus_dmamap_destroy(sc->sc_dmat, sc->sc_desc_map); 370 bus_dmamem_unmap(sc->sc_dmat, sc->sc_desc, PAGE_SIZE); 371 bus_dmamem_free(sc->sc_dmat, sc->sc_desc_segs, sc->sc_desc_nsegs); 372 } 373 374 int 375 amlmmc_intr(void *arg) 376 { 377 struct amlmmc_softc *sc = arg; 378 uint32_t status; 379 380 status = HREAD4(sc, SD_EMMC_STATUS); 381 if ((status & SD_EMMC_STATUS_MASK) == 0) 382 return 0; 383 384 HWRITE4(sc, SD_EMMC_STATUS, status); 385 sc->sc_status = status & SD_EMMC_STATUS_MASK; 386 wakeup(sc); 387 return 1; 388 } 389 390 void 391 amlmmc_set_blklen(struct amlmmc_softc *sc, int blklen) 392 { 393 uint32_t cfg; 394 395 if (blklen == sc->sc_blklen) 396 return; 397 398 cfg = HREAD4(sc, SD_EMMC_CFG); 399 cfg &= ~SD_EMMC_CFG_BL_LEN_MASK; 400 cfg |= (fls(blklen) - 1) << SD_EMMC_CFG_BL_LEN_SHIFT; 401 HWRITE4(sc, SD_EMMC_CFG, cfg); 402 sc->sc_blklen = blklen; 403 } 404 405 void 406 amlmmc_pwrseq_reset(uint32_t phandle) 407 { 408 uint32_t *gpios, *gpio; 409 int node; 410 int len; 411 412 node = OF_getnodebyphandle(phandle); 413 if (node == 0) 414 return; 415 416 if (!OF_is_compatible(node, "mmc-pwrseq-emmc")) 417 return; 418 419 len = OF_getproplen(node, "reset-gpios"); 420 if (len <= 0) 421 return; 422 423 gpios = malloc(len, M_TEMP, M_WAITOK); 424 OF_getpropintarray(node, "reset-gpios", gpios, len); 425 426 gpio = gpios; 427 while (gpio && gpio < gpios + (len / sizeof(uint32_t))) { 428 gpio_controller_config_pin(gpio, GPIO_CONFIG_OUTPUT); 429 gpio_controller_set_pin(gpio, 1); 430 delay(1); 431 gpio_controller_set_pin(gpio, 0); 432 delay(200); 433 gpio = gpio_controller_next_pin(gpio); 434 } 435 436 free(gpios, M_TEMP, len); 437 } 438 439 int 440 amlmmc_host_reset(sdmmc_chipset_handle_t sch) 441 { 442 printf("%s\n", __func__); 443 return 0; 444 } 445 446 uint32_t 447 amlmmc_host_ocr(sdmmc_chipset_handle_t sch) 448 { 449 struct amlmmc_softc *sc = sch; 450 return sc->sc_ocr; 451 } 452 453 int 454 amlmmc_host_maxblklen(sdmmc_chipset_handle_t sch) 455 { 456 return 512; 457 } 458 459 int 460 amlmmc_card_detect(sdmmc_chipset_handle_t sch) 461 { 462 struct amlmmc_softc *sc = sch; 463 464 if (OF_getproplen(sc->sc_node, "non-removable") == 0) 465 return 1; 466 467 if (sc->sc_gpio[0]) { 468 int inverted, val; 469 470 val = gpio_controller_get_pin(sc->sc_gpio); 471 472 inverted = (OF_getproplen(sc->sc_node, "cd-inverted") == 0); 473 return inverted ? !val : val; 474 } 475 476 return 1; 477 } 478 479 int 480 amlmmc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 481 { 482 struct amlmmc_softc *sc = sch; 483 uint32_t vdd = 0; 484 485 if (ISSET(ocr, MMC_OCR_3_2V_3_3V|MMC_OCR_3_3V_3_4V)) 486 vdd = 3300000; 487 488 /* enable mmc power */ 489 if (sc->sc_vmmc && vdd > 0) 490 regulator_enable(sc->sc_vmmc); 491 492 if (sc->sc_vqmmc && vdd > 0) 493 regulator_enable(sc->sc_vqmmc); 494 495 delay(10000); 496 497 sc->sc_vdd = vdd; 498 return 0; 499 } 500 501 int 502 amlmmc_bus_clock(sdmmc_chipset_handle_t sch, int freq, int timing) 503 { 504 struct amlmmc_softc *sc = sch; 505 uint32_t div, clock; 506 507 /* XXX The ODROID-N2 eMMC doesn't work properly above 150 MHz. */ 508 if (freq > 150000) 509 freq = 150000; 510 511 pinctrl_byname(sc->sc_node, "clk-gate"); 512 513 if (freq == 0) 514 return 0; 515 516 /* Convert clock frequency from kHz to Hz. */ 517 freq = freq * 1000; 518 519 /* Double the clock rate for DDR modes. */ 520 if (timing == SDMMC_TIMING_MMC_DDR52) 521 freq = freq * 2; 522 523 if (freq < (sc->sc_clkin1 / SD_EMMC_CLOCK_DIV_MAX)) { 524 div = (sc->sc_clkin0 + freq - 1) / freq; 525 clock = SD_EMMC_CLOCK_CLK_SRC_24M | div; 526 } else { 527 div = (sc->sc_clkin1 + freq - 1) / freq; 528 clock = SD_EMMC_CLOCK_CLK_SRC_FCLK | div; 529 } 530 if (div > SD_EMMC_CLOCK_DIV_MAX) 531 return EINVAL; 532 533 HSET4(sc, SD_EMMC_CFG, SD_EMMC_CFG_STOP_CLOCK); 534 535 if (timing == SDMMC_TIMING_MMC_DDR52) 536 HSET4(sc, SD_EMMC_CFG, SD_EMMC_CFG_DDR); 537 else 538 HCLR4(sc, SD_EMMC_CFG, SD_EMMC_CFG_DDR); 539 540 clock |= SD_EMMC_CLOCK_ALWAYS_ON; 541 clock |= SD_EMMC_CLOCK_CO_PHASE_180; 542 clock |= SD_EMMC_CLOCK_TX_PHASE_0; 543 clock |= SD_EMMC_CLOCK_RX_PHASE_0; 544 HWRITE4(sc, SD_EMMC_CLOCK, clock); 545 546 HCLR4(sc, SD_EMMC_CFG, SD_EMMC_CFG_STOP_CLOCK); 547 548 pinctrl_byname(sc->sc_node, "default"); 549 550 return 0; 551 } 552 553 int 554 amlmmc_bus_width(sdmmc_chipset_handle_t sch, int width) 555 { 556 struct amlmmc_softc *sc = sch; 557 uint32_t cfg; 558 559 cfg = HREAD4(sc, SD_EMMC_CFG); 560 cfg &= ~SD_EMMC_CFG_BUS_WIDTH_MASK; 561 switch (width) { 562 case 1: 563 cfg |= SD_EMMC_CFG_BUS_WIDTH_1; 564 break; 565 case 4: 566 cfg |= SD_EMMC_CFG_BUS_WIDTH_4; 567 break; 568 case 8: 569 cfg |= SD_EMMC_CFG_BUS_WIDTH_8; 570 break; 571 default: 572 return EINVAL; 573 } 574 HWRITE4(sc, SD_EMMC_CFG, cfg); 575 576 return 0; 577 } 578 579 void 580 amlmmc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 581 { 582 struct amlmmc_softc *sc = sch; 583 uint32_t cmd_cfg, status; 584 uint32_t data_addr = 0; 585 int s; 586 587 KASSERT(sc->sc_status == 0); 588 589 /* Setup descriptor flags. */ 590 cmd_cfg = cmd->c_opcode << SD_EMMC_CMD_CFG_CMD_INDEX_SHIFT; 591 if (!ISSET(cmd->c_flags, SCF_RSP_PRESENT)) 592 cmd_cfg |= SD_EMMC_CMD_CFG_NO_RESP; 593 if (ISSET(cmd->c_flags, SCF_RSP_136)) 594 cmd_cfg |= SD_EMMC_CMD_CFG_RESP_128; 595 if (ISSET(cmd->c_flags, SCF_RSP_BSY)) 596 cmd_cfg |= SD_EMMC_CMD_CFG_R1B; 597 if (!ISSET(cmd->c_flags, SCF_RSP_CRC)) 598 cmd_cfg |= SD_EMMC_CMD_CFG_RESP_NOCRC; 599 if (cmd->c_datalen > 0) { 600 cmd_cfg |= SD_EMMC_CMD_CFG_DATA_IO; 601 if (cmd->c_datalen >= cmd->c_blklen) 602 cmd_cfg |= SD_EMMC_CMD_CFG_BLOCK_MODE; 603 if (!ISSET(cmd->c_flags, SCF_CMD_READ)) 604 cmd_cfg |= SD_EMMC_CMD_CFG_DATA_WR; 605 cmd_cfg |= SD_EMMC_CMD_CFG_TIMEOUT_4096; 606 } else { 607 cmd_cfg |= SD_EMMC_CMD_CFG_TIMEOUT_1024; 608 } 609 cmd_cfg |= SD_EMMC_CMD_CFG_OWNER; 610 611 /* If we have multiple DMA segments we need to use descriptors. */ 612 if (cmd->c_datalen > 0 && 613 cmd->c_dmamap && cmd->c_dmamap->dm_nsegs > 1) { 614 struct amlmmc_desc *desc = (struct amlmmc_desc *)sc->sc_desc; 615 int seg; 616 617 for (seg = 0; seg < cmd->c_dmamap->dm_nsegs; seg++) { 618 bus_addr_t addr = cmd->c_dmamap->dm_segs[seg].ds_addr; 619 bus_size_t len = cmd->c_dmamap->dm_segs[seg].ds_len; 620 621 if (seg == cmd->c_dmamap->dm_nsegs - 1) 622 cmd_cfg |= SD_EMMC_CMD_CFG_END_OF_CHAIN; 623 624 KASSERT((addr & 0x7) == 0); 625 desc[seg].cmd_cfg = cmd_cfg | (len / cmd->c_blklen); 626 desc[seg].cmd_arg = cmd->c_arg; 627 desc[seg].data_addr = addr; 628 desc[seg].resp_addr = 0; 629 cmd_cfg |= SD_EMMC_CMD_CFG_NO_CMD; 630 } 631 632 bus_dmamap_sync(sc->sc_dmat, sc->sc_desc_map, 0, 633 cmd->c_dmamap->dm_nsegs * sizeof(struct amlmmc_desc), 634 BUS_DMASYNC_PREWRITE); 635 HWRITE4(sc, SD_EMMC_START, SD_EMMC_START_START | 636 sc->sc_desc_map->dm_segs[0].ds_addr); 637 goto wait; 638 } 639 640 /* Bounce if we don't have a DMA map. */ 641 if (cmd->c_datalen > 0 && !cmd->c_dmamap) { 642 /* Abuse DMA descriptor memory as bounce buffer. */ 643 KASSERT(cmd->c_datalen <= PAGE_SIZE); 644 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 645 bus_dmamap_sync(sc->sc_dmat, sc->sc_desc_map, 0, 646 cmd->c_datalen, BUS_DMASYNC_PREREAD); 647 } else { 648 memcpy(sc->sc_desc, cmd->c_data, cmd->c_datalen); 649 bus_dmamap_sync(sc->sc_dmat, sc->sc_desc_map, 0, 650 cmd->c_datalen, BUS_DMASYNC_PREWRITE); 651 } 652 } 653 654 if (cmd->c_datalen > 0) { 655 if (cmd->c_datalen >= cmd->c_blklen) { 656 amlmmc_set_blklen(sc, cmd->c_blklen); 657 cmd_cfg |= cmd->c_datalen / cmd->c_blklen; 658 } else { 659 cmd_cfg |= cmd->c_datalen; 660 } 661 662 if (cmd->c_dmamap) 663 data_addr = cmd->c_dmamap->dm_segs[0].ds_addr; 664 else 665 data_addr = sc->sc_desc_map->dm_segs[0].ds_addr; 666 } 667 668 cmd_cfg |= SD_EMMC_CMD_CFG_END_OF_CHAIN; 669 670 KASSERT((data_addr & 0x7) == 0); 671 HWRITE4(sc, SD_EMMC_CMD_CFG, cmd_cfg); 672 HWRITE4(sc, SD_EMMC_CMD_DAT, data_addr); 673 HWRITE4(sc, SD_EMMC_CMD_RSP, 0); 674 bus_space_barrier(sc->sc_iot, sc->sc_ioh, SD_EMMC_CMD_CFG, 675 SD_EMMC_CMD_RSP1 - SD_EMMC_CMD_CFG, BUS_SPACE_BARRIER_WRITE); 676 HWRITE4(sc, SD_EMMC_CMD_ARG, cmd->c_arg); 677 678 wait: 679 s = splbio(); 680 while (sc->sc_status == 0) { 681 if (tsleep_nsec(sc, PWAIT, "amlmmc", 10000000000)) 682 break; 683 } 684 status = sc->sc_status; 685 sc->sc_status = 0; 686 splx(s); 687 688 if (!ISSET(status, SD_EMMC_STATUS_END_OF_CHAIN)) 689 cmd->c_error = ETIMEDOUT; 690 else if (ISSET(status, SD_EMMC_STATUS_DESC_TIMEOUT)) 691 cmd->c_error = ETIMEDOUT; 692 else if (ISSET(status, SD_EMMC_STATUS_RESP_TIMEOUT)) 693 cmd->c_error = ETIMEDOUT; 694 else if (ISSET(status, SD_EMMC_STATUS_ERR_MASK)) 695 cmd->c_error = EIO; 696 697 if (ISSET(cmd->c_flags, SCF_RSP_PRESENT)) { 698 if (ISSET(cmd->c_flags, SCF_RSP_136)) { 699 cmd->c_resp[0] = HREAD4(sc, SD_EMMC_CMD_RSP); 700 cmd->c_resp[1] = HREAD4(sc, SD_EMMC_CMD_RSP1); 701 cmd->c_resp[2] = HREAD4(sc, SD_EMMC_CMD_RSP2); 702 cmd->c_resp[3] = HREAD4(sc, SD_EMMC_CMD_RSP3); 703 if (ISSET(cmd->c_flags, SCF_RSP_CRC)) { 704 cmd->c_resp[0] = (cmd->c_resp[0] >> 8) | 705 (cmd->c_resp[1] << 24); 706 cmd->c_resp[1] = (cmd->c_resp[1] >> 8) | 707 (cmd->c_resp[2] << 24); 708 cmd->c_resp[2] = (cmd->c_resp[2] >> 8) | 709 (cmd->c_resp[3] << 24); 710 cmd->c_resp[3] = (cmd->c_resp[3] >> 8); 711 } 712 } else { 713 cmd->c_resp[0] = HREAD4(sc, SD_EMMC_CMD_RSP); 714 } 715 } 716 717 /* Unbounce if we don't have a DMA map. */ 718 if (cmd->c_datalen > 0 && !cmd->c_dmamap) { 719 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 720 bus_dmamap_sync(sc->sc_dmat, sc->sc_desc_map, 0, 721 cmd->c_datalen, BUS_DMASYNC_POSTREAD); 722 memcpy(cmd->c_data, sc->sc_desc, cmd->c_datalen); 723 } else { 724 bus_dmamap_sync(sc->sc_dmat, sc->sc_desc_map, 0, 725 cmd->c_datalen, BUS_DMASYNC_POSTWRITE); 726 } 727 } 728 729 /* Cleanup descriptors. */ 730 if (cmd->c_datalen > 0 && 731 cmd->c_dmamap && cmd->c_dmamap->dm_nsegs > 1) { 732 HWRITE4(sc, SD_EMMC_START, SD_EMMC_START_STOP); 733 bus_dmamap_sync(sc->sc_dmat, sc->sc_desc_map, 0, 734 cmd->c_dmamap->dm_nsegs * sizeof(struct amlmmc_desc), 735 BUS_DMASYNC_POSTWRITE); 736 } 737 738 SET(cmd->c_flags, SCF_ITSDONE); 739 } 740 741 int 742 amlmmc_signal_voltage(sdmmc_chipset_handle_t sch, int signal_voltage) 743 { 744 struct amlmmc_softc *sc = sch; 745 uint32_t vccq; 746 747 if (sc->sc_vqmmc == 0) 748 return ENODEV; 749 750 switch (signal_voltage) { 751 case SDMMC_SIGNAL_VOLTAGE_180: 752 vccq = 1800000; 753 break; 754 case SDMMC_SIGNAL_VOLTAGE_330: 755 vccq = 3300000; 756 break; 757 default: 758 return EINVAL; 759 } 760 761 if (regulator_get_voltage(sc->sc_vqmmc) == vccq) 762 return 0; 763 764 return regulator_set_voltage(sc->sc_vqmmc, vccq); 765 } 766 767 int 768 amlmmc_execute_tuning(sdmmc_chipset_handle_t sch, int timing) 769 { 770 struct amlmmc_softc *sc = sch; 771 struct sdmmc_command cmd; 772 uint32_t adjust, cfg, div; 773 int opcode, delay; 774 char data[128]; 775 776 switch (timing) { 777 case SDMMC_TIMING_MMC_HS200: 778 opcode = MMC_SEND_TUNING_BLOCK_HS200; 779 break; 780 case SDMMC_TIMING_UHS_SDR50: 781 case SDMMC_TIMING_UHS_SDR104: 782 opcode = MMC_SEND_TUNING_BLOCK; 783 break; 784 default: 785 return EINVAL; 786 } 787 788 cfg = HREAD4(sc, SD_EMMC_CFG); 789 div = HREAD4(sc, SD_EMMC_CLOCK) & SD_EMMC_CLOCK_DIV_MAX; 790 791 adjust = HREAD4(sc, SD_EMMC_ADJUST); 792 adjust |= SD_EMMC_ADJUST_ADJ_FIXED; 793 HWRITE4(sc, SD_EMMC_ADJUST, adjust); 794 795 for (delay = 0; delay < div; delay++) { 796 adjust &= ~SD_EMMC_ADJUST_ADJ_DELAY_MASK; 797 adjust |= (delay << SD_EMMC_ADJUST_ADJ_DELAY_SHIFT); 798 HWRITE4(sc, SD_EMMC_ADJUST, adjust); 799 800 memset(&cmd, 0, sizeof(cmd)); 801 cmd.c_opcode = opcode; 802 cmd.c_arg = 0; 803 cmd.c_flags = SCF_CMD_ADTC | SCF_CMD_READ | SCF_RSP_R1; 804 if (cfg & SD_EMMC_CFG_BUS_WIDTH_8) { 805 cmd.c_blklen = cmd.c_datalen = 128; 806 } else { 807 cmd.c_blklen = cmd.c_datalen = 64; 808 } 809 cmd.c_data = data; 810 811 amlmmc_exec_command(sch, &cmd); 812 if (cmd.c_error == 0) 813 return 0; 814 } 815 816 adjust = HREAD4(sc, SD_EMMC_ADJUST); 817 adjust &= ~SD_EMMC_ADJUST_ADJ_FIXED; 818 HWRITE4(sc, SD_EMMC_ADJUST, adjust); 819 820 return EIO; 821 } 822