1 /* $OpenBSD: glkgpio.c,v 1.5 2022/04/06 18:59:27 naddy Exp $ */ 2 /* 3 * Copyright (c) 2016 Mark Kettenis 4 * Copyright (c) 2019 James Hastings 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #include <sys/param.h> 20 #include <sys/malloc.h> 21 #include <sys/systm.h> 22 23 #include <dev/acpi/acpireg.h> 24 #include <dev/acpi/acpivar.h> 25 #include <dev/acpi/acpidev.h> 26 #include <dev/acpi/amltypes.h> 27 #include <dev/acpi/dsdt.h> 28 29 #define GLKGPIO_CONF_TXSTATE 0x00000001 30 #define GLKGPIO_CONF_RXSTATE 0x00000002 31 #define GLKGPIO_CONF_RXINV 0x00800000 32 #define GLKGPIO_CONF_RXEV_EDGE 0x02000000 33 #define GLKGPIO_CONF_RXEV_ZERO 0x04000000 34 #define GLKGPIO_CONF_RXEV_MASK 0x06000000 35 36 #define GLKGPIO_IRQ_STS 0x100 37 #define GLKGPIO_IRQ_EN 0x110 38 #define GLKGPIO_PAD_CFG0 0x600 39 40 struct glkgpio_intrhand { 41 int (*ih_func)(void *); 42 void *ih_arg; 43 }; 44 45 struct glkgpio_softc { 46 struct device sc_dev; 47 struct acpi_softc *sc_acpi; 48 struct aml_node *sc_node; 49 50 bus_space_tag_t sc_memt; 51 bus_space_handle_t sc_memh; 52 void *sc_ih; 53 54 int sc_npins; 55 struct glkgpio_intrhand *sc_pin_ih; 56 57 struct acpi_gpio sc_gpio; 58 }; 59 60 int glkgpio_match(struct device *, void *, void *); 61 void glkgpio_attach(struct device *, struct device *, void *); 62 63 const struct cfattach glkgpio_ca = { 64 sizeof(struct glkgpio_softc), glkgpio_match, glkgpio_attach 65 }; 66 67 struct cfdriver glkgpio_cd = { 68 NULL, "glkgpio", DV_DULL 69 }; 70 71 const char *glkgpio_hids[] = { 72 "INT3453", 73 NULL 74 }; 75 76 int glkgpio_parse_resources(int, union acpi_resource *, void *); 77 int glkgpio_read_pin(void *, int); 78 void glkgpio_write_pin(void *, int, int); 79 void glkgpio_intr_establish(void *, int, int, int (*)(void *), void *); 80 int glkgpio_intr(void *); 81 82 int 83 glkgpio_match(struct device *parent, void *match, void *aux) 84 { 85 struct acpi_attach_args *aaa = aux; 86 struct cfdata *cf = match; 87 88 if (aaa->aaa_naddr < 1 || aaa->aaa_nirq < 1) 89 return 0; 90 return acpi_matchhids(aaa, glkgpio_hids, cf->cf_driver->cd_name); 91 } 92 93 void 94 glkgpio_attach(struct device *parent, struct device *self, void *aux) 95 { 96 struct glkgpio_softc *sc = (struct glkgpio_softc *)self; 97 struct acpi_attach_args *aaa = aux; 98 int64_t uid; 99 int i; 100 101 sc->sc_acpi = (struct acpi_softc *)parent; 102 sc->sc_node = aaa->aaa_node; 103 printf(" %s", sc->sc_node->name); 104 105 if (aml_evalinteger(sc->sc_acpi, sc->sc_node, "_UID", 0, NULL, &uid)) { 106 printf(": can't find uid\n"); 107 return; 108 } 109 110 printf(" uid %lld", uid); 111 112 switch (uid) { 113 case 1: 114 sc->sc_npins = 80; 115 break; 116 case 2: 117 sc->sc_npins = 80; 118 break; 119 case 3: 120 sc->sc_npins = 20; 121 break; 122 case 4: 123 sc->sc_npins = 35; 124 break; 125 default: 126 printf("\n"); 127 return; 128 } 129 130 printf(" addr 0x%llx/0x%llx", aaa->aaa_addr[0], aaa->aaa_size[0]); 131 printf(" irq %d", aaa->aaa_irq[0]); 132 133 sc->sc_memt = aaa->aaa_bst[0]; 134 if (bus_space_map(sc->sc_memt, aaa->aaa_addr[0], aaa->aaa_size[0], 135 0, &sc->sc_memh)) { 136 printf(": can't map registers\n"); 137 return; 138 } 139 140 sc->sc_pin_ih = mallocarray(sc->sc_npins, sizeof(*sc->sc_pin_ih), 141 M_DEVBUF, M_WAITOK | M_ZERO); 142 143 sc->sc_ih = acpi_intr_establish(aaa->aaa_irq[0], aaa->aaa_irq_flags[0], 144 IPL_BIO, glkgpio_intr, sc, sc->sc_dev.dv_xname); 145 if (sc->sc_ih == NULL) { 146 printf(": can't establish interrupt\n"); 147 goto unmap; 148 } 149 150 sc->sc_gpio.cookie = sc; 151 sc->sc_gpio.read_pin = glkgpio_read_pin; 152 sc->sc_gpio.write_pin = glkgpio_write_pin; 153 sc->sc_gpio.intr_establish = glkgpio_intr_establish; 154 sc->sc_node->gpio = &sc->sc_gpio; 155 156 /* Mask and clear all interrupts. */ 157 for (i = 0; i < sc->sc_npins; i++) { 158 if (i % 32 == 0) { 159 bus_space_write_4(sc->sc_memt, sc->sc_memh, 160 GLKGPIO_IRQ_EN + (i / 32) * 4, 0x00000000); 161 bus_space_write_4(sc->sc_memt, sc->sc_memh, 162 GLKGPIO_IRQ_STS + (i / 32) * 4, 0xffffffff); 163 } 164 } 165 166 printf(", %d pins\n", sc->sc_npins); 167 168 acpi_register_gpio(sc->sc_acpi, sc->sc_node); 169 return; 170 171 unmap: 172 free(sc->sc_pin_ih, M_DEVBUF, sc->sc_npins * sizeof(*sc->sc_pin_ih)); 173 bus_space_unmap(sc->sc_memt, sc->sc_memh, aaa->aaa_size[0]); 174 } 175 176 int 177 glkgpio_read_pin(void *cookie, int pin) 178 { 179 struct glkgpio_softc *sc = cookie; 180 uint32_t reg; 181 182 reg = bus_space_read_4(sc->sc_memt, sc->sc_memh, 183 GLKGPIO_PAD_CFG0 + pin * 16); 184 185 return !!(reg & GLKGPIO_CONF_RXSTATE); 186 } 187 188 void 189 glkgpio_write_pin(void *cookie, int pin, int value) 190 { 191 struct glkgpio_softc *sc = cookie; 192 uint32_t reg; 193 194 reg = bus_space_read_4(sc->sc_memt, sc->sc_memh, 195 GLKGPIO_PAD_CFG0 + pin * 16); 196 if (value) 197 reg |= GLKGPIO_CONF_TXSTATE; 198 else 199 reg &= ~GLKGPIO_CONF_TXSTATE; 200 bus_space_write_4(sc->sc_memt, sc->sc_memh, 201 GLKGPIO_PAD_CFG0 + pin * 16, reg); 202 } 203 204 void 205 glkgpio_intr_establish(void *cookie, int pin, int flags, 206 int (*func)(void *), void *arg) 207 { 208 struct glkgpio_softc *sc = cookie; 209 uint32_t reg; 210 211 KASSERT(pin >= 0 && pin < sc->sc_npins); 212 213 sc->sc_pin_ih[pin].ih_func = func; 214 sc->sc_pin_ih[pin].ih_arg = arg; 215 216 reg = bus_space_read_4(sc->sc_memt, sc->sc_memh, 217 GLKGPIO_PAD_CFG0 + pin * 16); 218 reg &= ~(GLKGPIO_CONF_RXEV_MASK | GLKGPIO_CONF_RXINV); 219 if ((flags & LR_GPIO_MODE) == 1) 220 reg |= GLKGPIO_CONF_RXEV_EDGE; 221 if ((flags & LR_GPIO_POLARITY) == LR_GPIO_ACTLO) 222 reg |= GLKGPIO_CONF_RXINV; 223 if ((flags & LR_GPIO_POLARITY) == LR_GPIO_ACTBOTH) 224 reg |= GLKGPIO_CONF_RXEV_EDGE | GLKGPIO_CONF_RXEV_ZERO; 225 bus_space_write_4(sc->sc_memt, sc->sc_memh, 226 GLKGPIO_PAD_CFG0 + pin * 16, reg); 227 228 reg = bus_space_read_4(sc->sc_memt, sc->sc_memh, 229 GLKGPIO_IRQ_EN + (pin / 32) * 4); 230 reg |= (1 << (pin % 32)); 231 bus_space_write_4(sc->sc_memt, sc->sc_memh, 232 GLKGPIO_IRQ_EN + (pin / 32) * 4, reg); 233 } 234 235 int 236 glkgpio_intr(void *arg) 237 { 238 struct glkgpio_softc *sc = arg; 239 uint32_t status, enable; 240 int rc = 0; 241 int pin; 242 243 for (pin = 0; pin < sc->sc_npins; pin++) { 244 if (pin % 32 == 0) { 245 status = bus_space_read_4(sc->sc_memt, sc->sc_memh, 246 GLKGPIO_IRQ_STS + (pin / 32) * 4); 247 bus_space_write_4(sc->sc_memt, sc->sc_memh, 248 GLKGPIO_IRQ_STS + (pin / 32) * 4, status); 249 enable = bus_space_read_4(sc->sc_memt, sc->sc_memh, 250 GLKGPIO_IRQ_EN + (pin / 32) * 4); 251 status &= enable; 252 } 253 if (status & (1 << (pin % 32))) { 254 if (sc->sc_pin_ih[pin].ih_func) 255 sc->sc_pin_ih[pin].ih_func(sc->sc_pin_ih[pin].ih_arg); 256 rc = 1; 257 } 258 } 259 return rc; 260 } 261