1 /* $OpenBSD: glkgpio.c,v 1.2 2020/05/22 10:16:37 kettenis Exp $ */ 2 /* 3 * Copyright (c) 2016 Mark Kettenis 4 * Copyright (c) 2019 James Hastings 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #include <sys/param.h> 20 #include <sys/malloc.h> 21 #include <sys/systm.h> 22 23 #include <dev/acpi/acpireg.h> 24 #include <dev/acpi/acpivar.h> 25 #include <dev/acpi/acpidev.h> 26 #include <dev/acpi/amltypes.h> 27 #include <dev/acpi/dsdt.h> 28 29 #define GLKGPIO_CONF_TXSTATE 0x00000001 30 #define GLKGPIO_CONF_RXSTATE 0x00000002 31 #define GLKGPIO_CONF_RXINV 0x00800000 32 #define GLKGPIO_CONF_RXEV_EDGE 0x02000000 33 #define GLKGPIO_CONF_RXEV_ZERO 0x04000000 34 #define GLKGPIO_CONF_RXEV_MASK 0x06000000 35 36 #define GLKGPIO_IRQ_STS 0x100 37 #define GLKGPIO_IRQ_EN 0x110 38 #define GLKGPIO_PAD_CFG0 0x600 39 40 struct glkgpio_intrhand { 41 int (*ih_func)(void *); 42 void *ih_arg; 43 }; 44 45 struct glkgpio_softc { 46 struct device sc_dev; 47 struct acpi_softc *sc_acpi; 48 struct aml_node *sc_node; 49 50 bus_space_tag_t sc_memt; 51 bus_space_handle_t sc_memh; 52 void *sc_ih; 53 54 int sc_npins; 55 struct glkgpio_intrhand *sc_pin_ih; 56 57 struct acpi_gpio sc_gpio; 58 }; 59 60 int glkgpio_match(struct device *, void *, void *); 61 void glkgpio_attach(struct device *, struct device *, void *); 62 63 struct cfattach glkgpio_ca = { 64 sizeof(struct glkgpio_softc), glkgpio_match, glkgpio_attach 65 }; 66 67 struct cfdriver glkgpio_cd = { 68 NULL, "glkgpio", DV_DULL 69 }; 70 71 const char *glkgpio_hids[] = { 72 "INT3453", 73 NULL 74 }; 75 76 int glkgpio_parse_resources(int, union acpi_resource *, void *); 77 int glkgpio_read_pin(void *, int); 78 void glkgpio_write_pin(void *, int, int); 79 void glkgpio_intr_establish(void *, int, int, int (*)(), void *); 80 int glkgpio_intr(void *); 81 82 int 83 glkgpio_match(struct device *parent, void *match, void *aux) 84 { 85 struct acpi_attach_args *aaa = aux; 86 struct cfdata *cf = match; 87 88 return acpi_matchhids(aaa, glkgpio_hids, cf->cf_driver->cd_name); 89 } 90 91 void 92 glkgpio_attach(struct device *parent, struct device *self, void *aux) 93 { 94 struct glkgpio_softc *sc = (struct glkgpio_softc *)self; 95 struct acpi_attach_args *aaa = aux; 96 int64_t uid; 97 int i; 98 99 sc->sc_acpi = (struct acpi_softc *)parent; 100 sc->sc_node = aaa->aaa_node; 101 printf(" %s", sc->sc_node->name); 102 103 if (aaa->aaa_naddr < 1) { 104 printf(": no registers\n"); 105 return; 106 } 107 108 if (aaa->aaa_nirq < 1) { 109 printf(": no interrupt\n"); 110 return; 111 } 112 113 if (aml_evalinteger(sc->sc_acpi, sc->sc_node, "_UID", 0, NULL, &uid)) { 114 printf(": can't find uid\n"); 115 return; 116 } 117 118 printf(" uid %lld", uid); 119 120 switch (uid) { 121 case 1: 122 sc->sc_npins = 80; 123 break; 124 case 2: 125 sc->sc_npins = 80; 126 break; 127 case 3: 128 sc->sc_npins = 20; 129 break; 130 case 4: 131 sc->sc_npins = 35; 132 break; 133 default: 134 printf("\n"); 135 return; 136 } 137 138 printf(" addr 0x%llx/0x%llx", aaa->aaa_addr[0], aaa->aaa_size[0]); 139 printf(" irq %d", aaa->aaa_irq[0]); 140 141 sc->sc_memt = aaa->aaa_bst[0]; 142 if (bus_space_map(sc->sc_memt, aaa->aaa_addr[0], aaa->aaa_size[0], 143 0, &sc->sc_memh)) { 144 printf(": can't map registers\n"); 145 return; 146 } 147 148 sc->sc_pin_ih = mallocarray(sc->sc_npins, sizeof(*sc->sc_pin_ih), 149 M_DEVBUF, M_WAITOK | M_ZERO); 150 151 sc->sc_ih = acpi_intr_establish(aaa->aaa_irq[0], aaa->aaa_irq_flags[0], 152 IPL_BIO, glkgpio_intr, sc, sc->sc_dev.dv_xname); 153 if (sc->sc_ih == NULL) { 154 printf(": can't establish interrupt\n"); 155 goto unmap; 156 } 157 158 sc->sc_gpio.cookie = sc; 159 sc->sc_gpio.read_pin = glkgpio_read_pin; 160 sc->sc_gpio.write_pin = glkgpio_write_pin; 161 sc->sc_gpio.intr_establish = glkgpio_intr_establish; 162 sc->sc_node->gpio = &sc->sc_gpio; 163 164 /* Mask and clear all interrupts. */ 165 for (i = 0; i < sc->sc_npins; i++) { 166 if (i % 32 == 0) { 167 bus_space_write_4(sc->sc_memt, sc->sc_memh, 168 GLKGPIO_IRQ_EN + (i / 32) * 4, 0x00000000); 169 bus_space_write_4(sc->sc_memt, sc->sc_memh, 170 GLKGPIO_IRQ_STS + (i / 32) * 4, 0xffffffff); 171 } 172 } 173 174 printf(", %d pins\n", sc->sc_npins); 175 176 acpi_register_gpio(sc->sc_acpi, sc->sc_node); 177 return; 178 179 unmap: 180 free(sc->sc_pin_ih, M_DEVBUF, sc->sc_npins * sizeof(*sc->sc_pin_ih)); 181 bus_space_unmap(sc->sc_memt, sc->sc_memh, aaa->aaa_size[0]); 182 } 183 184 int 185 glkgpio_read_pin(void *cookie, int pin) 186 { 187 struct glkgpio_softc *sc = cookie; 188 uint32_t reg; 189 190 reg = bus_space_read_4(sc->sc_memt, sc->sc_memh, 191 GLKGPIO_PAD_CFG0 + pin * 16); 192 193 return !!(reg & GLKGPIO_CONF_RXSTATE); 194 } 195 196 void 197 glkgpio_write_pin(void *cookie, int pin, int value) 198 { 199 struct glkgpio_softc *sc = cookie; 200 uint32_t reg; 201 202 reg = bus_space_read_4(sc->sc_memt, sc->sc_memh, 203 GLKGPIO_PAD_CFG0 + pin * 16); 204 if (value) 205 reg |= GLKGPIO_CONF_TXSTATE; 206 else 207 reg &= ~GLKGPIO_CONF_TXSTATE; 208 bus_space_write_4(sc->sc_memt, sc->sc_memh, 209 GLKGPIO_PAD_CFG0 + pin * 16, reg); 210 } 211 212 void 213 glkgpio_intr_establish(void *cookie, int pin, int flags, 214 int (*func)(void *), void *arg) 215 { 216 struct glkgpio_softc *sc = cookie; 217 uint32_t reg; 218 219 KASSERT(pin >= 0 && pin < sc->sc_npins); 220 221 sc->sc_pin_ih[pin].ih_func = func; 222 sc->sc_pin_ih[pin].ih_arg = arg; 223 224 reg = bus_space_read_4(sc->sc_memt, sc->sc_memh, 225 GLKGPIO_PAD_CFG0 + pin * 16); 226 reg &= ~(GLKGPIO_CONF_RXEV_MASK | GLKGPIO_CONF_RXINV); 227 if ((flags & LR_GPIO_MODE) == 1) 228 reg |= GLKGPIO_CONF_RXEV_EDGE; 229 if ((flags & LR_GPIO_POLARITY) == LR_GPIO_ACTLO) 230 reg |= GLKGPIO_CONF_RXINV; 231 if ((flags & LR_GPIO_POLARITY) == LR_GPIO_ACTBOTH) 232 reg |= GLKGPIO_CONF_RXEV_EDGE | GLKGPIO_CONF_RXEV_ZERO; 233 bus_space_write_4(sc->sc_memt, sc->sc_memh, 234 GLKGPIO_PAD_CFG0 + pin * 16, reg); 235 236 reg = bus_space_read_4(sc->sc_memt, sc->sc_memh, 237 GLKGPIO_IRQ_EN + (pin / 32) * 4); 238 reg |= (1 << (pin % 32)); 239 bus_space_write_4(sc->sc_memt, sc->sc_memh, 240 GLKGPIO_IRQ_EN + (pin / 32) * 4, reg); 241 } 242 243 int 244 glkgpio_intr(void *arg) 245 { 246 struct glkgpio_softc *sc = arg; 247 uint32_t status, enable; 248 int rc = 0; 249 int pin; 250 251 for (pin = 0; pin < sc->sc_npins; pin++) { 252 if (pin % 32 == 0) { 253 status = bus_space_read_4(sc->sc_memt, sc->sc_memh, 254 GLKGPIO_IRQ_STS + (pin / 32) * 4); 255 bus_space_write_4(sc->sc_memt, sc->sc_memh, 256 GLKGPIO_IRQ_STS + (pin / 32) * 4, status); 257 enable = bus_space_read_4(sc->sc_memt, sc->sc_memh, 258 GLKGPIO_IRQ_EN + (pin / 32) * 4); 259 status &= enable; 260 } 261 if (status & (1 << (pin % 32))) { 262 if (sc->sc_pin_ih[pin].ih_func) 263 sc->sc_pin_ih[pin].ih_func(sc->sc_pin_ih[pin].ih_arg); 264 rc = 1; 265 } 266 } 267 return rc; 268 } 269